Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6.git] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12  *
13  * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
14  * Copyright 2007 MontaVista Software, Inc.
15  *
16  * This program is free software; you can redistribute  it and/or modify it
17  * under  the terms of  the GNU General  Public License as published by the
18  * Free Software Foundation;  either version 2 of the  License, or (at your
19  * option) any later version.
20  *
21  *  Gianfar:  AKA Lambda Draconis, "Dragon"
22  *  RA 11 31 24.2
23  *  Dec +69 19 52
24  *  V 3.84
25  *  B-V +1.62
26  *
27  *  Theory of operation
28  *
29  *  The driver is initialized through of_device. Configuration information
30  *  is therefore conveyed through an OF-style device tree.
31  *
32  *  The Gianfar Ethernet Controller uses a ring of buffer
33  *  descriptors.  The beginning is indicated by a register
34  *  pointing to the physical address of the start of the ring.
35  *  The end is determined by a "wrap" bit being set in the
36  *  last descriptor of the ring.
37  *
38  *  When a packet is received, the RXF bit in the
39  *  IEVENT register is set, triggering an interrupt when the
40  *  corresponding bit in the IMASK register is also set (if
41  *  interrupt coalescing is active, then the interrupt may not
42  *  happen immediately, but will wait until either a set number
43  *  of frames or amount of time have passed).  In NAPI, the
44  *  interrupt handler will signal there is work to be done, and
45  *  exit. This method will start at the last known empty
46  *  descriptor, and process every subsequent descriptor until there
47  *  are none left with data (NAPI will stop after a set number of
48  *  packets to give time to other tasks, but will eventually
49  *  process all the packets).  The data arrives inside a
50  *  pre-allocated skb, and so after the skb is passed up to the
51  *  stack, a new skb must be allocated, and the address field in
52  *  the buffer descriptor must be updated to indicate this new
53  *  skb.
54  *
55  *  When the kernel requests that a packet be transmitted, the
56  *  driver starts where it left off last time, and points the
57  *  descriptor at the buffer which was passed in.  The driver
58  *  then informs the DMA engine that there are packets ready to
59  *  be transmitted.  Once the controller is finished transmitting
60  *  the packet, an interrupt may be triggered (under the same
61  *  conditions as for reception, but depending on the TXF bit).
62  *  The driver then cleans up the buffer.
63  */
64
65 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
66 #define DEBUG
67
68 #include <linux/kernel.h>
69 #include <linux/string.h>
70 #include <linux/errno.h>
71 #include <linux/unistd.h>
72 #include <linux/slab.h>
73 #include <linux/interrupt.h>
74 #include <linux/init.h>
75 #include <linux/delay.h>
76 #include <linux/netdevice.h>
77 #include <linux/etherdevice.h>
78 #include <linux/skbuff.h>
79 #include <linux/if_vlan.h>
80 #include <linux/spinlock.h>
81 #include <linux/mm.h>
82 #include <linux/of_mdio.h>
83 #include <linux/of_platform.h>
84 #include <linux/ip.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
87 #include <linux/in.h>
88 #include <linux/net_tstamp.h>
89
90 #include <asm/io.h>
91 #include <asm/reg.h>
92 #include <asm/irq.h>
93 #include <asm/uaccess.h>
94 #include <linux/module.h>
95 #include <linux/dma-mapping.h>
96 #include <linux/crc32.h>
97 #include <linux/mii.h>
98 #include <linux/phy.h>
99 #include <linux/phy_fixed.h>
100 #include <linux/of.h>
101 #include <linux/of_net.h>
102
103 #include "gianfar.h"
104 #include "fsl_pq_mdio.h"
105
106 #define TX_TIMEOUT      (1*HZ)
107 #undef BRIEF_GFAR_ERRORS
108 #undef VERBOSE_GFAR_ERRORS
109
110 const char gfar_driver_name[] = "Gianfar Ethernet";
111 const char gfar_driver_version[] = "1.3";
112
113 static int gfar_enet_open(struct net_device *dev);
114 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
115 static void gfar_reset_task(struct work_struct *work);
116 static void gfar_timeout(struct net_device *dev);
117 static int gfar_close(struct net_device *dev);
118 struct sk_buff *gfar_new_skb(struct net_device *dev);
119 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
120                 struct sk_buff *skb);
121 static int gfar_set_mac_address(struct net_device *dev);
122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
123 static irqreturn_t gfar_error(int irq, void *dev_id);
124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
126 static void adjust_link(struct net_device *dev);
127 static void init_registers(struct net_device *dev);
128 static int init_phy(struct net_device *dev);
129 static int gfar_probe(struct platform_device *ofdev);
130 static int gfar_remove(struct platform_device *ofdev);
131 static void free_skb_resources(struct gfar_private *priv);
132 static void gfar_set_multi(struct net_device *dev);
133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
134 static void gfar_configure_serdes(struct net_device *dev);
135 static int gfar_poll(struct napi_struct *napi, int budget);
136 #ifdef CONFIG_NET_POLL_CONTROLLER
137 static void gfar_netpoll(struct net_device *dev);
138 #endif
139 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
140 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
141 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
142                               int amount_pull);
143 static void gfar_vlan_rx_register(struct net_device *netdev,
144                                 struct vlan_group *grp);
145 void gfar_halt(struct net_device *dev);
146 static void gfar_halt_nodisable(struct net_device *dev);
147 void gfar_start(struct net_device *dev);
148 static void gfar_clear_exact_match(struct net_device *dev);
149 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
150                                   const u8 *addr);
151 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
152
153 MODULE_AUTHOR("Freescale Semiconductor, Inc");
154 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
155 MODULE_LICENSE("GPL");
156
157 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
158                             dma_addr_t buf)
159 {
160         u32 lstatus;
161
162         bdp->bufPtr = buf;
163
164         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
165         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
166                 lstatus |= BD_LFLAG(RXBD_WRAP);
167
168         eieio();
169
170         bdp->lstatus = lstatus;
171 }
172
173 static int gfar_init_bds(struct net_device *ndev)
174 {
175         struct gfar_private *priv = netdev_priv(ndev);
176         struct gfar_priv_tx_q *tx_queue = NULL;
177         struct gfar_priv_rx_q *rx_queue = NULL;
178         struct txbd8 *txbdp;
179         struct rxbd8 *rxbdp;
180         int i, j;
181
182         for (i = 0; i < priv->num_tx_queues; i++) {
183                 tx_queue = priv->tx_queue[i];
184                 /* Initialize some variables in our dev structure */
185                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
186                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
187                 tx_queue->cur_tx = tx_queue->tx_bd_base;
188                 tx_queue->skb_curtx = 0;
189                 tx_queue->skb_dirtytx = 0;
190
191                 /* Initialize Transmit Descriptor Ring */
192                 txbdp = tx_queue->tx_bd_base;
193                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
194                         txbdp->lstatus = 0;
195                         txbdp->bufPtr = 0;
196                         txbdp++;
197                 }
198
199                 /* Set the last descriptor in the ring to indicate wrap */
200                 txbdp--;
201                 txbdp->status |= TXBD_WRAP;
202         }
203
204         for (i = 0; i < priv->num_rx_queues; i++) {
205                 rx_queue = priv->rx_queue[i];
206                 rx_queue->cur_rx = rx_queue->rx_bd_base;
207                 rx_queue->skb_currx = 0;
208                 rxbdp = rx_queue->rx_bd_base;
209
210                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
211                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
212
213                         if (skb) {
214                                 gfar_init_rxbdp(rx_queue, rxbdp,
215                                                 rxbdp->bufPtr);
216                         } else {
217                                 skb = gfar_new_skb(ndev);
218                                 if (!skb) {
219                                         netdev_err(ndev, "Can't allocate RX buffers\n");
220                                         goto err_rxalloc_fail;
221                                 }
222                                 rx_queue->rx_skbuff[j] = skb;
223
224                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
225                         }
226
227                         rxbdp++;
228                 }
229
230         }
231
232         return 0;
233
234 err_rxalloc_fail:
235         free_skb_resources(priv);
236         return -ENOMEM;
237 }
238
239 static int gfar_alloc_skb_resources(struct net_device *ndev)
240 {
241         void *vaddr;
242         dma_addr_t addr;
243         int i, j, k;
244         struct gfar_private *priv = netdev_priv(ndev);
245         struct device *dev = &priv->ofdev->dev;
246         struct gfar_priv_tx_q *tx_queue = NULL;
247         struct gfar_priv_rx_q *rx_queue = NULL;
248
249         priv->total_tx_ring_size = 0;
250         for (i = 0; i < priv->num_tx_queues; i++)
251                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
252
253         priv->total_rx_ring_size = 0;
254         for (i = 0; i < priv->num_rx_queues; i++)
255                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
256
257         /* Allocate memory for the buffer descriptors */
258         vaddr = dma_alloc_coherent(dev,
259                         sizeof(struct txbd8) * priv->total_tx_ring_size +
260                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
261                         &addr, GFP_KERNEL);
262         if (!vaddr) {
263                 netif_err(priv, ifup, ndev,
264                           "Could not allocate buffer descriptors!\n");
265                 return -ENOMEM;
266         }
267
268         for (i = 0; i < priv->num_tx_queues; i++) {
269                 tx_queue = priv->tx_queue[i];
270                 tx_queue->tx_bd_base = vaddr;
271                 tx_queue->tx_bd_dma_base = addr;
272                 tx_queue->dev = ndev;
273                 /* enet DMA only understands physical addresses */
274                 addr    += sizeof(struct txbd8) *tx_queue->tx_ring_size;
275                 vaddr   += sizeof(struct txbd8) *tx_queue->tx_ring_size;
276         }
277
278         /* Start the rx descriptor ring where the tx ring leaves off */
279         for (i = 0; i < priv->num_rx_queues; i++) {
280                 rx_queue = priv->rx_queue[i];
281                 rx_queue->rx_bd_base = vaddr;
282                 rx_queue->rx_bd_dma_base = addr;
283                 rx_queue->dev = ndev;
284                 addr    += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
285                 vaddr   += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
286         }
287
288         /* Setup the skbuff rings */
289         for (i = 0; i < priv->num_tx_queues; i++) {
290                 tx_queue = priv->tx_queue[i];
291                 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
292                                   tx_queue->tx_ring_size, GFP_KERNEL);
293                 if (!tx_queue->tx_skbuff) {
294                         netif_err(priv, ifup, ndev,
295                                   "Could not allocate tx_skbuff\n");
296                         goto cleanup;
297                 }
298
299                 for (k = 0; k < tx_queue->tx_ring_size; k++)
300                         tx_queue->tx_skbuff[k] = NULL;
301         }
302
303         for (i = 0; i < priv->num_rx_queues; i++) {
304                 rx_queue = priv->rx_queue[i];
305                 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
306                                   rx_queue->rx_ring_size, GFP_KERNEL);
307
308                 if (!rx_queue->rx_skbuff) {
309                         netif_err(priv, ifup, ndev,
310                                   "Could not allocate rx_skbuff\n");
311                         goto cleanup;
312                 }
313
314                 for (j = 0; j < rx_queue->rx_ring_size; j++)
315                         rx_queue->rx_skbuff[j] = NULL;
316         }
317
318         if (gfar_init_bds(ndev))
319                 goto cleanup;
320
321         return 0;
322
323 cleanup:
324         free_skb_resources(priv);
325         return -ENOMEM;
326 }
327
328 static void gfar_init_tx_rx_base(struct gfar_private *priv)
329 {
330         struct gfar __iomem *regs = priv->gfargrp[0].regs;
331         u32 __iomem *baddr;
332         int i;
333
334         baddr = &regs->tbase0;
335         for(i = 0; i < priv->num_tx_queues; i++) {
336                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
337                 baddr   += 2;
338         }
339
340         baddr = &regs->rbase0;
341         for(i = 0; i < priv->num_rx_queues; i++) {
342                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
343                 baddr   += 2;
344         }
345 }
346
347 static void gfar_init_mac(struct net_device *ndev)
348 {
349         struct gfar_private *priv = netdev_priv(ndev);
350         struct gfar __iomem *regs = priv->gfargrp[0].regs;
351         u32 rctrl = 0;
352         u32 tctrl = 0;
353         u32 attrs = 0;
354
355         /* write the tx/rx base registers */
356         gfar_init_tx_rx_base(priv);
357
358         /* Configure the coalescing support */
359         gfar_configure_coalescing(priv, 0xFF, 0xFF);
360
361         if (priv->rx_filer_enable) {
362                 rctrl |= RCTRL_FILREN;
363                 /* Program the RIR0 reg with the required distribution */
364                 gfar_write(&regs->rir0, DEFAULT_RIR0);
365         }
366
367         if (ndev->features & NETIF_F_RXCSUM)
368                 rctrl |= RCTRL_CHECKSUMMING;
369
370         if (priv->extended_hash) {
371                 rctrl |= RCTRL_EXTHASH;
372
373                 gfar_clear_exact_match(ndev);
374                 rctrl |= RCTRL_EMEN;
375         }
376
377         if (priv->padding) {
378                 rctrl &= ~RCTRL_PAL_MASK;
379                 rctrl |= RCTRL_PADDING(priv->padding);
380         }
381
382         /* Insert receive time stamps into padding alignment bytes */
383         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
384                 rctrl &= ~RCTRL_PAL_MASK;
385                 rctrl |= RCTRL_PADDING(8);
386                 priv->padding = 8;
387         }
388
389         /* Enable HW time stamping if requested from user space */
390         if (priv->hwts_rx_en)
391                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
392
393         /* keep vlan related bits if it's enabled */
394         if (priv->vlgrp) {
395                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
396                 tctrl |= TCTRL_VLINS;
397         }
398
399         /* Init rctrl based on our settings */
400         gfar_write(&regs->rctrl, rctrl);
401
402         if (ndev->features & NETIF_F_IP_CSUM)
403                 tctrl |= TCTRL_INIT_CSUM;
404
405         tctrl |= TCTRL_TXSCHED_PRIO;
406
407         gfar_write(&regs->tctrl, tctrl);
408
409         /* Set the extraction length and index */
410         attrs = ATTRELI_EL(priv->rx_stash_size) |
411                 ATTRELI_EI(priv->rx_stash_index);
412
413         gfar_write(&regs->attreli, attrs);
414
415         /* Start with defaults, and add stashing or locking
416          * depending on the approprate variables */
417         attrs = ATTR_INIT_SETTINGS;
418
419         if (priv->bd_stash_en)
420                 attrs |= ATTR_BDSTASH;
421
422         if (priv->rx_stash_size != 0)
423                 attrs |= ATTR_BUFSTASH;
424
425         gfar_write(&regs->attr, attrs);
426
427         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
428         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
429         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
430 }
431
432 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
433 {
434         struct gfar_private *priv = netdev_priv(dev);
435         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
436         unsigned long tx_packets = 0, tx_bytes = 0;
437         int i = 0;
438
439         for (i = 0; i < priv->num_rx_queues; i++) {
440                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
441                 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
442                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
443         }
444
445         dev->stats.rx_packets = rx_packets;
446         dev->stats.rx_bytes = rx_bytes;
447         dev->stats.rx_dropped = rx_dropped;
448
449         for (i = 0; i < priv->num_tx_queues; i++) {
450                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
451                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
452         }
453
454         dev->stats.tx_bytes = tx_bytes;
455         dev->stats.tx_packets = tx_packets;
456
457         return &dev->stats;
458 }
459
460 static const struct net_device_ops gfar_netdev_ops = {
461         .ndo_open = gfar_enet_open,
462         .ndo_start_xmit = gfar_start_xmit,
463         .ndo_stop = gfar_close,
464         .ndo_change_mtu = gfar_change_mtu,
465         .ndo_set_features = gfar_set_features,
466         .ndo_set_multicast_list = gfar_set_multi,
467         .ndo_tx_timeout = gfar_timeout,
468         .ndo_do_ioctl = gfar_ioctl,
469         .ndo_get_stats = gfar_get_stats,
470         .ndo_vlan_rx_register = gfar_vlan_rx_register,
471         .ndo_set_mac_address = eth_mac_addr,
472         .ndo_validate_addr = eth_validate_addr,
473 #ifdef CONFIG_NET_POLL_CONTROLLER
474         .ndo_poll_controller = gfar_netpoll,
475 #endif
476 };
477
478 void lock_rx_qs(struct gfar_private *priv)
479 {
480         int i = 0x0;
481
482         for (i = 0; i < priv->num_rx_queues; i++)
483                 spin_lock(&priv->rx_queue[i]->rxlock);
484 }
485
486 void lock_tx_qs(struct gfar_private *priv)
487 {
488         int i = 0x0;
489
490         for (i = 0; i < priv->num_tx_queues; i++)
491                 spin_lock(&priv->tx_queue[i]->txlock);
492 }
493
494 void unlock_rx_qs(struct gfar_private *priv)
495 {
496         int i = 0x0;
497
498         for (i = 0; i < priv->num_rx_queues; i++)
499                 spin_unlock(&priv->rx_queue[i]->rxlock);
500 }
501
502 void unlock_tx_qs(struct gfar_private *priv)
503 {
504         int i = 0x0;
505
506         for (i = 0; i < priv->num_tx_queues; i++)
507                 spin_unlock(&priv->tx_queue[i]->txlock);
508 }
509
510 /* Returns 1 if incoming frames use an FCB */
511 static inline int gfar_uses_fcb(struct gfar_private *priv)
512 {
513         return priv->vlgrp || (priv->ndev->features & NETIF_F_RXCSUM) ||
514                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
515 }
516
517 static void free_tx_pointers(struct gfar_private *priv)
518 {
519         int i = 0;
520
521         for (i = 0; i < priv->num_tx_queues; i++)
522                 kfree(priv->tx_queue[i]);
523 }
524
525 static void free_rx_pointers(struct gfar_private *priv)
526 {
527         int i = 0;
528
529         for (i = 0; i < priv->num_rx_queues; i++)
530                 kfree(priv->rx_queue[i]);
531 }
532
533 static void unmap_group_regs(struct gfar_private *priv)
534 {
535         int i = 0;
536
537         for (i = 0; i < MAXGROUPS; i++)
538                 if (priv->gfargrp[i].regs)
539                         iounmap(priv->gfargrp[i].regs);
540 }
541
542 static void disable_napi(struct gfar_private *priv)
543 {
544         int i = 0;
545
546         for (i = 0; i < priv->num_grps; i++)
547                 napi_disable(&priv->gfargrp[i].napi);
548 }
549
550 static void enable_napi(struct gfar_private *priv)
551 {
552         int i = 0;
553
554         for (i = 0; i < priv->num_grps; i++)
555                 napi_enable(&priv->gfargrp[i].napi);
556 }
557
558 static int gfar_parse_group(struct device_node *np,
559                 struct gfar_private *priv, const char *model)
560 {
561         u32 *queue_mask;
562
563         priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
564         if (!priv->gfargrp[priv->num_grps].regs)
565                 return -ENOMEM;
566
567         priv->gfargrp[priv->num_grps].interruptTransmit =
568                         irq_of_parse_and_map(np, 0);
569
570         /* If we aren't the FEC we have multiple interrupts */
571         if (model && strcasecmp(model, "FEC")) {
572                 priv->gfargrp[priv->num_grps].interruptReceive =
573                         irq_of_parse_and_map(np, 1);
574                 priv->gfargrp[priv->num_grps].interruptError =
575                         irq_of_parse_and_map(np,2);
576                 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
577                     priv->gfargrp[priv->num_grps].interruptReceive  == NO_IRQ ||
578                     priv->gfargrp[priv->num_grps].interruptError    == NO_IRQ)
579                         return -EINVAL;
580         }
581
582         priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
583         priv->gfargrp[priv->num_grps].priv = priv;
584         spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
585         if(priv->mode == MQ_MG_MODE) {
586                 queue_mask = (u32 *)of_get_property(np,
587                                         "fsl,rx-bit-map", NULL);
588                 priv->gfargrp[priv->num_grps].rx_bit_map =
589                         queue_mask ?  *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
590                 queue_mask = (u32 *)of_get_property(np,
591                                         "fsl,tx-bit-map", NULL);
592                 priv->gfargrp[priv->num_grps].tx_bit_map =
593                         queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
594         } else {
595                 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
596                 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
597         }
598         priv->num_grps++;
599
600         return 0;
601 }
602
603 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
604 {
605         const char *model;
606         const char *ctype;
607         const void *mac_addr;
608         int err = 0, i;
609         struct net_device *dev = NULL;
610         struct gfar_private *priv = NULL;
611         struct device_node *np = ofdev->dev.of_node;
612         struct device_node *child = NULL;
613         const u32 *stash;
614         const u32 *stash_len;
615         const u32 *stash_idx;
616         unsigned int num_tx_qs, num_rx_qs;
617         u32 *tx_queues, *rx_queues;
618
619         if (!np || !of_device_is_available(np))
620                 return -ENODEV;
621
622         /* parse the num of tx and rx queues */
623         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
624         num_tx_qs = tx_queues ? *tx_queues : 1;
625
626         if (num_tx_qs > MAX_TX_QS) {
627                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
628                        num_tx_qs, MAX_TX_QS);
629                 pr_err("Cannot do alloc_etherdev, aborting\n");
630                 return -EINVAL;
631         }
632
633         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
634         num_rx_qs = rx_queues ? *rx_queues : 1;
635
636         if (num_rx_qs > MAX_RX_QS) {
637                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
638                        num_rx_qs, MAX_RX_QS);
639                 pr_err("Cannot do alloc_etherdev, aborting\n");
640                 return -EINVAL;
641         }
642
643         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
644         dev = *pdev;
645         if (NULL == dev)
646                 return -ENOMEM;
647
648         priv = netdev_priv(dev);
649         priv->node = ofdev->dev.of_node;
650         priv->ndev = dev;
651
652         priv->num_tx_queues = num_tx_qs;
653         netif_set_real_num_rx_queues(dev, num_rx_qs);
654         priv->num_rx_queues = num_rx_qs;
655         priv->num_grps = 0x0;
656
657         /* Init Rx queue filer rule set linked list*/
658         INIT_LIST_HEAD(&priv->rx_list.list);
659         priv->rx_list.count = 0;
660         mutex_init(&priv->rx_queue_access);
661
662         model = of_get_property(np, "model", NULL);
663
664         for (i = 0; i < MAXGROUPS; i++)
665                 priv->gfargrp[i].regs = NULL;
666
667         /* Parse and initialize group specific information */
668         if (of_device_is_compatible(np, "fsl,etsec2")) {
669                 priv->mode = MQ_MG_MODE;
670                 for_each_child_of_node(np, child) {
671                         err = gfar_parse_group(child, priv, model);
672                         if (err)
673                                 goto err_grp_init;
674                 }
675         } else {
676                 priv->mode = SQ_SG_MODE;
677                 err = gfar_parse_group(np, priv, model);
678                 if(err)
679                         goto err_grp_init;
680         }
681
682         for (i = 0; i < priv->num_tx_queues; i++)
683                priv->tx_queue[i] = NULL;
684         for (i = 0; i < priv->num_rx_queues; i++)
685                 priv->rx_queue[i] = NULL;
686
687         for (i = 0; i < priv->num_tx_queues; i++) {
688                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
689                                             GFP_KERNEL);
690                 if (!priv->tx_queue[i]) {
691                         err = -ENOMEM;
692                         goto tx_alloc_failed;
693                 }
694                 priv->tx_queue[i]->tx_skbuff = NULL;
695                 priv->tx_queue[i]->qindex = i;
696                 priv->tx_queue[i]->dev = dev;
697                 spin_lock_init(&(priv->tx_queue[i]->txlock));
698         }
699
700         for (i = 0; i < priv->num_rx_queues; i++) {
701                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
702                                             GFP_KERNEL);
703                 if (!priv->rx_queue[i]) {
704                         err = -ENOMEM;
705                         goto rx_alloc_failed;
706                 }
707                 priv->rx_queue[i]->rx_skbuff = NULL;
708                 priv->rx_queue[i]->qindex = i;
709                 priv->rx_queue[i]->dev = dev;
710                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
711         }
712
713
714         stash = of_get_property(np, "bd-stash", NULL);
715
716         if (stash) {
717                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
718                 priv->bd_stash_en = 1;
719         }
720
721         stash_len = of_get_property(np, "rx-stash-len", NULL);
722
723         if (stash_len)
724                 priv->rx_stash_size = *stash_len;
725
726         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
727
728         if (stash_idx)
729                 priv->rx_stash_index = *stash_idx;
730
731         if (stash_len || stash_idx)
732                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
733
734         mac_addr = of_get_mac_address(np);
735         if (mac_addr)
736                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
737
738         if (model && !strcasecmp(model, "TSEC"))
739                 priv->device_flags =
740                         FSL_GIANFAR_DEV_HAS_GIGABIT |
741                         FSL_GIANFAR_DEV_HAS_COALESCE |
742                         FSL_GIANFAR_DEV_HAS_RMON |
743                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
744         if (model && !strcasecmp(model, "eTSEC"))
745                 priv->device_flags =
746                         FSL_GIANFAR_DEV_HAS_GIGABIT |
747                         FSL_GIANFAR_DEV_HAS_COALESCE |
748                         FSL_GIANFAR_DEV_HAS_RMON |
749                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
750                         FSL_GIANFAR_DEV_HAS_PADDING |
751                         FSL_GIANFAR_DEV_HAS_CSUM |
752                         FSL_GIANFAR_DEV_HAS_VLAN |
753                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
754                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
755                         FSL_GIANFAR_DEV_HAS_TIMER;
756
757         ctype = of_get_property(np, "phy-connection-type", NULL);
758
759         /* We only care about rgmii-id.  The rest are autodetected */
760         if (ctype && !strcmp(ctype, "rgmii-id"))
761                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
762         else
763                 priv->interface = PHY_INTERFACE_MODE_MII;
764
765         if (of_get_property(np, "fsl,magic-packet", NULL))
766                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
767
768         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
769
770         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
771         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
772
773         return 0;
774
775 rx_alloc_failed:
776         free_rx_pointers(priv);
777 tx_alloc_failed:
778         free_tx_pointers(priv);
779 err_grp_init:
780         unmap_group_regs(priv);
781         free_netdev(dev);
782         return err;
783 }
784
785 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
786                         struct ifreq *ifr, int cmd)
787 {
788         struct hwtstamp_config config;
789         struct gfar_private *priv = netdev_priv(netdev);
790
791         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
792                 return -EFAULT;
793
794         /* reserved for future extensions */
795         if (config.flags)
796                 return -EINVAL;
797
798         switch (config.tx_type) {
799         case HWTSTAMP_TX_OFF:
800                 priv->hwts_tx_en = 0;
801                 break;
802         case HWTSTAMP_TX_ON:
803                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
804                         return -ERANGE;
805                 priv->hwts_tx_en = 1;
806                 break;
807         default:
808                 return -ERANGE;
809         }
810
811         switch (config.rx_filter) {
812         case HWTSTAMP_FILTER_NONE:
813                 if (priv->hwts_rx_en) {
814                         stop_gfar(netdev);
815                         priv->hwts_rx_en = 0;
816                         startup_gfar(netdev);
817                 }
818                 break;
819         default:
820                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
821                         return -ERANGE;
822                 if (!priv->hwts_rx_en) {
823                         stop_gfar(netdev);
824                         priv->hwts_rx_en = 1;
825                         startup_gfar(netdev);
826                 }
827                 config.rx_filter = HWTSTAMP_FILTER_ALL;
828                 break;
829         }
830
831         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
832                 -EFAULT : 0;
833 }
834
835 /* Ioctl MII Interface */
836 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
837 {
838         struct gfar_private *priv = netdev_priv(dev);
839
840         if (!netif_running(dev))
841                 return -EINVAL;
842
843         if (cmd == SIOCSHWTSTAMP)
844                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
845
846         if (!priv->phydev)
847                 return -ENODEV;
848
849         return phy_mii_ioctl(priv->phydev, rq, cmd);
850 }
851
852 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
853 {
854         unsigned int new_bit_map = 0x0;
855         int mask = 0x1 << (max_qs - 1), i;
856         for (i = 0; i < max_qs; i++) {
857                 if (bit_map & mask)
858                         new_bit_map = new_bit_map + (1 << i);
859                 mask = mask >> 0x1;
860         }
861         return new_bit_map;
862 }
863
864 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
865                                    u32 class)
866 {
867         u32 rqfpr = FPR_FILER_MASK;
868         u32 rqfcr = 0x0;
869
870         rqfar--;
871         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
872         priv->ftp_rqfpr[rqfar] = rqfpr;
873         priv->ftp_rqfcr[rqfar] = rqfcr;
874         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
875
876         rqfar--;
877         rqfcr = RQFCR_CMP_NOMATCH;
878         priv->ftp_rqfpr[rqfar] = rqfpr;
879         priv->ftp_rqfcr[rqfar] = rqfcr;
880         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
881
882         rqfar--;
883         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
884         rqfpr = class;
885         priv->ftp_rqfcr[rqfar] = rqfcr;
886         priv->ftp_rqfpr[rqfar] = rqfpr;
887         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
888
889         rqfar--;
890         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
891         rqfpr = class;
892         priv->ftp_rqfcr[rqfar] = rqfcr;
893         priv->ftp_rqfpr[rqfar] = rqfpr;
894         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
895
896         return rqfar;
897 }
898
899 static void gfar_init_filer_table(struct gfar_private *priv)
900 {
901         int i = 0x0;
902         u32 rqfar = MAX_FILER_IDX;
903         u32 rqfcr = 0x0;
904         u32 rqfpr = FPR_FILER_MASK;
905
906         /* Default rule */
907         rqfcr = RQFCR_CMP_MATCH;
908         priv->ftp_rqfcr[rqfar] = rqfcr;
909         priv->ftp_rqfpr[rqfar] = rqfpr;
910         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
911
912         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
913         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
914         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
915         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
916         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
917         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
918
919         /* cur_filer_idx indicated the first non-masked rule */
920         priv->cur_filer_idx = rqfar;
921
922         /* Rest are masked rules */
923         rqfcr = RQFCR_CMP_NOMATCH;
924         for (i = 0; i < rqfar; i++) {
925                 priv->ftp_rqfcr[i] = rqfcr;
926                 priv->ftp_rqfpr[i] = rqfpr;
927                 gfar_write_filer(priv, i, rqfcr, rqfpr);
928         }
929 }
930
931 static void gfar_detect_errata(struct gfar_private *priv)
932 {
933         struct device *dev = &priv->ofdev->dev;
934         unsigned int pvr = mfspr(SPRN_PVR);
935         unsigned int svr = mfspr(SPRN_SVR);
936         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
937         unsigned int rev = svr & 0xffff;
938
939         /* MPC8313 Rev 2.0 and higher; All MPC837x */
940         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
941                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
942                 priv->errata |= GFAR_ERRATA_74;
943
944         /* MPC8313 and MPC837x all rev */
945         if ((pvr == 0x80850010 && mod == 0x80b0) ||
946                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
947                 priv->errata |= GFAR_ERRATA_76;
948
949         /* MPC8313 and MPC837x all rev */
950         if ((pvr == 0x80850010 && mod == 0x80b0) ||
951                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
952                 priv->errata |= GFAR_ERRATA_A002;
953
954         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
955         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
956                         (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
957                 priv->errata |= GFAR_ERRATA_12;
958
959         if (priv->errata)
960                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
961                          priv->errata);
962 }
963
964 /* Set up the ethernet device structure, private data,
965  * and anything else we need before we start */
966 static int gfar_probe(struct platform_device *ofdev)
967 {
968         u32 tempval;
969         struct net_device *dev = NULL;
970         struct gfar_private *priv = NULL;
971         struct gfar __iomem *regs = NULL;
972         int err = 0, i, grp_idx = 0;
973         int len_devname;
974         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
975         u32 isrg = 0;
976         u32 __iomem *baddr;
977
978         err = gfar_of_init(ofdev, &dev);
979
980         if (err)
981                 return err;
982
983         priv = netdev_priv(dev);
984         priv->ndev = dev;
985         priv->ofdev = ofdev;
986         priv->node = ofdev->dev.of_node;
987         SET_NETDEV_DEV(dev, &ofdev->dev);
988
989         spin_lock_init(&priv->bflock);
990         INIT_WORK(&priv->reset_task, gfar_reset_task);
991
992         dev_set_drvdata(&ofdev->dev, priv);
993         regs = priv->gfargrp[0].regs;
994
995         gfar_detect_errata(priv);
996
997         /* Stop the DMA engine now, in case it was running before */
998         /* (The firmware could have used it, and left it running). */
999         gfar_halt(dev);
1000
1001         /* Reset MAC layer */
1002         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1003
1004         /* We need to delay at least 3 TX clocks */
1005         udelay(2);
1006
1007         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1008         gfar_write(&regs->maccfg1, tempval);
1009
1010         /* Initialize MACCFG2. */
1011         tempval = MACCFG2_INIT_SETTINGS;
1012         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1013                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1014         gfar_write(&regs->maccfg2, tempval);
1015
1016         /* Initialize ECNTRL */
1017         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1018
1019         /* Set the dev->base_addr to the gfar reg region */
1020         dev->base_addr = (unsigned long) regs;
1021
1022         SET_NETDEV_DEV(dev, &ofdev->dev);
1023
1024         /* Fill in the dev structure */
1025         dev->watchdog_timeo = TX_TIMEOUT;
1026         dev->mtu = 1500;
1027         dev->netdev_ops = &gfar_netdev_ops;
1028         dev->ethtool_ops = &gfar_ethtool_ops;
1029
1030         /* Register for napi ...We are registering NAPI for each grp */
1031         for (i = 0; i < priv->num_grps; i++)
1032                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
1033
1034         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1035                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1036                         NETIF_F_RXCSUM;
1037                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1038                         NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1039         }
1040
1041         priv->vlgrp = NULL;
1042
1043         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
1044                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1045
1046         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1047                 priv->extended_hash = 1;
1048                 priv->hash_width = 9;
1049
1050                 priv->hash_regs[0] = &regs->igaddr0;
1051                 priv->hash_regs[1] = &regs->igaddr1;
1052                 priv->hash_regs[2] = &regs->igaddr2;
1053                 priv->hash_regs[3] = &regs->igaddr3;
1054                 priv->hash_regs[4] = &regs->igaddr4;
1055                 priv->hash_regs[5] = &regs->igaddr5;
1056                 priv->hash_regs[6] = &regs->igaddr6;
1057                 priv->hash_regs[7] = &regs->igaddr7;
1058                 priv->hash_regs[8] = &regs->gaddr0;
1059                 priv->hash_regs[9] = &regs->gaddr1;
1060                 priv->hash_regs[10] = &regs->gaddr2;
1061                 priv->hash_regs[11] = &regs->gaddr3;
1062                 priv->hash_regs[12] = &regs->gaddr4;
1063                 priv->hash_regs[13] = &regs->gaddr5;
1064                 priv->hash_regs[14] = &regs->gaddr6;
1065                 priv->hash_regs[15] = &regs->gaddr7;
1066
1067         } else {
1068                 priv->extended_hash = 0;
1069                 priv->hash_width = 8;
1070
1071                 priv->hash_regs[0] = &regs->gaddr0;
1072                 priv->hash_regs[1] = &regs->gaddr1;
1073                 priv->hash_regs[2] = &regs->gaddr2;
1074                 priv->hash_regs[3] = &regs->gaddr3;
1075                 priv->hash_regs[4] = &regs->gaddr4;
1076                 priv->hash_regs[5] = &regs->gaddr5;
1077                 priv->hash_regs[6] = &regs->gaddr6;
1078                 priv->hash_regs[7] = &regs->gaddr7;
1079         }
1080
1081         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1082                 priv->padding = DEFAULT_PADDING;
1083         else
1084                 priv->padding = 0;
1085
1086         if (dev->features & NETIF_F_IP_CSUM ||
1087                         priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1088                 dev->hard_header_len += GMAC_FCB_LEN;
1089
1090         /* Program the isrg regs only if number of grps > 1 */
1091         if (priv->num_grps > 1) {
1092                 baddr = &regs->isrg0;
1093                 for (i = 0; i < priv->num_grps; i++) {
1094                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1095                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1096                         gfar_write(baddr, isrg);
1097                         baddr++;
1098                         isrg = 0x0;
1099                 }
1100         }
1101
1102         /* Need to reverse the bit maps as  bit_map's MSB is q0
1103          * but, for_each_set_bit parses from right to left, which
1104          * basically reverses the queue numbers */
1105         for (i = 0; i< priv->num_grps; i++) {
1106                 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1107                                 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1108                 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1109                                 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1110         }
1111
1112         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1113          * also assign queues to groups */
1114         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1115                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1116                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1117                                 priv->num_rx_queues) {
1118                         priv->gfargrp[grp_idx].num_rx_queues++;
1119                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1120                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1121                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1122                 }
1123                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1124                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1125                                 priv->num_tx_queues) {
1126                         priv->gfargrp[grp_idx].num_tx_queues++;
1127                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1128                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1129                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1130                 }
1131                 priv->gfargrp[grp_idx].rstat = rstat;
1132                 priv->gfargrp[grp_idx].tstat = tstat;
1133                 rstat = tstat =0;
1134         }
1135
1136         gfar_write(&regs->rqueue, rqueue);
1137         gfar_write(&regs->tqueue, tqueue);
1138
1139         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1140
1141         /* Initializing some of the rx/tx queue level parameters */
1142         for (i = 0; i < priv->num_tx_queues; i++) {
1143                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1144                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1145                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1146                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1147         }
1148
1149         for (i = 0; i < priv->num_rx_queues; i++) {
1150                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1151                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1152                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1153         }
1154
1155         /* always enable rx filer*/
1156         priv->rx_filer_enable = 1;
1157         /* Enable most messages by default */
1158         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1159
1160         /* Carrier starts down, phylib will bring it up */
1161         netif_carrier_off(dev);
1162
1163         err = register_netdev(dev);
1164
1165         if (err) {
1166                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1167                 goto register_fail;
1168         }
1169
1170         device_init_wakeup(&dev->dev,
1171                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1172
1173         /* fill out IRQ number and name fields */
1174         len_devname = strlen(dev->name);
1175         for (i = 0; i < priv->num_grps; i++) {
1176                 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1177                                 len_devname);
1178                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1179                         strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1180                                 "_g", sizeof("_g"));
1181                         priv->gfargrp[i].int_name_tx[
1182                                 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1183                         strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1184                                 priv->gfargrp[i].int_name_tx)],
1185                                 "_tx", sizeof("_tx") + 1);
1186
1187                         strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1188                                         len_devname);
1189                         strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1190                                         "_g", sizeof("_g"));
1191                         priv->gfargrp[i].int_name_rx[
1192                                 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1193                         strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1194                                 priv->gfargrp[i].int_name_rx)],
1195                                 "_rx", sizeof("_rx") + 1);
1196
1197                         strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1198                                         len_devname);
1199                         strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1200                                 "_g", sizeof("_g"));
1201                         priv->gfargrp[i].int_name_er[strlen(
1202                                         priv->gfargrp[i].int_name_er)] = i+48;
1203                         strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1204                                 priv->gfargrp[i].int_name_er)],
1205                                 "_er", sizeof("_er") + 1);
1206                 } else
1207                         priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1208         }
1209
1210         /* Initialize the filer table */
1211         gfar_init_filer_table(priv);
1212
1213         /* Create all the sysfs files */
1214         gfar_init_sysfs(dev);
1215
1216         /* Print out the device info */
1217         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1218
1219         /* Even more device info helps when determining which kernel */
1220         /* provided which set of benchmarks. */
1221         netdev_info(dev, "Running with NAPI enabled\n");
1222         for (i = 0; i < priv->num_rx_queues; i++)
1223                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1224                             i, priv->rx_queue[i]->rx_ring_size);
1225         for(i = 0; i < priv->num_tx_queues; i++)
1226                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1227                             i, priv->tx_queue[i]->tx_ring_size);
1228
1229         return 0;
1230
1231 register_fail:
1232         unmap_group_regs(priv);
1233         free_tx_pointers(priv);
1234         free_rx_pointers(priv);
1235         if (priv->phy_node)
1236                 of_node_put(priv->phy_node);
1237         if (priv->tbi_node)
1238                 of_node_put(priv->tbi_node);
1239         free_netdev(dev);
1240         return err;
1241 }
1242
1243 static int gfar_remove(struct platform_device *ofdev)
1244 {
1245         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1246
1247         if (priv->phy_node)
1248                 of_node_put(priv->phy_node);
1249         if (priv->tbi_node)
1250                 of_node_put(priv->tbi_node);
1251
1252         dev_set_drvdata(&ofdev->dev, NULL);
1253
1254         unregister_netdev(priv->ndev);
1255         unmap_group_regs(priv);
1256         free_netdev(priv->ndev);
1257
1258         return 0;
1259 }
1260
1261 #ifdef CONFIG_PM
1262
1263 static int gfar_suspend(struct device *dev)
1264 {
1265         struct gfar_private *priv = dev_get_drvdata(dev);
1266         struct net_device *ndev = priv->ndev;
1267         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1268         unsigned long flags;
1269         u32 tempval;
1270
1271         int magic_packet = priv->wol_en &&
1272                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1273
1274         netif_device_detach(ndev);
1275
1276         if (netif_running(ndev)) {
1277
1278                 local_irq_save(flags);
1279                 lock_tx_qs(priv);
1280                 lock_rx_qs(priv);
1281
1282                 gfar_halt_nodisable(ndev);
1283
1284                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1285                 tempval = gfar_read(&regs->maccfg1);
1286
1287                 tempval &= ~MACCFG1_TX_EN;
1288
1289                 if (!magic_packet)
1290                         tempval &= ~MACCFG1_RX_EN;
1291
1292                 gfar_write(&regs->maccfg1, tempval);
1293
1294                 unlock_rx_qs(priv);
1295                 unlock_tx_qs(priv);
1296                 local_irq_restore(flags);
1297
1298                 disable_napi(priv);
1299
1300                 if (magic_packet) {
1301                         /* Enable interrupt on Magic Packet */
1302                         gfar_write(&regs->imask, IMASK_MAG);
1303
1304                         /* Enable Magic Packet mode */
1305                         tempval = gfar_read(&regs->maccfg2);
1306                         tempval |= MACCFG2_MPEN;
1307                         gfar_write(&regs->maccfg2, tempval);
1308                 } else {
1309                         phy_stop(priv->phydev);
1310                 }
1311         }
1312
1313         return 0;
1314 }
1315
1316 static int gfar_resume(struct device *dev)
1317 {
1318         struct gfar_private *priv = dev_get_drvdata(dev);
1319         struct net_device *ndev = priv->ndev;
1320         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1321         unsigned long flags;
1322         u32 tempval;
1323         int magic_packet = priv->wol_en &&
1324                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1325
1326         if (!netif_running(ndev)) {
1327                 netif_device_attach(ndev);
1328                 return 0;
1329         }
1330
1331         if (!magic_packet && priv->phydev)
1332                 phy_start(priv->phydev);
1333
1334         /* Disable Magic Packet mode, in case something
1335          * else woke us up.
1336          */
1337         local_irq_save(flags);
1338         lock_tx_qs(priv);
1339         lock_rx_qs(priv);
1340
1341         tempval = gfar_read(&regs->maccfg2);
1342         tempval &= ~MACCFG2_MPEN;
1343         gfar_write(&regs->maccfg2, tempval);
1344
1345         gfar_start(ndev);
1346
1347         unlock_rx_qs(priv);
1348         unlock_tx_qs(priv);
1349         local_irq_restore(flags);
1350
1351         netif_device_attach(ndev);
1352
1353         enable_napi(priv);
1354
1355         return 0;
1356 }
1357
1358 static int gfar_restore(struct device *dev)
1359 {
1360         struct gfar_private *priv = dev_get_drvdata(dev);
1361         struct net_device *ndev = priv->ndev;
1362
1363         if (!netif_running(ndev))
1364                 return 0;
1365
1366         gfar_init_bds(ndev);
1367         init_registers(ndev);
1368         gfar_set_mac_address(ndev);
1369         gfar_init_mac(ndev);
1370         gfar_start(ndev);
1371
1372         priv->oldlink = 0;
1373         priv->oldspeed = 0;
1374         priv->oldduplex = -1;
1375
1376         if (priv->phydev)
1377                 phy_start(priv->phydev);
1378
1379         netif_device_attach(ndev);
1380         enable_napi(priv);
1381
1382         return 0;
1383 }
1384
1385 static struct dev_pm_ops gfar_pm_ops = {
1386         .suspend = gfar_suspend,
1387         .resume = gfar_resume,
1388         .freeze = gfar_suspend,
1389         .thaw = gfar_resume,
1390         .restore = gfar_restore,
1391 };
1392
1393 #define GFAR_PM_OPS (&gfar_pm_ops)
1394
1395 #else
1396
1397 #define GFAR_PM_OPS NULL
1398
1399 #endif
1400
1401 /* Reads the controller's registers to determine what interface
1402  * connects it to the PHY.
1403  */
1404 static phy_interface_t gfar_get_interface(struct net_device *dev)
1405 {
1406         struct gfar_private *priv = netdev_priv(dev);
1407         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1408         u32 ecntrl;
1409
1410         ecntrl = gfar_read(&regs->ecntrl);
1411
1412         if (ecntrl & ECNTRL_SGMII_MODE)
1413                 return PHY_INTERFACE_MODE_SGMII;
1414
1415         if (ecntrl & ECNTRL_TBI_MODE) {
1416                 if (ecntrl & ECNTRL_REDUCED_MODE)
1417                         return PHY_INTERFACE_MODE_RTBI;
1418                 else
1419                         return PHY_INTERFACE_MODE_TBI;
1420         }
1421
1422         if (ecntrl & ECNTRL_REDUCED_MODE) {
1423                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1424                         return PHY_INTERFACE_MODE_RMII;
1425                 else {
1426                         phy_interface_t interface = priv->interface;
1427
1428                         /*
1429                          * This isn't autodetected right now, so it must
1430                          * be set by the device tree or platform code.
1431                          */
1432                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1433                                 return PHY_INTERFACE_MODE_RGMII_ID;
1434
1435                         return PHY_INTERFACE_MODE_RGMII;
1436                 }
1437         }
1438
1439         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1440                 return PHY_INTERFACE_MODE_GMII;
1441
1442         return PHY_INTERFACE_MODE_MII;
1443 }
1444
1445
1446 /* Initializes driver's PHY state, and attaches to the PHY.
1447  * Returns 0 on success.
1448  */
1449 static int init_phy(struct net_device *dev)
1450 {
1451         struct gfar_private *priv = netdev_priv(dev);
1452         uint gigabit_support =
1453                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1454                 SUPPORTED_1000baseT_Full : 0;
1455         phy_interface_t interface;
1456
1457         priv->oldlink = 0;
1458         priv->oldspeed = 0;
1459         priv->oldduplex = -1;
1460
1461         interface = gfar_get_interface(dev);
1462
1463         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1464                                       interface);
1465         if (!priv->phydev)
1466                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1467                                                          interface);
1468         if (!priv->phydev) {
1469                 dev_err(&dev->dev, "could not attach to PHY\n");
1470                 return -ENODEV;
1471         }
1472
1473         if (interface == PHY_INTERFACE_MODE_SGMII)
1474                 gfar_configure_serdes(dev);
1475
1476         /* Remove any features not supported by the controller */
1477         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1478         priv->phydev->advertising = priv->phydev->supported;
1479
1480         return 0;
1481 }
1482
1483 /*
1484  * Initialize TBI PHY interface for communicating with the
1485  * SERDES lynx PHY on the chip.  We communicate with this PHY
1486  * through the MDIO bus on each controller, treating it as a
1487  * "normal" PHY at the address found in the TBIPA register.  We assume
1488  * that the TBIPA register is valid.  Either the MDIO bus code will set
1489  * it to a value that doesn't conflict with other PHYs on the bus, or the
1490  * value doesn't matter, as there are no other PHYs on the bus.
1491  */
1492 static void gfar_configure_serdes(struct net_device *dev)
1493 {
1494         struct gfar_private *priv = netdev_priv(dev);
1495         struct phy_device *tbiphy;
1496
1497         if (!priv->tbi_node) {
1498                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1499                                     "device tree specify a tbi-handle\n");
1500                 return;
1501         }
1502
1503         tbiphy = of_phy_find_device(priv->tbi_node);
1504         if (!tbiphy) {
1505                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1506                 return;
1507         }
1508
1509         /*
1510          * If the link is already up, we must already be ok, and don't need to
1511          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1512          * everything for us?  Resetting it takes the link down and requires
1513          * several seconds for it to come back.
1514          */
1515         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1516                 return;
1517
1518         /* Single clk mode, mii mode off(for serdes communication) */
1519         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1520
1521         phy_write(tbiphy, MII_ADVERTISE,
1522                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1523                         ADVERTISE_1000XPSE_ASYM);
1524
1525         phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1526                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1527 }
1528
1529 static void init_registers(struct net_device *dev)
1530 {
1531         struct gfar_private *priv = netdev_priv(dev);
1532         struct gfar __iomem *regs = NULL;
1533         int i = 0;
1534
1535         for (i = 0; i < priv->num_grps; i++) {
1536                 regs = priv->gfargrp[i].regs;
1537                 /* Clear IEVENT */
1538                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1539
1540                 /* Initialize IMASK */
1541                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1542         }
1543
1544         regs = priv->gfargrp[0].regs;
1545         /* Init hash registers to zero */
1546         gfar_write(&regs->igaddr0, 0);
1547         gfar_write(&regs->igaddr1, 0);
1548         gfar_write(&regs->igaddr2, 0);
1549         gfar_write(&regs->igaddr3, 0);
1550         gfar_write(&regs->igaddr4, 0);
1551         gfar_write(&regs->igaddr5, 0);
1552         gfar_write(&regs->igaddr6, 0);
1553         gfar_write(&regs->igaddr7, 0);
1554
1555         gfar_write(&regs->gaddr0, 0);
1556         gfar_write(&regs->gaddr1, 0);
1557         gfar_write(&regs->gaddr2, 0);
1558         gfar_write(&regs->gaddr3, 0);
1559         gfar_write(&regs->gaddr4, 0);
1560         gfar_write(&regs->gaddr5, 0);
1561         gfar_write(&regs->gaddr6, 0);
1562         gfar_write(&regs->gaddr7, 0);
1563
1564         /* Zero out the rmon mib registers if it has them */
1565         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1566                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1567
1568                 /* Mask off the CAM interrupts */
1569                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1570                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1571         }
1572
1573         /* Initialize the max receive buffer length */
1574         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1575
1576         /* Initialize the Minimum Frame Length Register */
1577         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1578 }
1579
1580 static int __gfar_is_rx_idle(struct gfar_private *priv)
1581 {
1582         u32 res;
1583
1584         /*
1585          * Normaly TSEC should not hang on GRS commands, so we should
1586          * actually wait for IEVENT_GRSC flag.
1587          */
1588         if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1589                 return 0;
1590
1591         /*
1592          * Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1593          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1594          * and the Rx can be safely reset.
1595          */
1596         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1597         res &= 0x7f807f80;
1598         if ((res & 0xffff) == (res >> 16))
1599                 return 1;
1600
1601         return 0;
1602 }
1603
1604 /* Halt the receive and transmit queues */
1605 static void gfar_halt_nodisable(struct net_device *dev)
1606 {
1607         struct gfar_private *priv = netdev_priv(dev);
1608         struct gfar __iomem *regs = NULL;
1609         u32 tempval;
1610         int i = 0;
1611
1612         for (i = 0; i < priv->num_grps; i++) {
1613                 regs = priv->gfargrp[i].regs;
1614                 /* Mask all interrupts */
1615                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1616
1617                 /* Clear all interrupts */
1618                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1619         }
1620
1621         regs = priv->gfargrp[0].regs;
1622         /* Stop the DMA, and wait for it to stop */
1623         tempval = gfar_read(&regs->dmactrl);
1624         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1625             != (DMACTRL_GRS | DMACTRL_GTS)) {
1626                 int ret;
1627
1628                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1629                 gfar_write(&regs->dmactrl, tempval);
1630
1631                 do {
1632                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1633                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1634                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1635                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1636                                 ret = __gfar_is_rx_idle(priv);
1637                 } while (!ret);
1638         }
1639 }
1640
1641 /* Halt the receive and transmit queues */
1642 void gfar_halt(struct net_device *dev)
1643 {
1644         struct gfar_private *priv = netdev_priv(dev);
1645         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1646         u32 tempval;
1647
1648         gfar_halt_nodisable(dev);
1649
1650         /* Disable Rx and Tx */
1651         tempval = gfar_read(&regs->maccfg1);
1652         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1653         gfar_write(&regs->maccfg1, tempval);
1654 }
1655
1656 static void free_grp_irqs(struct gfar_priv_grp *grp)
1657 {
1658         free_irq(grp->interruptError, grp);
1659         free_irq(grp->interruptTransmit, grp);
1660         free_irq(grp->interruptReceive, grp);
1661 }
1662
1663 void stop_gfar(struct net_device *dev)
1664 {
1665         struct gfar_private *priv = netdev_priv(dev);
1666         unsigned long flags;
1667         int i;
1668
1669         phy_stop(priv->phydev);
1670
1671
1672         /* Lock it down */
1673         local_irq_save(flags);
1674         lock_tx_qs(priv);
1675         lock_rx_qs(priv);
1676
1677         gfar_halt(dev);
1678
1679         unlock_rx_qs(priv);
1680         unlock_tx_qs(priv);
1681         local_irq_restore(flags);
1682
1683         /* Free the IRQs */
1684         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1685                 for (i = 0; i < priv->num_grps; i++)
1686                         free_grp_irqs(&priv->gfargrp[i]);
1687         } else {
1688                 for (i = 0; i < priv->num_grps; i++)
1689                         free_irq(priv->gfargrp[i].interruptTransmit,
1690                                         &priv->gfargrp[i]);
1691         }
1692
1693         free_skb_resources(priv);
1694 }
1695
1696 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1697 {
1698         struct txbd8 *txbdp;
1699         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1700         int i, j;
1701
1702         txbdp = tx_queue->tx_bd_base;
1703
1704         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1705                 if (!tx_queue->tx_skbuff[i])
1706                         continue;
1707
1708                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1709                                 txbdp->length, DMA_TO_DEVICE);
1710                 txbdp->lstatus = 0;
1711                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1712                                 j++) {
1713                         txbdp++;
1714                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1715                                         txbdp->length, DMA_TO_DEVICE);
1716                 }
1717                 txbdp++;
1718                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1719                 tx_queue->tx_skbuff[i] = NULL;
1720         }
1721         kfree(tx_queue->tx_skbuff);
1722 }
1723
1724 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1725 {
1726         struct rxbd8 *rxbdp;
1727         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1728         int i;
1729
1730         rxbdp = rx_queue->rx_bd_base;
1731
1732         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1733                 if (rx_queue->rx_skbuff[i]) {
1734                         dma_unmap_single(&priv->ofdev->dev,
1735                                         rxbdp->bufPtr, priv->rx_buffer_size,
1736                                         DMA_FROM_DEVICE);
1737                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1738                         rx_queue->rx_skbuff[i] = NULL;
1739                 }
1740                 rxbdp->lstatus = 0;
1741                 rxbdp->bufPtr = 0;
1742                 rxbdp++;
1743         }
1744         kfree(rx_queue->rx_skbuff);
1745 }
1746
1747 /* If there are any tx skbs or rx skbs still around, free them.
1748  * Then free tx_skbuff and rx_skbuff */
1749 static void free_skb_resources(struct gfar_private *priv)
1750 {
1751         struct gfar_priv_tx_q *tx_queue = NULL;
1752         struct gfar_priv_rx_q *rx_queue = NULL;
1753         int i;
1754
1755         /* Go through all the buffer descriptors and free their data buffers */
1756         for (i = 0; i < priv->num_tx_queues; i++) {
1757                 tx_queue = priv->tx_queue[i];
1758                 if(tx_queue->tx_skbuff)
1759                         free_skb_tx_queue(tx_queue);
1760         }
1761
1762         for (i = 0; i < priv->num_rx_queues; i++) {
1763                 rx_queue = priv->rx_queue[i];
1764                 if(rx_queue->rx_skbuff)
1765                         free_skb_rx_queue(rx_queue);
1766         }
1767
1768         dma_free_coherent(&priv->ofdev->dev,
1769                         sizeof(struct txbd8) * priv->total_tx_ring_size +
1770                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
1771                         priv->tx_queue[0]->tx_bd_base,
1772                         priv->tx_queue[0]->tx_bd_dma_base);
1773         skb_queue_purge(&priv->rx_recycle);
1774 }
1775
1776 void gfar_start(struct net_device *dev)
1777 {
1778         struct gfar_private *priv = netdev_priv(dev);
1779         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1780         u32 tempval;
1781         int i = 0;
1782
1783         /* Enable Rx and Tx in MACCFG1 */
1784         tempval = gfar_read(&regs->maccfg1);
1785         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1786         gfar_write(&regs->maccfg1, tempval);
1787
1788         /* Initialize DMACTRL to have WWR and WOP */
1789         tempval = gfar_read(&regs->dmactrl);
1790         tempval |= DMACTRL_INIT_SETTINGS;
1791         gfar_write(&regs->dmactrl, tempval);
1792
1793         /* Make sure we aren't stopped */
1794         tempval = gfar_read(&regs->dmactrl);
1795         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1796         gfar_write(&regs->dmactrl, tempval);
1797
1798         for (i = 0; i < priv->num_grps; i++) {
1799                 regs = priv->gfargrp[i].regs;
1800                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1801                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1802                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1803                 /* Unmask the interrupts we look for */
1804                 gfar_write(&regs->imask, IMASK_DEFAULT);
1805         }
1806
1807         dev->trans_start = jiffies; /* prevent tx timeout */
1808 }
1809
1810 void gfar_configure_coalescing(struct gfar_private *priv,
1811         unsigned long tx_mask, unsigned long rx_mask)
1812 {
1813         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1814         u32 __iomem *baddr;
1815         int i = 0;
1816
1817         /* Backward compatible case ---- even if we enable
1818          * multiple queues, there's only single reg to program
1819          */
1820         gfar_write(&regs->txic, 0);
1821         if(likely(priv->tx_queue[0]->txcoalescing))
1822                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1823
1824         gfar_write(&regs->rxic, 0);
1825         if(unlikely(priv->rx_queue[0]->rxcoalescing))
1826                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1827
1828         if (priv->mode == MQ_MG_MODE) {
1829                 baddr = &regs->txic0;
1830                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1831                         if (likely(priv->tx_queue[i]->txcoalescing)) {
1832                                 gfar_write(baddr + i, 0);
1833                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1834                         }
1835                 }
1836
1837                 baddr = &regs->rxic0;
1838                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1839                         if (likely(priv->rx_queue[i]->rxcoalescing)) {
1840                                 gfar_write(baddr + i, 0);
1841                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1842                         }
1843                 }
1844         }
1845 }
1846
1847 static int register_grp_irqs(struct gfar_priv_grp *grp)
1848 {
1849         struct gfar_private *priv = grp->priv;
1850         struct net_device *dev = priv->ndev;
1851         int err;
1852
1853         /* If the device has multiple interrupts, register for
1854          * them.  Otherwise, only register for the one */
1855         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1856                 /* Install our interrupt handlers for Error,
1857                  * Transmit, and Receive */
1858                 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1859                                 grp->int_name_er,grp)) < 0) {
1860                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1861                                   grp->interruptError);
1862
1863                         goto err_irq_fail;
1864                 }
1865
1866                 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1867                                 0, grp->int_name_tx, grp)) < 0) {
1868                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1869                                   grp->interruptTransmit);
1870                         goto tx_irq_fail;
1871                 }
1872
1873                 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1874                                 grp->int_name_rx, grp)) < 0) {
1875                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1876                                   grp->interruptReceive);
1877                         goto rx_irq_fail;
1878                 }
1879         } else {
1880                 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1881                                 grp->int_name_tx, grp)) < 0) {
1882                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1883                                   grp->interruptTransmit);
1884                         goto err_irq_fail;
1885                 }
1886         }
1887
1888         return 0;
1889
1890 rx_irq_fail:
1891         free_irq(grp->interruptTransmit, grp);
1892 tx_irq_fail:
1893         free_irq(grp->interruptError, grp);
1894 err_irq_fail:
1895         return err;
1896
1897 }
1898
1899 /* Bring the controller up and running */
1900 int startup_gfar(struct net_device *ndev)
1901 {
1902         struct gfar_private *priv = netdev_priv(ndev);
1903         struct gfar __iomem *regs = NULL;
1904         int err, i, j;
1905
1906         for (i = 0; i < priv->num_grps; i++) {
1907                 regs= priv->gfargrp[i].regs;
1908                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1909         }
1910
1911         regs= priv->gfargrp[0].regs;
1912         err = gfar_alloc_skb_resources(ndev);
1913         if (err)
1914                 return err;
1915
1916         gfar_init_mac(ndev);
1917
1918         for (i = 0; i < priv->num_grps; i++) {
1919                 err = register_grp_irqs(&priv->gfargrp[i]);
1920                 if (err) {
1921                         for (j = 0; j < i; j++)
1922                                 free_grp_irqs(&priv->gfargrp[j]);
1923                         goto irq_fail;
1924                 }
1925         }
1926
1927         /* Start the controller */
1928         gfar_start(ndev);
1929
1930         phy_start(priv->phydev);
1931
1932         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1933
1934         return 0;
1935
1936 irq_fail:
1937         free_skb_resources(priv);
1938         return err;
1939 }
1940
1941 /* Called when something needs to use the ethernet device */
1942 /* Returns 0 for success. */
1943 static int gfar_enet_open(struct net_device *dev)
1944 {
1945         struct gfar_private *priv = netdev_priv(dev);
1946         int err;
1947
1948         enable_napi(priv);
1949
1950         skb_queue_head_init(&priv->rx_recycle);
1951
1952         /* Initialize a bunch of registers */
1953         init_registers(dev);
1954
1955         gfar_set_mac_address(dev);
1956
1957         err = init_phy(dev);
1958
1959         if (err) {
1960                 disable_napi(priv);
1961                 return err;
1962         }
1963
1964         err = startup_gfar(dev);
1965         if (err) {
1966                 disable_napi(priv);
1967                 return err;
1968         }
1969
1970         netif_tx_start_all_queues(dev);
1971
1972         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1973
1974         return err;
1975 }
1976
1977 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1978 {
1979         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1980
1981         memset(fcb, 0, GMAC_FCB_LEN);
1982
1983         return fcb;
1984 }
1985
1986 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1987 {
1988         u8 flags = 0;
1989
1990         /* If we're here, it's a IP packet with a TCP or UDP
1991          * payload.  We set it to checksum, using a pseudo-header
1992          * we provide
1993          */
1994         flags = TXFCB_DEFAULT;
1995
1996         /* Tell the controller what the protocol is */
1997         /* And provide the already calculated phcs */
1998         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1999                 flags |= TXFCB_UDP;
2000                 fcb->phcs = udp_hdr(skb)->check;
2001         } else
2002                 fcb->phcs = tcp_hdr(skb)->check;
2003
2004         /* l3os is the distance between the start of the
2005          * frame (skb->data) and the start of the IP hdr.
2006          * l4os is the distance between the start of the
2007          * l3 hdr and the l4 hdr */
2008         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
2009         fcb->l4os = skb_network_header_len(skb);
2010
2011         fcb->flags = flags;
2012 }
2013
2014 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2015 {
2016         fcb->flags |= TXFCB_VLN;
2017         fcb->vlctl = vlan_tx_tag_get(skb);
2018 }
2019
2020 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2021                                struct txbd8 *base, int ring_size)
2022 {
2023         struct txbd8 *new_bd = bdp + stride;
2024
2025         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2026 }
2027
2028 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2029                 int ring_size)
2030 {
2031         return skip_txbd(bdp, 1, base, ring_size);
2032 }
2033
2034 /* This is called by the kernel when a frame is ready for transmission. */
2035 /* It is pointed to by the dev->hard_start_xmit function pointer */
2036 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2037 {
2038         struct gfar_private *priv = netdev_priv(dev);
2039         struct gfar_priv_tx_q *tx_queue = NULL;
2040         struct netdev_queue *txq;
2041         struct gfar __iomem *regs = NULL;
2042         struct txfcb *fcb = NULL;
2043         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2044         u32 lstatus;
2045         int i, rq = 0, do_tstamp = 0;
2046         u32 bufaddr;
2047         unsigned long flags;
2048         unsigned int nr_frags, nr_txbds, length;
2049
2050         /*
2051          * TOE=1 frames larger than 2500 bytes may see excess delays
2052          * before start of transmission.
2053          */
2054         if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2055                         skb->ip_summed == CHECKSUM_PARTIAL &&
2056                         skb->len > 2500)) {
2057                 int ret;
2058
2059                 ret = skb_checksum_help(skb);
2060                 if (ret)
2061                         return ret;
2062         }
2063
2064         rq = skb->queue_mapping;
2065         tx_queue = priv->tx_queue[rq];
2066         txq = netdev_get_tx_queue(dev, rq);
2067         base = tx_queue->tx_bd_base;
2068         regs = tx_queue->grp->regs;
2069
2070         /* check if time stamp should be generated */
2071         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2072                      priv->hwts_tx_en))
2073                 do_tstamp = 1;
2074
2075         /* make space for additional header when fcb is needed */
2076         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2077                         vlan_tx_tag_present(skb) ||
2078                         unlikely(do_tstamp)) &&
2079                         (skb_headroom(skb) < GMAC_FCB_LEN)) {
2080                 struct sk_buff *skb_new;
2081
2082                 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
2083                 if (!skb_new) {
2084                         dev->stats.tx_errors++;
2085                         kfree_skb(skb);
2086                         return NETDEV_TX_OK;
2087                 }
2088                 kfree_skb(skb);
2089                 skb = skb_new;
2090         }
2091
2092         /* total number of fragments in the SKB */
2093         nr_frags = skb_shinfo(skb)->nr_frags;
2094
2095         /* calculate the required number of TxBDs for this skb */
2096         if (unlikely(do_tstamp))
2097                 nr_txbds = nr_frags + 2;
2098         else
2099                 nr_txbds = nr_frags + 1;
2100
2101         /* check if there is space to queue this packet */
2102         if (nr_txbds > tx_queue->num_txbdfree) {
2103                 /* no space, stop the queue */
2104                 netif_tx_stop_queue(txq);
2105                 dev->stats.tx_fifo_errors++;
2106                 return NETDEV_TX_BUSY;
2107         }
2108
2109         /* Update transmit stats */
2110         tx_queue->stats.tx_bytes += skb->len;
2111         tx_queue->stats.tx_packets++;
2112
2113         txbdp = txbdp_start = tx_queue->cur_tx;
2114         lstatus = txbdp->lstatus;
2115
2116         /* Time stamp insertion requires one additional TxBD */
2117         if (unlikely(do_tstamp))
2118                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2119                                 tx_queue->tx_ring_size);
2120
2121         if (nr_frags == 0) {
2122                 if (unlikely(do_tstamp))
2123                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2124                                         TXBD_INTERRUPT);
2125                 else
2126                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2127         } else {
2128                 /* Place the fragment addresses and lengths into the TxBDs */
2129                 for (i = 0; i < nr_frags; i++) {
2130                         /* Point at the next BD, wrapping as needed */
2131                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2132
2133                         length = skb_shinfo(skb)->frags[i].size;
2134
2135                         lstatus = txbdp->lstatus | length |
2136                                 BD_LFLAG(TXBD_READY);
2137
2138                         /* Handle the last BD specially */
2139                         if (i == nr_frags - 1)
2140                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2141
2142                         bufaddr = dma_map_page(&priv->ofdev->dev,
2143                                         skb_shinfo(skb)->frags[i].page,
2144                                         skb_shinfo(skb)->frags[i].page_offset,
2145                                         length,
2146                                         DMA_TO_DEVICE);
2147
2148                         /* set the TxBD length and buffer pointer */
2149                         txbdp->bufPtr = bufaddr;
2150                         txbdp->lstatus = lstatus;
2151                 }
2152
2153                 lstatus = txbdp_start->lstatus;
2154         }
2155
2156         /* Set up checksumming */
2157         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2158                 fcb = gfar_add_fcb(skb);
2159                 /* as specified by errata */
2160                 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12)
2161                              && ((unsigned long)fcb % 0x20) > 0x18)) {
2162                         __skb_pull(skb, GMAC_FCB_LEN);
2163                         skb_checksum_help(skb);
2164                 } else {
2165                         lstatus |= BD_LFLAG(TXBD_TOE);
2166                         gfar_tx_checksum(skb, fcb);
2167                 }
2168         }
2169
2170         if (vlan_tx_tag_present(skb)) {
2171                 if (unlikely(NULL == fcb)) {
2172                         fcb = gfar_add_fcb(skb);
2173                         lstatus |= BD_LFLAG(TXBD_TOE);
2174                 }
2175
2176                 gfar_tx_vlan(skb, fcb);
2177         }
2178
2179         /* Setup tx hardware time stamping if requested */
2180         if (unlikely(do_tstamp)) {
2181                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2182                 if (fcb == NULL)
2183                         fcb = gfar_add_fcb(skb);
2184                 fcb->ptp = 1;
2185                 lstatus |= BD_LFLAG(TXBD_TOE);
2186         }
2187
2188         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2189                         skb_headlen(skb), DMA_TO_DEVICE);
2190
2191         /*
2192          * If time stamping is requested one additional TxBD must be set up. The
2193          * first TxBD points to the FCB and must have a data length of
2194          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2195          * the full frame length.
2196          */
2197         if (unlikely(do_tstamp)) {
2198                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2199                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2200                                 (skb_headlen(skb) - GMAC_FCB_LEN);
2201                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2202         } else {
2203                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2204         }
2205
2206         /*
2207          * We can work in parallel with gfar_clean_tx_ring(), except
2208          * when modifying num_txbdfree. Note that we didn't grab the lock
2209          * when we were reading the num_txbdfree and checking for available
2210          * space, that's because outside of this function it can only grow,
2211          * and once we've got needed space, it cannot suddenly disappear.
2212          *
2213          * The lock also protects us from gfar_error(), which can modify
2214          * regs->tstat and thus retrigger the transfers, which is why we
2215          * also must grab the lock before setting ready bit for the first
2216          * to be transmitted BD.
2217          */
2218         spin_lock_irqsave(&tx_queue->txlock, flags);
2219
2220         /*
2221          * The powerpc-specific eieio() is used, as wmb() has too strong
2222          * semantics (it requires synchronization between cacheable and
2223          * uncacheable mappings, which eieio doesn't provide and which we
2224          * don't need), thus requiring a more expensive sync instruction.  At
2225          * some point, the set of architecture-independent barrier functions
2226          * should be expanded to include weaker barriers.
2227          */
2228         eieio();
2229
2230         txbdp_start->lstatus = lstatus;
2231
2232         eieio(); /* force lstatus write before tx_skbuff */
2233
2234         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2235
2236         /* Update the current skb pointer to the next entry we will use
2237          * (wrapping if necessary) */
2238         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2239                 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2240
2241         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2242
2243         /* reduce TxBD free count */
2244         tx_queue->num_txbdfree -= (nr_txbds);
2245
2246         /* If the next BD still needs to be cleaned up, then the bds
2247            are full.  We need to tell the kernel to stop sending us stuff. */
2248         if (!tx_queue->num_txbdfree) {
2249                 netif_tx_stop_queue(txq);
2250
2251                 dev->stats.tx_fifo_errors++;
2252         }
2253
2254         /* Tell the DMA to go go go */
2255         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2256
2257         /* Unlock priv */
2258         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2259
2260         return NETDEV_TX_OK;
2261 }
2262
2263 /* Stops the kernel queue, and halts the controller */
2264 static int gfar_close(struct net_device *dev)
2265 {
2266         struct gfar_private *priv = netdev_priv(dev);
2267
2268         disable_napi(priv);
2269
2270         cancel_work_sync(&priv->reset_task);
2271         stop_gfar(dev);
2272
2273         /* Disconnect from the PHY */
2274         phy_disconnect(priv->phydev);
2275         priv->phydev = NULL;
2276
2277         netif_tx_stop_all_queues(dev);
2278
2279         return 0;
2280 }
2281
2282 /* Changes the mac address if the controller is not running. */
2283 static int gfar_set_mac_address(struct net_device *dev)
2284 {
2285         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2286
2287         return 0;
2288 }
2289
2290 /* Check if rx parser should be activated */
2291 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2292 {
2293         struct gfar __iomem *regs;
2294         u32 tempval;
2295
2296         regs = priv->gfargrp[0].regs;
2297
2298         tempval = gfar_read(&regs->rctrl);
2299         /* If parse is no longer required, then disable parser */
2300         if (tempval & RCTRL_REQ_PARSER)
2301                 tempval |= RCTRL_PRSDEP_INIT;
2302         else
2303                 tempval &= ~RCTRL_PRSDEP_INIT;
2304         gfar_write(&regs->rctrl, tempval);
2305 }
2306
2307
2308 /* Enables and disables VLAN insertion/extraction */
2309 static void gfar_vlan_rx_register(struct net_device *dev,
2310                 struct vlan_group *grp)
2311 {
2312         struct gfar_private *priv = netdev_priv(dev);
2313         struct gfar __iomem *regs = NULL;
2314         unsigned long flags;
2315         u32 tempval;
2316
2317         regs = priv->gfargrp[0].regs;
2318         local_irq_save(flags);
2319         lock_rx_qs(priv);
2320
2321         priv->vlgrp = grp;
2322
2323         if (grp) {
2324                 /* Enable VLAN tag insertion */
2325                 tempval = gfar_read(&regs->tctrl);
2326                 tempval |= TCTRL_VLINS;
2327
2328                 gfar_write(&regs->tctrl, tempval);
2329
2330                 /* Enable VLAN tag extraction */
2331                 tempval = gfar_read(&regs->rctrl);
2332                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2333                 gfar_write(&regs->rctrl, tempval);
2334         } else {
2335                 /* Disable VLAN tag insertion */
2336                 tempval = gfar_read(&regs->tctrl);
2337                 tempval &= ~TCTRL_VLINS;
2338                 gfar_write(&regs->tctrl, tempval);
2339
2340                 /* Disable VLAN tag extraction */
2341                 tempval = gfar_read(&regs->rctrl);
2342                 tempval &= ~RCTRL_VLEX;
2343                 gfar_write(&regs->rctrl, tempval);
2344
2345                 gfar_check_rx_parser_mode(priv);
2346         }
2347
2348         gfar_change_mtu(dev, dev->mtu);
2349
2350         unlock_rx_qs(priv);
2351         local_irq_restore(flags);
2352 }
2353
2354 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2355 {
2356         int tempsize, tempval;
2357         struct gfar_private *priv = netdev_priv(dev);
2358         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2359         int oldsize = priv->rx_buffer_size;
2360         int frame_size = new_mtu + ETH_HLEN;
2361
2362         if (priv->vlgrp)
2363                 frame_size += VLAN_HLEN;
2364
2365         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2366                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2367                 return -EINVAL;
2368         }
2369
2370         if (gfar_uses_fcb(priv))
2371                 frame_size += GMAC_FCB_LEN;
2372
2373         frame_size += priv->padding;
2374
2375         tempsize =
2376             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2377             INCREMENTAL_BUFFER_SIZE;
2378
2379         /* Only stop and start the controller if it isn't already
2380          * stopped, and we changed something */
2381         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2382                 stop_gfar(dev);
2383
2384         priv->rx_buffer_size = tempsize;
2385
2386         dev->mtu = new_mtu;
2387
2388         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2389         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2390
2391         /* If the mtu is larger than the max size for standard
2392          * ethernet frames (ie, a jumbo frame), then set maccfg2
2393          * to allow huge frames, and to check the length */
2394         tempval = gfar_read(&regs->maccfg2);
2395
2396         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2397                         gfar_has_errata(priv, GFAR_ERRATA_74))
2398                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2399         else
2400                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2401
2402         gfar_write(&regs->maccfg2, tempval);
2403
2404         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2405                 startup_gfar(dev);
2406
2407         return 0;
2408 }
2409
2410 /* gfar_reset_task gets scheduled when a packet has not been
2411  * transmitted after a set amount of time.
2412  * For now, assume that clearing out all the structures, and
2413  * starting over will fix the problem.
2414  */
2415 static void gfar_reset_task(struct work_struct *work)
2416 {
2417         struct gfar_private *priv = container_of(work, struct gfar_private,
2418                         reset_task);
2419         struct net_device *dev = priv->ndev;
2420
2421         if (dev->flags & IFF_UP) {
2422                 netif_tx_stop_all_queues(dev);
2423                 stop_gfar(dev);
2424                 startup_gfar(dev);
2425                 netif_tx_start_all_queues(dev);
2426         }
2427
2428         netif_tx_schedule_all(dev);
2429 }
2430
2431 static void gfar_timeout(struct net_device *dev)
2432 {
2433         struct gfar_private *priv = netdev_priv(dev);
2434
2435         dev->stats.tx_errors++;
2436         schedule_work(&priv->reset_task);
2437 }
2438
2439 static void gfar_align_skb(struct sk_buff *skb)
2440 {
2441         /* We need the data buffer to be aligned properly.  We will reserve
2442          * as many bytes as needed to align the data properly
2443          */
2444         skb_reserve(skb, RXBUF_ALIGNMENT -
2445                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2446 }
2447
2448 /* Interrupt Handler for Transmit complete */
2449 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2450 {
2451         struct net_device *dev = tx_queue->dev;
2452         struct gfar_private *priv = netdev_priv(dev);
2453         struct gfar_priv_rx_q *rx_queue = NULL;
2454         struct txbd8 *bdp, *next = NULL;
2455         struct txbd8 *lbdp = NULL;
2456         struct txbd8 *base = tx_queue->tx_bd_base;
2457         struct sk_buff *skb;
2458         int skb_dirtytx;
2459         int tx_ring_size = tx_queue->tx_ring_size;
2460         int frags = 0, nr_txbds = 0;
2461         int i;
2462         int howmany = 0;
2463         u32 lstatus;
2464         size_t buflen;
2465
2466         rx_queue = priv->rx_queue[tx_queue->qindex];
2467         bdp = tx_queue->dirty_tx;
2468         skb_dirtytx = tx_queue->skb_dirtytx;
2469
2470         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2471                 unsigned long flags;
2472
2473                 frags = skb_shinfo(skb)->nr_frags;
2474
2475                 /*
2476                  * When time stamping, one additional TxBD must be freed.
2477                  * Also, we need to dma_unmap_single() the TxPAL.
2478                  */
2479                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2480                         nr_txbds = frags + 2;
2481                 else
2482                         nr_txbds = frags + 1;
2483
2484                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2485
2486                 lstatus = lbdp->lstatus;
2487
2488                 /* Only clean completed frames */
2489                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2490                                 (lstatus & BD_LENGTH_MASK))
2491                         break;
2492
2493                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2494                         next = next_txbd(bdp, base, tx_ring_size);
2495                         buflen = next->length + GMAC_FCB_LEN;
2496                 } else
2497                         buflen = bdp->length;
2498
2499                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2500                                 buflen, DMA_TO_DEVICE);
2501
2502                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2503                         struct skb_shared_hwtstamps shhwtstamps;
2504                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2505                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2506                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2507                         skb_tstamp_tx(skb, &shhwtstamps);
2508                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2509                         bdp = next;
2510                 }
2511
2512                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2513                 bdp = next_txbd(bdp, base, tx_ring_size);
2514
2515                 for (i = 0; i < frags; i++) {
2516                         dma_unmap_page(&priv->ofdev->dev,
2517                                         bdp->bufPtr,
2518                                         bdp->length,
2519                                         DMA_TO_DEVICE);
2520                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2521                         bdp = next_txbd(bdp, base, tx_ring_size);
2522                 }
2523
2524                 /*
2525                  * If there's room in the queue (limit it to rx_buffer_size)
2526                  * we add this skb back into the pool, if it's the right size
2527                  */
2528                 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2529                                 skb_recycle_check(skb, priv->rx_buffer_size +
2530                                         RXBUF_ALIGNMENT)) {
2531                         gfar_align_skb(skb);
2532                         skb_queue_head(&priv->rx_recycle, skb);
2533                 } else
2534                         dev_kfree_skb_any(skb);
2535
2536                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2537
2538                 skb_dirtytx = (skb_dirtytx + 1) &
2539                         TX_RING_MOD_MASK(tx_ring_size);
2540
2541                 howmany++;
2542                 spin_lock_irqsave(&tx_queue->txlock, flags);
2543                 tx_queue->num_txbdfree += nr_txbds;
2544                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2545         }
2546
2547         /* If we freed a buffer, we can restart transmission, if necessary */
2548         if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2549                 netif_wake_subqueue(dev, tx_queue->qindex);
2550
2551         /* Update dirty indicators */
2552         tx_queue->skb_dirtytx = skb_dirtytx;
2553         tx_queue->dirty_tx = bdp;
2554
2555         return howmany;
2556 }
2557
2558 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2559 {
2560         unsigned long flags;
2561
2562         spin_lock_irqsave(&gfargrp->grplock, flags);
2563         if (napi_schedule_prep(&gfargrp->napi)) {
2564                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2565                 __napi_schedule(&gfargrp->napi);
2566         } else {
2567                 /*
2568                  * Clear IEVENT, so interrupts aren't called again
2569                  * because of the packets that have already arrived.
2570                  */
2571                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2572         }
2573         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2574
2575 }
2576
2577 /* Interrupt Handler for Transmit complete */
2578 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2579 {
2580         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2581         return IRQ_HANDLED;
2582 }
2583
2584 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2585                 struct sk_buff *skb)
2586 {
2587         struct net_device *dev = rx_queue->dev;
2588         struct gfar_private *priv = netdev_priv(dev);
2589         dma_addr_t buf;
2590
2591         buf = dma_map_single(&priv->ofdev->dev, skb->data,
2592                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2593         gfar_init_rxbdp(rx_queue, bdp, buf);
2594 }
2595
2596 static struct sk_buff * gfar_alloc_skb(struct net_device *dev)
2597 {
2598         struct gfar_private *priv = netdev_priv(dev);
2599         struct sk_buff *skb = NULL;
2600
2601         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2602         if (!skb)
2603                 return NULL;
2604
2605         gfar_align_skb(skb);
2606
2607         return skb;
2608 }
2609
2610 struct sk_buff * gfar_new_skb(struct net_device *dev)
2611 {
2612         struct gfar_private *priv = netdev_priv(dev);
2613         struct sk_buff *skb = NULL;
2614
2615         skb = skb_dequeue(&priv->rx_recycle);
2616         if (!skb)
2617                 skb = gfar_alloc_skb(dev);
2618
2619         return skb;
2620 }
2621
2622 static inline void count_errors(unsigned short status, struct net_device *dev)
2623 {
2624         struct gfar_private *priv = netdev_priv(dev);
2625         struct net_device_stats *stats = &dev->stats;
2626         struct gfar_extra_stats *estats = &priv->extra_stats;
2627
2628         /* If the packet was truncated, none of the other errors
2629          * matter */
2630         if (status & RXBD_TRUNCATED) {
2631                 stats->rx_length_errors++;
2632
2633                 estats->rx_trunc++;
2634
2635                 return;
2636         }
2637         /* Count the errors, if there were any */
2638         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2639                 stats->rx_length_errors++;
2640
2641                 if (status & RXBD_LARGE)
2642                         estats->rx_large++;
2643                 else
2644                         estats->rx_short++;
2645         }
2646         if (status & RXBD_NONOCTET) {
2647                 stats->rx_frame_errors++;
2648                 estats->rx_nonoctet++;
2649         }
2650         if (status & RXBD_CRCERR) {
2651                 estats->rx_crcerr++;
2652                 stats->rx_crc_errors++;
2653         }
2654         if (status & RXBD_OVERRUN) {
2655                 estats->rx_overrun++;
2656                 stats->rx_crc_errors++;
2657         }
2658 }
2659
2660 irqreturn_t gfar_receive(int irq, void *grp_id)
2661 {
2662         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2663         return IRQ_HANDLED;
2664 }
2665
2666 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2667 {
2668         /* If valid headers were found, and valid sums
2669          * were verified, then we tell the kernel that no
2670          * checksumming is necessary.  Otherwise, it is */
2671         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2672                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2673         else
2674                 skb_checksum_none_assert(skb);
2675 }
2676
2677
2678 /* gfar_process_frame() -- handle one incoming packet if skb
2679  * isn't NULL.  */
2680 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2681                               int amount_pull)
2682 {
2683         struct gfar_private *priv = netdev_priv(dev);
2684         struct rxfcb *fcb = NULL;
2685
2686         int ret;
2687
2688         /* fcb is at the beginning if exists */
2689         fcb = (struct rxfcb *)skb->data;
2690
2691         /* Remove the FCB from the skb */
2692         /* Remove the padded bytes, if there are any */
2693         if (amount_pull) {
2694                 skb_record_rx_queue(skb, fcb->rq);
2695                 skb_pull(skb, amount_pull);
2696         }
2697
2698         /* Get receive timestamp from the skb */
2699         if (priv->hwts_rx_en) {
2700                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2701                 u64 *ns = (u64 *) skb->data;
2702                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2703                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2704         }
2705
2706         if (priv->padding)
2707                 skb_pull(skb, priv->padding);
2708
2709         if (dev->features & NETIF_F_RXCSUM)
2710                 gfar_rx_checksum(skb, fcb);
2711
2712         /* Tell the skb what kind of packet this is */
2713         skb->protocol = eth_type_trans(skb, dev);
2714
2715         /* Send the packet up the stack */
2716         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2717                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2718         else
2719                 ret = netif_receive_skb(skb);
2720
2721         if (NET_RX_DROP == ret)
2722                 priv->extra_stats.kernel_dropped++;
2723
2724         return 0;
2725 }
2726
2727 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2728  *   until the budget/quota has been reached. Returns the number
2729  *   of frames handled
2730  */
2731 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2732 {
2733         struct net_device *dev = rx_queue->dev;
2734         struct rxbd8 *bdp, *base;
2735         struct sk_buff *skb;
2736         int pkt_len;
2737         int amount_pull;
2738         int howmany = 0;
2739         struct gfar_private *priv = netdev_priv(dev);
2740
2741         /* Get the first full descriptor */
2742         bdp = rx_queue->cur_rx;
2743         base = rx_queue->rx_bd_base;
2744
2745         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2746
2747         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2748                 struct sk_buff *newskb;
2749                 rmb();
2750
2751                 /* Add another skb for the future */
2752                 newskb = gfar_new_skb(dev);
2753
2754                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2755
2756                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2757                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
2758
2759                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2760                                 bdp->length > priv->rx_buffer_size))
2761                         bdp->status = RXBD_LARGE;
2762
2763                 /* We drop the frame if we failed to allocate a new buffer */
2764                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2765                                  bdp->status & RXBD_ERR)) {
2766                         count_errors(bdp->status, dev);
2767
2768                         if (unlikely(!newskb))
2769                                 newskb = skb;
2770                         else if (skb)
2771                                 skb_queue_head(&priv->rx_recycle, skb);
2772                 } else {
2773                         /* Increment the number of packets */
2774                         rx_queue->stats.rx_packets++;
2775                         howmany++;
2776
2777                         if (likely(skb)) {
2778                                 pkt_len = bdp->length - ETH_FCS_LEN;
2779                                 /* Remove the FCS from the packet length */
2780                                 skb_put(skb, pkt_len);
2781                                 rx_queue->stats.rx_bytes += pkt_len;
2782                                 skb_record_rx_queue(skb, rx_queue->qindex);
2783                                 gfar_process_frame(dev, skb, amount_pull);
2784
2785                         } else {
2786                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2787                                 rx_queue->stats.rx_dropped++;
2788                                 priv->extra_stats.rx_skbmissing++;
2789                         }
2790
2791                 }
2792
2793                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2794
2795                 /* Setup the new bdp */
2796                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2797
2798                 /* Update to the next pointer */
2799                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2800
2801                 /* update to point at the next skb */
2802                 rx_queue->skb_currx =
2803                     (rx_queue->skb_currx + 1) &
2804                     RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2805         }
2806
2807         /* Update the current rxbd pointer to be the next one */
2808         rx_queue->cur_rx = bdp;
2809
2810         return howmany;
2811 }
2812
2813 static int gfar_poll(struct napi_struct *napi, int budget)
2814 {
2815         struct gfar_priv_grp *gfargrp = container_of(napi,
2816                         struct gfar_priv_grp, napi);
2817         struct gfar_private *priv = gfargrp->priv;
2818         struct gfar __iomem *regs = gfargrp->regs;
2819         struct gfar_priv_tx_q *tx_queue = NULL;
2820         struct gfar_priv_rx_q *rx_queue = NULL;
2821         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2822         int tx_cleaned = 0, i, left_over_budget = budget;
2823         unsigned long serviced_queues = 0;
2824         int num_queues = 0;
2825
2826         num_queues = gfargrp->num_rx_queues;
2827         budget_per_queue = budget/num_queues;
2828
2829         /* Clear IEVENT, so interrupts aren't called again
2830          * because of the packets that have already arrived */
2831         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2832
2833         while (num_queues && left_over_budget) {
2834
2835                 budget_per_queue = left_over_budget/num_queues;
2836                 left_over_budget = 0;
2837
2838                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2839                         if (test_bit(i, &serviced_queues))
2840                                 continue;
2841                         rx_queue = priv->rx_queue[i];
2842                         tx_queue = priv->tx_queue[rx_queue->qindex];
2843
2844                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2845                         rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2846                                                         budget_per_queue);
2847                         rx_cleaned += rx_cleaned_per_queue;
2848                         if(rx_cleaned_per_queue < budget_per_queue) {
2849                                 left_over_budget = left_over_budget +
2850                                         (budget_per_queue - rx_cleaned_per_queue);
2851                                 set_bit(i, &serviced_queues);
2852                                 num_queues--;
2853                         }
2854                 }
2855         }
2856
2857         if (tx_cleaned)
2858                 return budget;
2859
2860         if (rx_cleaned < budget) {
2861                 napi_complete(napi);
2862
2863                 /* Clear the halt bit in RSTAT */
2864                 gfar_write(&regs->rstat, gfargrp->rstat);
2865
2866                 gfar_write(&regs->imask, IMASK_DEFAULT);
2867
2868                 /* If we are coalescing interrupts, update the timer */
2869                 /* Otherwise, clear it */
2870                 gfar_configure_coalescing(priv,
2871                                 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
2872         }
2873
2874         return rx_cleaned;
2875 }
2876
2877 #ifdef CONFIG_NET_POLL_CONTROLLER
2878 /*
2879  * Polling 'interrupt' - used by things like netconsole to send skbs
2880  * without having to re-enable interrupts. It's not called while
2881  * the interrupt routine is executing.
2882  */
2883 static void gfar_netpoll(struct net_device *dev)
2884 {
2885         struct gfar_private *priv = netdev_priv(dev);
2886         int i = 0;
2887
2888         /* If the device has multiple interrupts, run tx/rx */
2889         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2890                 for (i = 0; i < priv->num_grps; i++) {
2891                         disable_irq(priv->gfargrp[i].interruptTransmit);
2892                         disable_irq(priv->gfargrp[i].interruptReceive);
2893                         disable_irq(priv->gfargrp[i].interruptError);
2894                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2895                                                 &priv->gfargrp[i]);
2896                         enable_irq(priv->gfargrp[i].interruptError);
2897                         enable_irq(priv->gfargrp[i].interruptReceive);
2898                         enable_irq(priv->gfargrp[i].interruptTransmit);
2899                 }
2900         } else {
2901                 for (i = 0; i < priv->num_grps; i++) {
2902                         disable_irq(priv->gfargrp[i].interruptTransmit);
2903                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2904                                                 &priv->gfargrp[i]);
2905                         enable_irq(priv->gfargrp[i].interruptTransmit);
2906                 }
2907         }
2908 }
2909 #endif
2910
2911 /* The interrupt handler for devices with one interrupt */
2912 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2913 {
2914         struct gfar_priv_grp *gfargrp = grp_id;
2915
2916         /* Save ievent for future reference */
2917         u32 events = gfar_read(&gfargrp->regs->ievent);
2918
2919         /* Check for reception */
2920         if (events & IEVENT_RX_MASK)
2921                 gfar_receive(irq, grp_id);
2922
2923         /* Check for transmit completion */
2924         if (events & IEVENT_TX_MASK)
2925                 gfar_transmit(irq, grp_id);
2926
2927         /* Check for errors */
2928         if (events & IEVENT_ERR_MASK)
2929                 gfar_error(irq, grp_id);
2930
2931         return IRQ_HANDLED;
2932 }
2933
2934 /* Called every time the controller might need to be made
2935  * aware of new link state.  The PHY code conveys this
2936  * information through variables in the phydev structure, and this
2937  * function converts those variables into the appropriate
2938  * register values, and can bring down the device if needed.
2939  */
2940 static void adjust_link(struct net_device *dev)
2941 {
2942         struct gfar_private *priv = netdev_priv(dev);
2943         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2944         unsigned long flags;
2945         struct phy_device *phydev = priv->phydev;
2946         int new_state = 0;
2947
2948         local_irq_save(flags);
2949         lock_tx_qs(priv);
2950
2951         if (phydev->link) {
2952                 u32 tempval = gfar_read(&regs->maccfg2);
2953                 u32 ecntrl = gfar_read(&regs->ecntrl);
2954
2955                 /* Now we make sure that we can be in full duplex mode.
2956                  * If not, we operate in half-duplex mode. */
2957                 if (phydev->duplex != priv->oldduplex) {
2958                         new_state = 1;
2959                         if (!(phydev->duplex))
2960                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2961                         else
2962                                 tempval |= MACCFG2_FULL_DUPLEX;
2963
2964                         priv->oldduplex = phydev->duplex;
2965                 }
2966
2967                 if (phydev->speed != priv->oldspeed) {
2968                         new_state = 1;
2969                         switch (phydev->speed) {
2970                         case 1000:
2971                                 tempval =
2972                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2973
2974                                 ecntrl &= ~(ECNTRL_R100);
2975                                 break;
2976                         case 100:
2977                         case 10:
2978                                 tempval =
2979                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2980
2981                                 /* Reduced mode distinguishes
2982                                  * between 10 and 100 */
2983                                 if (phydev->speed == SPEED_100)
2984                                         ecntrl |= ECNTRL_R100;
2985                                 else
2986                                         ecntrl &= ~(ECNTRL_R100);
2987                                 break;
2988                         default:
2989                                 netif_warn(priv, link, dev,
2990                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
2991                                            phydev->speed);
2992                                 break;
2993                         }
2994
2995                         priv->oldspeed = phydev->speed;
2996                 }
2997
2998                 gfar_write(&regs->maccfg2, tempval);
2999                 gfar_write(&regs->ecntrl, ecntrl);
3000
3001                 if (!priv->oldlink) {
3002                         new_state = 1;
3003                         priv->oldlink = 1;
3004                 }
3005         } else if (priv->oldlink) {
3006                 new_state = 1;
3007                 priv->oldlink = 0;
3008                 priv->oldspeed = 0;
3009                 priv->oldduplex = -1;
3010         }
3011
3012         if (new_state && netif_msg_link(priv))
3013                 phy_print_status(phydev);
3014         unlock_tx_qs(priv);
3015         local_irq_restore(flags);
3016 }
3017
3018 /* Update the hash table based on the current list of multicast
3019  * addresses we subscribe to.  Also, change the promiscuity of
3020  * the device based on the flags (this function is called
3021  * whenever dev->flags is changed */
3022 static void gfar_set_multi(struct net_device *dev)
3023 {
3024         struct netdev_hw_addr *ha;
3025         struct gfar_private *priv = netdev_priv(dev);
3026         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3027         u32 tempval;
3028
3029         if (dev->flags & IFF_PROMISC) {
3030                 /* Set RCTRL to PROM */
3031                 tempval = gfar_read(&regs->rctrl);
3032                 tempval |= RCTRL_PROM;
3033                 gfar_write(&regs->rctrl, tempval);
3034         } else {
3035                 /* Set RCTRL to not PROM */
3036                 tempval = gfar_read(&regs->rctrl);
3037                 tempval &= ~(RCTRL_PROM);
3038                 gfar_write(&regs->rctrl, tempval);
3039         }
3040
3041         if (dev->flags & IFF_ALLMULTI) {
3042                 /* Set the hash to rx all multicast frames */
3043                 gfar_write(&regs->igaddr0, 0xffffffff);
3044                 gfar_write(&regs->igaddr1, 0xffffffff);
3045                 gfar_write(&regs->igaddr2, 0xffffffff);
3046                 gfar_write(&regs->igaddr3, 0xffffffff);
3047                 gfar_write(&regs->igaddr4, 0xffffffff);
3048                 gfar_write(&regs->igaddr5, 0xffffffff);
3049                 gfar_write(&regs->igaddr6, 0xffffffff);
3050                 gfar_write(&regs->igaddr7, 0xffffffff);
3051                 gfar_write(&regs->gaddr0, 0xffffffff);
3052                 gfar_write(&regs->gaddr1, 0xffffffff);
3053                 gfar_write(&regs->gaddr2, 0xffffffff);
3054                 gfar_write(&regs->gaddr3, 0xffffffff);
3055                 gfar_write(&regs->gaddr4, 0xffffffff);
3056                 gfar_write(&regs->gaddr5, 0xffffffff);
3057                 gfar_write(&regs->gaddr6, 0xffffffff);
3058                 gfar_write(&regs->gaddr7, 0xffffffff);
3059         } else {
3060                 int em_num;
3061                 int idx;
3062
3063                 /* zero out the hash */
3064                 gfar_write(&regs->igaddr0, 0x0);
3065                 gfar_write(&regs->igaddr1, 0x0);
3066                 gfar_write(&regs->igaddr2, 0x0);
3067                 gfar_write(&regs->igaddr3, 0x0);
3068                 gfar_write(&regs->igaddr4, 0x0);
3069                 gfar_write(&regs->igaddr5, 0x0);
3070                 gfar_write(&regs->igaddr6, 0x0);
3071                 gfar_write(&regs->igaddr7, 0x0);
3072                 gfar_write(&regs->gaddr0, 0x0);
3073                 gfar_write(&regs->gaddr1, 0x0);
3074                 gfar_write(&regs->gaddr2, 0x0);
3075                 gfar_write(&regs->gaddr3, 0x0);
3076                 gfar_write(&regs->gaddr4, 0x0);
3077                 gfar_write(&regs->gaddr5, 0x0);
3078                 gfar_write(&regs->gaddr6, 0x0);
3079                 gfar_write(&regs->gaddr7, 0x0);
3080
3081                 /* If we have extended hash tables, we need to
3082                  * clear the exact match registers to prepare for
3083                  * setting them */
3084                 if (priv->extended_hash) {
3085                         em_num = GFAR_EM_NUM + 1;
3086                         gfar_clear_exact_match(dev);
3087                         idx = 1;
3088                 } else {
3089                         idx = 0;
3090                         em_num = 0;
3091                 }
3092
3093                 if (netdev_mc_empty(dev))
3094                         return;
3095
3096                 /* Parse the list, and set the appropriate bits */
3097                 netdev_for_each_mc_addr(ha, dev) {
3098                         if (idx < em_num) {
3099                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3100                                 idx++;
3101                         } else
3102                                 gfar_set_hash_for_addr(dev, ha->addr);
3103                 }
3104         }
3105 }
3106
3107
3108 /* Clears each of the exact match registers to zero, so they
3109  * don't interfere with normal reception */
3110 static void gfar_clear_exact_match(struct net_device *dev)
3111 {
3112         int idx;
3113         static const u8 zero_arr[MAC_ADDR_LEN] = {0, 0, 0, 0, 0, 0};
3114
3115         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3116                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3117 }
3118
3119 /* Set the appropriate hash bit for the given addr */
3120 /* The algorithm works like so:
3121  * 1) Take the Destination Address (ie the multicast address), and
3122  * do a CRC on it (little endian), and reverse the bits of the
3123  * result.
3124  * 2) Use the 8 most significant bits as a hash into a 256-entry
3125  * table.  The table is controlled through 8 32-bit registers:
3126  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3127  * gaddr7.  This means that the 3 most significant bits in the
3128  * hash index which gaddr register to use, and the 5 other bits
3129  * indicate which bit (assuming an IBM numbering scheme, which
3130  * for PowerPC (tm) is usually the case) in the register holds
3131  * the entry. */
3132 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3133 {
3134         u32 tempval;
3135         struct gfar_private *priv = netdev_priv(dev);
3136         u32 result = ether_crc(MAC_ADDR_LEN, addr);
3137         int width = priv->hash_width;
3138         u8 whichbit = (result >> (32 - width)) & 0x1f;
3139         u8 whichreg = result >> (32 - width + 5);
3140         u32 value = (1 << (31-whichbit));
3141
3142         tempval = gfar_read(priv->hash_regs[whichreg]);
3143         tempval |= value;
3144         gfar_write(priv->hash_regs[whichreg], tempval);
3145 }
3146
3147
3148 /* There are multiple MAC Address register pairs on some controllers
3149  * This function sets the numth pair to a given address
3150  */
3151 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3152                                   const u8 *addr)
3153 {
3154         struct gfar_private *priv = netdev_priv(dev);
3155         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3156         int idx;
3157         char tmpbuf[MAC_ADDR_LEN];
3158         u32 tempval;
3159         u32 __iomem *macptr = &regs->macstnaddr1;
3160
3161         macptr += num*2;
3162
3163         /* Now copy it into the mac registers backwards, cuz */
3164         /* little endian is silly */
3165         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3166                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3167
3168         gfar_write(macptr, *((u32 *) (tmpbuf)));
3169
3170         tempval = *((u32 *) (tmpbuf + 4));
3171
3172         gfar_write(macptr+1, tempval);
3173 }
3174
3175 /* GFAR error interrupt handler */
3176 static irqreturn_t gfar_error(int irq, void *grp_id)
3177 {
3178         struct gfar_priv_grp *gfargrp = grp_id;
3179         struct gfar __iomem *regs = gfargrp->regs;
3180         struct gfar_private *priv= gfargrp->priv;
3181         struct net_device *dev = priv->ndev;
3182
3183         /* Save ievent for future reference */
3184         u32 events = gfar_read(&regs->ievent);
3185
3186         /* Clear IEVENT */
3187         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3188
3189         /* Magic Packet is not an error. */
3190         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3191             (events & IEVENT_MAG))
3192                 events &= ~IEVENT_MAG;
3193
3194         /* Hmm... */
3195         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3196                 netdev_dbg(dev, "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3197                            events, gfar_read(&regs->imask));
3198
3199         /* Update the error counters */
3200         if (events & IEVENT_TXE) {
3201                 dev->stats.tx_errors++;
3202
3203                 if (events & IEVENT_LC)
3204                         dev->stats.tx_window_errors++;
3205                 if (events & IEVENT_CRL)
3206                         dev->stats.tx_aborted_errors++;
3207                 if (events & IEVENT_XFUN) {
3208                         unsigned long flags;
3209
3210                         netif_dbg(priv, tx_err, dev,
3211                                   "TX FIFO underrun, packet dropped\n");
3212                         dev->stats.tx_dropped++;
3213                         priv->extra_stats.tx_underrun++;
3214
3215                         local_irq_save(flags);
3216                         lock_tx_qs(priv);
3217
3218                         /* Reactivate the Tx Queues */
3219                         gfar_write(&regs->tstat, gfargrp->tstat);
3220
3221                         unlock_tx_qs(priv);
3222                         local_irq_restore(flags);
3223                 }
3224                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3225         }
3226         if (events & IEVENT_BSY) {
3227                 dev->stats.rx_errors++;
3228                 priv->extra_stats.rx_bsy++;
3229
3230                 gfar_receive(irq, grp_id);
3231
3232                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3233                           gfar_read(&regs->rstat));
3234         }
3235         if (events & IEVENT_BABR) {
3236                 dev->stats.rx_errors++;
3237                 priv->extra_stats.rx_babr++;
3238
3239                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3240         }
3241         if (events & IEVENT_EBERR) {
3242                 priv->extra_stats.eberr++;
3243                 netif_dbg(priv, rx_err, dev, "bus error\n");
3244         }
3245         if (events & IEVENT_RXC)
3246                 netif_dbg(priv, rx_status, dev, "control frame\n");
3247
3248         if (events & IEVENT_BABT) {
3249                 priv->extra_stats.tx_babt++;
3250                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3251         }
3252         return IRQ_HANDLED;
3253 }
3254
3255 static struct of_device_id gfar_match[] =
3256 {
3257         {
3258                 .type = "network",
3259                 .compatible = "gianfar",
3260         },
3261         {
3262                 .compatible = "fsl,etsec2",
3263         },
3264         {},
3265 };
3266 MODULE_DEVICE_TABLE(of, gfar_match);
3267
3268 /* Structure for a device driver */
3269 static struct platform_driver gfar_driver = {
3270         .driver = {
3271                 .name = "fsl-gianfar",
3272                 .owner = THIS_MODULE,
3273                 .pm = GFAR_PM_OPS,
3274                 .of_match_table = gfar_match,
3275         },
3276         .probe = gfar_probe,
3277         .remove = gfar_remove,
3278 };
3279
3280 static int __init gfar_init(void)
3281 {
3282         return platform_driver_register(&gfar_driver);
3283 }
3284
3285 static void __exit gfar_exit(void)
3286 {
3287         platform_driver_unregister(&gfar_driver);
3288 }
3289
3290 module_init(gfar_init);
3291 module_exit(gfar_exit);
3292