drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  *
  12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
  13  * Copyright (c) 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #include <linux/kernel.h>
  65 #include <linux/string.h>
  66 #include <linux/errno.h>
  67 #include <linux/unistd.h>
  68 #include <linux/slab.h>
  69 #include <linux/interrupt.h>
  70 #include <linux/init.h>
  71 #include <linux/delay.h>
  72 #include <linux/netdevice.h>
  73 #include <linux/etherdevice.h>
  74 #include <linux/skbuff.h>
  75 #include <linux/if_vlan.h>
  76 #include <linux/spinlock.h>
  77 #include <linux/mm.h>
  78 #include <linux/of_platform.h>
  79 #include <linux/ip.h>
  80 #include <linux/tcp.h>
  81 #include <linux/udp.h>
  82 #include <linux/in.h>
  83
  84 #include <asm/io.h>
  85 #include <asm/irq.h>
  86 #include <asm/uaccess.h>
  87 #include <linux/module.h>
  88 #include <linux/dma-mapping.h>
  89 #include <linux/crc32.h>
  90 #include <linux/mii.h>
  91 #include <linux/phy.h>
  92 #include <linux/phy_fixed.h>
  93 #include <linux/of.h>
  94
  95 #include "gianfar.h"
  96 #include "fsl_pq_mdio.h"
  97
  98 #define TX_TIMEOUT      (1*HZ)
  99 #undef BRIEF_GFAR_ERRORS
 100 #undef VERBOSE_GFAR_ERRORS
 101
 102 const char gfar_driver_name[] = "Gianfar Ethernet";
 103 const char gfar_driver_version[] = "1.3";
 104
 105 static int gfar_enet_open(struct net_device *dev);
 106 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 107 static void gfar_reset_task(struct work_struct *work);
 108 static void gfar_timeout(struct net_device *dev);
 109 static int gfar_close(struct net_device *dev);
 110 struct sk_buff *gfar_new_skb(struct net_device *dev);
 111 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
 112                 struct sk_buff *skb);
 113 static int gfar_set_mac_address(struct net_device *dev);
 114 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 115 static irqreturn_t gfar_error(int irq, void *dev_id);
 116 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 117 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 118 static void adjust_link(struct net_device *dev);
 119 static void init_registers(struct net_device *dev);
 120 static int init_phy(struct net_device *dev);
 121 static int gfar_probe(struct of_device *ofdev,
 122                 const struct of_device_id *match);
 123 static int gfar_remove(struct of_device *ofdev);
 124 static void free_skb_resources(struct gfar_private *priv);
 125 static void gfar_set_multi(struct net_device *dev);
 126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 127 static void gfar_configure_serdes(struct net_device *dev);
 128 static int gfar_poll(struct napi_struct *napi, int budget);
 129 #ifdef CONFIG_NET_POLL_CONTROLLER
 130 static void gfar_netpoll(struct net_device *dev);
 131 #endif
 132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
 133 static int gfar_clean_tx_ring(struct net_device *dev);
 134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 135                               int amount_pull);
 136 static void gfar_vlan_rx_register(struct net_device *netdev,
 137                                 struct vlan_group *grp);
 138 void gfar_halt(struct net_device *dev);
 139 static void gfar_halt_nodisable(struct net_device *dev);
 140 void gfar_start(struct net_device *dev);
 141 static void gfar_clear_exact_match(struct net_device *dev);
 142 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 143 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 144
 145 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 146 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 147 MODULE_LICENSE("GPL");
 148
 149 static const struct net_device_ops gfar_netdev_ops = {
 150         .ndo_open = gfar_enet_open,
 151         .ndo_start_xmit = gfar_start_xmit,
 152         .ndo_stop = gfar_close,
 153         .ndo_change_mtu = gfar_change_mtu,
 154         .ndo_set_multicast_list = gfar_set_multi,
 155         .ndo_tx_timeout = gfar_timeout,
 156         .ndo_do_ioctl = gfar_ioctl,
 157         .ndo_vlan_rx_register = gfar_vlan_rx_register,
 158 #ifdef CONFIG_NET_POLL_CONTROLLER
 159         .ndo_poll_controller = gfar_netpoll,
 160 #endif
 161 };
 162
 163 /* Returns 1 if incoming frames use an FCB */
 164 static inline int gfar_uses_fcb(struct gfar_private *priv)
 165 {
 166         return priv->vlgrp || priv->rx_csum_enable;
 167 }
 168
 169 static int gfar_of_init(struct net_device *dev)
 170 {
 171         struct device_node *phy, *mdio;
 172         const unsigned int *id;
 173         const char *model;
 174         const char *ctype;
 175         const void *mac_addr;
 176         const phandle *ph;
 177         u64 addr, size;
 178         int err = 0;
 179         struct gfar_private *priv = netdev_priv(dev);
 180         struct device_node *np = priv->node;
 181         char bus_name[MII_BUS_ID_SIZE];
 182         const u32 *stash;
 183         const u32 *stash_len;
 184         const u32 *stash_idx;
 185
 186         if (!np || !of_device_is_available(np))
 187                 return -ENODEV;
 188
 189         /* get a pointer to the register memory */
 190         addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
 191         priv->regs = ioremap(addr, size);
 192
 193         if (priv->regs == NULL)
 194                 return -ENOMEM;
 195
 196         priv->interruptTransmit = irq_of_parse_and_map(np, 0);
 197
 198         model = of_get_property(np, "model", NULL);
 199
 200         /* If we aren't the FEC we have multiple interrupts */
 201         if (model && strcasecmp(model, "FEC")) {
 202                 priv->interruptReceive = irq_of_parse_and_map(np, 1);
 203
 204                 priv->interruptError = irq_of_parse_and_map(np, 2);
 205
 206                 if (priv->interruptTransmit < 0 ||
 207                                 priv->interruptReceive < 0 ||
 208                                 priv->interruptError < 0) {
 209                         err = -EINVAL;
 210                         goto err_out;
 211                 }
 212         }
 213
 214         stash = of_get_property(np, "bd-stash", NULL);
 215
 216         if(stash) {
 217                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 218                 priv->bd_stash_en = 1;
 219         }
 220
 221         stash_len = of_get_property(np, "rx-stash-len", NULL);
 222
 223         if (stash_len)
 224                 priv->rx_stash_size = *stash_len;
 225
 226         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 227
 228         if (stash_idx)
 229                 priv->rx_stash_index = *stash_idx;
 230
 231         if (stash_len || stash_idx)
 232                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 233
 234         mac_addr = of_get_mac_address(np);
 235         if (mac_addr)
 236                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
 237
 238         if (model && !strcasecmp(model, "TSEC"))
 239                 priv->device_flags =
 240                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 241                         FSL_GIANFAR_DEV_HAS_COALESCE |
 242                         FSL_GIANFAR_DEV_HAS_RMON |
 243                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 244         if (model && !strcasecmp(model, "eTSEC"))
 245                 priv->device_flags =
 246                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 247                         FSL_GIANFAR_DEV_HAS_COALESCE |
 248                         FSL_GIANFAR_DEV_HAS_RMON |
 249                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 250                         FSL_GIANFAR_DEV_HAS_PADDING |
 251                         FSL_GIANFAR_DEV_HAS_CSUM |
 252                         FSL_GIANFAR_DEV_HAS_VLAN |
 253                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 254                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
 255
 256         ctype = of_get_property(np, "phy-connection-type", NULL);
 257
 258         /* We only care about rgmii-id.  The rest are autodetected */
 259         if (ctype && !strcmp(ctype, "rgmii-id"))
 260                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 261         else
 262                 priv->interface = PHY_INTERFACE_MODE_MII;
 263
 264         if (of_get_property(np, "fsl,magic-packet", NULL))
 265                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 266
 267         ph = of_get_property(np, "phy-handle", NULL);
 268         if (ph == NULL) {
 269                 u32 *fixed_link;
 270
 271                 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
 272                 if (!fixed_link) {
 273                         err = -ENODEV;
 274                         goto err_out;
 275                 }
 276
 277                 snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id),
 278                                 PHY_ID_FMT, "0", fixed_link[0]);
 279         } else {
 280                 phy = of_find_node_by_phandle(*ph);
 281
 282                 if (phy == NULL) {
 283                         err = -ENODEV;
 284                         goto err_out;
 285                 }
 286
 287                 mdio = of_get_parent(phy);
 288
 289                 id = of_get_property(phy, "reg", NULL);
 290
 291                 of_node_put(phy);
 292
 293                 fsl_pq_mdio_bus_name(bus_name, mdio);
 294                 of_node_put(mdio);
 295                 snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id), "%s:%02x",
 296                                 bus_name, *id);
 297         }
 298
 299         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 300         ph = of_get_property(np, "tbi-handle", NULL);
 301         if (ph) {
 302                 struct device_node *tbi = of_find_node_by_phandle(*ph);
 303                 struct of_device *ofdev;
 304                 struct mii_bus *bus;
 305
 306                 if (!tbi)
 307                         return 0;
 308
 309                 mdio = of_get_parent(tbi);
 310                 if (!mdio)
 311                         return 0;
 312
 313                 ofdev = of_find_device_by_node(mdio);
 314
 315                 of_node_put(mdio);
 316
 317                 id = of_get_property(tbi, "reg", NULL);
 318                 if (!id)
 319                         return 0;
 320
 321                 of_node_put(tbi);
 322
 323                 bus = dev_get_drvdata(&ofdev->dev);
 324
 325                 priv->tbiphy = bus->phy_map[*id];
 326         }
 327
 328         return 0;
 329
 330 err_out:
 331         iounmap(priv->regs);
 332         return err;
 333 }
 334
 335 /* Ioctl MII Interface */
 336 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 337 {
 338         struct gfar_private *priv = netdev_priv(dev);
 339
 340         if (!netif_running(dev))
 341                 return -EINVAL;
 342
 343         if (!priv->phydev)
 344                 return -ENODEV;
 345
 346         return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
 347 }
 348
 349 /* Set up the ethernet device structure, private data,
 350  * and anything else we need before we start */
 351 static int gfar_probe(struct of_device *ofdev,
 352                 const struct of_device_id *match)
 353 {
 354         u32 tempval;
 355         struct net_device *dev = NULL;
 356         struct gfar_private *priv = NULL;
 357         DECLARE_MAC_BUF(mac);
 358         int err = 0;
 359         int len_devname;
 360
 361         /* Create an ethernet device instance */
 362         dev = alloc_etherdev(sizeof (*priv));
 363
 364         if (NULL == dev)
 365                 return -ENOMEM;
 366
 367         priv = netdev_priv(dev);
 368         priv->ndev = dev;
 369         priv->ofdev = ofdev;
 370         priv->node = ofdev->node;
 371         SET_NETDEV_DEV(dev, &ofdev->dev);
 372
 373         err = gfar_of_init(dev);
 374
 375         if (err)
 376                 goto regs_fail;
 377
 378         spin_lock_init(&priv->txlock);
 379         spin_lock_init(&priv->rxlock);
 380         spin_lock_init(&priv->bflock);
 381         INIT_WORK(&priv->reset_task, gfar_reset_task);
 382
 383         dev_set_drvdata(&ofdev->dev, priv);
 384
 385         /* Stop the DMA engine now, in case it was running before */
 386         /* (The firmware could have used it, and left it running). */
 387         gfar_halt(dev);
 388
 389         /* Reset MAC layer */
 390         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 391
 392         /* We need to delay at least 3 TX clocks */
 393         udelay(2);
 394
 395         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 396         gfar_write(&priv->regs->maccfg1, tempval);
 397
 398         /* Initialize MACCFG2. */
 399         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
 400
 401         /* Initialize ECNTRL */
 402         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
 403
 404         /* Set the dev->base_addr to the gfar reg region */
 405         dev->base_addr = (unsigned long) (priv->regs);
 406
 407         SET_NETDEV_DEV(dev, &ofdev->dev);
 408
 409         /* Fill in the dev structure */
 410         dev->watchdog_timeo = TX_TIMEOUT;
 411         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
 412         dev->mtu = 1500;
 413
 414         dev->netdev_ops = &gfar_netdev_ops;
 415         dev->ethtool_ops = &gfar_ethtool_ops;
 416
 417         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 418                 priv->rx_csum_enable = 1;
 419                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
 420         } else
 421                 priv->rx_csum_enable = 0;
 422
 423         priv->vlgrp = NULL;
 424
 425         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
 426                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 427
 428         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 429                 priv->extended_hash = 1;
 430                 priv->hash_width = 9;
 431
 432                 priv->hash_regs[0] = &priv->regs->igaddr0;
 433                 priv->hash_regs[1] = &priv->regs->igaddr1;
 434                 priv->hash_regs[2] = &priv->regs->igaddr2;
 435                 priv->hash_regs[3] = &priv->regs->igaddr3;
 436                 priv->hash_regs[4] = &priv->regs->igaddr4;
 437                 priv->hash_regs[5] = &priv->regs->igaddr5;
 438                 priv->hash_regs[6] = &priv->regs->igaddr6;
 439                 priv->hash_regs[7] = &priv->regs->igaddr7;
 440                 priv->hash_regs[8] = &priv->regs->gaddr0;
 441                 priv->hash_regs[9] = &priv->regs->gaddr1;
 442                 priv->hash_regs[10] = &priv->regs->gaddr2;
 443                 priv->hash_regs[11] = &priv->regs->gaddr3;
 444                 priv->hash_regs[12] = &priv->regs->gaddr4;
 445                 priv->hash_regs[13] = &priv->regs->gaddr5;
 446                 priv->hash_regs[14] = &priv->regs->gaddr6;
 447                 priv->hash_regs[15] = &priv->regs->gaddr7;
 448
 449         } else {
 450                 priv->extended_hash = 0;
 451                 priv->hash_width = 8;
 452
 453                 priv->hash_regs[0] = &priv->regs->gaddr0;
 454                 priv->hash_regs[1] = &priv->regs->gaddr1;
 455                 priv->hash_regs[2] = &priv->regs->gaddr2;
 456                 priv->hash_regs[3] = &priv->regs->gaddr3;
 457                 priv->hash_regs[4] = &priv->regs->gaddr4;
 458                 priv->hash_regs[5] = &priv->regs->gaddr5;
 459                 priv->hash_regs[6] = &priv->regs->gaddr6;
 460                 priv->hash_regs[7] = &priv->regs->gaddr7;
 461         }
 462
 463         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
 464                 priv->padding = DEFAULT_PADDING;
 465         else
 466                 priv->padding = 0;
 467
 468         if (dev->features & NETIF_F_IP_CSUM)
 469                 dev->hard_header_len += GMAC_FCB_LEN;
 470
 471         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
 472         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
 473         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
 474         priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
 475
 476         priv->txcoalescing = DEFAULT_TX_COALESCE;
 477         priv->txic = DEFAULT_TXIC;
 478         priv->rxcoalescing = DEFAULT_RX_COALESCE;
 479         priv->rxic = DEFAULT_RXIC;
 480
 481         /* Enable most messages by default */
 482         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
 483
 484         /* Carrier starts down, phylib will bring it up */
 485         netif_carrier_off(dev);
 486
 487         err = register_netdev(dev);
 488
 489         if (err) {
 490                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
 491                                 dev->name);
 492                 goto register_fail;
 493         }
 494
 495         device_init_wakeup(&dev->dev,
 496                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 497
 498         /* fill out IRQ number and name fields */
 499         len_devname = strlen(dev->name);
 500         strncpy(&priv->int_name_tx[0], dev->name, len_devname);
 501         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 502                 strncpy(&priv->int_name_tx[len_devname],
 503                         "_tx", sizeof("_tx") + 1);
 504
 505                 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
 506                 strncpy(&priv->int_name_rx[len_devname],
 507                         "_rx", sizeof("_rx") + 1);
 508
 509                 strncpy(&priv->int_name_er[0], dev->name, len_devname);
 510                 strncpy(&priv->int_name_er[len_devname],
 511                         "_er", sizeof("_er") + 1);
 512         } else
 513                 priv->int_name_tx[len_devname] = '\0';
 514
 515         /* Create all the sysfs files */
 516         gfar_init_sysfs(dev);
 517
 518         /* Print out the device info */
 519         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
 520
 521         /* Even more device info helps when determining which kernel */
 522         /* provided which set of benchmarks. */
 523         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
 524         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
 525                dev->name, priv->rx_ring_size, priv->tx_ring_size);
 526
 527         return 0;
 528
 529 register_fail:
 530         iounmap(priv->regs);
 531 regs_fail:
 532         free_netdev(dev);
 533         return err;
 534 }
 535
 536 static int gfar_remove(struct of_device *ofdev)
 537 {
 538         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
 539
 540         dev_set_drvdata(&ofdev->dev, NULL);
 541
 542         iounmap(priv->regs);
 543         free_netdev(priv->ndev);
 544
 545         return 0;
 546 }
 547
 548 #ifdef CONFIG_PM
 549 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
 550 {
 551         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
 552         struct net_device *dev = priv->ndev;
 553         unsigned long flags;
 554         u32 tempval;
 555
 556         int magic_packet = priv->wol_en &&
 557                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 558
 559         netif_device_detach(dev);
 560
 561         if (netif_running(dev)) {
 562                 spin_lock_irqsave(&priv->txlock, flags);
 563                 spin_lock(&priv->rxlock);
 564
 565                 gfar_halt_nodisable(dev);
 566
 567                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
 568                 tempval = gfar_read(&priv->regs->maccfg1);
 569
 570                 tempval &= ~MACCFG1_TX_EN;
 571
 572                 if (!magic_packet)
 573                         tempval &= ~MACCFG1_RX_EN;
 574
 575                 gfar_write(&priv->regs->maccfg1, tempval);
 576
 577                 spin_unlock(&priv->rxlock);
 578                 spin_unlock_irqrestore(&priv->txlock, flags);
 579
 580                 napi_disable(&priv->napi);
 581
 582                 if (magic_packet) {
 583                         /* Enable interrupt on Magic Packet */
 584                         gfar_write(&priv->regs->imask, IMASK_MAG);
 585
 586                         /* Enable Magic Packet mode */
 587                         tempval = gfar_read(&priv->regs->maccfg2);
 588                         tempval |= MACCFG2_MPEN;
 589                         gfar_write(&priv->regs->maccfg2, tempval);
 590                 } else {
 591                         phy_stop(priv->phydev);
 592                 }
 593         }
 594
 595         return 0;
 596 }
 597
 598 static int gfar_resume(struct of_device *ofdev)
 599 {
 600         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
 601         struct net_device *dev = priv->ndev;
 602         unsigned long flags;
 603         u32 tempval;
 604         int magic_packet = priv->wol_en &&
 605                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
 606
 607         if (!netif_running(dev)) {
 608                 netif_device_attach(dev);
 609                 return 0;
 610         }
 611
 612         if (!magic_packet && priv->phydev)
 613                 phy_start(priv->phydev);
 614
 615         /* Disable Magic Packet mode, in case something
 616          * else woke us up.
 617          */
 618
 619         spin_lock_irqsave(&priv->txlock, flags);
 620         spin_lock(&priv->rxlock);
 621
 622         tempval = gfar_read(&priv->regs->maccfg2);
 623         tempval &= ~MACCFG2_MPEN;
 624         gfar_write(&priv->regs->maccfg2, tempval);
 625
 626         gfar_start(dev);
 627
 628         spin_unlock(&priv->rxlock);
 629         spin_unlock_irqrestore(&priv->txlock, flags);
 630
 631         netif_device_attach(dev);
 632
 633         napi_enable(&priv->napi);
 634
 635         return 0;
 636 }
 637 #else
 638 #define gfar_suspend NULL
 639 #define gfar_resume NULL
 640 #endif
 641
 642 /* Reads the controller's registers to determine what interface
 643  * connects it to the PHY.
 644  */
 645 static phy_interface_t gfar_get_interface(struct net_device *dev)
 646 {
 647         struct gfar_private *priv = netdev_priv(dev);
 648         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
 649
 650         if (ecntrl & ECNTRL_SGMII_MODE)
 651                 return PHY_INTERFACE_MODE_SGMII;
 652
 653         if (ecntrl & ECNTRL_TBI_MODE) {
 654                 if (ecntrl & ECNTRL_REDUCED_MODE)
 655                         return PHY_INTERFACE_MODE_RTBI;
 656                 else
 657                         return PHY_INTERFACE_MODE_TBI;
 658         }
 659
 660         if (ecntrl & ECNTRL_REDUCED_MODE) {
 661                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 662                         return PHY_INTERFACE_MODE_RMII;
 663                 else {
 664                         phy_interface_t interface = priv->interface;
 665
 666                         /*
 667                          * This isn't autodetected right now, so it must
 668                          * be set by the device tree or platform code.
 669                          */
 670                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
 671                                 return PHY_INTERFACE_MODE_RGMII_ID;
 672
 673                         return PHY_INTERFACE_MODE_RGMII;
 674                 }
 675         }
 676
 677         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 678                 return PHY_INTERFACE_MODE_GMII;
 679
 680         return PHY_INTERFACE_MODE_MII;
 681 }
 682
 683
 684 /* Initializes driver's PHY state, and attaches to the PHY.
 685  * Returns 0 on success.
 686  */
 687 static int init_phy(struct net_device *dev)
 688 {
 689         struct gfar_private *priv = netdev_priv(dev);
 690         uint gigabit_support =
 691                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
 692                 SUPPORTED_1000baseT_Full : 0;
 693         struct phy_device *phydev;
 694         phy_interface_t interface;
 695
 696         priv->oldlink = 0;
 697         priv->oldspeed = 0;
 698         priv->oldduplex = -1;
 699
 700         interface = gfar_get_interface(dev);
 701
 702         phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface);
 703
 704         if (interface == PHY_INTERFACE_MODE_SGMII)
 705                 gfar_configure_serdes(dev);
 706
 707         if (IS_ERR(phydev)) {
 708                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 709                 return PTR_ERR(phydev);
 710         }
 711
 712         /* Remove any features not supported by the controller */
 713         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
 714         phydev->advertising = phydev->supported;
 715
 716         priv->phydev = phydev;
 717
 718         return 0;
 719 }
 720
 721 /*
 722  * Initialize TBI PHY interface for communicating with the
 723  * SERDES lynx PHY on the chip.  We communicate with this PHY
 724  * through the MDIO bus on each controller, treating it as a
 725  * "normal" PHY at the address found in the TBIPA register.  We assume
 726  * that the TBIPA register is valid.  Either the MDIO bus code will set
 727  * it to a value that doesn't conflict with other PHYs on the bus, or the
 728  * value doesn't matter, as there are no other PHYs on the bus.
 729  */
 730 static void gfar_configure_serdes(struct net_device *dev)
 731 {
 732         struct gfar_private *priv = netdev_priv(dev);
 733
 734         if (!priv->tbiphy) {
 735                 printk(KERN_WARNING "SGMII mode requires that the device "
 736                                 "tree specify a tbi-handle\n");
 737                 return;
 738         }
 739
 740         /*
 741          * If the link is already up, we must already be ok, and don't need to
 742          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
 743          * everything for us?  Resetting it takes the link down and requires
 744          * several seconds for it to come back.
 745          */
 746         if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS)
 747                 return;
 748
 749         /* Single clk mode, mii mode off(for serdes communication) */
 750         phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT);
 751
 752         phy_write(priv->tbiphy, MII_ADVERTISE,
 753                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
 754                         ADVERTISE_1000XPSE_ASYM);
 755
 756         phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE |
 757                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
 758 }
 759
 760 static void init_registers(struct net_device *dev)
 761 {
 762         struct gfar_private *priv = netdev_priv(dev);
 763
 764         /* Clear IEVENT */
 765         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
 766
 767         /* Initialize IMASK */
 768         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
 769
 770         /* Init hash registers to zero */
 771         gfar_write(&priv->regs->igaddr0, 0);
 772         gfar_write(&priv->regs->igaddr1, 0);
 773         gfar_write(&priv->regs->igaddr2, 0);
 774         gfar_write(&priv->regs->igaddr3, 0);
 775         gfar_write(&priv->regs->igaddr4, 0);
 776         gfar_write(&priv->regs->igaddr5, 0);
 777         gfar_write(&priv->regs->igaddr6, 0);
 778         gfar_write(&priv->regs->igaddr7, 0);
 779
 780         gfar_write(&priv->regs->gaddr0, 0);
 781         gfar_write(&priv->regs->gaddr1, 0);
 782         gfar_write(&priv->regs->gaddr2, 0);
 783         gfar_write(&priv->regs->gaddr3, 0);
 784         gfar_write(&priv->regs->gaddr4, 0);
 785         gfar_write(&priv->regs->gaddr5, 0);
 786         gfar_write(&priv->regs->gaddr6, 0);
 787         gfar_write(&priv->regs->gaddr7, 0);
 788
 789         /* Zero out the rmon mib registers if it has them */
 790         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
 791                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
 792
 793                 /* Mask off the CAM interrupts */
 794                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
 795                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
 796         }
 797
 798         /* Initialize the max receive buffer length */
 799         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
 800
 801         /* Initialize the Minimum Frame Length Register */
 802         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
 803 }
 804
 805
 806 /* Halt the receive and transmit queues */
 807 static void gfar_halt_nodisable(struct net_device *dev)
 808 {
 809         struct gfar_private *priv = netdev_priv(dev);
 810         struct gfar __iomem *regs = priv->regs;
 811         u32 tempval;
 812
 813         /* Mask all interrupts */
 814         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 815
 816         /* Clear all interrupts */
 817         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 818
 819         /* Stop the DMA, and wait for it to stop */
 820         tempval = gfar_read(&priv->regs->dmactrl);
 821         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
 822             != (DMACTRL_GRS | DMACTRL_GTS)) {
 823                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 824                 gfar_write(&priv->regs->dmactrl, tempval);
 825
 826                 while (!(gfar_read(&priv->regs->ievent) &
 827                          (IEVENT_GRSC | IEVENT_GTSC)))
 828                         cpu_relax();
 829         }
 830 }
 831
 832 /* Halt the receive and transmit queues */
 833 void gfar_halt(struct net_device *dev)
 834 {
 835         struct gfar_private *priv = netdev_priv(dev);
 836         struct gfar __iomem *regs = priv->regs;
 837         u32 tempval;
 838
 839         gfar_halt_nodisable(dev);
 840
 841         /* Disable Rx and Tx */
 842         tempval = gfar_read(&regs->maccfg1);
 843         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
 844         gfar_write(&regs->maccfg1, tempval);
 845 }
 846
 847 void stop_gfar(struct net_device *dev)
 848 {
 849         struct gfar_private *priv = netdev_priv(dev);
 850         struct gfar __iomem *regs = priv->regs;
 851         unsigned long flags;
 852
 853         phy_stop(priv->phydev);
 854
 855         /* Lock it down */
 856         spin_lock_irqsave(&priv->txlock, flags);
 857         spin_lock(&priv->rxlock);
 858
 859         gfar_halt(dev);
 860
 861         spin_unlock(&priv->rxlock);
 862         spin_unlock_irqrestore(&priv->txlock, flags);
 863
 864         /* Free the IRQs */
 865         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 866                 free_irq(priv->interruptError, dev);
 867                 free_irq(priv->interruptTransmit, dev);
 868                 free_irq(priv->interruptReceive, dev);
 869         } else {
 870                 free_irq(priv->interruptTransmit, dev);
 871         }
 872
 873         free_skb_resources(priv);
 874
 875         dma_free_coherent(&priv->ofdev->dev,
 876                         sizeof(struct txbd8)*priv->tx_ring_size
 877                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 878                         priv->tx_bd_base,
 879                         gfar_read(&regs->tbase0));
 880 }
 881
 882 /* If there are any tx skbs or rx skbs still around, free them.
 883  * Then free tx_skbuff and rx_skbuff */
 884 static void free_skb_resources(struct gfar_private *priv)
 885 {
 886         struct rxbd8 *rxbdp;
 887         struct txbd8 *txbdp;
 888         int i, j;
 889
 890         /* Go through all the buffer descriptors and free their data buffers */
 891         txbdp = priv->tx_bd_base;
 892
 893         for (i = 0; i < priv->tx_ring_size; i++) {
 894                 if (!priv->tx_skbuff[i])
 895                         continue;
 896
 897                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
 898                                 txbdp->length, DMA_TO_DEVICE);
 899                 txbdp->lstatus = 0;
 900                 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
 901                         txbdp++;
 902                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
 903                                         txbdp->length, DMA_TO_DEVICE);
 904                 }
 905                 txbdp++;
 906                 dev_kfree_skb_any(priv->tx_skbuff[i]);
 907                 priv->tx_skbuff[i] = NULL;
 908         }
 909
 910         kfree(priv->tx_skbuff);
 911
 912         rxbdp = priv->rx_bd_base;
 913
 914         /* rx_skbuff is not guaranteed to be allocated, so only
 915          * free it and its contents if it is allocated */
 916         if(priv->rx_skbuff != NULL) {
 917                 for (i = 0; i < priv->rx_ring_size; i++) {
 918                         if (priv->rx_skbuff[i]) {
 919                                 dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
 920                                                 priv->rx_buffer_size,
 921                                                 DMA_FROM_DEVICE);
 922
 923                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 924                                 priv->rx_skbuff[i] = NULL;
 925                         }
 926
 927                         rxbdp->lstatus = 0;
 928                         rxbdp->bufPtr = 0;
 929
 930                         rxbdp++;
 931                 }
 932
 933                 kfree(priv->rx_skbuff);
 934         }
 935 }
 936
 937 void gfar_start(struct net_device *dev)
 938 {
 939         struct gfar_private *priv = netdev_priv(dev);
 940         struct gfar __iomem *regs = priv->regs;
 941         u32 tempval;
 942
 943         /* Enable Rx and Tx in MACCFG1 */
 944         tempval = gfar_read(&regs->maccfg1);
 945         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 946         gfar_write(&regs->maccfg1, tempval);
 947
 948         /* Initialize DMACTRL to have WWR and WOP */
 949         tempval = gfar_read(&priv->regs->dmactrl);
 950         tempval |= DMACTRL_INIT_SETTINGS;
 951         gfar_write(&priv->regs->dmactrl, tempval);
 952
 953         /* Make sure we aren't stopped */
 954         tempval = gfar_read(&priv->regs->dmactrl);
 955         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 956         gfar_write(&priv->regs->dmactrl, tempval);
 957
 958         /* Clear THLT/RHLT, so that the DMA starts polling now */
 959         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
 960         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
 961
 962         /* Unmask the interrupts we look for */
 963         gfar_write(&regs->imask, IMASK_DEFAULT);
 964
 965         dev->trans_start = jiffies;
 966 }
 967
 968 /* Bring the controller up and running */
 969 int startup_gfar(struct net_device *dev)
 970 {
 971         struct txbd8 *txbdp;
 972         struct rxbd8 *rxbdp;
 973         dma_addr_t addr = 0;
 974         unsigned long vaddr;
 975         int i;
 976         struct gfar_private *priv = netdev_priv(dev);
 977         struct gfar __iomem *regs = priv->regs;
 978         int err = 0;
 979         u32 rctrl = 0;
 980         u32 attrs = 0;
 981
 982         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 983
 984         /* Allocate memory for the buffer descriptors */
 985         vaddr = (unsigned long) dma_alloc_coherent(&priv->ofdev->dev,
 986                         sizeof (struct txbd8) * priv->tx_ring_size +
 987                         sizeof (struct rxbd8) * priv->rx_ring_size,
 988                         &addr, GFP_KERNEL);
 989
 990         if (vaddr == 0) {
 991                 if (netif_msg_ifup(priv))
 992                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
 993                                         dev->name);
 994                 return -ENOMEM;
 995         }
 996
 997         priv->tx_bd_base = (struct txbd8 *) vaddr;
 998
 999         /* enet DMA only understands physical addresses */
1000         gfar_write(&regs->tbase0, addr);
1001
1002         /* Start the rx descriptor ring where the tx ring leaves off */
1003         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
1004         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
1005         priv->rx_bd_base = (struct rxbd8 *) vaddr;
1006         gfar_write(&regs->rbase0, addr);
1007
1008         /* Setup the skbuff rings */
1009         priv->tx_skbuff =
1010             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
1011                                         priv->tx_ring_size, GFP_KERNEL);
1012
1013         if (NULL == priv->tx_skbuff) {
1014                 if (netif_msg_ifup(priv))
1015                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
1016                                         dev->name);
1017                 err = -ENOMEM;
1018                 goto tx_skb_fail;
1019         }
1020
1021         for (i = 0; i < priv->tx_ring_size; i++)
1022                 priv->tx_skbuff[i] = NULL;
1023
1024         priv->rx_skbuff =
1025             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
1026                                         priv->rx_ring_size, GFP_KERNEL);
1027
1028         if (NULL == priv->rx_skbuff) {
1029                 if (netif_msg_ifup(priv))
1030                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
1031                                         dev->name);
1032                 err = -ENOMEM;
1033                 goto rx_skb_fail;
1034         }
1035
1036         for (i = 0; i < priv->rx_ring_size; i++)
1037                 priv->rx_skbuff[i] = NULL;
1038
1039         /* Initialize some variables in our dev structure */
1040         priv->num_txbdfree = priv->tx_ring_size;
1041         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
1042         priv->cur_rx = priv->rx_bd_base;
1043         priv->skb_curtx = priv->skb_dirtytx = 0;
1044         priv->skb_currx = 0;
1045
1046         /* Initialize Transmit Descriptor Ring */
1047         txbdp = priv->tx_bd_base;
1048         for (i = 0; i < priv->tx_ring_size; i++) {
1049                 txbdp->lstatus = 0;
1050                 txbdp->bufPtr = 0;
1051                 txbdp++;
1052         }
1053
1054         /* Set the last descriptor in the ring to indicate wrap */
1055         txbdp--;
1056         txbdp->status |= TXBD_WRAP;
1057
1058         rxbdp = priv->rx_bd_base;
1059         for (i = 0; i < priv->rx_ring_size; i++) {
1060                 struct sk_buff *skb;
1061
1062                 skb = gfar_new_skb(dev);
1063
1064                 if (!skb) {
1065                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
1066                                         dev->name);
1067
1068                         goto err_rxalloc_fail;
1069                 }
1070
1071                 priv->rx_skbuff[i] = skb;
1072
1073                 gfar_new_rxbdp(dev, rxbdp, skb);
1074
1075                 rxbdp++;
1076         }
1077
1078         /* Set the last descriptor in the ring to wrap */
1079         rxbdp--;
1080         rxbdp->status |= RXBD_WRAP;
1081
1082         /* If the device has multiple interrupts, register for
1083          * them.  Otherwise, only register for the one */
1084         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1085                 /* Install our interrupt handlers for Error,
1086                  * Transmit, and Receive */
1087                 if (request_irq(priv->interruptError, gfar_error,
1088                                 0, priv->int_name_er, dev) < 0) {
1089                         if (netif_msg_intr(priv))
1090                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1091                                         dev->name, priv->interruptError);
1092
1093                         err = -1;
1094                         goto err_irq_fail;
1095                 }
1096
1097                 if (request_irq(priv->interruptTransmit, gfar_transmit,
1098                                 0, priv->int_name_tx, dev) < 0) {
1099                         if (netif_msg_intr(priv))
1100                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1101                                         dev->name, priv->interruptTransmit);
1102
1103                         err = -1;
1104
1105                         goto tx_irq_fail;
1106                 }
1107
1108                 if (request_irq(priv->interruptReceive, gfar_receive,
1109                                 0, priv->int_name_rx, dev) < 0) {
1110                         if (netif_msg_intr(priv))
1111                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1112                                                 dev->name, priv->interruptReceive);
1113
1114                         err = -1;
1115                         goto rx_irq_fail;
1116                 }
1117         } else {
1118                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1119                                 0, priv->int_name_tx, dev) < 0) {
1120                         if (netif_msg_intr(priv))
1121                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1122                                         dev->name, priv->interruptTransmit);
1123
1124                         err = -1;
1125                         goto err_irq_fail;
1126                 }
1127         }
1128
1129         phy_start(priv->phydev);
1130
1131         /* Configure the coalescing support */
1132         gfar_write(&regs->txic, 0);
1133         if (priv->txcoalescing)
1134                 gfar_write(&regs->txic, priv->txic);
1135
1136         gfar_write(&regs->rxic, 0);
1137         if (priv->rxcoalescing)
1138                 gfar_write(&regs->rxic, priv->rxic);
1139
1140         if (priv->rx_csum_enable)
1141                 rctrl |= RCTRL_CHECKSUMMING;
1142
1143         if (priv->extended_hash) {
1144                 rctrl |= RCTRL_EXTHASH;
1145
1146                 gfar_clear_exact_match(dev);
1147                 rctrl |= RCTRL_EMEN;
1148         }
1149
1150         if (priv->padding) {
1151                 rctrl &= ~RCTRL_PAL_MASK;
1152                 rctrl |= RCTRL_PADDING(priv->padding);
1153         }
1154
1155         /* Init rctrl based on our settings */
1156         gfar_write(&priv->regs->rctrl, rctrl);
1157
1158         if (dev->features & NETIF_F_IP_CSUM)
1159                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1160
1161         /* Set the extraction length and index */
1162         attrs = ATTRELI_EL(priv->rx_stash_size) |
1163                 ATTRELI_EI(priv->rx_stash_index);
1164
1165         gfar_write(&priv->regs->attreli, attrs);
1166
1167         /* Start with defaults, and add stashing or locking
1168          * depending on the approprate variables */
1169         attrs = ATTR_INIT_SETTINGS;
1170
1171         if (priv->bd_stash_en)
1172                 attrs |= ATTR_BDSTASH;
1173
1174         if (priv->rx_stash_size != 0)
1175                 attrs |= ATTR_BUFSTASH;
1176
1177         gfar_write(&priv->regs->attr, attrs);
1178
1179         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1180         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1181         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1182
1183         /* Start the controller */
1184         gfar_start(dev);
1185
1186         return 0;
1187
1188 rx_irq_fail:
1189         free_irq(priv->interruptTransmit, dev);
1190 tx_irq_fail:
1191         free_irq(priv->interruptError, dev);
1192 err_irq_fail:
1193 err_rxalloc_fail:
1194 rx_skb_fail:
1195         free_skb_resources(priv);
1196 tx_skb_fail:
1197         dma_free_coherent(&priv->ofdev->dev,
1198                         sizeof(struct txbd8)*priv->tx_ring_size
1199                         + sizeof(struct rxbd8)*priv->rx_ring_size,
1200                         priv->tx_bd_base,
1201                         gfar_read(&regs->tbase0));
1202
1203         return err;
1204 }
1205
1206 /* Called when something needs to use the ethernet device */
1207 /* Returns 0 for success. */
1208 static int gfar_enet_open(struct net_device *dev)
1209 {
1210         struct gfar_private *priv = netdev_priv(dev);
1211         int err;
1212
1213         napi_enable(&priv->napi);
1214
1215         skb_queue_head_init(&priv->rx_recycle);
1216
1217         /* Initialize a bunch of registers */
1218         init_registers(dev);
1219
1220         gfar_set_mac_address(dev);
1221
1222         err = init_phy(dev);
1223
1224         if(err) {
1225                 napi_disable(&priv->napi);
1226                 return err;
1227         }
1228
1229         err = startup_gfar(dev);
1230         if (err) {
1231                 napi_disable(&priv->napi);
1232                 return err;
1233         }
1234
1235         netif_start_queue(dev);
1236
1237         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1238
1239         return err;
1240 }
1241
1242 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1243 {
1244         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1245         cacheable_memzero(fcb, GMAC_FCB_LEN);
1246
1247         return fcb;
1248 }
1249
1250 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1251 {
1252         u8 flags = 0;
1253
1254         /* If we're here, it's a IP packet with a TCP or UDP
1255          * payload.  We set it to checksum, using a pseudo-header
1256          * we provide
1257          */
1258         flags = TXFCB_DEFAULT;
1259
1260         /* Tell the controller what the protocol is */
1261         /* And provide the already calculated phcs */
1262         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1263                 flags |= TXFCB_UDP;
1264                 fcb->phcs = udp_hdr(skb)->check;
1265         } else
1266                 fcb->phcs = tcp_hdr(skb)->check;
1267
1268         /* l3os is the distance between the start of the
1269          * frame (skb->data) and the start of the IP hdr.
1270          * l4os is the distance between the start of the
1271          * l3 hdr and the l4 hdr */
1272         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1273         fcb->l4os = skb_network_header_len(skb);
1274
1275         fcb->flags = flags;
1276 }
1277
1278 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1279 {
1280         fcb->flags |= TXFCB_VLN;
1281         fcb->vlctl = vlan_tx_tag_get(skb);
1282 }
1283
1284 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1285                                struct txbd8 *base, int ring_size)
1286 {
1287         struct txbd8 *new_bd = bdp + stride;
1288
1289         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1290 }
1291
1292 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1293                 int ring_size)
1294 {
1295         return skip_txbd(bdp, 1, base, ring_size);
1296 }
1297
1298 /* This is called by the kernel when a frame is ready for transmission. */
1299 /* It is pointed to by the dev->hard_start_xmit function pointer */
1300 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1301 {
1302         struct gfar_private *priv = netdev_priv(dev);
1303         struct txfcb *fcb = NULL;
1304         struct txbd8 *txbdp, *txbdp_start, *base;
1305         u32 lstatus;
1306         int i;
1307         u32 bufaddr;
1308         unsigned long flags;
1309         unsigned int nr_frags, length;
1310
1311         base = priv->tx_bd_base;
1312
1313         /* make space for additional header when fcb is needed */
1314         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1315                         (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1316                         (skb_headroom(skb) < GMAC_FCB_LEN)) {
1317                 struct sk_buff *skb_new;
1318
1319                 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1320                 if (!skb_new) {
1321                         dev->stats.tx_errors++;
1322                         kfree_skb(skb);
1323                         return NETDEV_TX_OK;
1324                 }
1325                 kfree_skb(skb);
1326                 skb = skb_new;
1327         }
1328
1329         /* total number of fragments in the SKB */
1330         nr_frags = skb_shinfo(skb)->nr_frags;
1331
1332         spin_lock_irqsave(&priv->txlock, flags);
1333
1334         /* check if there is space to queue this packet */
1335         if ((nr_frags+1) > priv->num_txbdfree) {
1336                 /* no space, stop the queue */
1337                 netif_stop_queue(dev);
1338                 dev->stats.tx_fifo_errors++;
1339                 spin_unlock_irqrestore(&priv->txlock, flags);
1340                 return NETDEV_TX_BUSY;
1341         }
1342
1343         /* Update transmit stats */
1344         dev->stats.tx_bytes += skb->len;
1345
1346         txbdp = txbdp_start = priv->cur_tx;
1347
1348         if (nr_frags == 0) {
1349                 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1350         } else {
1351                 /* Place the fragment addresses and lengths into the TxBDs */
1352                 for (i = 0; i < nr_frags; i++) {
1353                         /* Point at the next BD, wrapping as needed */
1354                         txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1355
1356                         length = skb_shinfo(skb)->frags[i].size;
1357
1358                         lstatus = txbdp->lstatus | length |
1359                                 BD_LFLAG(TXBD_READY);
1360
1361                         /* Handle the last BD specially */
1362                         if (i == nr_frags - 1)
1363                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1364
1365                         bufaddr = dma_map_page(&priv->ofdev->dev,
1366                                         skb_shinfo(skb)->frags[i].page,
1367                                         skb_shinfo(skb)->frags[i].page_offset,
1368                                         length,
1369                                         DMA_TO_DEVICE);
1370
1371                         /* set the TxBD length and buffer pointer */
1372                         txbdp->bufPtr = bufaddr;
1373                         txbdp->lstatus = lstatus;
1374                 }
1375
1376                 lstatus = txbdp_start->lstatus;
1377         }
1378
1379         /* Set up checksumming */
1380         if (CHECKSUM_PARTIAL == skb->ip_summed) {
1381                 fcb = gfar_add_fcb(skb);
1382                 lstatus |= BD_LFLAG(TXBD_TOE);
1383                 gfar_tx_checksum(skb, fcb);
1384         }
1385
1386         if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1387                 if (unlikely(NULL == fcb)) {
1388                         fcb = gfar_add_fcb(skb);
1389                         lstatus |= BD_LFLAG(TXBD_TOE);
1390                 }
1391
1392                 gfar_tx_vlan(skb, fcb);
1393         }
1394
1395         /* setup the TxBD length and buffer pointer for the first BD */
1396         priv->tx_skbuff[priv->skb_curtx] = skb;
1397         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1398                         skb_headlen(skb), DMA_TO_DEVICE);
1399
1400         lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1401
1402         /*
1403          * The powerpc-specific eieio() is used, as wmb() has too strong
1404          * semantics (it requires synchronization between cacheable and
1405          * uncacheable mappings, which eieio doesn't provide and which we
1406          * don't need), thus requiring a more expensive sync instruction.  At
1407          * some point, the set of architecture-independent barrier functions
1408          * should be expanded to include weaker barriers.
1409          */
1410         eieio();
1411
1412         txbdp_start->lstatus = lstatus;
1413
1414         /* Update the current skb pointer to the next entry we will use
1415          * (wrapping if necessary) */
1416         priv->skb_curtx = (priv->skb_curtx + 1) &
1417                 TX_RING_MOD_MASK(priv->tx_ring_size);
1418
1419         priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1420
1421         /* reduce TxBD free count */
1422         priv->num_txbdfree -= (nr_frags + 1);
1423
1424         dev->trans_start = jiffies;
1425
1426         /* If the next BD still needs to be cleaned up, then the bds
1427            are full.  We need to tell the kernel to stop sending us stuff. */
1428         if (!priv->num_txbdfree) {
1429                 netif_stop_queue(dev);
1430
1431                 dev->stats.tx_fifo_errors++;
1432         }
1433
1434         /* Tell the DMA to go go go */
1435         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1436
1437         /* Unlock priv */
1438         spin_unlock_irqrestore(&priv->txlock, flags);
1439
1440         return NETDEV_TX_OK;
1441 }
1442
1443 /* Stops the kernel queue, and halts the controller */
1444 static int gfar_close(struct net_device *dev)
1445 {
1446         struct gfar_private *priv = netdev_priv(dev);
1447
1448         napi_disable(&priv->napi);
1449
1450         skb_queue_purge(&priv->rx_recycle);
1451         cancel_work_sync(&priv->reset_task);
1452         stop_gfar(dev);
1453
1454         /* Disconnect from the PHY */
1455         phy_disconnect(priv->phydev);
1456         priv->phydev = NULL;
1457
1458         netif_stop_queue(dev);
1459
1460         return 0;
1461 }
1462
1463 /* Changes the mac address if the controller is not running. */
1464 static int gfar_set_mac_address(struct net_device *dev)
1465 {
1466         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1467
1468         return 0;
1469 }
1470
1471
1472 /* Enables and disables VLAN insertion/extraction */
1473 static void gfar_vlan_rx_register(struct net_device *dev,
1474                 struct vlan_group *grp)
1475 {
1476         struct gfar_private *priv = netdev_priv(dev);
1477         unsigned long flags;
1478         u32 tempval;
1479
1480         spin_lock_irqsave(&priv->rxlock, flags);
1481
1482         priv->vlgrp = grp;
1483
1484         if (grp) {
1485                 /* Enable VLAN tag insertion */
1486                 tempval = gfar_read(&priv->regs->tctrl);
1487                 tempval |= TCTRL_VLINS;
1488
1489                 gfar_write(&priv->regs->tctrl, tempval);
1490
1491                 /* Enable VLAN tag extraction */
1492                 tempval = gfar_read(&priv->regs->rctrl);
1493                 tempval |= RCTRL_VLEX;
1494                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1495                 gfar_write(&priv->regs->rctrl, tempval);
1496         } else {
1497                 /* Disable VLAN tag insertion */
1498                 tempval = gfar_read(&priv->regs->tctrl);
1499                 tempval &= ~TCTRL_VLINS;
1500                 gfar_write(&priv->regs->tctrl, tempval);
1501
1502                 /* Disable VLAN tag extraction */
1503                 tempval = gfar_read(&priv->regs->rctrl);
1504                 tempval &= ~RCTRL_VLEX;
1505                 /* If parse is no longer required, then disable parser */
1506                 if (tempval & RCTRL_REQ_PARSER)
1507                         tempval |= RCTRL_PRSDEP_INIT;
1508                 else
1509                         tempval &= ~RCTRL_PRSDEP_INIT;
1510                 gfar_write(&priv->regs->rctrl, tempval);
1511         }
1512
1513         gfar_change_mtu(dev, dev->mtu);
1514
1515         spin_unlock_irqrestore(&priv->rxlock, flags);
1516 }
1517
1518 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1519 {
1520         int tempsize, tempval;
1521         struct gfar_private *priv = netdev_priv(dev);
1522         int oldsize = priv->rx_buffer_size;
1523         int frame_size = new_mtu + ETH_HLEN;
1524
1525         if (priv->vlgrp)
1526                 frame_size += VLAN_HLEN;
1527
1528         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1529                 if (netif_msg_drv(priv))
1530                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1531                                         dev->name);
1532                 return -EINVAL;
1533         }
1534
1535         if (gfar_uses_fcb(priv))
1536                 frame_size += GMAC_FCB_LEN;
1537
1538         frame_size += priv->padding;
1539
1540         tempsize =
1541             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1542             INCREMENTAL_BUFFER_SIZE;
1543
1544         /* Only stop and start the controller if it isn't already
1545          * stopped, and we changed something */
1546         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1547                 stop_gfar(dev);
1548
1549         priv->rx_buffer_size = tempsize;
1550
1551         dev->mtu = new_mtu;
1552
1553         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1554         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1555
1556         /* If the mtu is larger than the max size for standard
1557          * ethernet frames (ie, a jumbo frame), then set maccfg2
1558          * to allow huge frames, and to check the length */
1559         tempval = gfar_read(&priv->regs->maccfg2);
1560
1561         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1562                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1563         else
1564                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1565
1566         gfar_write(&priv->regs->maccfg2, tempval);
1567
1568         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1569                 startup_gfar(dev);
1570
1571         return 0;
1572 }
1573
1574 /* gfar_reset_task gets scheduled when a packet has not been
1575  * transmitted after a set amount of time.
1576  * For now, assume that clearing out all the structures, and
1577  * starting over will fix the problem.
1578  */
1579 static void gfar_reset_task(struct work_struct *work)
1580 {
1581         struct gfar_private *priv = container_of(work, struct gfar_private,
1582                         reset_task);
1583         struct net_device *dev = priv->ndev;
1584
1585         if (dev->flags & IFF_UP) {
1586                 netif_stop_queue(dev);
1587                 stop_gfar(dev);
1588                 startup_gfar(dev);
1589                 netif_start_queue(dev);
1590         }
1591
1592         netif_tx_schedule_all(dev);
1593 }
1594
1595 static void gfar_timeout(struct net_device *dev)
1596 {
1597         struct gfar_private *priv = netdev_priv(dev);
1598
1599         dev->stats.tx_errors++;
1600         schedule_work(&priv->reset_task);
1601 }
1602
1603 /* Interrupt Handler for Transmit complete */
1604 static int gfar_clean_tx_ring(struct net_device *dev)
1605 {
1606         struct gfar_private *priv = netdev_priv(dev);
1607         struct txbd8 *bdp;
1608         struct txbd8 *lbdp = NULL;
1609         struct txbd8 *base = priv->tx_bd_base;
1610         struct sk_buff *skb;
1611         int skb_dirtytx;
1612         int tx_ring_size = priv->tx_ring_size;
1613         int frags = 0;
1614         int i;
1615         int howmany = 0;
1616         u32 lstatus;
1617
1618         bdp = priv->dirty_tx;
1619         skb_dirtytx = priv->skb_dirtytx;
1620
1621         while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1622                 frags = skb_shinfo(skb)->nr_frags;
1623                 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1624
1625                 lstatus = lbdp->lstatus;
1626
1627                 /* Only clean completed frames */
1628                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1629                                 (lstatus & BD_LENGTH_MASK))
1630                         break;
1631
1632                 dma_unmap_single(&priv->ofdev->dev,
1633                                 bdp->bufPtr,
1634                                 bdp->length,
1635                                 DMA_TO_DEVICE);
1636
1637                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1638                 bdp = next_txbd(bdp, base, tx_ring_size);
1639
1640                 for (i = 0; i < frags; i++) {
1641                         dma_unmap_page(&priv->ofdev->dev,
1642                                         bdp->bufPtr,
1643                                         bdp->length,
1644                                         DMA_TO_DEVICE);
1645                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1646                         bdp = next_txbd(bdp, base, tx_ring_size);
1647                 }
1648
1649                 /*
1650                  * If there's room in the queue (limit it to rx_buffer_size)
1651                  * we add this skb back into the pool, if it's the right size
1652                  */
1653                 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1654                                 skb_recycle_check(skb, priv->rx_buffer_size +
1655                                         RXBUF_ALIGNMENT))
1656                         __skb_queue_head(&priv->rx_recycle, skb);
1657                 else
1658                         dev_kfree_skb_any(skb);
1659
1660                 priv->tx_skbuff[skb_dirtytx] = NULL;
1661
1662                 skb_dirtytx = (skb_dirtytx + 1) &
1663                         TX_RING_MOD_MASK(tx_ring_size);
1664
1665                 howmany++;
1666                 priv->num_txbdfree += frags + 1;
1667         }
1668
1669         /* If we freed a buffer, we can restart transmission, if necessary */
1670         if (netif_queue_stopped(dev) && priv->num_txbdfree)
1671                 netif_wake_queue(dev);
1672
1673         /* Update dirty indicators */
1674         priv->skb_dirtytx = skb_dirtytx;
1675         priv->dirty_tx = bdp;
1676
1677         dev->stats.tx_packets += howmany;
1678
1679         return howmany;
1680 }
1681
1682 static void gfar_schedule_cleanup(struct net_device *dev)
1683 {
1684         struct gfar_private *priv = netdev_priv(dev);
1685         unsigned long flags;
1686
1687         spin_lock_irqsave(&priv->txlock, flags);
1688         spin_lock(&priv->rxlock);
1689
1690         if (napi_schedule_prep(&priv->napi)) {
1691                 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1692                 __napi_schedule(&priv->napi);
1693         } else {
1694                 /*
1695                  * Clear IEVENT, so interrupts aren't called again
1696                  * because of the packets that have already arrived.
1697                  */
1698                 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1699         }
1700
1701         spin_unlock(&priv->rxlock);
1702         spin_unlock_irqrestore(&priv->txlock, flags);
1703 }
1704
1705 /* Interrupt Handler for Transmit complete */
1706 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1707 {
1708         gfar_schedule_cleanup((struct net_device *)dev_id);
1709         return IRQ_HANDLED;
1710 }
1711
1712 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1713                 struct sk_buff *skb)
1714 {
1715         struct gfar_private *priv = netdev_priv(dev);
1716         u32 lstatus;
1717
1718         bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1719                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1720
1721         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1722
1723         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1724                 lstatus |= BD_LFLAG(RXBD_WRAP);
1725
1726         eieio();
1727
1728         bdp->lstatus = lstatus;
1729 }
1730
1731
1732 struct sk_buff * gfar_new_skb(struct net_device *dev)
1733 {
1734         unsigned int alignamount;
1735         struct gfar_private *priv = netdev_priv(dev);
1736         struct sk_buff *skb = NULL;
1737
1738         skb = __skb_dequeue(&priv->rx_recycle);
1739         if (!skb)
1740                 skb = netdev_alloc_skb(dev,
1741                                 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1742
1743         if (!skb)
1744                 return NULL;
1745
1746         alignamount = RXBUF_ALIGNMENT -
1747                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1748
1749         /* We need the data buffer to be aligned properly.  We will reserve
1750          * as many bytes as needed to align the data properly
1751          */
1752         skb_reserve(skb, alignamount);
1753
1754         return skb;
1755 }
1756
1757 static inline void count_errors(unsigned short status, struct net_device *dev)
1758 {
1759         struct gfar_private *priv = netdev_priv(dev);
1760         struct net_device_stats *stats = &dev->stats;
1761         struct gfar_extra_stats *estats = &priv->extra_stats;
1762
1763         /* If the packet was truncated, none of the other errors
1764          * matter */
1765         if (status & RXBD_TRUNCATED) {
1766                 stats->rx_length_errors++;
1767
1768                 estats->rx_trunc++;
1769
1770                 return;
1771         }
1772         /* Count the errors, if there were any */
1773         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1774                 stats->rx_length_errors++;
1775
1776                 if (status & RXBD_LARGE)
1777                         estats->rx_large++;
1778                 else
1779                         estats->rx_short++;
1780         }
1781         if (status & RXBD_NONOCTET) {
1782                 stats->rx_frame_errors++;
1783                 estats->rx_nonoctet++;
1784         }
1785         if (status & RXBD_CRCERR) {
1786                 estats->rx_crcerr++;
1787                 stats->rx_crc_errors++;
1788         }
1789         if (status & RXBD_OVERRUN) {
1790                 estats->rx_overrun++;
1791                 stats->rx_crc_errors++;
1792         }
1793 }
1794
1795 irqreturn_t gfar_receive(int irq, void *dev_id)
1796 {
1797         gfar_schedule_cleanup((struct net_device *)dev_id);
1798         return IRQ_HANDLED;
1799 }
1800
1801 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1802 {
1803         /* If valid headers were found, and valid sums
1804          * were verified, then we tell the kernel that no
1805          * checksumming is necessary.  Otherwise, it is */
1806         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1807                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1808         else
1809                 skb->ip_summed = CHECKSUM_NONE;
1810 }
1811
1812
1813 /* gfar_process_frame() -- handle one incoming packet if skb
1814  * isn't NULL.  */
1815 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1816                               int amount_pull)
1817 {
1818         struct gfar_private *priv = netdev_priv(dev);
1819         struct rxfcb *fcb = NULL;
1820
1821         int ret;
1822
1823         /* fcb is at the beginning if exists */
1824         fcb = (struct rxfcb *)skb->data;
1825
1826         /* Remove the FCB from the skb */
1827         /* Remove the padded bytes, if there are any */
1828         if (amount_pull)
1829                 skb_pull(skb, amount_pull);
1830
1831         if (priv->rx_csum_enable)
1832                 gfar_rx_checksum(skb, fcb);
1833
1834         /* Tell the skb what kind of packet this is */
1835         skb->protocol = eth_type_trans(skb, dev);
1836
1837         /* Send the packet up the stack */
1838         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1839                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1840         else
1841                 ret = netif_receive_skb(skb);
1842
1843         if (NET_RX_DROP == ret)
1844                 priv->extra_stats.kernel_dropped++;
1845
1846         return 0;
1847 }
1848
1849 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1850  *   until the budget/quota has been reached. Returns the number
1851  *   of frames handled
1852  */
1853 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1854 {
1855         struct rxbd8 *bdp, *base;
1856         struct sk_buff *skb;
1857         int pkt_len;
1858         int amount_pull;
1859         int howmany = 0;
1860         struct gfar_private *priv = netdev_priv(dev);
1861
1862         /* Get the first full descriptor */
1863         bdp = priv->cur_rx;
1864         base = priv->rx_bd_base;
1865
1866         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1867                 priv->padding;
1868
1869         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1870                 struct sk_buff *newskb;
1871                 rmb();
1872
1873                 /* Add another skb for the future */
1874                 newskb = gfar_new_skb(dev);
1875
1876                 skb = priv->rx_skbuff[priv->skb_currx];
1877
1878                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
1879                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
1880
1881                 /* We drop the frame if we failed to allocate a new buffer */
1882                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1883                                  bdp->status & RXBD_ERR)) {
1884                         count_errors(bdp->status, dev);
1885
1886                         if (unlikely(!newskb))
1887                                 newskb = skb;
1888                         else if (skb)
1889                                 __skb_queue_head(&priv->rx_recycle, skb);
1890                 } else {
1891                         /* Increment the number of packets */
1892                         dev->stats.rx_packets++;
1893                         howmany++;
1894
1895                         if (likely(skb)) {
1896                                 pkt_len = bdp->length - ETH_FCS_LEN;
1897                                 /* Remove the FCS from the packet length */
1898                                 skb_put(skb, pkt_len);
1899                                 dev->stats.rx_bytes += pkt_len;
1900
1901                                 if (in_irq() || irqs_disabled())
1902                                         printk("Interrupt problem!\n");
1903                                 gfar_process_frame(dev, skb, amount_pull);
1904
1905                         } else {
1906                                 if (netif_msg_rx_err(priv))
1907                                         printk(KERN_WARNING
1908                                                "%s: Missing skb!\n", dev->name);
1909                                 dev->stats.rx_dropped++;
1910                                 priv->extra_stats.rx_skbmissing++;
1911                         }
1912
1913                 }
1914
1915                 priv->rx_skbuff[priv->skb_currx] = newskb;
1916
1917                 /* Setup the new bdp */
1918                 gfar_new_rxbdp(dev, bdp, newskb);
1919
1920                 /* Update to the next pointer */
1921                 bdp = next_bd(bdp, base, priv->rx_ring_size);
1922
1923                 /* update to point at the next skb */
1924                 priv->skb_currx =
1925                     (priv->skb_currx + 1) &
1926                     RX_RING_MOD_MASK(priv->rx_ring_size);
1927         }
1928
1929         /* Update the current rxbd pointer to be the next one */
1930         priv->cur_rx = bdp;
1931
1932         return howmany;
1933 }
1934
1935 static int gfar_poll(struct napi_struct *napi, int budget)
1936 {
1937         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1938         struct net_device *dev = priv->ndev;
1939         int tx_cleaned = 0;
1940         int rx_cleaned = 0;
1941         unsigned long flags;
1942
1943         /* Clear IEVENT, so interrupts aren't called again
1944          * because of the packets that have already arrived */
1945         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1946
1947         /* If we fail to get the lock, don't bother with the TX BDs */
1948         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1949                 tx_cleaned = gfar_clean_tx_ring(dev);
1950                 spin_unlock_irqrestore(&priv->txlock, flags);
1951         }
1952
1953         rx_cleaned = gfar_clean_rx_ring(dev, budget);
1954
1955         if (tx_cleaned)
1956                 return budget;
1957
1958         if (rx_cleaned < budget) {
1959                 napi_complete(napi);
1960
1961                 /* Clear the halt bit in RSTAT */
1962                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1963
1964                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1965
1966                 /* If we are coalescing interrupts, update the timer */
1967                 /* Otherwise, clear it */
1968                 if (likely(priv->rxcoalescing)) {
1969                         gfar_write(&priv->regs->rxic, 0);
1970                         gfar_write(&priv->regs->rxic, priv->rxic);
1971                 }
1972                 if (likely(priv->txcoalescing)) {
1973                         gfar_write(&priv->regs->txic, 0);
1974                         gfar_write(&priv->regs->txic, priv->txic);
1975                 }
1976         }
1977
1978         return rx_cleaned;
1979 }
1980
1981 #ifdef CONFIG_NET_POLL_CONTROLLER
1982 /*
1983  * Polling 'interrupt' - used by things like netconsole to send skbs
1984  * without having to re-enable interrupts. It's not called while
1985  * the interrupt routine is executing.
1986  */
1987 static void gfar_netpoll(struct net_device *dev)
1988 {
1989         struct gfar_private *priv = netdev_priv(dev);
1990
1991         /* If the device has multiple interrupts, run tx/rx */
1992         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1993                 disable_irq(priv->interruptTransmit);
1994                 disable_irq(priv->interruptReceive);
1995                 disable_irq(priv->interruptError);
1996                 gfar_interrupt(priv->interruptTransmit, dev);
1997                 enable_irq(priv->interruptError);
1998                 enable_irq(priv->interruptReceive);
1999                 enable_irq(priv->interruptTransmit);
2000         } else {
2001                 disable_irq(priv->interruptTransmit);
2002                 gfar_interrupt(priv->interruptTransmit, dev);
2003                 enable_irq(priv->interruptTransmit);
2004         }
2005 }
2006 #endif
2007
2008 /* The interrupt handler for devices with one interrupt */
2009 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
2010 {
2011         struct net_device *dev = dev_id;
2012         struct gfar_private *priv = netdev_priv(dev);
2013
2014         /* Save ievent for future reference */
2015         u32 events = gfar_read(&priv->regs->ievent);
2016
2017         /* Check for reception */
2018         if (events & IEVENT_RX_MASK)
2019                 gfar_receive(irq, dev_id);
2020
2021         /* Check for transmit completion */
2022         if (events & IEVENT_TX_MASK)
2023                 gfar_transmit(irq, dev_id);
2024
2025         /* Check for errors */
2026         if (events & IEVENT_ERR_MASK)
2027                 gfar_error(irq, dev_id);
2028
2029         return IRQ_HANDLED;
2030 }
2031
2032 /* Called every time the controller might need to be made
2033  * aware of new link state.  The PHY code conveys this
2034  * information through variables in the phydev structure, and this
2035  * function converts those variables into the appropriate
2036  * register values, and can bring down the device if needed.
2037  */
2038 static void adjust_link(struct net_device *dev)
2039 {
2040         struct gfar_private *priv = netdev_priv(dev);
2041         struct gfar __iomem *regs = priv->regs;
2042         unsigned long flags;
2043         struct phy_device *phydev = priv->phydev;
2044         int new_state = 0;
2045
2046         spin_lock_irqsave(&priv->txlock, flags);
2047         if (phydev->link) {
2048                 u32 tempval = gfar_read(&regs->maccfg2);
2049                 u32 ecntrl = gfar_read(&regs->ecntrl);
2050
2051                 /* Now we make sure that we can be in full duplex mode.
2052                  * If not, we operate in half-duplex mode. */
2053                 if (phydev->duplex != priv->oldduplex) {
2054                         new_state = 1;
2055                         if (!(phydev->duplex))
2056                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2057                         else
2058                                 tempval |= MACCFG2_FULL_DUPLEX;
2059
2060                         priv->oldduplex = phydev->duplex;
2061                 }
2062
2063                 if (phydev->speed != priv->oldspeed) {
2064                         new_state = 1;
2065                         switch (phydev->speed) {
2066                         case 1000:
2067                                 tempval =
2068                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2069
2070                                 ecntrl &= ~(ECNTRL_R100);
2071                                 break;
2072                         case 100:
2073                         case 10:
2074                                 tempval =
2075                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2076
2077                                 /* Reduced mode distinguishes
2078                                  * between 10 and 100 */
2079                                 if (phydev->speed == SPEED_100)
2080                                         ecntrl |= ECNTRL_R100;
2081                                 else
2082                                         ecntrl &= ~(ECNTRL_R100);
2083                                 break;
2084                         default:
2085                                 if (netif_msg_link(priv))
2086                                         printk(KERN_WARNING
2087                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
2088                                                 dev->name, phydev->speed);
2089                                 break;
2090                         }
2091
2092                         priv->oldspeed = phydev->speed;
2093                 }
2094
2095                 gfar_write(&regs->maccfg2, tempval);
2096                 gfar_write(&regs->ecntrl, ecntrl);
2097
2098                 if (!priv->oldlink) {
2099                         new_state = 1;
2100                         priv->oldlink = 1;
2101                 }
2102         } else if (priv->oldlink) {
2103                 new_state = 1;
2104                 priv->oldlink = 0;
2105                 priv->oldspeed = 0;
2106                 priv->oldduplex = -1;
2107         }
2108
2109         if (new_state && netif_msg_link(priv))
2110                 phy_print_status(phydev);
2111
2112         spin_unlock_irqrestore(&priv->txlock, flags);
2113 }
2114
2115 /* Update the hash table based on the current list of multicast
2116  * addresses we subscribe to.  Also, change the promiscuity of
2117  * the device based on the flags (this function is called
2118  * whenever dev->flags is changed */
2119 static void gfar_set_multi(struct net_device *dev)
2120 {
2121         struct dev_mc_list *mc_ptr;
2122         struct gfar_private *priv = netdev_priv(dev);
2123         struct gfar __iomem *regs = priv->regs;
2124         u32 tempval;
2125
2126         if(dev->flags & IFF_PROMISC) {
2127                 /* Set RCTRL to PROM */
2128                 tempval = gfar_read(&regs->rctrl);
2129                 tempval |= RCTRL_PROM;
2130                 gfar_write(&regs->rctrl, tempval);
2131         } else {
2132                 /* Set RCTRL to not PROM */
2133                 tempval = gfar_read(&regs->rctrl);
2134                 tempval &= ~(RCTRL_PROM);
2135                 gfar_write(&regs->rctrl, tempval);
2136         }
2137
2138         if(dev->flags & IFF_ALLMULTI) {
2139                 /* Set the hash to rx all multicast frames */
2140                 gfar_write(&regs->igaddr0, 0xffffffff);
2141                 gfar_write(&regs->igaddr1, 0xffffffff);
2142                 gfar_write(&regs->igaddr2, 0xffffffff);
2143                 gfar_write(&regs->igaddr3, 0xffffffff);
2144                 gfar_write(&regs->igaddr4, 0xffffffff);
2145                 gfar_write(&regs->igaddr5, 0xffffffff);
2146                 gfar_write(&regs->igaddr6, 0xffffffff);
2147                 gfar_write(&regs->igaddr7, 0xffffffff);
2148                 gfar_write(&regs->gaddr0, 0xffffffff);
2149                 gfar_write(&regs->gaddr1, 0xffffffff);
2150                 gfar_write(&regs->gaddr2, 0xffffffff);
2151                 gfar_write(&regs->gaddr3, 0xffffffff);
2152                 gfar_write(&regs->gaddr4, 0xffffffff);
2153                 gfar_write(&regs->gaddr5, 0xffffffff);
2154                 gfar_write(&regs->gaddr6, 0xffffffff);
2155                 gfar_write(&regs->gaddr7, 0xffffffff);
2156         } else {
2157                 int em_num;
2158                 int idx;
2159
2160                 /* zero out the hash */
2161                 gfar_write(&regs->igaddr0, 0x0);
2162                 gfar_write(&regs->igaddr1, 0x0);
2163                 gfar_write(&regs->igaddr2, 0x0);
2164                 gfar_write(&regs->igaddr3, 0x0);
2165                 gfar_write(&regs->igaddr4, 0x0);
2166                 gfar_write(&regs->igaddr5, 0x0);
2167                 gfar_write(&regs->igaddr6, 0x0);
2168                 gfar_write(&regs->igaddr7, 0x0);
2169                 gfar_write(&regs->gaddr0, 0x0);
2170                 gfar_write(&regs->gaddr1, 0x0);
2171                 gfar_write(&regs->gaddr2, 0x0);
2172                 gfar_write(&regs->gaddr3, 0x0);
2173                 gfar_write(&regs->gaddr4, 0x0);
2174                 gfar_write(&regs->gaddr5, 0x0);
2175                 gfar_write(&regs->gaddr6, 0x0);
2176                 gfar_write(&regs->gaddr7, 0x0);
2177
2178                 /* If we have extended hash tables, we need to
2179                  * clear the exact match registers to prepare for
2180                  * setting them */
2181                 if (priv->extended_hash) {
2182                         em_num = GFAR_EM_NUM + 1;
2183                         gfar_clear_exact_match(dev);
2184                         idx = 1;
2185                 } else {
2186                         idx = 0;
2187                         em_num = 0;
2188                 }
2189
2190                 if(dev->mc_count == 0)
2191                         return;
2192
2193                 /* Parse the list, and set the appropriate bits */
2194                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2195                         if (idx < em_num) {
2196                                 gfar_set_mac_for_addr(dev, idx,
2197                                                 mc_ptr->dmi_addr);
2198                                 idx++;
2199                         } else
2200                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2201                 }
2202         }
2203
2204         return;
2205 }
2206
2207
2208 /* Clears each of the exact match registers to zero, so they
2209  * don't interfere with normal reception */
2210 static void gfar_clear_exact_match(struct net_device *dev)
2211 {
2212         int idx;
2213         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2214
2215         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2216                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2217 }
2218
2219 /* Set the appropriate hash bit for the given addr */
2220 /* The algorithm works like so:
2221  * 1) Take the Destination Address (ie the multicast address), and
2222  * do a CRC on it (little endian), and reverse the bits of the
2223  * result.
2224  * 2) Use the 8 most significant bits as a hash into a 256-entry
2225  * table.  The table is controlled through 8 32-bit registers:
2226  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2227  * gaddr7.  This means that the 3 most significant bits in the
2228  * hash index which gaddr register to use, and the 5 other bits
2229  * indicate which bit (assuming an IBM numbering scheme, which
2230  * for PowerPC (tm) is usually the case) in the register holds
2231  * the entry. */
2232 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2233 {
2234         u32 tempval;
2235         struct gfar_private *priv = netdev_priv(dev);
2236         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2237         int width = priv->hash_width;
2238         u8 whichbit = (result >> (32 - width)) & 0x1f;
2239         u8 whichreg = result >> (32 - width + 5);
2240         u32 value = (1 << (31-whichbit));
2241
2242         tempval = gfar_read(priv->hash_regs[whichreg]);
2243         tempval |= value;
2244         gfar_write(priv->hash_regs[whichreg], tempval);
2245
2246         return;
2247 }
2248
2249
2250 /* There are multiple MAC Address register pairs on some controllers
2251  * This function sets the numth pair to a given address
2252  */
2253 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2254 {
2255         struct gfar_private *priv = netdev_priv(dev);
2256         int idx;
2257         char tmpbuf[MAC_ADDR_LEN];
2258         u32 tempval;
2259         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2260
2261         macptr += num*2;
2262
2263         /* Now copy it into the mac registers backwards, cuz */
2264         /* little endian is silly */
2265         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2266                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2267
2268         gfar_write(macptr, *((u32 *) (tmpbuf)));
2269
2270         tempval = *((u32 *) (tmpbuf + 4));
2271
2272         gfar_write(macptr+1, tempval);
2273 }
2274
2275 /* GFAR error interrupt handler */
2276 static irqreturn_t gfar_error(int irq, void *dev_id)
2277 {
2278         struct net_device *dev = dev_id;
2279         struct gfar_private *priv = netdev_priv(dev);
2280
2281         /* Save ievent for future reference */
2282         u32 events = gfar_read(&priv->regs->ievent);
2283
2284         /* Clear IEVENT */
2285         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2286
2287         /* Magic Packet is not an error. */
2288         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2289             (events & IEVENT_MAG))
2290                 events &= ~IEVENT_MAG;
2291
2292         /* Hmm... */
2293         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2294                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2295                        dev->name, events, gfar_read(&priv->regs->imask));
2296
2297         /* Update the error counters */
2298         if (events & IEVENT_TXE) {
2299                 dev->stats.tx_errors++;
2300
2301                 if (events & IEVENT_LC)
2302                         dev->stats.tx_window_errors++;
2303                 if (events & IEVENT_CRL)
2304                         dev->stats.tx_aborted_errors++;
2305                 if (events & IEVENT_XFUN) {
2306                         if (netif_msg_tx_err(priv))
2307                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2308                                        "packet dropped.\n", dev->name);
2309                         dev->stats.tx_dropped++;
2310                         priv->extra_stats.tx_underrun++;
2311
2312                         /* Reactivate the Tx Queues */
2313                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2314                 }
2315                 if (netif_msg_tx_err(priv))
2316                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2317         }
2318         if (events & IEVENT_BSY) {
2319                 dev->stats.rx_errors++;
2320                 priv->extra_stats.rx_bsy++;
2321
2322                 gfar_receive(irq, dev_id);
2323
2324                 if (netif_msg_rx_err(priv))
2325                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2326                                dev->name, gfar_read(&priv->regs->rstat));
2327         }
2328         if (events & IEVENT_BABR) {
2329                 dev->stats.rx_errors++;
2330                 priv->extra_stats.rx_babr++;
2331
2332                 if (netif_msg_rx_err(priv))
2333                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2334         }
2335         if (events & IEVENT_EBERR) {
2336                 priv->extra_stats.eberr++;
2337                 if (netif_msg_rx_err(priv))
2338                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2339         }
2340         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2341                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2342
2343         if (events & IEVENT_BABT) {
2344                 priv->extra_stats.tx_babt++;
2345                 if (netif_msg_tx_err(priv))
2346                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2347         }
2348         return IRQ_HANDLED;
2349 }
2350
2351 /* work with hotplug and coldplug */
2352 MODULE_ALIAS("platform:fsl-gianfar");
2353
2354 static struct of_device_id gfar_match[] =
2355 {
2356         {
2357                 .type = "network",
2358                 .compatible = "gianfar",
2359         },
2360         {},
2361 };
2362
2363 /* Structure for a device driver */
2364 static struct of_platform_driver gfar_driver = {
2365         .name = "fsl-gianfar",
2366         .match_table = gfar_match,
2367
2368         .probe = gfar_probe,
2369         .remove = gfar_remove,
2370         .suspend = gfar_suspend,
2371         .resume = gfar_resume,
2372 };
2373
2374 static int __init gfar_init(void)
2375 {
2376         return of_register_platform_driver(&gfar_driver);
2377 }
2378
2379 static void __exit gfar_exit(void)
2380 {
2381         of_unregister_platform_driver(&gfar_driver);
2382 }
2383
2384 module_init(gfar_init);
2385 module_exit(gfar_exit);
2386