970a3f415244f88076de15c51ec5ba7338401efc
[linux-2.6.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
1 /*******************************************************************************
2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3   ST Ethernet IPs are built around a Synopsys IP Core.
4
5         Copyright(C) 2007-2011 STMicroelectronics Ltd
6
7   This program is free software; you can redistribute it and/or modify it
8   under the terms and conditions of the GNU General Public License,
9   version 2, as published by the Free Software Foundation.
10
11   This program is distributed in the hope it will be useful, but WITHOUT
12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14   more details.
15
16   You should have received a copy of the GNU General Public License along with
17   this program; if not, write to the Free Software Foundation, Inc.,
18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20   The full GNU General Public License is included in this distribution in
21   the file called "COPYING".
22
23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25   Documentation available at:
26         http://www.stlinux.com
27   Support available at:
28         https://bugzilla.stlinux.com/
29 *******************************************************************************/
30
31 #include <linux/kernel.h>
32 #include <linux/interrupt.h>
33 #include <linux/ip.h>
34 #include <linux/tcp.h>
35 #include <linux/skbuff.h>
36 #include <linux/ethtool.h>
37 #include <linux/if_ether.h>
38 #include <linux/crc32.h>
39 #include <linux/mii.h>
40 #include <linux/if.h>
41 #include <linux/if_vlan.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/slab.h>
44 #include <linux/prefetch.h>
45 #ifdef CONFIG_STMMAC_DEBUG_FS
46 #include <linux/debugfs.h>
47 #include <linux/seq_file.h>
48 #endif
49 #include "stmmac.h"
50
51 #undef STMMAC_DEBUG
52 /*#define STMMAC_DEBUG*/
53 #ifdef STMMAC_DEBUG
54 #define DBG(nlevel, klevel, fmt, args...) \
55                 ((void)(netif_msg_##nlevel(priv) && \
56                 printk(KERN_##klevel fmt, ## args)))
57 #else
58 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
59 #endif
60
61 #undef STMMAC_RX_DEBUG
62 /*#define STMMAC_RX_DEBUG*/
63 #ifdef STMMAC_RX_DEBUG
64 #define RX_DBG(fmt, args...)  printk(fmt, ## args)
65 #else
66 #define RX_DBG(fmt, args...)  do { } while (0)
67 #endif
68
69 #undef STMMAC_XMIT_DEBUG
70 /*#define STMMAC_XMIT_DEBUG*/
71 #ifdef STMMAC_TX_DEBUG
72 #define TX_DBG(fmt, args...)  printk(fmt, ## args)
73 #else
74 #define TX_DBG(fmt, args...)  do { } while (0)
75 #endif
76
77 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
78 #define JUMBO_LEN       9000
79
80 /* Module parameters */
81 #define TX_TIMEO 5000 /* default 5 seconds */
82 static int watchdog = TX_TIMEO;
83 module_param(watchdog, int, S_IRUGO | S_IWUSR);
84 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
85
86 static int debug = -1;          /* -1: default, 0: no output, 16:  all */
87 module_param(debug, int, S_IRUGO | S_IWUSR);
88 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
89
90 int phyaddr = -1;
91 module_param(phyaddr, int, S_IRUGO);
92 MODULE_PARM_DESC(phyaddr, "Physical device address");
93
94 #define DMA_TX_SIZE 256
95 static int dma_txsize = DMA_TX_SIZE;
96 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
97 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
98
99 #define DMA_RX_SIZE 256
100 static int dma_rxsize = DMA_RX_SIZE;
101 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
102 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
103
104 static int flow_ctrl = FLOW_OFF;
105 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
106 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
107
108 static int pause = PAUSE_TIME;
109 module_param(pause, int, S_IRUGO | S_IWUSR);
110 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
111
112 #define TC_DEFAULT 64
113 static int tc = TC_DEFAULT;
114 module_param(tc, int, S_IRUGO | S_IWUSR);
115 MODULE_PARM_DESC(tc, "DMA threshold control value");
116
117 /* Pay attention to tune this parameter; take care of both
118  * hardware capability and network stabitily/performance impact.
119  * Many tests showed that ~4ms latency seems to be good enough. */
120 #ifdef CONFIG_STMMAC_TIMER
121 #define DEFAULT_PERIODIC_RATE   256
122 static int tmrate = DEFAULT_PERIODIC_RATE;
123 module_param(tmrate, int, S_IRUGO | S_IWUSR);
124 MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
125 #endif
126
127 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
128 static int buf_sz = DMA_BUFFER_SIZE;
129 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
130 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
131
132 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
133                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
134                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
135
136 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
137
138 #ifdef CONFIG_STMMAC_DEBUG_FS
139 static int stmmac_init_fs(struct net_device *dev);
140 static void stmmac_exit_fs(void);
141 #endif
142
143 /**
144  * stmmac_verify_args - verify the driver parameters.
145  * Description: it verifies if some wrong parameter is passed to the driver.
146  * Note that wrong parameters are replaced with the default values.
147  */
148 static void stmmac_verify_args(void)
149 {
150         if (unlikely(watchdog < 0))
151                 watchdog = TX_TIMEO;
152         if (unlikely(dma_rxsize < 0))
153                 dma_rxsize = DMA_RX_SIZE;
154         if (unlikely(dma_txsize < 0))
155                 dma_txsize = DMA_TX_SIZE;
156         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
157                 buf_sz = DMA_BUFFER_SIZE;
158         if (unlikely(flow_ctrl > 1))
159                 flow_ctrl = FLOW_AUTO;
160         else if (likely(flow_ctrl < 0))
161                 flow_ctrl = FLOW_OFF;
162         if (unlikely((pause < 0) || (pause > 0xffff)))
163                 pause = PAUSE_TIME;
164 }
165
166 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
167 static void print_pkt(unsigned char *buf, int len)
168 {
169         int j;
170         pr_info("len = %d byte, buf addr: 0x%p", len, buf);
171         for (j = 0; j < len; j++) {
172                 if ((j % 16) == 0)
173                         pr_info("\n %03x:", j);
174                 pr_info(" %02x", buf[j]);
175         }
176         pr_info("\n");
177 }
178 #endif
179
180 /* minimum number of free TX descriptors required to wake up TX process */
181 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
182
183 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
184 {
185         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
186 }
187
188 /* On some ST platforms, some HW system configuraton registers have to be
189  * set according to the link speed negotiated.
190  */
191 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
192 {
193         struct phy_device *phydev = priv->phydev;
194
195         if (likely(priv->plat->fix_mac_speed))
196                 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
197                                           phydev->speed);
198 }
199
200 /**
201  * stmmac_adjust_link
202  * @dev: net device structure
203  * Description: it adjusts the link parameters.
204  */
205 static void stmmac_adjust_link(struct net_device *dev)
206 {
207         struct stmmac_priv *priv = netdev_priv(dev);
208         struct phy_device *phydev = priv->phydev;
209         unsigned long flags;
210         int new_state = 0;
211         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
212
213         if (phydev == NULL)
214                 return;
215
216         DBG(probe, DEBUG, "stmmac_adjust_link: called.  address %d link %d\n",
217             phydev->addr, phydev->link);
218
219         spin_lock_irqsave(&priv->lock, flags);
220         if (phydev->link) {
221                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
222
223                 /* Now we make sure that we can be in full duplex mode.
224                  * If not, we operate in half-duplex mode. */
225                 if (phydev->duplex != priv->oldduplex) {
226                         new_state = 1;
227                         if (!(phydev->duplex))
228                                 ctrl &= ~priv->hw->link.duplex;
229                         else
230                                 ctrl |= priv->hw->link.duplex;
231                         priv->oldduplex = phydev->duplex;
232                 }
233                 /* Flow Control operation */
234                 if (phydev->pause)
235                         priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
236                                                  fc, pause_time);
237
238                 if (phydev->speed != priv->speed) {
239                         new_state = 1;
240                         switch (phydev->speed) {
241                         case 1000:
242                                 if (likely(priv->plat->has_gmac))
243                                         ctrl &= ~priv->hw->link.port;
244                                 stmmac_hw_fix_mac_speed(priv);
245                                 break;
246                         case 100:
247                         case 10:
248                                 if (priv->plat->has_gmac) {
249                                         ctrl |= priv->hw->link.port;
250                                         if (phydev->speed == SPEED_100) {
251                                                 ctrl |= priv->hw->link.speed;
252                                         } else {
253                                                 ctrl &= ~(priv->hw->link.speed);
254                                         }
255                                 } else {
256                                         ctrl &= ~priv->hw->link.port;
257                                 }
258                                 stmmac_hw_fix_mac_speed(priv);
259                                 break;
260                         default:
261                                 if (netif_msg_link(priv))
262                                         pr_warning("%s: Speed (%d) is not 10"
263                                        " or 100!\n", dev->name, phydev->speed);
264                                 break;
265                         }
266
267                         priv->speed = phydev->speed;
268                 }
269
270                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
271
272                 if (!priv->oldlink) {
273                         new_state = 1;
274                         priv->oldlink = 1;
275                 }
276         } else if (priv->oldlink) {
277                 new_state = 1;
278                 priv->oldlink = 0;
279                 priv->speed = 0;
280                 priv->oldduplex = -1;
281         }
282
283         if (new_state && netif_msg_link(priv))
284                 phy_print_status(phydev);
285
286         spin_unlock_irqrestore(&priv->lock, flags);
287
288         DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
289 }
290
291 /**
292  * stmmac_init_phy - PHY initialization
293  * @dev: net device structure
294  * Description: it initializes the driver's PHY state, and attaches the PHY
295  * to the mac driver.
296  *  Return value:
297  *  0 on success
298  */
299 static int stmmac_init_phy(struct net_device *dev)
300 {
301         struct stmmac_priv *priv = netdev_priv(dev);
302         struct phy_device *phydev;
303         char phy_id[MII_BUS_ID_SIZE + 3];
304         char bus_id[MII_BUS_ID_SIZE];
305         int interface = priv->plat->interface;
306         priv->oldlink = 0;
307         priv->speed = 0;
308         priv->oldduplex = -1;
309
310         snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", priv->plat->bus_id);
311         snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
312                  priv->plat->phy_addr);
313         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id);
314
315         phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface);
316
317         if (IS_ERR(phydev)) {
318                 pr_err("%s: Could not attach to PHY\n", dev->name);
319                 return PTR_ERR(phydev);
320         }
321
322         /* Stop Advertising 1000BASE Capability if interface is not GMII */
323         if ((interface == PHY_INTERFACE_MODE_MII) ||
324             (interface == PHY_INTERFACE_MODE_RMII))
325                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
326                                          SUPPORTED_1000baseT_Full);
327
328         /*
329          * Broken HW is sometimes missing the pull-up resistor on the
330          * MDIO line, which results in reads to non-existent devices returning
331          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
332          * device as well.
333          * Note: phydev->phy_id is the result of reading the UID PHY registers.
334          */
335         if (phydev->phy_id == 0) {
336                 phy_disconnect(phydev);
337                 return -ENODEV;
338         }
339         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
340                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
341
342         priv->phydev = phydev;
343
344         return 0;
345 }
346
347 /**
348  * display_ring
349  * @p: pointer to the ring.
350  * @size: size of the ring.
351  * Description: display all the descriptors within the ring.
352  */
353 static void display_ring(struct dma_desc *p, int size)
354 {
355         struct tmp_s {
356                 u64 a;
357                 unsigned int b;
358                 unsigned int c;
359         };
360         int i;
361         for (i = 0; i < size; i++) {
362                 struct tmp_s *x = (struct tmp_s *)(p + i);
363                 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
364                        i, (unsigned int)virt_to_phys(&p[i]),
365                        (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
366                        x->b, x->c);
367                 pr_info("\n");
368         }
369 }
370
371 static int stmmac_set_bfsize(int mtu, int bufsize)
372 {
373         int ret = bufsize;
374
375         if (mtu >= BUF_SIZE_4KiB)
376                 ret = BUF_SIZE_8KiB;
377         else if (mtu >= BUF_SIZE_2KiB)
378                 ret = BUF_SIZE_4KiB;
379         else if (mtu >= DMA_BUFFER_SIZE)
380                 ret = BUF_SIZE_2KiB;
381         else
382                 ret = DMA_BUFFER_SIZE;
383
384         return ret;
385 }
386
387 /**
388  * init_dma_desc_rings - init the RX/TX descriptor rings
389  * @dev: net device structure
390  * Description:  this function initializes the DMA RX/TX descriptors
391  * and allocates the socket buffers. It suppors the chained and ring
392  * modes.
393  */
394 static void init_dma_desc_rings(struct net_device *dev)
395 {
396         int i;
397         struct stmmac_priv *priv = netdev_priv(dev);
398         struct sk_buff *skb;
399         unsigned int txsize = priv->dma_tx_size;
400         unsigned int rxsize = priv->dma_rx_size;
401         unsigned int bfsize;
402         int dis_ic = 0;
403         int des3_as_data_buf = 0;
404
405         /* Set the max buffer size according to the DESC mode
406          * and the MTU. Note that RING mode allows 16KiB bsize. */
407         bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
408
409         if (bfsize == BUF_SIZE_16KiB)
410                 des3_as_data_buf = 1;
411         else
412                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
413
414 #ifdef CONFIG_STMMAC_TIMER
415         /* Disable interrupts on completion for the reception if timer is on */
416         if (likely(priv->tm->enable))
417                 dis_ic = 1;
418 #endif
419
420         DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
421             txsize, rxsize, bfsize);
422
423         priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
424         priv->rx_skbuff =
425             kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
426         priv->dma_rx =
427             (struct dma_desc *)dma_alloc_coherent(priv->device,
428                                                   rxsize *
429                                                   sizeof(struct dma_desc),
430                                                   &priv->dma_rx_phy,
431                                                   GFP_KERNEL);
432         priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
433                                        GFP_KERNEL);
434         priv->dma_tx =
435             (struct dma_desc *)dma_alloc_coherent(priv->device,
436                                                   txsize *
437                                                   sizeof(struct dma_desc),
438                                                   &priv->dma_tx_phy,
439                                                   GFP_KERNEL);
440
441         if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
442                 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
443                 return;
444         }
445
446         DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, "
447             "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
448             dev->name, priv->dma_rx, priv->dma_tx,
449             (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
450
451         /* RX INITIALIZATION */
452         DBG(probe, INFO, "stmmac: SKB addresses:\n"
453                          "skb\t\tskb data\tdma data\n");
454
455         for (i = 0; i < rxsize; i++) {
456                 struct dma_desc *p = priv->dma_rx + i;
457
458                 skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN,
459                                          GFP_KERNEL);
460                 if (unlikely(skb == NULL)) {
461                         pr_err("%s: Rx init fails; skb is NULL\n", __func__);
462                         break;
463                 }
464                 skb_reserve(skb, NET_IP_ALIGN);
465                 priv->rx_skbuff[i] = skb;
466                 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
467                                                 bfsize, DMA_FROM_DEVICE);
468
469                 p->des2 = priv->rx_skbuff_dma[i];
470
471                 priv->hw->ring->init_desc3(des3_as_data_buf, p);
472
473                 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
474                         priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
475         }
476         priv->cur_rx = 0;
477         priv->dirty_rx = (unsigned int)(i - rxsize);
478         priv->dma_buf_sz = bfsize;
479         buf_sz = bfsize;
480
481         /* TX INITIALIZATION */
482         for (i = 0; i < txsize; i++) {
483                 priv->tx_skbuff[i] = NULL;
484                 priv->dma_tx[i].des2 = 0;
485         }
486
487         /* In case of Chained mode this sets the des3 to the next
488          * element in the chain */
489         priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize);
490         priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize);
491
492         priv->dirty_tx = 0;
493         priv->cur_tx = 0;
494
495         /* Clear the Rx/Tx descriptors */
496         priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
497         priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
498
499         if (netif_msg_hw(priv)) {
500                 pr_info("RX descriptor ring:\n");
501                 display_ring(priv->dma_rx, rxsize);
502                 pr_info("TX descriptor ring:\n");
503                 display_ring(priv->dma_tx, txsize);
504         }
505 }
506
507 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
508 {
509         int i;
510
511         for (i = 0; i < priv->dma_rx_size; i++) {
512                 if (priv->rx_skbuff[i]) {
513                         dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
514                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
515                         dev_kfree_skb_any(priv->rx_skbuff[i]);
516                 }
517                 priv->rx_skbuff[i] = NULL;
518         }
519 }
520
521 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
522 {
523         int i;
524
525         for (i = 0; i < priv->dma_tx_size; i++) {
526                 if (priv->tx_skbuff[i] != NULL) {
527                         struct dma_desc *p = priv->dma_tx + i;
528                         if (p->des2)
529                                 dma_unmap_single(priv->device, p->des2,
530                                                  priv->hw->desc->get_tx_len(p),
531                                                  DMA_TO_DEVICE);
532                         dev_kfree_skb_any(priv->tx_skbuff[i]);
533                         priv->tx_skbuff[i] = NULL;
534                 }
535         }
536 }
537
538 static void free_dma_desc_resources(struct stmmac_priv *priv)
539 {
540         /* Release the DMA TX/RX socket buffers */
541         dma_free_rx_skbufs(priv);
542         dma_free_tx_skbufs(priv);
543
544         /* Free the region of consistent memory previously allocated for
545          * the DMA */
546         dma_free_coherent(priv->device,
547                           priv->dma_tx_size * sizeof(struct dma_desc),
548                           priv->dma_tx, priv->dma_tx_phy);
549         dma_free_coherent(priv->device,
550                           priv->dma_rx_size * sizeof(struct dma_desc),
551                           priv->dma_rx, priv->dma_rx_phy);
552         kfree(priv->rx_skbuff_dma);
553         kfree(priv->rx_skbuff);
554         kfree(priv->tx_skbuff);
555 }
556
557 /**
558  *  stmmac_dma_operation_mode - HW DMA operation mode
559  *  @priv : pointer to the private device structure.
560  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
561  *  or Store-And-Forward capability.
562  */
563 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
564 {
565         if (likely(priv->plat->force_sf_dma_mode ||
566                 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
567                 /*
568                  * In case of GMAC, SF mode can be enabled
569                  * to perform the TX COE in HW. This depends on:
570                  * 1) TX COE if actually supported
571                  * 2) There is no bugged Jumbo frame support
572                  *    that needs to not insert csum in the TDES.
573                  */
574                 priv->hw->dma->dma_mode(priv->ioaddr,
575                                         SF_DMA_MODE, SF_DMA_MODE);
576                 tc = SF_DMA_MODE;
577         } else
578                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
579 }
580
581 /**
582  * stmmac_tx:
583  * @priv: private driver structure
584  * Description: it reclaims resources after transmission completes.
585  */
586 static void stmmac_tx(struct stmmac_priv *priv)
587 {
588         unsigned int txsize = priv->dma_tx_size;
589
590         spin_lock(&priv->tx_lock);
591
592         while (priv->dirty_tx != priv->cur_tx) {
593                 int last;
594                 unsigned int entry = priv->dirty_tx % txsize;
595                 struct sk_buff *skb = priv->tx_skbuff[entry];
596                 struct dma_desc *p = priv->dma_tx + entry;
597
598                 /* Check if the descriptor is owned by the DMA. */
599                 if (priv->hw->desc->get_tx_owner(p))
600                         break;
601
602                 /* Verify tx error by looking at the last segment */
603                 last = priv->hw->desc->get_tx_ls(p);
604                 if (likely(last)) {
605                         int tx_error =
606                                 priv->hw->desc->tx_status(&priv->dev->stats,
607                                                           &priv->xstats, p,
608                                                           priv->ioaddr);
609                         if (likely(tx_error == 0)) {
610                                 priv->dev->stats.tx_packets++;
611                                 priv->xstats.tx_pkt_n++;
612                         } else
613                                 priv->dev->stats.tx_errors++;
614                 }
615                 TX_DBG("%s: curr %d, dirty %d\n", __func__,
616                         priv->cur_tx, priv->dirty_tx);
617
618                 if (likely(p->des2))
619                         dma_unmap_single(priv->device, p->des2,
620                                          priv->hw->desc->get_tx_len(p),
621                                          DMA_TO_DEVICE);
622                 priv->hw->ring->clean_desc3(p);
623
624                 if (likely(skb != NULL)) {
625                         /*
626                          * If there's room in the queue (limit it to size)
627                          * we add this skb back into the pool,
628                          * if it's the right size.
629                          */
630                         if ((skb_queue_len(&priv->rx_recycle) <
631                                 priv->dma_rx_size) &&
632                                 skb_recycle_check(skb, priv->dma_buf_sz))
633                                 __skb_queue_head(&priv->rx_recycle, skb);
634                         else
635                                 dev_kfree_skb(skb);
636
637                         priv->tx_skbuff[entry] = NULL;
638                 }
639
640                 priv->hw->desc->release_tx_desc(p);
641
642                 entry = (++priv->dirty_tx) % txsize;
643         }
644         if (unlikely(netif_queue_stopped(priv->dev) &&
645                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
646                 netif_tx_lock(priv->dev);
647                 if (netif_queue_stopped(priv->dev) &&
648                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
649                         TX_DBG("%s: restart transmit\n", __func__);
650                         netif_wake_queue(priv->dev);
651                 }
652                 netif_tx_unlock(priv->dev);
653         }
654         spin_unlock(&priv->tx_lock);
655 }
656
657 static inline void stmmac_enable_irq(struct stmmac_priv *priv)
658 {
659 #ifdef CONFIG_STMMAC_TIMER
660         if (likely(priv->tm->enable))
661                 priv->tm->timer_start(tmrate);
662         else
663 #endif
664                 priv->hw->dma->enable_dma_irq(priv->ioaddr);
665 }
666
667 static inline void stmmac_disable_irq(struct stmmac_priv *priv)
668 {
669 #ifdef CONFIG_STMMAC_TIMER
670         if (likely(priv->tm->enable))
671                 priv->tm->timer_stop();
672         else
673 #endif
674                 priv->hw->dma->disable_dma_irq(priv->ioaddr);
675 }
676
677 static int stmmac_has_work(struct stmmac_priv *priv)
678 {
679         unsigned int has_work = 0;
680         int rxret, tx_work = 0;
681
682         rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
683                 (priv->cur_rx % priv->dma_rx_size));
684
685         if (priv->dirty_tx != priv->cur_tx)
686                 tx_work = 1;
687
688         if (likely(!rxret || tx_work))
689                 has_work = 1;
690
691         return has_work;
692 }
693
694 static inline void _stmmac_schedule(struct stmmac_priv *priv)
695 {
696         if (likely(stmmac_has_work(priv))) {
697                 stmmac_disable_irq(priv);
698                 napi_schedule(&priv->napi);
699         }
700 }
701
702 #ifdef CONFIG_STMMAC_TIMER
703 void stmmac_schedule(struct net_device *dev)
704 {
705         struct stmmac_priv *priv = netdev_priv(dev);
706
707         priv->xstats.sched_timer_n++;
708
709         _stmmac_schedule(priv);
710 }
711
712 static void stmmac_no_timer_started(unsigned int x)
713 {;
714 };
715
716 static void stmmac_no_timer_stopped(void)
717 {;
718 };
719 #endif
720
721 /**
722  * stmmac_tx_err:
723  * @priv: pointer to the private device structure
724  * Description: it cleans the descriptors and restarts the transmission
725  * in case of errors.
726  */
727 static void stmmac_tx_err(struct stmmac_priv *priv)
728 {
729         netif_stop_queue(priv->dev);
730
731         priv->hw->dma->stop_tx(priv->ioaddr);
732         dma_free_tx_skbufs(priv);
733         priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
734         priv->dirty_tx = 0;
735         priv->cur_tx = 0;
736         priv->hw->dma->start_tx(priv->ioaddr);
737
738         priv->dev->stats.tx_errors++;
739         netif_wake_queue(priv->dev);
740 }
741
742
743 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
744 {
745         int status;
746
747         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
748         if (likely(status == handle_tx_rx))
749                 _stmmac_schedule(priv);
750
751         else if (unlikely(status == tx_hard_error_bump_tc)) {
752                 /* Try to bump up the dma threshold on this failure */
753                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
754                         tc += 64;
755                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
756                         priv->xstats.threshold = tc;
757                 }
758         } else if (unlikely(status == tx_hard_error))
759                 stmmac_tx_err(priv);
760 }
761
762 static void stmmac_mmc_setup(struct stmmac_priv *priv)
763 {
764         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
765                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
766
767         /* Mask MMC irq, counters are managed in SW and registers
768          * are cleared on each READ eventually. */
769         dwmac_mmc_intr_all_mask(priv->ioaddr);
770
771         if (priv->dma_cap.rmon) {
772                 dwmac_mmc_ctrl(priv->ioaddr, mode);
773                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
774         } else
775                 pr_info(" No MAC Management Counters available\n");
776 }
777
778 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
779 {
780         u32 hwid = priv->hw->synopsys_uid;
781
782         /* Only check valid Synopsys Id because old MAC chips
783          * have no HW registers where get the ID */
784         if (likely(hwid)) {
785                 u32 uid = ((hwid & 0x0000ff00) >> 8);
786                 u32 synid = (hwid & 0x000000ff);
787
788                 pr_info("STMMAC - user ID: 0x%x, Synopsys ID: 0x%x\n",
789                         uid, synid);
790
791                 return synid;
792         }
793         return 0;
794 }
795
796 /**
797  * stmmac_selec_desc_mode
798  * @dev : device pointer
799  * Description: select the Enhanced/Alternate or Normal descriptors */
800 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
801 {
802         if (priv->plat->enh_desc) {
803                 pr_info(" Enhanced/Alternate descriptors\n");
804                 priv->hw->desc = &enh_desc_ops;
805         } else {
806                 pr_info(" Normal descriptors\n");
807                 priv->hw->desc = &ndesc_ops;
808         }
809 }
810
811 /**
812  * stmmac_get_hw_features
813  * @priv : private device pointer
814  * Description:
815  *  new GMAC chip generations have a new register to indicate the
816  *  presence of the optional feature/functions.
817  *  This can be also used to override the value passed through the
818  *  platform and necessary for old MAC10/100 and GMAC chips.
819  */
820 static int stmmac_get_hw_features(struct stmmac_priv *priv)
821 {
822         u32 hw_cap = 0;
823
824         if (priv->hw->dma->get_hw_feature) {
825                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
826
827                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
828                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
829                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
830                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
831                 priv->dma_cap.multi_addr =
832                         (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
833                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
834                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
835                 priv->dma_cap.pmt_remote_wake_up =
836                         (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
837                 priv->dma_cap.pmt_magic_frame =
838                         (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
839                 /* MMC */
840                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
841                 /* IEEE 1588-2002*/
842                 priv->dma_cap.time_stamp =
843                         (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
844                 /* IEEE 1588-2008*/
845                 priv->dma_cap.atime_stamp =
846                         (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
847                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
848                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
849                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
850                 /* TX and RX csum */
851                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
852                 priv->dma_cap.rx_coe_type1 =
853                         (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
854                 priv->dma_cap.rx_coe_type2 =
855                         (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
856                 priv->dma_cap.rxfifo_over_2048 =
857                         (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
858                 /* TX and RX number of channels */
859                 priv->dma_cap.number_rx_channel =
860                         (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
861                 priv->dma_cap.number_tx_channel =
862                         (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
863                 /* Alternate (enhanced) DESC mode*/
864                 priv->dma_cap.enh_desc =
865                         (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
866
867         }
868
869         return hw_cap;
870 }
871
872 /**
873  * stmmac_mac_device_setup
874  * @dev : device pointer
875  * Description: this is to attach the GMAC or MAC 10/100
876  * main core structures that will be completed during the
877  * open step.
878  */
879 static int stmmac_mac_device_setup(struct net_device *dev)
880 {
881         struct stmmac_priv *priv = netdev_priv(dev);
882
883         struct mac_device_info *device;
884
885         if (priv->plat->has_gmac)
886                 device = dwmac1000_setup(priv->ioaddr);
887         else
888                 device = dwmac100_setup(priv->ioaddr);
889
890         if (!device)
891                 return -ENOMEM;
892
893         priv->hw = device;
894         priv->hw->ring = &ring_mode_ops;
895
896         if (device_can_wakeup(priv->device)) {
897                 priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */
898                 enable_irq_wake(priv->wol_irq);
899         }
900
901         return 0;
902 }
903
904 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
905 {
906         /* verify if the MAC address is valid, in case of failures it
907          * generates a random MAC address */
908         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
909                 priv->hw->mac->get_umac_addr((void __iomem *)
910                                              priv->dev->base_addr,
911                                              priv->dev->dev_addr, 0);
912                 if  (!is_valid_ether_addr(priv->dev->dev_addr))
913                         random_ether_addr(priv->dev->dev_addr);
914         }
915         pr_warning("%s: device MAC address %pM\n", priv->dev->name,
916                                                    priv->dev->dev_addr);
917 }
918
919 /**
920  *  stmmac_open - open entry point of the driver
921  *  @dev : pointer to the device structure.
922  *  Description:
923  *  This function is the open entry point of the driver.
924  *  Return value:
925  *  0 on success and an appropriate (-)ve integer as defined in errno.h
926  *  file on failure.
927  */
928 static int stmmac_open(struct net_device *dev)
929 {
930         struct stmmac_priv *priv = netdev_priv(dev);
931         int ret;
932
933         /* MAC HW device setup */
934         ret = stmmac_mac_device_setup(dev);
935         if (ret < 0)
936                 return ret;
937
938         stmmac_check_ether_addr(priv);
939
940         stmmac_verify_args();
941
942         /* Override with kernel parameters if supplied XXX CRS XXX
943          * this needs to have multiple instances */
944         if ((phyaddr >= 0) && (phyaddr <= 31))
945                 priv->plat->phy_addr = phyaddr;
946
947         /* MDIO bus Registration */
948         ret = stmmac_mdio_register(dev);
949         if (ret < 0) {
950                 pr_debug("%s: MDIO bus (id: %d) registration failed",
951                          __func__, priv->plat->bus_id);
952                 return ret;
953         }
954
955 #ifdef CONFIG_STMMAC_TIMER
956         priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
957         if (unlikely(priv->tm == NULL)) {
958                 pr_err("%s: ERROR: timer memory alloc failed\n", __func__);
959                 return -ENOMEM;
960         }
961         priv->tm->freq = tmrate;
962
963         /* Test if the external timer can be actually used.
964          * In case of failure continue without timer. */
965         if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
966                 pr_warning("stmmaceth: cannot attach the external timer.\n");
967                 priv->tm->freq = 0;
968                 priv->tm->timer_start = stmmac_no_timer_started;
969                 priv->tm->timer_stop = stmmac_no_timer_stopped;
970         } else
971                 priv->tm->enable = 1;
972 #endif
973         ret = stmmac_init_phy(dev);
974         if (unlikely(ret)) {
975                 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
976                 goto open_error;
977         }
978
979         stmmac_get_synopsys_id(priv);
980
981         priv->hw_cap_support = stmmac_get_hw_features(priv);
982
983         if (priv->hw_cap_support) {
984                 pr_info(" Support DMA HW capability register");
985
986                 /* We can override some gmac/dma configuration fields: e.g.
987                  * enh_desc, tx_coe (e.g. that are passed through the
988                  * platform) with the values from the HW capability
989                  * register (if supported).
990                  */
991                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
992                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
993                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
994
995                 /* By default disable wol on magic frame if not supported */
996                 if (!priv->dma_cap.pmt_magic_frame)
997                         priv->wolopts &= ~WAKE_MAGIC;
998
999         } else
1000                 pr_info(" No HW DMA feature register supported");
1001
1002         /* Select the enhnaced/normal descriptor structures */
1003         stmmac_selec_desc_mode(priv);
1004
1005         /* PMT module is not integrated in all the MAC devices. */
1006         if (priv->plat->pmt) {
1007                 pr_info(" Remote wake-up capable\n");
1008                 device_set_wakeup_capable(priv->device, 1);
1009         }
1010
1011         priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr);
1012         if (priv->rx_coe)
1013                 pr_info(" Checksum Offload Engine supported\n");
1014         if (priv->plat->tx_coe)
1015                 pr_info(" Checksum insertion supported\n");
1016
1017         /* Create and initialize the TX/RX descriptors chains. */
1018         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1019         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1020         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1021         init_dma_desc_rings(dev);
1022
1023         /* DMA initialization and SW reset */
1024         ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl,
1025                                   priv->dma_tx_phy, priv->dma_rx_phy);
1026         if (ret < 0) {
1027                 pr_err("%s: DMA initialization failed\n", __func__);
1028                 goto open_error;
1029         }
1030
1031         /* Copy the MAC addr into the HW  */
1032         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1033         /* If required, perform hw setup of the bus. */
1034         if (priv->plat->bus_setup)
1035                 priv->plat->bus_setup(priv->ioaddr);
1036         /* Initialize the MAC Core */
1037         priv->hw->mac->core_init(priv->ioaddr);
1038
1039         netdev_update_features(dev);
1040
1041         /* Request the IRQ lines */
1042         ret = request_irq(dev->irq, stmmac_interrupt,
1043                          IRQF_SHARED, dev->name, dev);
1044         if (unlikely(ret < 0)) {
1045                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1046                        __func__, dev->irq, ret);
1047                 goto open_error;
1048         }
1049
1050         /* Request the Wake IRQ in case of another line is used for WoL */
1051         if (priv->wol_irq != dev->irq) {
1052                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1053                                   IRQF_SHARED, dev->name, dev);
1054                 if (unlikely(ret < 0)) {
1055                         pr_err("%s: ERROR: allocating the ext WoL IRQ %d "
1056                                "(error: %d)\n", __func__, priv->wol_irq, ret);
1057                         goto open_error_wolirq;
1058                 }
1059         }
1060
1061         /* Enable the MAC Rx/Tx */
1062         stmmac_set_mac(priv->ioaddr, true);
1063
1064         /* Set the HW DMA mode and the COE */
1065         stmmac_dma_operation_mode(priv);
1066
1067         /* Extra statistics */
1068         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1069         priv->xstats.threshold = tc;
1070
1071         stmmac_mmc_setup(priv);
1072
1073 #ifdef CONFIG_STMMAC_DEBUG_FS
1074         ret = stmmac_init_fs(dev);
1075         if (ret < 0)
1076                 pr_warning("\tFailed debugFS registration");
1077 #endif
1078         /* Start the ball rolling... */
1079         DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1080         priv->hw->dma->start_tx(priv->ioaddr);
1081         priv->hw->dma->start_rx(priv->ioaddr);
1082
1083 #ifdef CONFIG_STMMAC_TIMER
1084         priv->tm->timer_start(tmrate);
1085 #endif
1086         /* Dump DMA/MAC registers */
1087         if (netif_msg_hw(priv)) {
1088                 priv->hw->mac->dump_regs(priv->ioaddr);
1089                 priv->hw->dma->dump_regs(priv->ioaddr);
1090         }
1091
1092         if (priv->phydev)
1093                 phy_start(priv->phydev);
1094
1095         napi_enable(&priv->napi);
1096         skb_queue_head_init(&priv->rx_recycle);
1097         netif_start_queue(dev);
1098
1099         return 0;
1100
1101 open_error_wolirq:
1102         free_irq(dev->irq, dev);
1103
1104 open_error:
1105 #ifdef CONFIG_STMMAC_TIMER
1106         kfree(priv->tm);
1107 #endif
1108         if (priv->phydev)
1109                 phy_disconnect(priv->phydev);
1110
1111         return ret;
1112 }
1113
1114 /**
1115  *  stmmac_release - close entry point of the driver
1116  *  @dev : device pointer.
1117  *  Description:
1118  *  This is the stop entry point of the driver.
1119  */
1120 static int stmmac_release(struct net_device *dev)
1121 {
1122         struct stmmac_priv *priv = netdev_priv(dev);
1123
1124         /* Stop and disconnect the PHY */
1125         if (priv->phydev) {
1126                 phy_stop(priv->phydev);
1127                 phy_disconnect(priv->phydev);
1128                 priv->phydev = NULL;
1129         }
1130
1131         netif_stop_queue(dev);
1132
1133 #ifdef CONFIG_STMMAC_TIMER
1134         /* Stop and release the timer */
1135         stmmac_close_ext_timer();
1136         if (priv->tm != NULL)
1137                 kfree(priv->tm);
1138 #endif
1139         napi_disable(&priv->napi);
1140         skb_queue_purge(&priv->rx_recycle);
1141
1142         /* Free the IRQ lines */
1143         free_irq(dev->irq, dev);
1144         if (priv->wol_irq != dev->irq)
1145                 free_irq(priv->wol_irq, dev);
1146
1147         /* Stop TX/RX DMA and clear the descriptors */
1148         priv->hw->dma->stop_tx(priv->ioaddr);
1149         priv->hw->dma->stop_rx(priv->ioaddr);
1150
1151         /* Release and free the Rx/Tx resources */
1152         free_dma_desc_resources(priv);
1153
1154         /* Disable the MAC Rx/Tx */
1155         stmmac_set_mac(priv->ioaddr, false);
1156
1157         netif_carrier_off(dev);
1158
1159 #ifdef CONFIG_STMMAC_DEBUG_FS
1160         stmmac_exit_fs();
1161 #endif
1162         stmmac_mdio_unregister(dev);
1163
1164         return 0;
1165 }
1166
1167 /**
1168  *  stmmac_xmit:
1169  *  @skb : the socket buffer
1170  *  @dev : device pointer
1171  *  Description : Tx entry point of the driver.
1172  */
1173 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1174 {
1175         struct stmmac_priv *priv = netdev_priv(dev);
1176         unsigned int txsize = priv->dma_tx_size;
1177         unsigned int entry;
1178         int i, csum_insertion = 0;
1179         int nfrags = skb_shinfo(skb)->nr_frags;
1180         struct dma_desc *desc, *first;
1181         unsigned int nopaged_len = skb_headlen(skb);
1182
1183         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1184                 if (!netif_queue_stopped(dev)) {
1185                         netif_stop_queue(dev);
1186                         /* This is a hard error, log it. */
1187                         pr_err("%s: BUG! Tx Ring full when queue awake\n",
1188                                 __func__);
1189                 }
1190                 return NETDEV_TX_BUSY;
1191         }
1192
1193         spin_lock(&priv->tx_lock);
1194
1195         entry = priv->cur_tx % txsize;
1196
1197 #ifdef STMMAC_XMIT_DEBUG
1198         if ((skb->len > ETH_FRAME_LEN) || nfrags)
1199                 pr_info("stmmac xmit:\n"
1200                        "\tskb addr %p - len: %d - nopaged_len: %d\n"
1201                        "\tn_frags: %d - ip_summed: %d - %s gso\n",
1202                        skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1203                        !skb_is_gso(skb) ? "isn't" : "is");
1204 #endif
1205
1206         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1207
1208         desc = priv->dma_tx + entry;
1209         first = desc;
1210
1211 #ifdef STMMAC_XMIT_DEBUG
1212         if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1213                 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1214                        "\t\tn_frags: %d, ip_summed: %d\n",
1215                        skb->len, nopaged_len, nfrags, skb->ip_summed);
1216 #endif
1217         priv->tx_skbuff[entry] = skb;
1218
1219         if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) {
1220                 entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion);
1221                 desc = priv->dma_tx + entry;
1222         } else {
1223                 desc->des2 = dma_map_single(priv->device, skb->data,
1224                                         nopaged_len, DMA_TO_DEVICE);
1225                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1226                                                 csum_insertion);
1227         }
1228
1229         for (i = 0; i < nfrags; i++) {
1230                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1231                 int len = skb_frag_size(frag);
1232
1233                 entry = (++priv->cur_tx) % txsize;
1234                 desc = priv->dma_tx + entry;
1235
1236                 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1237                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1238                                               DMA_TO_DEVICE);
1239                 priv->tx_skbuff[entry] = NULL;
1240                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
1241                 wmb();
1242                 priv->hw->desc->set_tx_owner(desc);
1243         }
1244
1245         /* Interrupt on completition only for the latest segment */
1246         priv->hw->desc->close_tx_desc(desc);
1247
1248 #ifdef CONFIG_STMMAC_TIMER
1249         /* Clean IC while using timer */
1250         if (likely(priv->tm->enable))
1251                 priv->hw->desc->clear_tx_ic(desc);
1252 #endif
1253
1254         wmb();
1255
1256         /* To avoid raise condition */
1257         priv->hw->desc->set_tx_owner(first);
1258
1259         priv->cur_tx++;
1260
1261 #ifdef STMMAC_XMIT_DEBUG
1262         if (netif_msg_pktdata(priv)) {
1263                 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1264                        "first=%p, nfrags=%d\n",
1265                        (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1266                        entry, first, nfrags);
1267                 display_ring(priv->dma_tx, txsize);
1268                 pr_info(">>> frame to be transmitted: ");
1269                 print_pkt(skb->data, skb->len);
1270         }
1271 #endif
1272         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1273                 TX_DBG("%s: stop transmitted packets\n", __func__);
1274                 netif_stop_queue(dev);
1275         }
1276
1277         dev->stats.tx_bytes += skb->len;
1278
1279         skb_tx_timestamp(skb);
1280
1281         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1282
1283         spin_unlock(&priv->tx_lock);
1284
1285         return NETDEV_TX_OK;
1286 }
1287
1288 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1289 {
1290         unsigned int rxsize = priv->dma_rx_size;
1291         int bfsize = priv->dma_buf_sz;
1292         struct dma_desc *p = priv->dma_rx;
1293
1294         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1295                 unsigned int entry = priv->dirty_rx % rxsize;
1296                 if (likely(priv->rx_skbuff[entry] == NULL)) {
1297                         struct sk_buff *skb;
1298
1299                         skb = __skb_dequeue(&priv->rx_recycle);
1300                         if (skb == NULL)
1301                                 skb = netdev_alloc_skb_ip_align(priv->dev,
1302                                                                 bfsize);
1303
1304                         if (unlikely(skb == NULL))
1305                                 break;
1306
1307                         priv->rx_skbuff[entry] = skb;
1308                         priv->rx_skbuff_dma[entry] =
1309                             dma_map_single(priv->device, skb->data, bfsize,
1310                                            DMA_FROM_DEVICE);
1311
1312                         (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1313
1314                         if (unlikely(priv->plat->has_gmac))
1315                                 priv->hw->ring->refill_desc3(bfsize, p + entry);
1316
1317                         RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1318                 }
1319                 wmb();
1320                 priv->hw->desc->set_rx_owner(p + entry);
1321         }
1322 }
1323
1324 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1325 {
1326         unsigned int rxsize = priv->dma_rx_size;
1327         unsigned int entry = priv->cur_rx % rxsize;
1328         unsigned int next_entry;
1329         unsigned int count = 0;
1330         struct dma_desc *p = priv->dma_rx + entry;
1331         struct dma_desc *p_next;
1332
1333 #ifdef STMMAC_RX_DEBUG
1334         if (netif_msg_hw(priv)) {
1335                 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1336                 display_ring(priv->dma_rx, rxsize);
1337         }
1338 #endif
1339         count = 0;
1340         while (!priv->hw->desc->get_rx_owner(p)) {
1341                 int status;
1342
1343                 if (count >= limit)
1344                         break;
1345
1346                 count++;
1347
1348                 next_entry = (++priv->cur_rx) % rxsize;
1349                 p_next = priv->dma_rx + next_entry;
1350                 prefetch(p_next);
1351
1352                 /* read the status of the incoming frame */
1353                 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1354                                                     &priv->xstats, p));
1355                 if (unlikely(status == discard_frame))
1356                         priv->dev->stats.rx_errors++;
1357                 else {
1358                         struct sk_buff *skb;
1359                         int frame_len;
1360
1361                         frame_len = priv->hw->desc->get_rx_frame_len(p);
1362                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1363                          * Type frames (LLC/LLC-SNAP) */
1364                         if (unlikely(status != llc_snap))
1365                                 frame_len -= ETH_FCS_LEN;
1366 #ifdef STMMAC_RX_DEBUG
1367                         if (frame_len > ETH_FRAME_LEN)
1368                                 pr_debug("\tRX frame size %d, COE status: %d\n",
1369                                         frame_len, status);
1370
1371                         if (netif_msg_hw(priv))
1372                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1373                                         p, entry, p->des2);
1374 #endif
1375                         skb = priv->rx_skbuff[entry];
1376                         if (unlikely(!skb)) {
1377                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
1378                                         priv->dev->name);
1379                                 priv->dev->stats.rx_dropped++;
1380                                 break;
1381                         }
1382                         prefetch(skb->data - NET_IP_ALIGN);
1383                         priv->rx_skbuff[entry] = NULL;
1384
1385                         skb_put(skb, frame_len);
1386                         dma_unmap_single(priv->device,
1387                                          priv->rx_skbuff_dma[entry],
1388                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
1389 #ifdef STMMAC_RX_DEBUG
1390                         if (netif_msg_pktdata(priv)) {
1391                                 pr_info(" frame received (%dbytes)", frame_len);
1392                                 print_pkt(skb->data, frame_len);
1393                         }
1394 #endif
1395                         skb->protocol = eth_type_trans(skb, priv->dev);
1396
1397                         if (unlikely(!priv->rx_coe)) {
1398                                 /* No RX COE for old mac10/100 devices */
1399                                 skb_checksum_none_assert(skb);
1400                                 netif_receive_skb(skb);
1401                         } else {
1402                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1403                                 napi_gro_receive(&priv->napi, skb);
1404                         }
1405
1406                         priv->dev->stats.rx_packets++;
1407                         priv->dev->stats.rx_bytes += frame_len;
1408                 }
1409                 entry = next_entry;
1410                 p = p_next;     /* use prefetched values */
1411         }
1412
1413         stmmac_rx_refill(priv);
1414
1415         priv->xstats.rx_pkt_n += count;
1416
1417         return count;
1418 }
1419
1420 /**
1421  *  stmmac_poll - stmmac poll method (NAPI)
1422  *  @napi : pointer to the napi structure.
1423  *  @budget : maximum number of packets that the current CPU can receive from
1424  *            all interfaces.
1425  *  Description :
1426  *   This function implements the the reception process.
1427  *   Also it runs the TX completion thread
1428  */
1429 static int stmmac_poll(struct napi_struct *napi, int budget)
1430 {
1431         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1432         int work_done = 0;
1433
1434         priv->xstats.poll_n++;
1435         stmmac_tx(priv);
1436         work_done = stmmac_rx(priv, budget);
1437
1438         if (work_done < budget) {
1439                 napi_complete(napi);
1440                 stmmac_enable_irq(priv);
1441         }
1442         return work_done;
1443 }
1444
1445 /**
1446  *  stmmac_tx_timeout
1447  *  @dev : Pointer to net device structure
1448  *  Description: this function is called when a packet transmission fails to
1449  *   complete within a reasonable tmrate. The driver will mark the error in the
1450  *   netdev structure and arrange for the device to be reset to a sane state
1451  *   in order to transmit a new packet.
1452  */
1453 static void stmmac_tx_timeout(struct net_device *dev)
1454 {
1455         struct stmmac_priv *priv = netdev_priv(dev);
1456
1457         /* Clear Tx resources and restart transmitting again */
1458         stmmac_tx_err(priv);
1459 }
1460
1461 /* Configuration changes (passed on by ifconfig) */
1462 static int stmmac_config(struct net_device *dev, struct ifmap *map)
1463 {
1464         if (dev->flags & IFF_UP)        /* can't act on a running interface */
1465                 return -EBUSY;
1466
1467         /* Don't allow changing the I/O address */
1468         if (map->base_addr != dev->base_addr) {
1469                 pr_warning("%s: can't change I/O address\n", dev->name);
1470                 return -EOPNOTSUPP;
1471         }
1472
1473         /* Don't allow changing the IRQ */
1474         if (map->irq != dev->irq) {
1475                 pr_warning("%s: can't change IRQ number %d\n",
1476                        dev->name, dev->irq);
1477                 return -EOPNOTSUPP;
1478         }
1479
1480         /* ignore other fields */
1481         return 0;
1482 }
1483
1484 /**
1485  *  stmmac_set_rx_mode - entry point for multicast addressing
1486  *  @dev : pointer to the device structure
1487  *  Description:
1488  *  This function is a driver entry point which gets called by the kernel
1489  *  whenever multicast addresses must be enabled/disabled.
1490  *  Return value:
1491  *  void.
1492  */
1493 static void stmmac_set_rx_mode(struct net_device *dev)
1494 {
1495         struct stmmac_priv *priv = netdev_priv(dev);
1496
1497         spin_lock(&priv->lock);
1498         priv->hw->mac->set_filter(dev);
1499         spin_unlock(&priv->lock);
1500 }
1501
1502 /**
1503  *  stmmac_change_mtu - entry point to change MTU size for the device.
1504  *  @dev : device pointer.
1505  *  @new_mtu : the new MTU size for the device.
1506  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
1507  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
1508  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
1509  *  Return value:
1510  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1511  *  file on failure.
1512  */
1513 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1514 {
1515         struct stmmac_priv *priv = netdev_priv(dev);
1516         int max_mtu;
1517
1518         if (netif_running(dev)) {
1519                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1520                 return -EBUSY;
1521         }
1522
1523         if (priv->plat->enh_desc)
1524                 max_mtu = JUMBO_LEN;
1525         else
1526                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
1527
1528         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1529                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1530                 return -EINVAL;
1531         }
1532
1533         dev->mtu = new_mtu;
1534         netdev_update_features(dev);
1535
1536         return 0;
1537 }
1538
1539 static netdev_features_t stmmac_fix_features(struct net_device *dev,
1540         netdev_features_t features)
1541 {
1542         struct stmmac_priv *priv = netdev_priv(dev);
1543
1544         if (!priv->rx_coe)
1545                 features &= ~NETIF_F_RXCSUM;
1546         if (!priv->plat->tx_coe)
1547                 features &= ~NETIF_F_ALL_CSUM;
1548
1549         /* Some GMAC devices have a bugged Jumbo frame support that
1550          * needs to have the Tx COE disabled for oversized frames
1551          * (due to limited buffer sizes). In this case we disable
1552          * the TX csum insertionin the TDES and not use SF. */
1553         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1554                 features &= ~NETIF_F_ALL_CSUM;
1555
1556         return features;
1557 }
1558
1559 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1560 {
1561         struct net_device *dev = (struct net_device *)dev_id;
1562         struct stmmac_priv *priv = netdev_priv(dev);
1563
1564         if (unlikely(!dev)) {
1565                 pr_err("%s: invalid dev pointer\n", __func__);
1566                 return IRQ_NONE;
1567         }
1568
1569         if (priv->plat->has_gmac)
1570                 /* To handle GMAC own interrupts */
1571                 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr);
1572
1573         stmmac_dma_interrupt(priv);
1574
1575         return IRQ_HANDLED;
1576 }
1577
1578 #ifdef CONFIG_NET_POLL_CONTROLLER
1579 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1580  * to allow network I/O with interrupts disabled. */
1581 static void stmmac_poll_controller(struct net_device *dev)
1582 {
1583         disable_irq(dev->irq);
1584         stmmac_interrupt(dev->irq, dev);
1585         enable_irq(dev->irq);
1586 }
1587 #endif
1588
1589 /**
1590  *  stmmac_ioctl - Entry point for the Ioctl
1591  *  @dev: Device pointer.
1592  *  @rq: An IOCTL specefic structure, that can contain a pointer to
1593  *  a proprietary structure used to pass information to the driver.
1594  *  @cmd: IOCTL command
1595  *  Description:
1596  *  Currently there are no special functionality supported in IOCTL, just the
1597  *  phy_mii_ioctl(...) can be invoked.
1598  */
1599 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1600 {
1601         struct stmmac_priv *priv = netdev_priv(dev);
1602         int ret;
1603
1604         if (!netif_running(dev))
1605                 return -EINVAL;
1606
1607         if (!priv->phydev)
1608                 return -EINVAL;
1609
1610         ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1611
1612         return ret;
1613 }
1614
1615 #ifdef CONFIG_STMMAC_DEBUG_FS
1616 static struct dentry *stmmac_fs_dir;
1617 static struct dentry *stmmac_rings_status;
1618 static struct dentry *stmmac_dma_cap;
1619
1620 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1621 {
1622         struct tmp_s {
1623                 u64 a;
1624                 unsigned int b;
1625                 unsigned int c;
1626         };
1627         int i;
1628         struct net_device *dev = seq->private;
1629         struct stmmac_priv *priv = netdev_priv(dev);
1630
1631         seq_printf(seq, "=======================\n");
1632         seq_printf(seq, " RX descriptor ring\n");
1633         seq_printf(seq, "=======================\n");
1634
1635         for (i = 0; i < priv->dma_rx_size; i++) {
1636                 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i);
1637                 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1638                            i, (unsigned int)(x->a),
1639                            (unsigned int)((x->a) >> 32), x->b, x->c);
1640                 seq_printf(seq, "\n");
1641         }
1642
1643         seq_printf(seq, "\n");
1644         seq_printf(seq, "=======================\n");
1645         seq_printf(seq, "  TX descriptor ring\n");
1646         seq_printf(seq, "=======================\n");
1647
1648         for (i = 0; i < priv->dma_tx_size; i++) {
1649                 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i);
1650                 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1651                            i, (unsigned int)(x->a),
1652                            (unsigned int)((x->a) >> 32), x->b, x->c);
1653                 seq_printf(seq, "\n");
1654         }
1655
1656         return 0;
1657 }
1658
1659 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1660 {
1661         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1662 }
1663
1664 static const struct file_operations stmmac_rings_status_fops = {
1665         .owner = THIS_MODULE,
1666         .open = stmmac_sysfs_ring_open,
1667         .read = seq_read,
1668         .llseek = seq_lseek,
1669         .release = seq_release,
1670 };
1671
1672 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1673 {
1674         struct net_device *dev = seq->private;
1675         struct stmmac_priv *priv = netdev_priv(dev);
1676
1677         if (!priv->hw_cap_support) {
1678                 seq_printf(seq, "DMA HW features not supported\n");
1679                 return 0;
1680         }
1681
1682         seq_printf(seq, "==============================\n");
1683         seq_printf(seq, "\tDMA HW features\n");
1684         seq_printf(seq, "==============================\n");
1685
1686         seq_printf(seq, "\t10/100 Mbps %s\n",
1687                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1688         seq_printf(seq, "\t1000 Mbps %s\n",
1689                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
1690         seq_printf(seq, "\tHalf duple %s\n",
1691                    (priv->dma_cap.half_duplex) ? "Y" : "N");
1692         seq_printf(seq, "\tHash Filter: %s\n",
1693                    (priv->dma_cap.hash_filter) ? "Y" : "N");
1694         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1695                    (priv->dma_cap.multi_addr) ? "Y" : "N");
1696         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1697                    (priv->dma_cap.pcs) ? "Y" : "N");
1698         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1699                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
1700         seq_printf(seq, "\tPMT Remote wake up: %s\n",
1701                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1702         seq_printf(seq, "\tPMT Magic Frame: %s\n",
1703                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1704         seq_printf(seq, "\tRMON module: %s\n",
1705                    (priv->dma_cap.rmon) ? "Y" : "N");
1706         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1707                    (priv->dma_cap.time_stamp) ? "Y" : "N");
1708         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1709                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
1710         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1711                    (priv->dma_cap.eee) ? "Y" : "N");
1712         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1713         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1714                    (priv->dma_cap.tx_coe) ? "Y" : "N");
1715         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1716                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1717         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1718                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1719         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1720                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1721         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1722                    priv->dma_cap.number_rx_channel);
1723         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1724                    priv->dma_cap.number_tx_channel);
1725         seq_printf(seq, "\tEnhanced descriptors: %s\n",
1726                    (priv->dma_cap.enh_desc) ? "Y" : "N");
1727
1728         return 0;
1729 }
1730
1731 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1732 {
1733         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1734 }
1735
1736 static const struct file_operations stmmac_dma_cap_fops = {
1737         .owner = THIS_MODULE,
1738         .open = stmmac_sysfs_dma_cap_open,
1739         .read = seq_read,
1740         .llseek = seq_lseek,
1741         .release = seq_release,
1742 };
1743
1744 static int stmmac_init_fs(struct net_device *dev)
1745 {
1746         /* Create debugfs entries */
1747         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
1748
1749         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
1750                 pr_err("ERROR %s, debugfs create directory failed\n",
1751                        STMMAC_RESOURCE_NAME);
1752
1753                 return -ENOMEM;
1754         }
1755
1756         /* Entry to report DMA RX/TX rings */
1757         stmmac_rings_status = debugfs_create_file("descriptors_status",
1758                                            S_IRUGO, stmmac_fs_dir, dev,
1759                                            &stmmac_rings_status_fops);
1760
1761         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
1762                 pr_info("ERROR creating stmmac ring debugfs file\n");
1763                 debugfs_remove(stmmac_fs_dir);
1764
1765                 return -ENOMEM;
1766         }
1767
1768         /* Entry to report the DMA HW features */
1769         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
1770                                              dev, &stmmac_dma_cap_fops);
1771
1772         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
1773                 pr_info("ERROR creating stmmac MMC debugfs file\n");
1774                 debugfs_remove(stmmac_rings_status);
1775                 debugfs_remove(stmmac_fs_dir);
1776
1777                 return -ENOMEM;
1778         }
1779
1780         return 0;
1781 }
1782
1783 static void stmmac_exit_fs(void)
1784 {
1785         debugfs_remove(stmmac_rings_status);
1786         debugfs_remove(stmmac_dma_cap);
1787         debugfs_remove(stmmac_fs_dir);
1788 }
1789 #endif /* CONFIG_STMMAC_DEBUG_FS */
1790
1791 static const struct net_device_ops stmmac_netdev_ops = {
1792         .ndo_open = stmmac_open,
1793         .ndo_start_xmit = stmmac_xmit,
1794         .ndo_stop = stmmac_release,
1795         .ndo_change_mtu = stmmac_change_mtu,
1796         .ndo_fix_features = stmmac_fix_features,
1797         .ndo_set_rx_mode = stmmac_set_rx_mode,
1798         .ndo_tx_timeout = stmmac_tx_timeout,
1799         .ndo_do_ioctl = stmmac_ioctl,
1800         .ndo_set_config = stmmac_config,
1801 #ifdef CONFIG_NET_POLL_CONTROLLER
1802         .ndo_poll_controller = stmmac_poll_controller,
1803 #endif
1804         .ndo_set_mac_address = eth_mac_addr,
1805 };
1806
1807 /**
1808  * stmmac_dvr_probe
1809  * @device: device pointer
1810  * Description: this is the main probe function used to
1811  * call the alloc_etherdev, allocate the priv structure.
1812  */
1813 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
1814                                         struct plat_stmmacenet_data *plat_dat)
1815 {
1816         int ret = 0;
1817         struct net_device *ndev = NULL;
1818         struct stmmac_priv *priv;
1819
1820         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1821         if (!ndev) {
1822                 pr_err("%s: ERROR: allocating the device\n", __func__);
1823                 return NULL;
1824         }
1825
1826         SET_NETDEV_DEV(ndev, device);
1827
1828         priv = netdev_priv(ndev);
1829         priv->device = device;
1830         priv->dev = ndev;
1831
1832         ether_setup(ndev);
1833
1834         ndev->netdev_ops = &stmmac_netdev_ops;
1835         stmmac_set_ethtool_ops(ndev);
1836
1837         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1838         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1839         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
1840 #ifdef STMMAC_VLAN_TAG_USED
1841         /* Both mac100 and gmac support receive VLAN tag detection */
1842         ndev->features |= NETIF_F_HW_VLAN_RX;
1843 #endif
1844         priv->msg_enable = netif_msg_init(debug, default_msg_level);
1845
1846         if (flow_ctrl)
1847                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
1848
1849         priv->pause = pause;
1850         priv->plat = plat_dat;
1851         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
1852
1853         spin_lock_init(&priv->lock);
1854         spin_lock_init(&priv->tx_lock);
1855
1856         ret = register_netdev(ndev);
1857         if (ret) {
1858                 pr_err("%s: ERROR %i registering the device\n",
1859                        __func__, ret);
1860                 goto error;
1861         }
1862
1863         DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1864             ndev->name, (ndev->features & NETIF_F_SG) ? "on" : "off",
1865             (ndev->features & NETIF_F_IP_CSUM) ? "on" : "off");
1866
1867         return priv;
1868
1869 error:
1870         netif_napi_del(&priv->napi);
1871
1872         unregister_netdev(ndev);
1873         free_netdev(ndev);
1874
1875         return NULL;
1876 }
1877
1878 /**
1879  * stmmac_dvr_remove
1880  * @ndev: net device pointer
1881  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1882  * changes the link status, releases the DMA descriptor rings.
1883  */
1884 int stmmac_dvr_remove(struct net_device *ndev)
1885 {
1886         struct stmmac_priv *priv = netdev_priv(ndev);
1887
1888         pr_info("%s:\n\tremoving driver", __func__);
1889
1890         priv->hw->dma->stop_rx(priv->ioaddr);
1891         priv->hw->dma->stop_tx(priv->ioaddr);
1892
1893         stmmac_set_mac(priv->ioaddr, false);
1894         netif_carrier_off(ndev);
1895         unregister_netdev(ndev);
1896         free_netdev(ndev);
1897
1898         return 0;
1899 }
1900
1901 #ifdef CONFIG_PM
1902 int stmmac_suspend(struct net_device *ndev)
1903 {
1904         struct stmmac_priv *priv = netdev_priv(ndev);
1905         int dis_ic = 0;
1906
1907         if (!ndev || !netif_running(ndev))
1908                 return 0;
1909
1910         if (priv->phydev)
1911                 phy_stop(priv->phydev);
1912
1913         spin_lock(&priv->lock);
1914
1915         netif_device_detach(ndev);
1916         netif_stop_queue(ndev);
1917
1918 #ifdef CONFIG_STMMAC_TIMER
1919         priv->tm->timer_stop();
1920         if (likely(priv->tm->enable))
1921                 dis_ic = 1;
1922 #endif
1923         napi_disable(&priv->napi);
1924
1925         /* Stop TX/RX DMA */
1926         priv->hw->dma->stop_tx(priv->ioaddr);
1927         priv->hw->dma->stop_rx(priv->ioaddr);
1928         /* Clear the Rx/Tx descriptors */
1929         priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
1930                                      dis_ic);
1931         priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
1932
1933         /* Enable Power down mode by programming the PMT regs */
1934         if (device_may_wakeup(priv->device))
1935                 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
1936         else
1937                 stmmac_set_mac(priv->ioaddr, false);
1938
1939         spin_unlock(&priv->lock);
1940         return 0;
1941 }
1942
1943 int stmmac_resume(struct net_device *ndev)
1944 {
1945         struct stmmac_priv *priv = netdev_priv(ndev);
1946
1947         if (!netif_running(ndev))
1948                 return 0;
1949
1950         spin_lock(&priv->lock);
1951
1952         /* Power Down bit, into the PM register, is cleared
1953          * automatically as soon as a magic packet or a Wake-up frame
1954          * is received. Anyway, it's better to manually clear
1955          * this bit because it can generate problems while resuming
1956          * from another devices (e.g. serial console). */
1957         if (device_may_wakeup(priv->device))
1958                 priv->hw->mac->pmt(priv->ioaddr, 0);
1959
1960         netif_device_attach(ndev);
1961
1962         /* Enable the MAC and DMA */
1963         stmmac_set_mac(priv->ioaddr, true);
1964         priv->hw->dma->start_tx(priv->ioaddr);
1965         priv->hw->dma->start_rx(priv->ioaddr);
1966
1967 #ifdef CONFIG_STMMAC_TIMER
1968         if (likely(priv->tm->enable))
1969                 priv->tm->timer_start(tmrate);
1970 #endif
1971         napi_enable(&priv->napi);
1972
1973         netif_start_queue(ndev);
1974
1975         spin_unlock(&priv->lock);
1976
1977         if (priv->phydev)
1978                 phy_start(priv->phydev);
1979
1980         return 0;
1981 }
1982
1983 int stmmac_freeze(struct net_device *ndev)
1984 {
1985         if (!ndev || !netif_running(ndev))
1986                 return 0;
1987
1988         return stmmac_release(ndev);
1989 }
1990
1991 int stmmac_restore(struct net_device *ndev)
1992 {
1993         if (!ndev || !netif_running(ndev))
1994                 return 0;
1995
1996         return stmmac_open(ndev);
1997 }
1998 #endif /* CONFIG_PM */
1999
2000 #ifndef MODULE
2001 static int __init stmmac_cmdline_opt(char *str)
2002 {
2003         char *opt;
2004
2005         if (!str || !*str)
2006                 return -EINVAL;
2007         while ((opt = strsep(&str, ",")) != NULL) {
2008                 if (!strncmp(opt, "debug:", 6)) {
2009                         if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug))
2010                                 goto err;
2011                 } else if (!strncmp(opt, "phyaddr:", 8)) {
2012                         if (strict_strtoul(opt + 8, 0,
2013                                            (unsigned long *)&phyaddr))
2014                                 goto err;
2015                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2016                         if (strict_strtoul(opt + 11, 0,
2017                                            (unsigned long *)&dma_txsize))
2018                                 goto err;
2019                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2020                         if (strict_strtoul(opt + 11, 0,
2021                                            (unsigned long *)&dma_rxsize))
2022                                 goto err;
2023                 } else if (!strncmp(opt, "buf_sz:", 7)) {
2024                         if (strict_strtoul(opt + 7, 0,
2025                                            (unsigned long *)&buf_sz))
2026                                 goto err;
2027                 } else if (!strncmp(opt, "tc:", 3)) {
2028                         if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc))
2029                                 goto err;
2030                 } else if (!strncmp(opt, "watchdog:", 9)) {
2031                         if (strict_strtoul(opt + 9, 0,
2032                                            (unsigned long *)&watchdog))
2033                                 goto err;
2034                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2035                         if (strict_strtoul(opt + 10, 0,
2036                                            (unsigned long *)&flow_ctrl))
2037                                 goto err;
2038                 } else if (!strncmp(opt, "pause:", 6)) {
2039                         if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause))
2040                                 goto err;
2041 #ifdef CONFIG_STMMAC_TIMER
2042                 } else if (!strncmp(opt, "tmrate:", 7)) {
2043                         if (strict_strtoul(opt + 7, 0,
2044                                            (unsigned long *)&tmrate))
2045                                 goto err;
2046 #endif
2047                 }
2048         }
2049         return 0;
2050
2051 err:
2052         pr_err("%s: ERROR broken module parameter conversion", __func__);
2053         return -EINVAL;
2054 }
2055
2056 __setup("stmmaceth=", stmmac_cmdline_opt);
2057 #endif
2058
2059 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2060 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2061 MODULE_LICENSE("GPL");