7c7b54e4828eae30372f5842180b62d4787d8e30
[linux-2.6.git] / drivers / net / cpmac.c
1 /*
2  * Copyright (C) 2006, 2007 Eugene Konev
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
17  */
18
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/moduleparam.h>
22
23 #include <linux/sched.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/types.h>
28 #include <linux/delay.h>
29 #include <linux/version.h>
30
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/phy_fixed.h>
38 #include <linux/platform_device.h>
39 #include <linux/dma-mapping.h>
40 #include <asm/gpio.h>
41 #include <asm/atomic.h>
42
43 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
44 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
45 MODULE_LICENSE("GPL");
46 MODULE_ALIAS("platform:cpmac");
47
48 static int debug_level = 8;
49 static int dumb_switch;
50
51 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
52 module_param(debug_level, int, 0444);
53 module_param(dumb_switch, int, 0444);
54
55 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
56 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
57
58 #define CPMAC_VERSION "0.5.0"
59 /* frame size + 802.1q tag */
60 #define CPMAC_SKB_SIZE          (ETH_FRAME_LEN + 4)
61 #define CPMAC_QUEUES    8
62
63 /* Ethernet registers */
64 #define CPMAC_TX_CONTROL                0x0004
65 #define CPMAC_TX_TEARDOWN               0x0008
66 #define CPMAC_RX_CONTROL                0x0014
67 #define CPMAC_RX_TEARDOWN               0x0018
68 #define CPMAC_MBP                       0x0100
69 # define MBP_RXPASSCRC                  0x40000000
70 # define MBP_RXQOS                      0x20000000
71 # define MBP_RXNOCHAIN                  0x10000000
72 # define MBP_RXCMF                      0x01000000
73 # define MBP_RXSHORT                    0x00800000
74 # define MBP_RXCEF                      0x00400000
75 # define MBP_RXPROMISC                  0x00200000
76 # define MBP_PROMISCCHAN(channel)       (((channel) & 0x7) << 16)
77 # define MBP_RXBCAST                    0x00002000
78 # define MBP_BCASTCHAN(channel)         (((channel) & 0x7) << 8)
79 # define MBP_RXMCAST                    0x00000020
80 # define MBP_MCASTCHAN(channel)         ((channel) & 0x7)
81 #define CPMAC_UNICAST_ENABLE            0x0104
82 #define CPMAC_UNICAST_CLEAR             0x0108
83 #define CPMAC_MAX_LENGTH                0x010c
84 #define CPMAC_BUFFER_OFFSET             0x0110
85 #define CPMAC_MAC_CONTROL               0x0160
86 # define MAC_TXPTYPE                    0x00000200
87 # define MAC_TXPACE                     0x00000040
88 # define MAC_MII                        0x00000020
89 # define MAC_TXFLOW                     0x00000010
90 # define MAC_RXFLOW                     0x00000008
91 # define MAC_MTEST                      0x00000004
92 # define MAC_LOOPBACK                   0x00000002
93 # define MAC_FDX                        0x00000001
94 #define CPMAC_MAC_STATUS                0x0164
95 # define MAC_STATUS_QOS                 0x00000004
96 # define MAC_STATUS_RXFLOW              0x00000002
97 # define MAC_STATUS_TXFLOW              0x00000001
98 #define CPMAC_TX_INT_ENABLE             0x0178
99 #define CPMAC_TX_INT_CLEAR              0x017c
100 #define CPMAC_MAC_INT_VECTOR            0x0180
101 # define MAC_INT_STATUS                 0x00080000
102 # define MAC_INT_HOST                   0x00040000
103 # define MAC_INT_RX                     0x00020000
104 # define MAC_INT_TX                     0x00010000
105 #define CPMAC_MAC_EOI_VECTOR            0x0184
106 #define CPMAC_RX_INT_ENABLE             0x0198
107 #define CPMAC_RX_INT_CLEAR              0x019c
108 #define CPMAC_MAC_INT_ENABLE            0x01a8
109 #define CPMAC_MAC_INT_CLEAR             0x01ac
110 #define CPMAC_MAC_ADDR_LO(channel)      (0x01b0 + (channel) * 4)
111 #define CPMAC_MAC_ADDR_MID              0x01d0
112 #define CPMAC_MAC_ADDR_HI               0x01d4
113 #define CPMAC_MAC_HASH_LO               0x01d8
114 #define CPMAC_MAC_HASH_HI               0x01dc
115 #define CPMAC_TX_PTR(channel)           (0x0600 + (channel) * 4)
116 #define CPMAC_RX_PTR(channel)           (0x0620 + (channel) * 4)
117 #define CPMAC_TX_ACK(channel)           (0x0640 + (channel) * 4)
118 #define CPMAC_RX_ACK(channel)           (0x0660 + (channel) * 4)
119 #define CPMAC_REG_END                   0x0680
120 /*
121  * Rx/Tx statistics
122  * TODO: use some of them to fill stats in cpmac_stats()
123  */
124 #define CPMAC_STATS_RX_GOOD             0x0200
125 #define CPMAC_STATS_RX_BCAST            0x0204
126 #define CPMAC_STATS_RX_MCAST            0x0208
127 #define CPMAC_STATS_RX_PAUSE            0x020c
128 #define CPMAC_STATS_RX_CRC              0x0210
129 #define CPMAC_STATS_RX_ALIGN            0x0214
130 #define CPMAC_STATS_RX_OVER             0x0218
131 #define CPMAC_STATS_RX_JABBER           0x021c
132 #define CPMAC_STATS_RX_UNDER            0x0220
133 #define CPMAC_STATS_RX_FRAG             0x0224
134 #define CPMAC_STATS_RX_FILTER           0x0228
135 #define CPMAC_STATS_RX_QOSFILTER        0x022c
136 #define CPMAC_STATS_RX_OCTETS           0x0230
137
138 #define CPMAC_STATS_TX_GOOD             0x0234
139 #define CPMAC_STATS_TX_BCAST            0x0238
140 #define CPMAC_STATS_TX_MCAST            0x023c
141 #define CPMAC_STATS_TX_PAUSE            0x0240
142 #define CPMAC_STATS_TX_DEFER            0x0244
143 #define CPMAC_STATS_TX_COLLISION        0x0248
144 #define CPMAC_STATS_TX_SINGLECOLL       0x024c
145 #define CPMAC_STATS_TX_MULTICOLL        0x0250
146 #define CPMAC_STATS_TX_EXCESSCOLL       0x0254
147 #define CPMAC_STATS_TX_LATECOLL         0x0258
148 #define CPMAC_STATS_TX_UNDERRUN         0x025c
149 #define CPMAC_STATS_TX_CARRIERSENSE     0x0260
150 #define CPMAC_STATS_TX_OCTETS           0x0264
151
152 #define cpmac_read(base, reg)           (readl((void __iomem *)(base) + (reg)))
153 #define cpmac_write(base, reg, val)     (writel(val, (void __iomem *)(base) + \
154                                                 (reg)))
155
156 /* MDIO bus */
157 #define CPMAC_MDIO_VERSION              0x0000
158 #define CPMAC_MDIO_CONTROL              0x0004
159 # define MDIOC_IDLE                     0x80000000
160 # define MDIOC_ENABLE                   0x40000000
161 # define MDIOC_PREAMBLE                 0x00100000
162 # define MDIOC_FAULT                    0x00080000
163 # define MDIOC_FAULTDETECT              0x00040000
164 # define MDIOC_INTTEST                  0x00020000
165 # define MDIOC_CLKDIV(div)              ((div) & 0xff)
166 #define CPMAC_MDIO_ALIVE                0x0008
167 #define CPMAC_MDIO_LINK                 0x000c
168 #define CPMAC_MDIO_ACCESS(channel)      (0x0080 + (channel) * 8)
169 # define MDIO_BUSY                      0x80000000
170 # define MDIO_WRITE                     0x40000000
171 # define MDIO_REG(reg)                  (((reg) & 0x1f) << 21)
172 # define MDIO_PHY(phy)                  (((phy) & 0x1f) << 16)
173 # define MDIO_DATA(data)                ((data) & 0xffff)
174 #define CPMAC_MDIO_PHYSEL(channel)      (0x0084 + (channel) * 8)
175 # define PHYSEL_LINKSEL                 0x00000040
176 # define PHYSEL_LINKINT                 0x00000020
177
178 struct cpmac_desc {
179         u32 hw_next;
180         u32 hw_data;
181         u16 buflen;
182         u16 bufflags;
183         u16 datalen;
184         u16 dataflags;
185 #define CPMAC_SOP                       0x8000
186 #define CPMAC_EOP                       0x4000
187 #define CPMAC_OWN                       0x2000
188 #define CPMAC_EOQ                       0x1000
189         struct sk_buff *skb;
190         struct cpmac_desc *next;
191         struct cpmac_desc *prev;
192         dma_addr_t mapping;
193         dma_addr_t data_mapping;
194 };
195
196 struct cpmac_priv {
197         spinlock_t lock;
198         spinlock_t rx_lock;
199         struct cpmac_desc *rx_head;
200         int ring_size;
201         struct cpmac_desc *desc_ring;
202         dma_addr_t dma_ring;
203         void __iomem *regs;
204         struct mii_bus *mii_bus;
205         struct phy_device *phy;
206         char phy_name[BUS_ID_SIZE];
207         int oldlink, oldspeed, oldduplex;
208         u32 msg_enable;
209         struct net_device *dev;
210         struct work_struct reset_work;
211         struct platform_device *pdev;
212         struct napi_struct napi;
213         atomic_t reset_pending;
214 };
215
216 static irqreturn_t cpmac_irq(int, void *);
217 static void cpmac_hw_start(struct net_device *dev);
218 static void cpmac_hw_stop(struct net_device *dev);
219 static int cpmac_stop(struct net_device *dev);
220 static int cpmac_open(struct net_device *dev);
221
222 static void cpmac_dump_regs(struct net_device *dev)
223 {
224         int i;
225         struct cpmac_priv *priv = netdev_priv(dev);
226         for (i = 0; i < CPMAC_REG_END; i += 4) {
227                 if (i % 16 == 0) {
228                         if (i)
229                                 printk("\n");
230                         printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
231                                priv->regs + i);
232                 }
233                 printk(" %08x", cpmac_read(priv->regs, i));
234         }
235         printk("\n");
236 }
237
238 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
239 {
240         int i;
241         printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
242         for (i = 0; i < sizeof(*desc) / 4; i++)
243                 printk(" %08x", ((u32 *)desc)[i]);
244         printk("\n");
245 }
246
247 static void cpmac_dump_all_desc(struct net_device *dev)
248 {
249         struct cpmac_priv *priv = netdev_priv(dev);
250         struct cpmac_desc *dump = priv->rx_head;
251         do {
252                 cpmac_dump_desc(dev, dump);
253                 dump = dump->next;
254         } while (dump != priv->rx_head);
255 }
256
257 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
258 {
259         int i;
260         printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
261         for (i = 0; i < skb->len; i++) {
262                 if (i % 16 == 0) {
263                         if (i)
264                                 printk("\n");
265                         printk(KERN_DEBUG "%s: data[%p]:", dev->name,
266                                skb->data + i);
267                 }
268                 printk(" %02x", ((u8 *)skb->data)[i]);
269         }
270         printk("\n");
271 }
272
273 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
274 {
275         u32 val;
276
277         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
278                 cpu_relax();
279         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
280                     MDIO_PHY(phy_id));
281         while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
282                 cpu_relax();
283         return MDIO_DATA(val);
284 }
285
286 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
287                             int reg, u16 val)
288 {
289         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
290                 cpu_relax();
291         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
292                     MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
293         return 0;
294 }
295
296 static int cpmac_mdio_reset(struct mii_bus *bus)
297 {
298         ar7_device_reset(AR7_RESET_BIT_MDIO);
299         cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
300                     MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
301         return 0;
302 }
303
304 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
305
306 static struct mii_bus cpmac_mii = {
307         .name = "cpmac-mii",
308         .read = cpmac_mdio_read,
309         .write = cpmac_mdio_write,
310         .reset = cpmac_mdio_reset,
311         .irq = mii_irqs,
312 };
313
314 static int cpmac_config(struct net_device *dev, struct ifmap *map)
315 {
316         if (dev->flags & IFF_UP)
317                 return -EBUSY;
318
319         /* Don't allow changing the I/O address */
320         if (map->base_addr != dev->base_addr)
321                 return -EOPNOTSUPP;
322
323         /* ignore other fields */
324         return 0;
325 }
326
327 static void cpmac_set_multicast_list(struct net_device *dev)
328 {
329         struct dev_mc_list *iter;
330         int i;
331         u8 tmp;
332         u32 mbp, bit, hash[2] = { 0, };
333         struct cpmac_priv *priv = netdev_priv(dev);
334
335         mbp = cpmac_read(priv->regs, CPMAC_MBP);
336         if (dev->flags & IFF_PROMISC) {
337                 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
338                             MBP_RXPROMISC);
339         } else {
340                 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
341                 if (dev->flags & IFF_ALLMULTI) {
342                         /* enable all multicast mode */
343                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
344                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
345                 } else {
346                         /*
347                          * cpmac uses some strange mac address hashing
348                          * (not crc32)
349                          */
350                         for (i = 0, iter = dev->mc_list; i < dev->mc_count;
351                              i++, iter = iter->next) {
352                                 bit = 0;
353                                 tmp = iter->dmi_addr[0];
354                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
355                                 tmp = iter->dmi_addr[1];
356                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
357                                 tmp = iter->dmi_addr[2];
358                                 bit  ^= (tmp >> 6) ^ tmp;
359                                 tmp = iter->dmi_addr[3];
360                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
361                                 tmp = iter->dmi_addr[4];
362                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
363                                 tmp = iter->dmi_addr[5];
364                                 bit  ^= (tmp >> 6) ^ tmp;
365                                 bit &= 0x3f;
366                                 hash[bit / 32] |= 1 << (bit % 32);
367                         }
368
369                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
370                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
371                 }
372         }
373 }
374
375 static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
376                                     struct cpmac_desc *desc)
377 {
378         struct sk_buff *skb, *result = NULL;
379
380         if (unlikely(netif_msg_hw(priv)))
381                 cpmac_dump_desc(priv->dev, desc);
382         cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
383         if (unlikely(!desc->datalen)) {
384                 if (netif_msg_rx_err(priv) && net_ratelimit())
385                         printk(KERN_WARNING "%s: rx: spurious interrupt\n",
386                                priv->dev->name);
387                 return NULL;
388         }
389
390         skb = netdev_alloc_skb(priv->dev, CPMAC_SKB_SIZE);
391         if (likely(skb)) {
392                 skb_reserve(skb, 2);
393                 skb_put(desc->skb, desc->datalen);
394                 desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
395                 desc->skb->ip_summed = CHECKSUM_NONE;
396                 priv->dev->stats.rx_packets++;
397                 priv->dev->stats.rx_bytes += desc->datalen;
398                 result = desc->skb;
399                 dma_unmap_single(&priv->dev->dev, desc->data_mapping,
400                                  CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
401                 desc->skb = skb;
402                 desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
403                                                     CPMAC_SKB_SIZE,
404                                                     DMA_FROM_DEVICE);
405                 desc->hw_data = (u32)desc->data_mapping;
406                 if (unlikely(netif_msg_pktdata(priv))) {
407                         printk(KERN_DEBUG "%s: received packet:\n",
408                                priv->dev->name);
409                         cpmac_dump_skb(priv->dev, result);
410                 }
411         } else {
412                 if (netif_msg_rx_err(priv) && net_ratelimit())
413                         printk(KERN_WARNING
414                                "%s: low on skbs, dropping packet\n",
415                                priv->dev->name);
416                 priv->dev->stats.rx_dropped++;
417         }
418
419         desc->buflen = CPMAC_SKB_SIZE;
420         desc->dataflags = CPMAC_OWN;
421
422         return result;
423 }
424
425 static int cpmac_poll(struct napi_struct *napi, int budget)
426 {
427         struct sk_buff *skb;
428         struct cpmac_desc *desc, *restart;
429         struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
430         int received = 0, processed = 0;
431
432         spin_lock(&priv->rx_lock);
433         if (unlikely(!priv->rx_head)) {
434                 if (netif_msg_rx_err(priv) && net_ratelimit())
435                         printk(KERN_WARNING "%s: rx: polling, but no queue\n",
436                                priv->dev->name);
437                 spin_unlock(&priv->rx_lock);
438                 netif_rx_complete(priv->dev, napi);
439                 return 0;
440         }
441
442         desc = priv->rx_head;
443         restart = NULL;
444         while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
445                 processed++;
446
447                 if ((desc->dataflags & CPMAC_EOQ) != 0) {
448                         /* The last update to eoq->hw_next didn't happen
449                         * soon enough, and the receiver stopped here.
450                         *Remember this descriptor so we can restart
451                         * the receiver after freeing some space.
452                         */
453                         if (unlikely(restart)) {
454                                 if (netif_msg_rx_err(priv))
455                                         printk(KERN_ERR "%s: poll found a"
456                                                 " duplicate EOQ: %p and %p\n",
457                                                 priv->dev->name, restart, desc);
458                                 goto fatal_error;
459                         }
460
461                         restart = desc->next;
462                 }
463
464                 skb = cpmac_rx_one(priv, desc);
465                 if (likely(skb)) {
466                         netif_receive_skb(skb);
467                         received++;
468                 }
469                 desc = desc->next;
470         }
471
472         if (desc != priv->rx_head) {
473                 /* We freed some buffers, but not the whole ring,
474                  * add what we did free to the rx list */
475                 desc->prev->hw_next = (u32)0;
476                 priv->rx_head->prev->hw_next = priv->rx_head->mapping;
477         }
478
479         /* Optimization: If we did not actually process an EOQ (perhaps because
480          * of quota limits), check to see if the tail of the queue has EOQ set.
481         * We should immediately restart in that case so that the receiver can
482         * restart and run in parallel with more packet processing.
483         * This lets us handle slightly larger bursts before running
484         * out of ring space (assuming dev->weight < ring_size) */
485
486         if (!restart &&
487              (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ))
488                     == CPMAC_EOQ &&
489              (priv->rx_head->dataflags & CPMAC_OWN) != 0) {
490                 /* reset EOQ so the poll loop (above) doesn't try to
491                 * restart this when it eventually gets to this descriptor.
492                 */
493                 priv->rx_head->prev->dataflags &= ~CPMAC_EOQ;
494                 restart = priv->rx_head;
495         }
496
497         if (restart) {
498                 priv->dev->stats.rx_errors++;
499                 priv->dev->stats.rx_fifo_errors++;
500                 if (netif_msg_rx_err(priv) && net_ratelimit())
501                         printk(KERN_WARNING "%s: rx dma ring overrun\n",
502                                priv->dev->name);
503
504                 if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) {
505                         if (netif_msg_drv(priv))
506                                 printk(KERN_ERR "%s: cpmac_poll is trying to "
507                                         "restart rx from a descriptor that's "
508                                         "not free: %p\n",
509                                         priv->dev->name, restart);
510                                 goto fatal_error;
511                 }
512
513                 cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);
514         }
515
516         priv->rx_head = desc;
517         spin_unlock(&priv->rx_lock);
518         if (unlikely(netif_msg_rx_status(priv)))
519                 printk(KERN_DEBUG "%s: poll processed %d packets\n",
520                        priv->dev->name, received);
521         if (processed == 0) {
522                 /* we ran out of packets to read,
523                  * revert to interrupt-driven mode */
524                 netif_rx_complete(priv->dev, napi);
525                 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
526                 return 0;
527         }
528
529         return 1;
530
531 fatal_error:
532         /* Something went horribly wrong.
533          * Reset hardware to try to recover rather than wedging. */
534
535         if (netif_msg_drv(priv)) {
536                 printk(KERN_ERR "%s: cpmac_poll is confused. "
537                                 "Resetting hardware\n", priv->dev->name);
538                 cpmac_dump_all_desc(priv->dev);
539                 printk(KERN_DEBUG "%s: RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
540                         priv->dev->name,
541                         cpmac_read(priv->regs, CPMAC_RX_PTR(0)),
542                         cpmac_read(priv->regs, CPMAC_RX_ACK(0)));
543         }
544
545         spin_unlock(&priv->rx_lock);
546         netif_rx_complete(priv->dev, napi);
547         netif_stop_queue(priv->dev);
548         napi_disable(&priv->napi);
549
550         atomic_inc(&priv->reset_pending);
551         cpmac_hw_stop(priv->dev);
552         if (!schedule_work(&priv->reset_work))
553                 atomic_dec(&priv->reset_pending);
554         return 0;
555
556 }
557
558 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
559 {
560         int queue, len;
561         struct cpmac_desc *desc;
562         struct cpmac_priv *priv = netdev_priv(dev);
563
564         if (unlikely(atomic_read(&priv->reset_pending)))
565                 return NETDEV_TX_BUSY;
566
567         if (unlikely(skb_padto(skb, ETH_ZLEN)))
568                 return NETDEV_TX_OK;
569
570         len = max(skb->len, ETH_ZLEN);
571         queue = skb_get_queue_mapping(skb);
572         netif_stop_subqueue(dev, queue);
573
574         desc = &priv->desc_ring[queue];
575         if (unlikely(desc->dataflags & CPMAC_OWN)) {
576                 if (netif_msg_tx_err(priv) && net_ratelimit())
577                         printk(KERN_WARNING "%s: tx dma ring full\n",
578                                dev->name);
579                 return NETDEV_TX_BUSY;
580         }
581
582         spin_lock(&priv->lock);
583         dev->trans_start = jiffies;
584         spin_unlock(&priv->lock);
585         desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
586         desc->skb = skb;
587         desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
588                                             DMA_TO_DEVICE);
589         desc->hw_data = (u32)desc->data_mapping;
590         desc->datalen = len;
591         desc->buflen = len;
592         if (unlikely(netif_msg_tx_queued(priv)))
593                 printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
594                        skb->len);
595         if (unlikely(netif_msg_hw(priv)))
596                 cpmac_dump_desc(dev, desc);
597         if (unlikely(netif_msg_pktdata(priv)))
598                 cpmac_dump_skb(dev, skb);
599         cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
600
601         return NETDEV_TX_OK;
602 }
603
604 static void cpmac_end_xmit(struct net_device *dev, int queue)
605 {
606         struct cpmac_desc *desc;
607         struct cpmac_priv *priv = netdev_priv(dev);
608
609         desc = &priv->desc_ring[queue];
610         cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
611         if (likely(desc->skb)) {
612                 spin_lock(&priv->lock);
613                 dev->stats.tx_packets++;
614                 dev->stats.tx_bytes += desc->skb->len;
615                 spin_unlock(&priv->lock);
616                 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
617                                  DMA_TO_DEVICE);
618
619                 if (unlikely(netif_msg_tx_done(priv)))
620                         printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
621                                desc->skb, desc->skb->len);
622
623                 dev_kfree_skb_irq(desc->skb);
624                 desc->skb = NULL;
625                 if (netif_subqueue_stopped(dev, queue))
626                         netif_wake_subqueue(dev, queue);
627         } else {
628                 if (netif_msg_tx_err(priv) && net_ratelimit())
629                         printk(KERN_WARNING
630                                "%s: end_xmit: spurious interrupt\n", dev->name);
631                 if (netif_subqueue_stopped(dev, queue))
632                         netif_wake_subqueue(dev, queue);
633         }
634 }
635
636 static void cpmac_hw_stop(struct net_device *dev)
637 {
638         int i;
639         struct cpmac_priv *priv = netdev_priv(dev);
640         struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
641
642         ar7_device_reset(pdata->reset_bit);
643         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
644                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
645         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
646                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
647         for (i = 0; i < 8; i++) {
648                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
649                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
650         }
651         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
652         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
653         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
654         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
655         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
656                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
657 }
658
659 static void cpmac_hw_start(struct net_device *dev)
660 {
661         int i;
662         struct cpmac_priv *priv = netdev_priv(dev);
663         struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
664
665         ar7_device_reset(pdata->reset_bit);
666         for (i = 0; i < 8; i++) {
667                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
668                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
669         }
670         cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
671
672         cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
673                     MBP_RXMCAST);
674         cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
675         for (i = 0; i < 8; i++)
676                 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
677         cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
678         cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
679                     (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
680                     (dev->dev_addr[3] << 24));
681         cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
682         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
683         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
684         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
685         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
686         cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
687         cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
688         cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
689         cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
690
691         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
692                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
693         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
694                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
695         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
696                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
697                     MAC_FDX);
698 }
699
700 static void cpmac_clear_rx(struct net_device *dev)
701 {
702         struct cpmac_priv *priv = netdev_priv(dev);
703         struct cpmac_desc *desc;
704         int i;
705         if (unlikely(!priv->rx_head))
706                 return;
707         desc = priv->rx_head;
708         for (i = 0; i < priv->ring_size; i++) {
709                 if ((desc->dataflags & CPMAC_OWN) == 0) {
710                         if (netif_msg_rx_err(priv) && net_ratelimit())
711                                 printk(KERN_WARNING "%s: packet dropped\n",
712                                        dev->name);
713                         if (unlikely(netif_msg_hw(priv)))
714                                 cpmac_dump_desc(dev, desc);
715                         desc->dataflags = CPMAC_OWN;
716                         dev->stats.rx_dropped++;
717                 }
718                 desc->hw_next = desc->next->mapping;
719                 desc = desc->next;
720         }
721         priv->rx_head->prev->hw_next = 0;
722 }
723
724 static void cpmac_clear_tx(struct net_device *dev)
725 {
726         struct cpmac_priv *priv = netdev_priv(dev);
727         int i;
728         if (unlikely(!priv->desc_ring))
729                 return;
730         for (i = 0; i < CPMAC_QUEUES; i++) {
731                 priv->desc_ring[i].dataflags = 0;
732                 if (priv->desc_ring[i].skb) {
733                         dev_kfree_skb_any(priv->desc_ring[i].skb);
734                         priv->desc_ring[i].skb = NULL;
735                 }
736         }
737 }
738
739 static void cpmac_hw_error(struct work_struct *work)
740 {
741         int i;
742         struct cpmac_priv *priv =
743                 container_of(work, struct cpmac_priv, reset_work);
744
745         spin_lock(&priv->rx_lock);
746         cpmac_clear_rx(priv->dev);
747         spin_unlock(&priv->rx_lock);
748         cpmac_clear_tx(priv->dev);
749         cpmac_hw_start(priv->dev);
750         barrier();
751         atomic_dec(&priv->reset_pending);
752
753         for (i = 0; i < CPMAC_QUEUES; i++)
754                 netif_wake_subqueue(priv->dev, i);
755         netif_wake_queue(priv->dev);
756         cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
757 }
758
759 static void cpmac_check_status(struct net_device *dev)
760 {
761         struct cpmac_priv *priv = netdev_priv(dev);
762
763         u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS);
764         int rx_channel = (macstatus >> 8) & 7;
765         int rx_code = (macstatus >> 12) & 15;
766         int tx_channel = (macstatus >> 16) & 7;
767         int tx_code = (macstatus >> 20) & 15;
768
769         if (rx_code || tx_code) {
770                 if (netif_msg_drv(priv) && net_ratelimit()) {
771                         /* Can't find any documentation on what these
772                          *error codes actually are. So just log them and hope..
773                          */
774                         if (rx_code)
775                                 printk(KERN_WARNING "%s: host error %d on rx "
776                                      "channel %d (macstatus %08x), resetting\n",
777                                      dev->name, rx_code, rx_channel, macstatus);
778                         if (tx_code)
779                                 printk(KERN_WARNING "%s: host error %d on tx "
780                                      "channel %d (macstatus %08x), resetting\n",
781                                      dev->name, tx_code, tx_channel, macstatus);
782                 }
783
784                 netif_stop_queue(dev);
785                 cpmac_hw_stop(dev);
786                 if (schedule_work(&priv->reset_work))
787                         atomic_inc(&priv->reset_pending);
788                 if (unlikely(netif_msg_hw(priv)))
789                         cpmac_dump_regs(dev);
790         }
791         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
792 }
793
794 static irqreturn_t cpmac_irq(int irq, void *dev_id)
795 {
796         struct net_device *dev = dev_id;
797         struct cpmac_priv *priv;
798         int queue;
799         u32 status;
800
801         priv = netdev_priv(dev);
802
803         status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
804
805         if (unlikely(netif_msg_intr(priv)))
806                 printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
807                        status);
808
809         if (status & MAC_INT_TX)
810                 cpmac_end_xmit(dev, (status & 7));
811
812         if (status & MAC_INT_RX) {
813                 queue = (status >> 8) & 7;
814                 if (netif_rx_schedule_prep(dev, &priv->napi)) {
815                         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
816                         __netif_rx_schedule(dev, &priv->napi);
817                 }
818         }
819
820         cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
821
822         if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS)))
823                 cpmac_check_status(dev);
824
825         return IRQ_HANDLED;
826 }
827
828 static void cpmac_tx_timeout(struct net_device *dev)
829 {
830         int i;
831         struct cpmac_priv *priv = netdev_priv(dev);
832
833         spin_lock(&priv->lock);
834         dev->stats.tx_errors++;
835         spin_unlock(&priv->lock);
836         if (netif_msg_tx_err(priv) && net_ratelimit())
837                 printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
838
839         atomic_inc(&priv->reset_pending);
840         barrier();
841         cpmac_clear_tx(dev);
842         barrier();
843         atomic_dec(&priv->reset_pending);
844
845         netif_wake_queue(priv->dev);
846         for (i = 0; i < CPMAC_QUEUES; i++)
847                 netif_wake_subqueue(dev, i);
848 }
849
850 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
851 {
852         struct cpmac_priv *priv = netdev_priv(dev);
853         if (!(netif_running(dev)))
854                 return -EINVAL;
855         if (!priv->phy)
856                 return -EINVAL;
857         if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
858             (cmd == SIOCSMIIREG))
859                 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
860
861         return -EOPNOTSUPP;
862 }
863
864 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
865 {
866         struct cpmac_priv *priv = netdev_priv(dev);
867
868         if (priv->phy)
869                 return phy_ethtool_gset(priv->phy, cmd);
870
871         return -EINVAL;
872 }
873
874 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
875 {
876         struct cpmac_priv *priv = netdev_priv(dev);
877
878         if (!capable(CAP_NET_ADMIN))
879                 return -EPERM;
880
881         if (priv->phy)
882                 return phy_ethtool_sset(priv->phy, cmd);
883
884         return -EINVAL;
885 }
886
887 static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
888 {
889         struct cpmac_priv *priv = netdev_priv(dev);
890
891         ring->rx_max_pending = 1024;
892         ring->rx_mini_max_pending = 1;
893         ring->rx_jumbo_max_pending = 1;
894         ring->tx_max_pending = 1;
895
896         ring->rx_pending = priv->ring_size;
897         ring->rx_mini_pending = 1;
898         ring->rx_jumbo_pending = 1;
899         ring->tx_pending = 1;
900 }
901
902 static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
903 {
904         struct cpmac_priv *priv = netdev_priv(dev);
905
906         if (netif_running(dev))
907                 return -EBUSY;
908         priv->ring_size = ring->rx_pending;
909         return 0;
910 }
911
912 static void cpmac_get_drvinfo(struct net_device *dev,
913                               struct ethtool_drvinfo *info)
914 {
915         strcpy(info->driver, "cpmac");
916         strcpy(info->version, CPMAC_VERSION);
917         info->fw_version[0] = '\0';
918         sprintf(info->bus_info, "%s", "cpmac");
919         info->regdump_len = 0;
920 }
921
922 static const struct ethtool_ops cpmac_ethtool_ops = {
923         .get_settings = cpmac_get_settings,
924         .set_settings = cpmac_set_settings,
925         .get_drvinfo = cpmac_get_drvinfo,
926         .get_link = ethtool_op_get_link,
927         .get_ringparam = cpmac_get_ringparam,
928         .set_ringparam = cpmac_set_ringparam,
929 };
930
931 static void cpmac_adjust_link(struct net_device *dev)
932 {
933         struct cpmac_priv *priv = netdev_priv(dev);
934         int new_state = 0;
935
936         spin_lock(&priv->lock);
937         if (priv->phy->link) {
938                 netif_start_queue(dev);
939                 if (priv->phy->duplex != priv->oldduplex) {
940                         new_state = 1;
941                         priv->oldduplex = priv->phy->duplex;
942                 }
943
944                 if (priv->phy->speed != priv->oldspeed) {
945                         new_state = 1;
946                         priv->oldspeed = priv->phy->speed;
947                 }
948
949                 if (!priv->oldlink) {
950                         new_state = 1;
951                         priv->oldlink = 1;
952                         netif_schedule(dev);
953                 }
954         } else if (priv->oldlink) {
955                 netif_stop_queue(dev);
956                 new_state = 1;
957                 priv->oldlink = 0;
958                 priv->oldspeed = 0;
959                 priv->oldduplex = -1;
960         }
961
962         if (new_state && netif_msg_link(priv) && net_ratelimit())
963                 phy_print_status(priv->phy);
964
965         spin_unlock(&priv->lock);
966 }
967
968 static int cpmac_open(struct net_device *dev)
969 {
970         int i, size, res;
971         struct cpmac_priv *priv = netdev_priv(dev);
972         struct resource *mem;
973         struct cpmac_desc *desc;
974         struct sk_buff *skb;
975
976         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
977         if (!request_mem_region(mem->start, mem->end - mem->start, dev->name)) {
978                 if (netif_msg_drv(priv))
979                         printk(KERN_ERR "%s: failed to request registers\n",
980                                dev->name);
981                 res = -ENXIO;
982                 goto fail_reserve;
983         }
984
985         priv->regs = ioremap(mem->start, mem->end - mem->start);
986         if (!priv->regs) {
987                 if (netif_msg_drv(priv))
988                         printk(KERN_ERR "%s: failed to remap registers\n",
989                                dev->name);
990                 res = -ENXIO;
991                 goto fail_remap;
992         }
993
994         size = priv->ring_size + CPMAC_QUEUES;
995         priv->desc_ring = dma_alloc_coherent(&dev->dev,
996                                              sizeof(struct cpmac_desc) * size,
997                                              &priv->dma_ring,
998                                              GFP_KERNEL);
999         if (!priv->desc_ring) {
1000                 res = -ENOMEM;
1001                 goto fail_alloc;
1002         }
1003
1004         for (i = 0; i < size; i++)
1005                 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
1006
1007         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1008         for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
1009                 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
1010                 if (unlikely(!skb)) {
1011                         res = -ENOMEM;
1012                         goto fail_desc;
1013                 }
1014                 skb_reserve(skb, 2);
1015                 desc->skb = skb;
1016                 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
1017                                                     CPMAC_SKB_SIZE,
1018                                                     DMA_FROM_DEVICE);
1019                 desc->hw_data = (u32)desc->data_mapping;
1020                 desc->buflen = CPMAC_SKB_SIZE;
1021                 desc->dataflags = CPMAC_OWN;
1022                 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
1023                 desc->next->prev = desc;
1024                 desc->hw_next = (u32)desc->next->mapping;
1025         }
1026
1027         priv->rx_head->prev->hw_next = (u32)0;
1028
1029         if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
1030                                dev->name, dev))) {
1031                 if (netif_msg_drv(priv))
1032                         printk(KERN_ERR "%s: failed to obtain irq\n",
1033                                dev->name);
1034                 goto fail_irq;
1035         }
1036
1037         atomic_set(&priv->reset_pending, 0);
1038         INIT_WORK(&priv->reset_work, cpmac_hw_error);
1039         cpmac_hw_start(dev);
1040
1041         napi_enable(&priv->napi);
1042         priv->phy->state = PHY_CHANGELINK;
1043         phy_start(priv->phy);
1044
1045         return 0;
1046
1047 fail_irq:
1048 fail_desc:
1049         for (i = 0; i < priv->ring_size; i++) {
1050                 if (priv->rx_head[i].skb) {
1051                         dma_unmap_single(&dev->dev,
1052                                          priv->rx_head[i].data_mapping,
1053                                          CPMAC_SKB_SIZE,
1054                                          DMA_FROM_DEVICE);
1055                         kfree_skb(priv->rx_head[i].skb);
1056                 }
1057         }
1058 fail_alloc:
1059         kfree(priv->desc_ring);
1060         iounmap(priv->regs);
1061
1062 fail_remap:
1063         release_mem_region(mem->start, mem->end - mem->start);
1064
1065 fail_reserve:
1066         return res;
1067 }
1068
1069 static int cpmac_stop(struct net_device *dev)
1070 {
1071         int i;
1072         struct cpmac_priv *priv = netdev_priv(dev);
1073         struct resource *mem;
1074
1075         netif_stop_queue(dev);
1076
1077         cancel_work_sync(&priv->reset_work);
1078         napi_disable(&priv->napi);
1079         phy_stop(priv->phy);
1080
1081         cpmac_hw_stop(dev);
1082
1083         for (i = 0; i < 8; i++)
1084                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
1085         cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
1086         cpmac_write(priv->regs, CPMAC_MBP, 0);
1087
1088         free_irq(dev->irq, dev);
1089         iounmap(priv->regs);
1090         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
1091         release_mem_region(mem->start, mem->end - mem->start);
1092         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1093         for (i = 0; i < priv->ring_size; i++) {
1094                 if (priv->rx_head[i].skb) {
1095                         dma_unmap_single(&dev->dev,
1096                                          priv->rx_head[i].data_mapping,
1097                                          CPMAC_SKB_SIZE,
1098                                          DMA_FROM_DEVICE);
1099                         kfree_skb(priv->rx_head[i].skb);
1100                 }
1101         }
1102
1103         dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
1104                           (CPMAC_QUEUES + priv->ring_size),
1105                           priv->desc_ring, priv->dma_ring);
1106         return 0;
1107 }
1108
1109 static int external_switch;
1110
1111 static int __devinit cpmac_probe(struct platform_device *pdev)
1112 {
1113         int rc, phy_id, i;
1114         char *mdio_bus_id = "0";
1115         struct resource *mem;
1116         struct cpmac_priv *priv;
1117         struct net_device *dev;
1118         struct plat_cpmac_data *pdata;
1119         DECLARE_MAC_BUF(mac);
1120
1121         pdata = pdev->dev.platform_data;
1122
1123         for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1124                 if (!(pdata->phy_mask & (1 << phy_id)))
1125                         continue;
1126                 if (!cpmac_mii.phy_map[phy_id])
1127                         continue;
1128                 break;
1129         }
1130
1131         if (phy_id == PHY_MAX_ADDR) {
1132                 if (external_switch || dumb_switch) {
1133                         mdio_bus_id = 0; /* fixed phys bus */
1134                         phy_id = pdev->id;
1135                 } else {
1136                         dev_err(&pdev->dev, "no PHY present\n");
1137                         return -ENODEV;
1138                 }
1139         }
1140
1141         dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1142
1143         if (!dev) {
1144                 printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
1145                 return -ENOMEM;
1146         }
1147
1148         platform_set_drvdata(pdev, dev);
1149         priv = netdev_priv(dev);
1150
1151         priv->pdev = pdev;
1152         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1153         if (!mem) {
1154                 rc = -ENODEV;
1155                 goto fail;
1156         }
1157
1158         dev->irq = platform_get_irq_byname(pdev, "irq");
1159
1160         dev->open               = cpmac_open;
1161         dev->stop               = cpmac_stop;
1162         dev->set_config         = cpmac_config;
1163         dev->hard_start_xmit    = cpmac_start_xmit;
1164         dev->do_ioctl           = cpmac_ioctl;
1165         dev->set_multicast_list = cpmac_set_multicast_list;
1166         dev->tx_timeout         = cpmac_tx_timeout;
1167         dev->ethtool_ops        = &cpmac_ethtool_ops;
1168
1169         netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
1170
1171         spin_lock_init(&priv->lock);
1172         spin_lock_init(&priv->rx_lock);
1173         priv->dev = dev;
1174         priv->ring_size = 64;
1175         priv->msg_enable = netif_msg_init(debug_level, 0xff);
1176         memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr));
1177
1178         priv->phy = phy_connect(dev, cpmac_mii.phy_map[phy_id]->dev.bus_id,
1179                                 &cpmac_adjust_link, 0, PHY_INTERFACE_MODE_MII);
1180         if (IS_ERR(priv->phy)) {
1181                 if (netif_msg_drv(priv))
1182                         printk(KERN_ERR "%s: Could not attach to PHY\n",
1183                                dev->name);
1184                 return PTR_ERR(priv->phy);
1185         }
1186
1187         if ((rc = register_netdev(dev))) {
1188                 printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1189                        dev->name);
1190                 goto fail;
1191         }
1192
1193         if (netif_msg_probe(priv)) {
1194                 printk(KERN_INFO
1195                        "cpmac: device %s (regs: %p, irq: %d, phy: %s, "
1196                        "mac: %s)\n", dev->name, (void *)mem->start, dev->irq,
1197                        priv->phy_name, print_mac(mac, dev->dev_addr));
1198         }
1199         return 0;
1200
1201 fail:
1202         free_netdev(dev);
1203         return rc;
1204 }
1205
1206 static int __devexit cpmac_remove(struct platform_device *pdev)
1207 {
1208         struct net_device *dev = platform_get_drvdata(pdev);
1209         unregister_netdev(dev);
1210         free_netdev(dev);
1211         return 0;
1212 }
1213
1214 static struct platform_driver cpmac_driver = {
1215         .driver.name = "cpmac",
1216         .driver.owner = THIS_MODULE,
1217         .probe = cpmac_probe,
1218         .remove = __devexit_p(cpmac_remove),
1219 };
1220
1221 int __devinit cpmac_init(void)
1222 {
1223         u32 mask;
1224         int i, res;
1225
1226         cpmac_mii.priv = ioremap(AR7_REGS_MDIO, 256);
1227
1228         if (!cpmac_mii.priv) {
1229                 printk(KERN_ERR "Can't ioremap mdio registers\n");
1230                 return -ENXIO;
1231         }
1232
1233 #warning FIXME: unhardcode gpio&reset bits
1234         ar7_gpio_disable(26);
1235         ar7_gpio_disable(27);
1236         ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1237         ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1238         ar7_device_reset(AR7_RESET_BIT_EPHY);
1239
1240         cpmac_mii.reset(&cpmac_mii);
1241
1242         for (i = 0; i < 300000; i++)
1243                 if ((mask = cpmac_read(cpmac_mii.priv, CPMAC_MDIO_ALIVE)))
1244                         break;
1245                 else
1246                         cpu_relax();
1247
1248         mask &= 0x7fffffff;
1249         if (mask & (mask - 1)) {
1250                 external_switch = 1;
1251                 mask = 0;
1252         }
1253
1254         cpmac_mii.phy_mask = ~(mask | 0x80000000);
1255         snprintf(cpmac_mii.id, MII_BUS_ID_SIZE, "0");
1256
1257         res = mdiobus_register(&cpmac_mii);
1258         if (res)
1259                 goto fail_mii;
1260
1261         res = platform_driver_register(&cpmac_driver);
1262         if (res)
1263                 goto fail_cpmac;
1264
1265         return 0;
1266
1267 fail_cpmac:
1268         mdiobus_unregister(&cpmac_mii);
1269
1270 fail_mii:
1271         iounmap(cpmac_mii.priv);
1272
1273         return res;
1274 }
1275
1276 void __devexit cpmac_exit(void)
1277 {
1278         platform_driver_unregister(&cpmac_driver);
1279         mdiobus_unregister(&cpmac_mii);
1280         iounmap(cpmac_mii.priv);
1281 }
1282
1283 module_init(cpmac_init);
1284 module_exit(cpmac_exit);