bnx2x: New init infrastructure
[linux-2.6.git] / drivers / net / bnx2x_hsi.h
1 /* bnx2x_hsi.h: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2008 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  */
9
10
11 #define PORT_0                          0
12 #define PORT_1                          1
13 #define PORT_MAX                        2
14
15 /****************************************************************************
16  * Shared HW configuration                                                  *
17  ****************************************************************************/
18 struct shared_hw_cfg {                                   /* NVRAM Offset */
19         /* Up to 16 bytes of NULL-terminated string */
20         u8  part_num[16];                                       /* 0x104 */
21
22         u32 config;                                             /* 0x114 */
23 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
24 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT            0
25 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V             0x00000000
26 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V             0x00000001
27 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN        0x00000002
28
29 #define SHARED_HW_CFG_PORT_SWAP                     0x00000004
30
31 #define SHARED_HW_CFG_BEACON_WOL_EN                 0x00000008
32
33 #define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
34 #define SHARED_HW_CFG_MFW_SELECT_SHIFT              8
35         /* Whatever MFW found in NVM
36            (if multiple found, priority order is: NC-SI, UMP, IPMI) */
37 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT            0x00000000
38 #define SHARED_HW_CFG_MFW_SELECT_NC_SI              0x00000100
39 #define SHARED_HW_CFG_MFW_SELECT_UMP                0x00000200
40 #define SHARED_HW_CFG_MFW_SELECT_IPMI               0x00000300
41         /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
42           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
43 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI   0x00000400
44         /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
45           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
46 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI     0x00000500
47         /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
48           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
49 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP    0x00000600
50
51 #define SHARED_HW_CFG_LED_MODE_MASK                 0x000f0000
52 #define SHARED_HW_CFG_LED_MODE_SHIFT                16
53 #define SHARED_HW_CFG_LED_MAC1                      0x00000000
54 #define SHARED_HW_CFG_LED_PHY1                      0x00010000
55 #define SHARED_HW_CFG_LED_PHY2                      0x00020000
56 #define SHARED_HW_CFG_LED_PHY3                      0x00030000
57 #define SHARED_HW_CFG_LED_MAC2                      0x00040000
58 #define SHARED_HW_CFG_LED_PHY4                      0x00050000
59 #define SHARED_HW_CFG_LED_PHY5                      0x00060000
60 #define SHARED_HW_CFG_LED_PHY6                      0x00070000
61 #define SHARED_HW_CFG_LED_MAC3                      0x00080000
62 #define SHARED_HW_CFG_LED_PHY7                      0x00090000
63 #define SHARED_HW_CFG_LED_PHY9                      0x000a0000
64 #define SHARED_HW_CFG_LED_PHY11                     0x000b0000
65 #define SHARED_HW_CFG_LED_MAC4                      0x000c0000
66 #define SHARED_HW_CFG_LED_PHY8                      0x000d0000
67
68 #define SHARED_HW_CFG_AN_ENABLE_MASK                0x3f000000
69 #define SHARED_HW_CFG_AN_ENABLE_SHIFT               24
70 #define SHARED_HW_CFG_AN_ENABLE_CL37                0x01000000
71 #define SHARED_HW_CFG_AN_ENABLE_CL73                0x02000000
72 #define SHARED_HW_CFG_AN_ENABLE_BAM                 0x04000000
73 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION  0x08000000
74 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
75 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY          0x20000000
76
77         u32 config2;                                            /* 0x118 */
78         /* one time auto detect grace period (in sec) */
79 #define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff
80 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT            0
81
82 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED             0x00000100
83
84         /* The default value for the core clock is 250MHz and it is
85            achieved by setting the clock change to 4 */
86 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK             0x00000e00
87 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT            9
88
89 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ           0x00000000
90 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ           0x00001000
91
92 #define SHARED_HW_CFG_HIDE_PORT1                    0x00002000
93
94         u32 power_dissipated;                                   /* 0x11c */
95 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK            0xff000000
96 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT           24
97
98 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK         0x00ff0000
99 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT        16
100 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE      0x00000000
101 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT         0x00010000
102 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT        0x00020000
103 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT       0x00030000
104
105         u32 ump_nc_si_config;                                   /* 0x120 */
106 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
107 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT      0
108 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC        0x00000000
109 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY        0x00000001
110 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII        0x00000000
111 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII       0x00000002
112
113 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK       0x00000f00
114 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT      8
115
116 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000
117 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT  16
118 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE   0x00000000
119 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
120
121         u32 board;                                              /* 0x124 */
122 #define SHARED_HW_CFG_BOARD_TYPE_MASK               0x0000ffff
123 #define SHARED_HW_CFG_BOARD_TYPE_SHIFT              0
124 #define SHARED_HW_CFG_BOARD_TYPE_NONE               0x00000000
125 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1000     0x00000001
126 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1001     0x00000002
127 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G    0x00000003
128 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1004G    0x00000004
129 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1007G    0x00000005
130 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G    0x00000006
131 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G    0x00000007
132 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G    0x00000008
133 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G    0x00000009
134 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G    0x0000000a
135
136 #define SHARED_HW_CFG_BOARD_VER_MASK                0xffff0000
137 #define SHARED_HW_CFG_BOARD_VER_SHIFT               16
138 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0xf0000000
139 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT         28
140 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0x0f000000
141 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT         24
142 #define SHARED_HW_CFG_BOARD_REV_MASK                0x00ff0000
143 #define SHARED_HW_CFG_BOARD_REV_SHIFT               16
144
145         u32 reserved;                                           /* 0x128 */
146
147 };
148
149
150 /****************************************************************************
151  * Port HW configuration                                                    *
152  ****************************************************************************/
153 struct port_hw_cfg {                        /* port 0: 0x12c  port 1: 0x2bc */
154
155         u32 pci_id;
156 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000
157 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff
158
159         u32 pci_sub_id;
160 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000
161 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff
162
163         u32 power_dissipated;
164 #define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000
165 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT              24
166 #define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00ff0000
167 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT              16
168 #define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00
169 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT              8
170 #define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff
171 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT              0
172
173         u32 power_consumed;
174 #define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000
175 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT             24
176 #define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00ff0000
177 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT             16
178 #define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00
179 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT             8
180 #define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff
181 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT             0
182
183         u32 mac_upper;
184 #define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff
185 #define PORT_HW_CFG_UPPERMAC_SHIFT                  0
186         u32 mac_lower;
187
188         u32 iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
189         u32 iscsi_mac_lower;
190
191         u32 rdma_mac_upper;   /* Upper 16 bits are always zeroes */
192         u32 rdma_mac_lower;
193
194         u32 serdes_config;
195         /* for external PHY, or forced mode or during AN */
196 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
197 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT  16
198
199 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK    0x0000ffff
200 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT   0
201
202         u16 serdes_tx_driver_pre_emphasis[16];
203         u16 serdes_rx_driver_equalizer[16];
204
205         u32 xgxs_config_lane0;
206         u32 xgxs_config_lane1;
207         u32 xgxs_config_lane2;
208         u32 xgxs_config_lane3;
209         /* for external PHY, or forced mode or during AN */
210 #define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK   0xffff0000
211 #define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT  16
212
213 #define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK      0x0000ffff
214 #define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT     0
215
216         u16 xgxs_tx_driver_pre_emphasis_lane0[16];
217         u16 xgxs_tx_driver_pre_emphasis_lane1[16];
218         u16 xgxs_tx_driver_pre_emphasis_lane2[16];
219         u16 xgxs_tx_driver_pre_emphasis_lane3[16];
220
221         u16 xgxs_rx_driver_equalizer_lane0[16];
222         u16 xgxs_rx_driver_equalizer_lane1[16];
223         u16 xgxs_rx_driver_equalizer_lane2[16];
224         u16 xgxs_rx_driver_equalizer_lane3[16];
225
226         u32 lane_config;
227 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff
228 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT             0
229 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000ff
230 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT          0
231 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000ff00
232 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT          8
233 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000c000
234 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT      14
235         /* AN and forced */
236 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123          0x00001b1b
237         /* forced only */
238 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210          0x00001be4
239         /* forced only */
240 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120          0x0000d8d8
241         /* forced only */
242 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210          0x0000e4e4
243
244         u32 external_phy_config;
245 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xff000000
246 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT       24
247 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT      0x00000000
248 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482     0x01000000
249 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN    0xff000000
250
251 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00ff0000
252 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT       16
253
254 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000ff00
255 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT         8
256 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT        0x00000000
257 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071       0x00000100
258 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072       0x00000200
259 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073       0x00000300
260 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705       0x00000400
261 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706       0x00000500
262 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276       0x00000600
263 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481       0x00000700
264 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101       0x00000800
265 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE       0x0000fd00
266 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN      0x0000ff00
267
268 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff
269 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT         0
270
271         u32 speed_capability_mask;
272 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xffff0000
273 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT       16
274 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL    0x00010000
275 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF    0x00020000
276 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF   0x00040000
277 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL   0x00080000
278 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G          0x00100000
279 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G        0x00200000
280 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G         0x00400000
281 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G         0x00800000
282 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G       0x01000000
283 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G         0x02000000
284 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G         0x04000000
285 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G         0x08000000
286 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED    0xf0000000
287
288 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff
289 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT       0
290 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL    0x00000001
291 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF    0x00000002
292 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF   0x00000004
293 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL   0x00000008
294 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G          0x00000010
295 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G        0x00000020
296 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G         0x00000040
297 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G         0x00000080
298 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G       0x00000100
299 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G         0x00000200
300 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G         0x00000400
301 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G         0x00000800
302 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED    0x0000f000
303
304         u32 reserved[2];
305
306 };
307
308
309 /****************************************************************************
310  * Shared Feature configuration                                             *
311  ****************************************************************************/
312 struct shared_feat_cfg {                                 /* NVRAM Offset */
313
314         u32 config;                                             /* 0x450 */
315 #define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
316
317 };
318
319
320 /****************************************************************************
321  * Port Feature configuration                                               *
322  ****************************************************************************/
323 struct port_feat_cfg {                      /* port 0: 0x454  port 1: 0x4c8 */
324
325         u32 config;
326 #define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f
327 #define PORT_FEATURE_BAR1_SIZE_SHIFT                0
328 #define PORT_FEATURE_BAR1_SIZE_DISABLED             0x00000000
329 #define PORT_FEATURE_BAR1_SIZE_64K                  0x00000001
330 #define PORT_FEATURE_BAR1_SIZE_128K                 0x00000002
331 #define PORT_FEATURE_BAR1_SIZE_256K                 0x00000003
332 #define PORT_FEATURE_BAR1_SIZE_512K                 0x00000004
333 #define PORT_FEATURE_BAR1_SIZE_1M                   0x00000005
334 #define PORT_FEATURE_BAR1_SIZE_2M                   0x00000006
335 #define PORT_FEATURE_BAR1_SIZE_4M                   0x00000007
336 #define PORT_FEATURE_BAR1_SIZE_8M                   0x00000008
337 #define PORT_FEATURE_BAR1_SIZE_16M                  0x00000009
338 #define PORT_FEATURE_BAR1_SIZE_32M                  0x0000000a
339 #define PORT_FEATURE_BAR1_SIZE_64M                  0x0000000b
340 #define PORT_FEATURE_BAR1_SIZE_128M                 0x0000000c
341 #define PORT_FEATURE_BAR1_SIZE_256M                 0x0000000d
342 #define PORT_FEATURE_BAR1_SIZE_512M                 0x0000000e
343 #define PORT_FEATURE_BAR1_SIZE_1G                   0x0000000f
344 #define PORT_FEATURE_BAR2_SIZE_MASK                 0x000000f0
345 #define PORT_FEATURE_BAR2_SIZE_SHIFT                4
346 #define PORT_FEATURE_BAR2_SIZE_DISABLED             0x00000000
347 #define PORT_FEATURE_BAR2_SIZE_64K                  0x00000010
348 #define PORT_FEATURE_BAR2_SIZE_128K                 0x00000020
349 #define PORT_FEATURE_BAR2_SIZE_256K                 0x00000030
350 #define PORT_FEATURE_BAR2_SIZE_512K                 0x00000040
351 #define PORT_FEATURE_BAR2_SIZE_1M                   0x00000050
352 #define PORT_FEATURE_BAR2_SIZE_2M                   0x00000060
353 #define PORT_FEATURE_BAR2_SIZE_4M                   0x00000070
354 #define PORT_FEATURE_BAR2_SIZE_8M                   0x00000080
355 #define PORT_FEATURE_BAR2_SIZE_16M                  0x00000090
356 #define PORT_FEATURE_BAR2_SIZE_32M                  0x000000a0
357 #define PORT_FEATURE_BAR2_SIZE_64M                  0x000000b0
358 #define PORT_FEATURE_BAR2_SIZE_128M                 0x000000c0
359 #define PORT_FEATURE_BAR2_SIZE_256M                 0x000000d0
360 #define PORT_FEATURE_BAR2_SIZE_512M                 0x000000e0
361 #define PORT_FEATURE_BAR2_SIZE_1G                   0x000000f0
362 #define PORT_FEATURE_EN_SIZE_MASK                   0x07000000
363 #define PORT_FEATURE_EN_SIZE_SHIFT                  24
364 #define PORT_FEATURE_WOL_ENABLED                    0x01000000
365 #define PORT_FEATURE_MBA_ENABLED                    0x02000000
366 #define PORT_FEATURE_MFW_ENABLED                    0x04000000
367
368         u32 wol_config;
369         /* Default is used when driver sets to "auto" mode */
370 #define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003
371 #define PORT_FEATURE_WOL_DEFAULT_SHIFT              0
372 #define PORT_FEATURE_WOL_DEFAULT_DISABLE            0x00000000
373 #define PORT_FEATURE_WOL_DEFAULT_MAGIC              0x00000001
374 #define PORT_FEATURE_WOL_DEFAULT_ACPI               0x00000002
375 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI     0x00000003
376 #define PORT_FEATURE_WOL_RES_PAUSE_CAP              0x00000004
377 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008
378 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
379
380         u32 mba_config;
381 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000003
382 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT      0
383 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE        0x00000000
384 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL        0x00000001
385 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP      0x00000002
386 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB     0x00000003
387 #define PORT_FEATURE_MBA_RES_PAUSE_CAP              0x00000100
388 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP         0x00000200
389 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
390 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S              0x00000000
391 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B              0x00000800
392 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000ff000
393 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT         12
394 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED      0x00000000
395 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K            0x00001000
396 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K            0x00002000
397 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K            0x00003000
398 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K           0x00004000
399 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K           0x00005000
400 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K           0x00006000
401 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K          0x00007000
402 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K          0x00008000
403 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K          0x00009000
404 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M            0x0000a000
405 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M            0x0000b000
406 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M            0x0000c000
407 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M            0x0000d000
408 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M           0x0000e000
409 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M           0x0000f000
410 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00f00000
411 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT          20
412 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
413 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT       24
414 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO        0x00000000
415 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS         0x01000000
416 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H      0x02000000
417 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H      0x03000000
418 #define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3c000000
419 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT           26
420 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO            0x00000000
421 #define PORT_FEATURE_MBA_LINK_SPEED_10HD            0x04000000
422 #define PORT_FEATURE_MBA_LINK_SPEED_10FD            0x08000000
423 #define PORT_FEATURE_MBA_LINK_SPEED_100HD           0x0c000000
424 #define PORT_FEATURE_MBA_LINK_SPEED_100FD           0x10000000
425 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS           0x14000000
426 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS         0x18000000
427 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4      0x1c000000
428 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4      0x20000000
429 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR       0x24000000
430 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS          0x28000000
431 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS        0x2c000000
432 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS          0x30000000
433 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS          0x34000000
434 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS          0x38000000
435
436         u32 bmc_config;
437 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT      0x00000000
438 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN           0x00000001
439
440         u32 mba_vlan_cfg;
441 #define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff
442 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT             0
443 #define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
444
445         u32 resource_cfg;
446 #define PORT_FEATURE_RESOURCE_CFG_VALID             0x00000001
447 #define PORT_FEATURE_RESOURCE_CFG_DIAG              0x00000002
448 #define PORT_FEATURE_RESOURCE_CFG_L2                0x00000004
449 #define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x00000008
450 #define PORT_FEATURE_RESOURCE_CFG_RDMA              0x00000010
451
452         u32 smbus_config;
453         /* Obsolete */
454 #define PORT_FEATURE_SMBUS_EN                       0x00000001
455 #define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
456 #define PORT_FEATURE_SMBUS_ADDR_SHIFT               1
457
458         u32 reserved1;
459
460         u32 link_config;    /* Used as HW defaults for the driver */
461 #define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
462 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT         24
463         /* (forced) low speed switch (< 10G) */
464 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH           0x00000000
465         /* (forced) high speed switch (>= 10G) */
466 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH          0x01000000
467 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT         0x02000000
468 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT     0x03000000
469
470 #define PORT_FEATURE_LINK_SPEED_MASK                0x000f0000
471 #define PORT_FEATURE_LINK_SPEED_SHIFT               16
472 #define PORT_FEATURE_LINK_SPEED_AUTO                0x00000000
473 #define PORT_FEATURE_LINK_SPEED_10M_FULL            0x00010000
474 #define PORT_FEATURE_LINK_SPEED_10M_HALF            0x00020000
475 #define PORT_FEATURE_LINK_SPEED_100M_HALF           0x00030000
476 #define PORT_FEATURE_LINK_SPEED_100M_FULL           0x00040000
477 #define PORT_FEATURE_LINK_SPEED_1G                  0x00050000
478 #define PORT_FEATURE_LINK_SPEED_2_5G                0x00060000
479 #define PORT_FEATURE_LINK_SPEED_10G_CX4             0x00070000
480 #define PORT_FEATURE_LINK_SPEED_10G_KX4             0x00080000
481 #define PORT_FEATURE_LINK_SPEED_10G_KR              0x00090000
482 #define PORT_FEATURE_LINK_SPEED_12G                 0x000a0000
483 #define PORT_FEATURE_LINK_SPEED_12_5G               0x000b0000
484 #define PORT_FEATURE_LINK_SPEED_13G                 0x000c0000
485 #define PORT_FEATURE_LINK_SPEED_15G                 0x000d0000
486 #define PORT_FEATURE_LINK_SPEED_16G                 0x000e0000
487
488 #define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
489 #define PORT_FEATURE_FLOW_CONTROL_SHIFT             8
490 #define PORT_FEATURE_FLOW_CONTROL_AUTO              0x00000000
491 #define PORT_FEATURE_FLOW_CONTROL_TX                0x00000100
492 #define PORT_FEATURE_FLOW_CONTROL_RX                0x00000200
493 #define PORT_FEATURE_FLOW_CONTROL_BOTH              0x00000300
494 #define PORT_FEATURE_FLOW_CONTROL_NONE              0x00000400
495
496         /* The default for MCP link configuration,
497            uses the same defines as link_config */
498         u32 mfw_wol_link_cfg;
499
500         u32 reserved[19];
501
502 };
503
504
505 /*****************************************************************************
506  * Device Information                                                        *
507  *****************************************************************************/
508 struct dev_info {                                                    /* size */
509
510         u32    bc_rev; /* 8 bits each: major, minor, build */           /* 4 */
511
512         struct shared_hw_cfg     shared_hw_config;                     /* 40 */
513
514         struct port_hw_cfg       port_hw_config[PORT_MAX];      /* 400*2=800 */
515
516         struct shared_feat_cfg   shared_feature_config;                 /* 4 */
517
518         struct port_feat_cfg     port_feature_config[PORT_MAX]; /* 116*2=232 */
519
520 };
521
522
523 #define FUNC_0                          0
524 #define FUNC_1                          1
525 #define FUNC_2                          2
526 #define FUNC_3                          3
527 #define FUNC_4                          4
528 #define FUNC_5                          5
529 #define FUNC_6                          6
530 #define FUNC_7                          7
531 #define E1_FUNC_MAX                     2
532 #define E1H_FUNC_MAX                    8
533
534 #define VN_0                            0
535 #define VN_1                            1
536 #define VN_2                            2
537 #define VN_3                            3
538 #define E1VN_MAX                        1
539 #define E1HVN_MAX                       4
540
541
542 /* This value (in milliseconds) determines the frequency of the driver
543  * issuing the PULSE message code.  The firmware monitors this periodic
544  * pulse to determine when to switch to an OS-absent mode. */
545 #define DRV_PULSE_PERIOD_MS             250
546
547 /* This value (in milliseconds) determines how long the driver should
548  * wait for an acknowledgement from the firmware before timing out.  Once
549  * the firmware has timed out, the driver will assume there is no firmware
550  * running and there won't be any firmware-driver synchronization during a
551  * driver reset. */
552 #define FW_ACK_TIME_OUT_MS              5000
553
554 #define FW_ACK_POLL_TIME_MS             1
555
556 #define FW_ACK_NUM_OF_POLL      (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
557
558 /* LED Blink rate that will achieve ~15.9Hz */
559 #define LED_BLINK_RATE_VAL              480
560
561 /****************************************************************************
562  * Driver <-> FW Mailbox                                                    *
563  ****************************************************************************/
564 struct drv_port_mb {
565
566         u32 link_status;
567         /* Driver should update this field on any link change event */
568
569 #define LINK_STATUS_LINK_FLAG_MASK                      0x00000001
570 #define LINK_STATUS_LINK_UP                             0x00000001
571 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK               0x0000001E
572 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE    (0<<1)
573 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD              (1<<1)
574 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD              (2<<1)
575 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD            (3<<1)
576 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4              (4<<1)
577 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD            (5<<1)
578 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            (6<<1)
579 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (7<<1)
580 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD            (7<<1)
581 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD            (8<<1)
582 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD            (9<<1)
583 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD            (9<<1)
584 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD             (10<<1)
585 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD             (10<<1)
586 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD             (11<<1)
587 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD             (11<<1)
588 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD           (12<<1)
589 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD           (12<<1)
590 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD             (13<<1)
591 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD             (13<<1)
592 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD             (14<<1)
593 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD             (14<<1)
594 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD             (15<<1)
595 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD             (15<<1)
596
597 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK            0x00000020
598 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED              0x00000020
599
600 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE             0x00000040
601 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK        0x00000080
602 #define LINK_STATUS_PARALLEL_DETECTION_USED             0x00000080
603
604 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
605 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
606 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE          0x00000800
607 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE        0x00001000
608 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE        0x00002000
609 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE          0x00004000
610 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE          0x00008000
611
612 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK           0x00010000
613 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00010000
614
615 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK           0x00020000
616 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00020000
617
618 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
619 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0<<18)
620 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1<<18)
621 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2<<18)
622 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3<<18)
623
624 #define LINK_STATUS_SERDES_LINK                         0x00100000
625
626 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE        0x00200000
627 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE        0x00400000
628 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE         0x00800000
629 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE         0x01000000
630 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE       0x02000000
631 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE         0x04000000
632 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE         0x08000000
633 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE         0x10000000
634
635         u32 reserved[3];
636
637 };
638
639
640 struct drv_func_mb {
641
642         u32 drv_mb_header;
643 #define DRV_MSG_CODE_MASK                               0xffff0000
644 #define DRV_MSG_CODE_LOAD_REQ                           0x10000000
645 #define DRV_MSG_CODE_LOAD_DONE                          0x11000000
646 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN                  0x20000000
647 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS                 0x20010000
648 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP                 0x20020000
649 #define DRV_MSG_CODE_UNLOAD_DONE                        0x21000000
650 #define DRV_MSG_CODE_DIAG_ENTER_REQ                     0x50000000
651 #define DRV_MSG_CODE_DIAG_EXIT_REQ                      0x60000000
652 #define DRV_MSG_CODE_VALIDATE_KEY                       0x70000000
653 #define DRV_MSG_CODE_GET_CURR_KEY                       0x80000000
654 #define DRV_MSG_CODE_GET_UPGRADE_KEY                    0x81000000
655 #define DRV_MSG_CODE_GET_MANUF_KEY                      0x82000000
656 #define DRV_MSG_CODE_LOAD_L2B_PRAM                      0x90000000
657
658 #define DRV_MSG_SEQ_NUMBER_MASK                         0x0000ffff
659
660         u32 drv_mb_param;
661
662         u32 fw_mb_header;
663 #define FW_MSG_CODE_MASK                                0xffff0000
664 #define FW_MSG_CODE_DRV_LOAD_COMMON                     0x10100000
665 #define FW_MSG_CODE_DRV_LOAD_PORT                       0x10110000
666 #define FW_MSG_CODE_DRV_LOAD_FUNCTION                   0x10120000
667 #define FW_MSG_CODE_DRV_LOAD_REFUSED                    0x10200000
668 #define FW_MSG_CODE_DRV_LOAD_DONE                       0x11100000
669 #define FW_MSG_CODE_DRV_UNLOAD_COMMON                   0x20100000
670 #define FW_MSG_CODE_DRV_UNLOAD_PORT                     0x20110000
671 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION                 0x20120000
672 #define FW_MSG_CODE_DRV_UNLOAD_DONE                     0x21100000
673 #define FW_MSG_CODE_DIAG_ENTER_DONE                     0x50100000
674 #define FW_MSG_CODE_DIAG_REFUSE                         0x50200000
675 #define FW_MSG_CODE_DIAG_EXIT_DONE                      0x60100000
676 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS                0x70100000
677 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE                0x70200000
678 #define FW_MSG_CODE_GET_KEY_DONE                        0x80100000
679 #define FW_MSG_CODE_NO_KEY                              0x80f00000
680 #define FW_MSG_CODE_LIC_INFO_NOT_READY                  0x80f80000
681 #define FW_MSG_CODE_L2B_PRAM_LOADED                     0x90100000
682 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE             0x90210000
683 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE             0x90220000
684 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE             0x90230000
685 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE             0x90240000
686
687 #define FW_MSG_SEQ_NUMBER_MASK                          0x0000ffff
688
689         u32 fw_mb_param;
690
691         u32 drv_pulse_mb;
692 #define DRV_PULSE_SEQ_MASK                              0x00007fff
693 #define DRV_PULSE_SYSTEM_TIME_MASK                      0xffff0000
694         /* The system time is in the format of
695          * (year-2001)*12*32 + month*32 + day. */
696 #define DRV_PULSE_ALWAYS_ALIVE                          0x00008000
697         /* Indicate to the firmware not to go into the
698          * OS-absent when it is not getting driver pulse.
699          * This is used for debugging as well for PXE(MBA). */
700
701         u32 mcp_pulse_mb;
702 #define MCP_PULSE_SEQ_MASK                              0x00007fff
703 #define MCP_PULSE_ALWAYS_ALIVE                          0x00008000
704         /* Indicates to the driver not to assert due to lack
705          * of MCP response */
706 #define MCP_EVENT_MASK                                  0xffff0000
707 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ                0x00010000
708
709         u32 iscsi_boot_signature;
710         u32 iscsi_boot_block_offset;
711
712         u32 reserved[3];
713
714 };
715
716
717 /****************************************************************************
718  * Management firmware state                                                *
719  ****************************************************************************/
720 /* Allocate 440 bytes for management firmware */
721 #define MGMTFW_STATE_WORD_SIZE                              110
722
723 struct mgmtfw_state {
724         u32 opaque[MGMTFW_STATE_WORD_SIZE];
725 };
726
727
728 /****************************************************************************
729  * Shared Memory Region                                                     *
730  ****************************************************************************/
731 struct shmem_region {                          /*   SharedMem Offset (size) */
732
733         u32                     validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
734 #define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
735 #define SHR_MEM_FORMAT_REV_MASK                     0xff000000
736         /* validity bits */
737 #define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
738 #define SHR_MEM_VALIDITY_MB                         0x00200000
739 #define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
740 #define SHR_MEM_VALIDITY_RESERVED                   0x00000007
741         /* One licensing bit should be set */
742 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
743 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
744 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
745 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
746         /* Active MFW */
747 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
748 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
749 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
750 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
751 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
752 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
753
754         struct dev_info         dev_info;                /* 0x8     (0x438) */
755
756         u8                      reserved[52*PORT_MAX];
757
758         /* FW information (for internal FW use) */
759         u32                     fw_info_fio_offset;    /* 0x4a8       (0x4) */
760         struct mgmtfw_state     mgmtfw_state;          /* 0x4ac     (0x1b8) */
761
762         struct drv_port_mb      port_mb[PORT_MAX];     /* 0x664 (16*2=0x20) */
763 #if defined(b710)
764         struct drv_func_mb      func_mb[E1_FUNC_MAX];  /* 0x684 (44*2=0x58) */
765 #else
766         struct drv_func_mb      func_mb[E1H_FUNC_MAX];
767 #endif
768
769 };                                                     /* 0x6dc */
770
771
772 #define BCM_5710_FW_MAJOR_VERSION                       4
773 #define BCM_5710_FW_MINOR_VERSION                       0
774 #define BCM_5710_FW_REVISION_VERSION                    14
775 #define BCM_5710_FW_COMPILE_FLAGS                       1
776
777
778 /*
779  * attention bits
780  */
781 struct atten_def_status_block {
782         u32 attn_bits;
783         u32 attn_bits_ack;
784 #if defined(__BIG_ENDIAN)
785         u16 attn_bits_index;
786         u8 reserved0;
787         u8 status_block_id;
788 #elif defined(__LITTLE_ENDIAN)
789         u8 status_block_id;
790         u8 reserved0;
791         u16 attn_bits_index;
792 #endif
793         u32 reserved1;
794 };
795
796
797 /*
798  * common data for all protocols
799  */
800 struct doorbell_hdr {
801         u8 header;
802 #define DOORBELL_HDR_RX (0x1<<0)
803 #define DOORBELL_HDR_RX_SHIFT 0
804 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
805 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
806 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
807 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
808 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
809 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
810 };
811
812 /*
813  * doorbell message send to the chip
814  */
815 struct doorbell {
816 #if defined(__BIG_ENDIAN)
817         u16 zero_fill2;
818         u8 zero_fill1;
819         struct doorbell_hdr header;
820 #elif defined(__LITTLE_ENDIAN)
821         struct doorbell_hdr header;
822         u8 zero_fill1;
823         u16 zero_fill2;
824 #endif
825 };
826
827
828 /*
829  * IGU driver acknowlegement register
830  */
831 struct igu_ack_register {
832 #if defined(__BIG_ENDIAN)
833         u16 sb_id_and_flags;
834 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
835 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
836 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
837 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
838 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
839 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
840 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
841 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
842 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
843 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
844         u16 status_block_index;
845 #elif defined(__LITTLE_ENDIAN)
846         u16 status_block_index;
847         u16 sb_id_and_flags;
848 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
849 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
850 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
851 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
852 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
853 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
854 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
855 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
856 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
857 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
858 #endif
859 };
860
861
862 /*
863  * Parser parsing flags field
864  */
865 struct parsing_flags {
866         u16 flags;
867 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
868 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
869 #define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS (0x3<<1)
870 #define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS_SHIFT 1
871 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
872 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
873 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
874 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
875 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
876 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
877 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
878 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
879 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
880 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
881 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
882 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
883 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
884 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
885 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
886 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
887 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
888 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
889 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
890 #define PARSING_FLAGS_RESERVED0_SHIFT 14
891 };
892
893
894 /*
895  * dmae command structure
896  */
897 struct dmae_command {
898         u32 opcode;
899 #define DMAE_COMMAND_SRC (0x1<<0)
900 #define DMAE_COMMAND_SRC_SHIFT 0
901 #define DMAE_COMMAND_DST (0x3<<1)
902 #define DMAE_COMMAND_DST_SHIFT 1
903 #define DMAE_COMMAND_C_DST (0x1<<3)
904 #define DMAE_COMMAND_C_DST_SHIFT 3
905 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
906 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
907 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
908 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
909 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
910 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
911 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
912 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
913 #define DMAE_COMMAND_PORT (0x1<<11)
914 #define DMAE_COMMAND_PORT_SHIFT 11
915 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
916 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
917 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
918 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
919 #define DMAE_COMMAND_DST_RESET (0x1<<14)
920 #define DMAE_COMMAND_DST_RESET_SHIFT 14
921 #define DMAE_COMMAND_E1HVN (0x3<<15)
922 #define DMAE_COMMAND_E1HVN_SHIFT 15
923 #define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
924 #define DMAE_COMMAND_RESERVED0_SHIFT 17
925         u32 src_addr_lo;
926         u32 src_addr_hi;
927         u32 dst_addr_lo;
928         u32 dst_addr_hi;
929 #if defined(__BIG_ENDIAN)
930         u16 reserved1;
931         u16 len;
932 #elif defined(__LITTLE_ENDIAN)
933         u16 len;
934         u16 reserved1;
935 #endif
936         u32 comp_addr_lo;
937         u32 comp_addr_hi;
938         u32 comp_val;
939         u32 crc32;
940         u32 crc32_c;
941 #if defined(__BIG_ENDIAN)
942         u16 crc16_c;
943         u16 crc16;
944 #elif defined(__LITTLE_ENDIAN)
945         u16 crc16;
946         u16 crc16_c;
947 #endif
948 #if defined(__BIG_ENDIAN)
949         u16 reserved2;
950         u16 crc_t10;
951 #elif defined(__LITTLE_ENDIAN)
952         u16 crc_t10;
953         u16 reserved2;
954 #endif
955 #if defined(__BIG_ENDIAN)
956         u16 xsum8;
957         u16 xsum16;
958 #elif defined(__LITTLE_ENDIAN)
959         u16 xsum16;
960         u16 xsum8;
961 #endif
962 };
963
964
965 struct double_regpair {
966         u32 regpair0_lo;
967         u32 regpair0_hi;
968         u32 regpair1_lo;
969         u32 regpair1_hi;
970 };
971
972
973 /*
974  * The eth Rx Buffer Descriptor
975  */
976 struct eth_rx_bd {
977         u32 addr_lo;
978         u32 addr_hi;
979 };
980
981 /*
982  * The eth storm context of Ustorm
983  */
984 struct ustorm_eth_st_context {
985 #if defined(__BIG_ENDIAN)
986         u8 sb_index_number;
987         u8 status_block_id;
988         u8 __local_rx_bd_cons;
989         u8 __local_rx_bd_prod;
990 #elif defined(__LITTLE_ENDIAN)
991         u8 __local_rx_bd_prod;
992         u8 __local_rx_bd_cons;
993         u8 status_block_id;
994         u8 sb_index_number;
995 #endif
996 #if defined(__BIG_ENDIAN)
997         u16 rcq_cons;
998         u16 rx_bd_cons;
999 #elif defined(__LITTLE_ENDIAN)
1000         u16 rx_bd_cons;
1001         u16 rcq_cons;
1002 #endif
1003         u32 rx_bd_page_base_lo;
1004         u32 rx_bd_page_base_hi;
1005         u32 rcq_base_address_lo;
1006         u32 rcq_base_address_hi;
1007 #if defined(__BIG_ENDIAN)
1008         u16 __num_of_returned_cqes;
1009         u8 num_rss;
1010         u8 flags;
1011 #define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
1012 #define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
1013 #define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
1014 #define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
1015 #define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2)
1016 #define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2
1017 #define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3)
1018 #define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3
1019 #elif defined(__LITTLE_ENDIAN)
1020         u8 flags;
1021 #define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
1022 #define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
1023 #define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
1024 #define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
1025 #define USTORM_ETH_ST_CONTEXT_ENABLE_TPA (0x1<<2)
1026 #define USTORM_ETH_ST_CONTEXT_ENABLE_TPA_SHIFT 2
1027 #define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x1F<<3)
1028 #define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 3
1029         u8 num_rss;
1030         u16 __num_of_returned_cqes;
1031 #endif
1032 #if defined(__BIG_ENDIAN)
1033         u16 mc_alignment_size;
1034         u16 agg_threshold;
1035 #elif defined(__LITTLE_ENDIAN)
1036         u16 agg_threshold;
1037         u16 mc_alignment_size;
1038 #endif
1039         struct eth_rx_bd __local_bd_ring[16];
1040 };
1041
1042 /*
1043  * The eth storm context of Tstorm
1044  */
1045 struct tstorm_eth_st_context {
1046         u32 __reserved0[28];
1047 };
1048
1049 /*
1050  * The eth aggregative context section of Xstorm
1051  */
1052 struct xstorm_eth_extra_ag_context_section {
1053 #if defined(__BIG_ENDIAN)
1054         u8 __tcp_agg_vars1;
1055         u8 __reserved50;
1056         u16 __mss;
1057 #elif defined(__LITTLE_ENDIAN)
1058         u16 __mss;
1059         u8 __reserved50;
1060         u8 __tcp_agg_vars1;
1061 #endif
1062         u32 __snd_nxt;
1063         u32 __tx_wnd;
1064         u32 __snd_una;
1065         u32 __reserved53;
1066 #if defined(__BIG_ENDIAN)
1067         u8 __agg_val8_th;
1068         u8 __agg_val8;
1069         u16 __tcp_agg_vars2;
1070 #elif defined(__LITTLE_ENDIAN)
1071         u16 __tcp_agg_vars2;
1072         u8 __agg_val8;
1073         u8 __agg_val8_th;
1074 #endif
1075         u32 __reserved58;
1076         u32 __reserved59;
1077         u32 __reserved60;
1078         u32 __reserved61;
1079 #if defined(__BIG_ENDIAN)
1080         u16 __agg_val7_th;
1081         u16 __agg_val7;
1082 #elif defined(__LITTLE_ENDIAN)
1083         u16 __agg_val7;
1084         u16 __agg_val7_th;
1085 #endif
1086 #if defined(__BIG_ENDIAN)
1087         u8 __tcp_agg_vars5;
1088         u8 __tcp_agg_vars4;
1089         u8 __tcp_agg_vars3;
1090         u8 __reserved62;
1091 #elif defined(__LITTLE_ENDIAN)
1092         u8 __reserved62;
1093         u8 __tcp_agg_vars3;
1094         u8 __tcp_agg_vars4;
1095         u8 __tcp_agg_vars5;
1096 #endif
1097         u32 __tcp_agg_vars6;
1098 #if defined(__BIG_ENDIAN)
1099         u16 __agg_misc6;
1100         u16 __tcp_agg_vars7;
1101 #elif defined(__LITTLE_ENDIAN)
1102         u16 __tcp_agg_vars7;
1103         u16 __agg_misc6;
1104 #endif
1105         u32 __agg_val10;
1106         u32 __agg_val10_th;
1107 #if defined(__BIG_ENDIAN)
1108         u16 __reserved3;
1109         u8 __reserved2;
1110         u8 __agg_misc7;
1111 #elif defined(__LITTLE_ENDIAN)
1112         u8 __agg_misc7;
1113         u8 __reserved2;
1114         u16 __reserved3;
1115 #endif
1116 };
1117
1118 /*
1119  * The eth aggregative context of Xstorm
1120  */
1121 struct xstorm_eth_ag_context {
1122 #if defined(__BIG_ENDIAN)
1123         u16 __bd_prod;
1124         u8 __agg_vars1;
1125         u8 __state;
1126 #elif defined(__LITTLE_ENDIAN)
1127         u8 __state;
1128         u8 __agg_vars1;
1129         u16 __bd_prod;
1130 #endif
1131 #if defined(__BIG_ENDIAN)
1132         u8 cdu_reserved;
1133         u8 __agg_vars4;
1134         u8 __agg_vars3;
1135         u8 __agg_vars2;
1136 #elif defined(__LITTLE_ENDIAN)
1137         u8 __agg_vars2;
1138         u8 __agg_vars3;
1139         u8 __agg_vars4;
1140         u8 cdu_reserved;
1141 #endif
1142         u32 __more_packets_to_send;
1143 #if defined(__BIG_ENDIAN)
1144         u16 __agg_vars5;
1145         u16 __agg_val4_th;
1146 #elif defined(__LITTLE_ENDIAN)
1147         u16 __agg_val4_th;
1148         u16 __agg_vars5;
1149 #endif
1150         struct xstorm_eth_extra_ag_context_section __extra_section;
1151 #if defined(__BIG_ENDIAN)
1152         u16 __agg_vars7;
1153         u8 __agg_val3_th;
1154         u8 __agg_vars6;
1155 #elif defined(__LITTLE_ENDIAN)
1156         u8 __agg_vars6;
1157         u8 __agg_val3_th;
1158         u16 __agg_vars7;
1159 #endif
1160 #if defined(__BIG_ENDIAN)
1161         u16 __agg_val11_th;
1162         u16 __agg_val11;
1163 #elif defined(__LITTLE_ENDIAN)
1164         u16 __agg_val11;
1165         u16 __agg_val11_th;
1166 #endif
1167 #if defined(__BIG_ENDIAN)
1168         u8 __reserved1;
1169         u8 __agg_val6_th;
1170         u16 __agg_val9;
1171 #elif defined(__LITTLE_ENDIAN)
1172         u16 __agg_val9;
1173         u8 __agg_val6_th;
1174         u8 __reserved1;
1175 #endif
1176 #if defined(__BIG_ENDIAN)
1177         u16 __agg_val2_th;
1178         u16 __agg_val2;
1179 #elif defined(__LITTLE_ENDIAN)
1180         u16 __agg_val2;
1181         u16 __agg_val2_th;
1182 #endif
1183         u32 __agg_vars8;
1184 #if defined(__BIG_ENDIAN)
1185         u16 __agg_misc0;
1186         u16 __agg_val4;
1187 #elif defined(__LITTLE_ENDIAN)
1188         u16 __agg_val4;
1189         u16 __agg_misc0;
1190 #endif
1191 #if defined(__BIG_ENDIAN)
1192         u8 __agg_val3;
1193         u8 __agg_val6;
1194         u8 __agg_val5_th;
1195         u8 __agg_val5;
1196 #elif defined(__LITTLE_ENDIAN)
1197         u8 __agg_val5;
1198         u8 __agg_val5_th;
1199         u8 __agg_val6;
1200         u8 __agg_val3;
1201 #endif
1202 #if defined(__BIG_ENDIAN)
1203         u16 __agg_misc1;
1204         u16 __bd_ind_max_val;
1205 #elif defined(__LITTLE_ENDIAN)
1206         u16 __bd_ind_max_val;
1207         u16 __agg_misc1;
1208 #endif
1209         u32 __reserved57;
1210         u32 __agg_misc4;
1211         u32 __agg_misc5;
1212 };
1213
1214 /*
1215  * The eth aggregative context section of Tstorm
1216  */
1217 struct tstorm_eth_extra_ag_context_section {
1218         u32 __agg_val1;
1219 #if defined(__BIG_ENDIAN)
1220         u8 __tcp_agg_vars2;
1221         u8 __agg_val3;
1222         u16 __agg_val2;
1223 #elif defined(__LITTLE_ENDIAN)
1224         u16 __agg_val2;
1225         u8 __agg_val3;
1226         u8 __tcp_agg_vars2;
1227 #endif
1228 #if defined(__BIG_ENDIAN)
1229         u16 __agg_val5;
1230         u8 __agg_val6;
1231         u8 __tcp_agg_vars3;
1232 #elif defined(__LITTLE_ENDIAN)
1233         u8 __tcp_agg_vars3;
1234         u8 __agg_val6;
1235         u16 __agg_val5;
1236 #endif
1237         u32 __reserved63;
1238         u32 __reserved64;
1239         u32 __reserved65;
1240         u32 __reserved66;
1241         u32 __reserved67;
1242         u32 __tcp_agg_vars1;
1243         u32 __reserved61;
1244         u32 __reserved62;
1245         u32 __reserved2;
1246 };
1247
1248 /*
1249  * The eth aggregative context of Tstorm
1250  */
1251 struct tstorm_eth_ag_context {
1252 #if defined(__BIG_ENDIAN)
1253         u16 __reserved54;
1254         u8 __agg_vars1;
1255         u8 __state;
1256 #elif defined(__LITTLE_ENDIAN)
1257         u8 __state;
1258         u8 __agg_vars1;
1259         u16 __reserved54;
1260 #endif
1261 #if defined(__BIG_ENDIAN)
1262         u16 __agg_val4;
1263         u16 __agg_vars2;
1264 #elif defined(__LITTLE_ENDIAN)
1265         u16 __agg_vars2;
1266         u16 __agg_val4;
1267 #endif
1268         struct tstorm_eth_extra_ag_context_section __extra_section;
1269 };
1270
1271 /*
1272  * The eth aggregative context of Cstorm
1273  */
1274 struct cstorm_eth_ag_context {
1275         u32 __agg_vars1;
1276 #if defined(__BIG_ENDIAN)
1277         u8 __aux1_th;
1278         u8 __aux1_val;
1279         u16 __agg_vars2;
1280 #elif defined(__LITTLE_ENDIAN)
1281         u16 __agg_vars2;
1282         u8 __aux1_val;
1283         u8 __aux1_th;
1284 #endif
1285         u32 __num_of_treated_packet;
1286         u32 __last_packet_treated;
1287 #if defined(__BIG_ENDIAN)
1288         u16 __reserved58;
1289         u16 __reserved57;
1290 #elif defined(__LITTLE_ENDIAN)
1291         u16 __reserved57;
1292         u16 __reserved58;
1293 #endif
1294 #if defined(__BIG_ENDIAN)
1295         u8 __reserved62;
1296         u8 __reserved61;
1297         u8 __reserved60;
1298         u8 __reserved59;
1299 #elif defined(__LITTLE_ENDIAN)
1300         u8 __reserved59;
1301         u8 __reserved60;
1302         u8 __reserved61;
1303         u8 __reserved62;
1304 #endif
1305 #if defined(__BIG_ENDIAN)
1306         u16 __reserved64;
1307         u16 __reserved63;
1308 #elif defined(__LITTLE_ENDIAN)
1309         u16 __reserved63;
1310         u16 __reserved64;
1311 #endif
1312         u32 __reserved65;
1313 #if defined(__BIG_ENDIAN)
1314         u16 __agg_vars3;
1315         u16 __rq_inv_cnt;
1316 #elif defined(__LITTLE_ENDIAN)
1317         u16 __rq_inv_cnt;
1318         u16 __agg_vars3;
1319 #endif
1320 #if defined(__BIG_ENDIAN)
1321         u16 __packet_index_th;
1322         u16 __packet_index;
1323 #elif defined(__LITTLE_ENDIAN)
1324         u16 __packet_index;
1325         u16 __packet_index_th;
1326 #endif
1327 };
1328
1329 /*
1330  * The eth aggregative context of Ustorm
1331  */
1332 struct ustorm_eth_ag_context {
1333 #if defined(__BIG_ENDIAN)
1334         u8 __aux_counter_flags;
1335         u8 __agg_vars2;
1336         u8 __agg_vars1;
1337         u8 __state;
1338 #elif defined(__LITTLE_ENDIAN)
1339         u8 __state;
1340         u8 __agg_vars1;
1341         u8 __agg_vars2;
1342         u8 __aux_counter_flags;
1343 #endif
1344 #if defined(__BIG_ENDIAN)
1345         u8 cdu_usage;
1346         u8 __agg_misc2;
1347         u16 __agg_misc1;
1348 #elif defined(__LITTLE_ENDIAN)
1349         u16 __agg_misc1;
1350         u8 __agg_misc2;
1351         u8 cdu_usage;
1352 #endif
1353         u32 __agg_misc4;
1354 #if defined(__BIG_ENDIAN)
1355         u8 __agg_val3_th;
1356         u8 __agg_val3;
1357         u16 __agg_misc3;
1358 #elif defined(__LITTLE_ENDIAN)
1359         u16 __agg_misc3;
1360         u8 __agg_val3;
1361         u8 __agg_val3_th;
1362 #endif
1363         u32 __agg_val1;
1364         u32 __agg_misc4_th;
1365 #if defined(__BIG_ENDIAN)
1366         u16 __agg_val2_th;
1367         u16 __agg_val2;
1368 #elif defined(__LITTLE_ENDIAN)
1369         u16 __agg_val2;
1370         u16 __agg_val2_th;
1371 #endif
1372 #if defined(__BIG_ENDIAN)
1373         u16 __reserved2;
1374         u8 __decision_rules;
1375         u8 __decision_rule_enable_bits;
1376 #elif defined(__LITTLE_ENDIAN)
1377         u8 __decision_rule_enable_bits;
1378         u8 __decision_rules;
1379         u16 __reserved2;
1380 #endif
1381 };
1382
1383 /*
1384  * Timers connection context
1385  */
1386 struct timers_block_context {
1387         u32 __reserved_0;
1388         u32 __reserved_1;
1389         u32 __reserved_2;
1390         u32 __reserved_flags;
1391 };
1392
1393 /*
1394  * structure for easy accessability to assembler
1395  */
1396 struct eth_tx_bd_flags {
1397         u8 as_bitfield;
1398 #define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
1399 #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
1400 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
1401 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
1402 #define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2)
1403 #define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2
1404 #define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
1405 #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
1406 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
1407 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
1408 #define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
1409 #define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
1410 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
1411 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
1412 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
1413 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
1414 };
1415
1416 /*
1417  * The eth Tx Buffer Descriptor
1418  */
1419 struct eth_tx_bd {
1420         u32 addr_lo;
1421         u32 addr_hi;
1422         u16 nbd;
1423         u16 nbytes;
1424         u16 vlan;
1425         struct eth_tx_bd_flags bd_flags;
1426         u8 general_data;
1427 #define ETH_TX_BD_HDR_NBDS (0x3F<<0)
1428 #define ETH_TX_BD_HDR_NBDS_SHIFT 0
1429 #define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
1430 #define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
1431 };
1432
1433 /*
1434  * Tx parsing BD structure for ETH,Relevant in START
1435  */
1436 struct eth_tx_parse_bd {
1437         u8 global_data;
1438 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
1439 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
1440 #define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
1441 #define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
1442 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
1443 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
1444 #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
1445 #define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
1446 #define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
1447 #define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
1448         u8 tcp_flags;
1449 #define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
1450 #define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
1451 #define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
1452 #define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
1453 #define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
1454 #define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
1455 #define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
1456 #define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
1457 #define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
1458 #define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
1459 #define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
1460 #define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
1461 #define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
1462 #define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
1463 #define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
1464 #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
1465         u8 ip_hlen;
1466         s8 cs_offset;
1467         u16 total_hlen;
1468         u16 lso_mss;
1469         u16 tcp_pseudo_csum;
1470         u16 ip_id;
1471         u32 tcp_send_seq;
1472 };
1473
1474 /*
1475  * The last BD in the BD memory will hold a pointer to the next BD memory
1476  */
1477 struct eth_tx_next_bd {
1478         u32 addr_lo;
1479         u32 addr_hi;
1480         u8 reserved[8];
1481 };
1482
1483 /*
1484  * union for 3 Bd types
1485  */
1486 union eth_tx_bd_types {
1487         struct eth_tx_bd reg_bd;
1488         struct eth_tx_parse_bd parse_bd;
1489         struct eth_tx_next_bd next_bd;
1490 };
1491
1492 /*
1493  * The eth storm context of Xstorm
1494  */
1495 struct xstorm_eth_st_context {
1496         u32 tx_bd_page_base_lo;
1497         u32 tx_bd_page_base_hi;
1498 #if defined(__BIG_ENDIAN)
1499         u16 tx_bd_cons;
1500         u8 __reserved0;
1501         u8 __local_tx_bd_prod;
1502 #elif defined(__LITTLE_ENDIAN)
1503         u8 __local_tx_bd_prod;
1504         u8 __reserved0;
1505         u16 tx_bd_cons;
1506 #endif
1507         u32 db_data_addr_lo;
1508         u32 db_data_addr_hi;
1509         u32 __pkt_cons;
1510         u32 __gso_next;
1511         u32 is_eth_conn_1b;
1512         union eth_tx_bd_types __bds[13];
1513 };
1514
1515 /*
1516  * The eth storm context of Cstorm
1517  */
1518 struct cstorm_eth_st_context {
1519 #if defined(__BIG_ENDIAN)
1520         u16 __reserved0;
1521         u8 sb_index_number;
1522         u8 status_block_id;
1523 #elif defined(__LITTLE_ENDIAN)
1524         u8 status_block_id;
1525         u8 sb_index_number;
1526         u16 __reserved0;
1527 #endif
1528         u32 __reserved1[3];
1529 };
1530
1531 /*
1532  * Ethernet connection context
1533  */
1534 struct eth_context {
1535         struct ustorm_eth_st_context ustorm_st_context;
1536         struct tstorm_eth_st_context tstorm_st_context;
1537         struct xstorm_eth_ag_context xstorm_ag_context;
1538         struct tstorm_eth_ag_context tstorm_ag_context;
1539         struct cstorm_eth_ag_context cstorm_ag_context;
1540         struct ustorm_eth_ag_context ustorm_ag_context;
1541         struct timers_block_context timers_context;
1542         struct xstorm_eth_st_context xstorm_st_context;
1543         struct cstorm_eth_st_context cstorm_st_context;
1544 };
1545
1546
1547 /*
1548  * ethernet doorbell
1549  */
1550 struct eth_tx_doorbell {
1551 #if defined(__BIG_ENDIAN)
1552         u16 npackets;
1553         u8 params;
1554 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
1555 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
1556 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
1557 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
1558 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
1559 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
1560         struct doorbell_hdr hdr;
1561 #elif defined(__LITTLE_ENDIAN)
1562         struct doorbell_hdr hdr;
1563         u8 params;
1564 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
1565 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
1566 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
1567 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
1568 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
1569 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
1570         u16 npackets;
1571 #endif
1572 };
1573
1574
1575 /*
1576  * ustorm status block
1577  */
1578 struct ustorm_def_status_block {
1579         u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
1580         u16 status_block_index;
1581         u8 reserved0;
1582         u8 status_block_id;
1583         u32 __flags;
1584 };
1585
1586 /*
1587  * cstorm status block
1588  */
1589 struct cstorm_def_status_block {
1590         u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
1591         u16 status_block_index;
1592         u8 reserved0;
1593         u8 status_block_id;
1594         u32 __flags;
1595 };
1596
1597 /*
1598  * xstorm status block
1599  */
1600 struct xstorm_def_status_block {
1601         u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
1602         u16 status_block_index;
1603         u8 reserved0;
1604         u8 status_block_id;
1605         u32 __flags;
1606 };
1607
1608 /*
1609  * tstorm status block
1610  */
1611 struct tstorm_def_status_block {
1612         u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
1613         u16 status_block_index;
1614         u8 reserved0;
1615         u8 status_block_id;
1616         u32 __flags;
1617 };
1618
1619 /*
1620  * host status block
1621  */
1622 struct host_def_status_block {
1623         struct atten_def_status_block atten_status_block;
1624         struct ustorm_def_status_block u_def_status_block;
1625         struct cstorm_def_status_block c_def_status_block;
1626         struct xstorm_def_status_block x_def_status_block;
1627         struct tstorm_def_status_block t_def_status_block;
1628 };
1629
1630
1631 /*
1632  * ustorm status block
1633  */
1634 struct ustorm_status_block {
1635         u16 index_values[HC_USTORM_SB_NUM_INDICES];
1636         u16 status_block_index;
1637         u8 reserved0;
1638         u8 status_block_id;
1639         u32 __flags;
1640 };
1641
1642 /*
1643  * cstorm status block
1644  */
1645 struct cstorm_status_block {
1646         u16 index_values[HC_CSTORM_SB_NUM_INDICES];
1647         u16 status_block_index;
1648         u8 reserved0;
1649         u8 status_block_id;
1650         u32 __flags;
1651 };
1652
1653 /*
1654  * host status block
1655  */
1656 struct host_status_block {
1657         struct ustorm_status_block u_status_block;
1658         struct cstorm_status_block c_status_block;
1659 };
1660
1661
1662 /*
1663  * The data for RSS setup ramrod
1664  */
1665 struct eth_client_setup_ramrod_data {
1666         u32 client_id_5b;
1667         u8 is_rdma_1b;
1668         u8 reserved0;
1669         u16 reserved1;
1670 };
1671
1672
1673 /*
1674  * L2 dynamic host coalescing init parameters
1675  */
1676 struct eth_dynamic_hc_config {
1677         u32 threshold[3];
1678         u8 hc_timeout[4];
1679 };
1680
1681
1682 /*
1683  * regular eth FP CQE parameters struct
1684  */
1685 struct eth_fast_path_rx_cqe {
1686         u8 type;
1687         u8 error_type_flags;
1688 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<0)
1689 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 0
1690 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<1)
1691 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 1
1692 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<2)
1693 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 2
1694 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<3)
1695 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 3
1696 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<4)
1697 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 4
1698 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x7<<5)
1699 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 5
1700         u8 status_flags;
1701 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
1702 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
1703 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
1704 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
1705 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
1706 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
1707 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
1708 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
1709 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
1710 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
1711 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
1712 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
1713         u8 placement_offset;
1714         u32 rss_hash_result;
1715         u16 vlan_tag;
1716         u16 pkt_len;
1717         u16 queue_index;
1718         struct parsing_flags pars_flags;
1719 };
1720
1721
1722 /*
1723  * The data for RSS setup ramrod
1724  */
1725 struct eth_halt_ramrod_data {
1726         u32 client_id_5b;
1727         u32 reserved0;
1728 };
1729
1730
1731 /*
1732  * Place holder for ramrods protocol specific data
1733  */
1734 struct ramrod_data {
1735         u32 data_lo;
1736         u32 data_hi;
1737 };
1738
1739 /*
1740  * union for ramrod data for ethernet protocol (CQE) (force size of 16 bits)
1741  */
1742 union eth_ramrod_data {
1743         struct ramrod_data general;
1744 };
1745
1746
1747 /*
1748  * Rx Last BD in page (in ETH)
1749  */
1750 struct eth_rx_bd_next_page {
1751         u32 addr_lo;
1752         u32 addr_hi;
1753         u8 reserved[8];
1754 };
1755
1756
1757 /*
1758  * Eth Rx Cqe structure- general structure for ramrods
1759  */
1760 struct common_ramrod_eth_rx_cqe {
1761         u8 type;
1762         u8 conn_type_3b;
1763         u16 reserved;
1764         u32 conn_and_cmd_data;
1765 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
1766 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
1767 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
1768 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
1769         struct ramrod_data protocol_data;
1770 };
1771
1772 /*
1773  * Rx Last CQE in page (in ETH)
1774  */
1775 struct eth_rx_cqe_next_page {
1776         u32 addr_lo;
1777         u32 addr_hi;
1778         u32 reserved0;
1779         u32 reserved1;
1780 };
1781
1782 /*
1783  * union for all eth rx cqe types (fix their sizes)
1784  */
1785 union eth_rx_cqe {
1786         struct eth_fast_path_rx_cqe fast_path_cqe;
1787         struct common_ramrod_eth_rx_cqe ramrod_cqe;
1788         struct eth_rx_cqe_next_page next_page_cqe;
1789 };
1790
1791
1792 /*
1793  * common data for all protocols
1794  */
1795 struct spe_hdr {
1796         u32 conn_and_cmd_data;
1797 #define SPE_HDR_CID (0xFFFFFF<<0)
1798 #define SPE_HDR_CID_SHIFT 0
1799 #define SPE_HDR_CMD_ID (0xFF<<24)
1800 #define SPE_HDR_CMD_ID_SHIFT 24
1801         u16 type;
1802 #define SPE_HDR_CONN_TYPE (0xFF<<0)
1803 #define SPE_HDR_CONN_TYPE_SHIFT 0
1804 #define SPE_HDR_COMMON_RAMROD (0xFF<<8)
1805 #define SPE_HDR_COMMON_RAMROD_SHIFT 8
1806         u16 reserved;
1807 };
1808
1809 struct regpair {
1810         u32 lo;
1811         u32 hi;
1812 };
1813
1814 /*
1815  * ethernet slow path element
1816  */
1817 union eth_specific_data {
1818         u8 protocol_data[8];
1819         struct regpair mac_config_addr;
1820         struct eth_client_setup_ramrod_data client_setup_ramrod_data;
1821         struct eth_halt_ramrod_data halt_ramrod_data;
1822         struct regpair leading_cqe_addr;
1823         struct regpair update_data_addr;
1824 };
1825
1826 /*
1827  * ethernet slow path element
1828  */
1829 struct eth_spe {
1830         struct spe_hdr hdr;
1831         union eth_specific_data data;
1832 };
1833
1834
1835 /*
1836  * doorbell data in host memory
1837  */
1838 struct eth_tx_db_data {
1839         u32 packets_prod;
1840         u16 bds_prod;
1841         u16 reserved;
1842 };
1843
1844
1845 /*
1846  * Common configuration parameters per port in Tstorm
1847  */
1848 struct tstorm_eth_function_common_config {
1849         u32 config_flags;
1850 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
1851 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
1852 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
1853 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
1854 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
1855 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
1856 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
1857 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
1858 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4)
1859 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
1860 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
1861 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
1862 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3FFFFFF<<6)
1863 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 6
1864 #if defined(__BIG_ENDIAN)
1865         u16 __secondary_vlan_id;
1866         u8 leading_client_id;
1867         u8 rss_result_mask;
1868 #elif defined(__LITTLE_ENDIAN)
1869         u8 rss_result_mask;
1870         u8 leading_client_id;
1871         u16 __secondary_vlan_id;
1872 #endif
1873 };
1874
1875 /*
1876  * parameters for eth update ramrod
1877  */
1878 struct eth_update_ramrod_data {
1879         struct tstorm_eth_function_common_config func_config;
1880         u8 indirectionTable[128];
1881 };
1882
1883
1884 /*
1885  * MAC filtering configuration command header
1886  */
1887 struct mac_configuration_hdr {
1888         u8 length_6b;
1889         u8 offset;
1890         u16 reserved0;
1891         u32 reserved1;
1892 };
1893
1894 /*
1895  * MAC address in list for ramrod
1896  */
1897 struct tstorm_cam_entry {
1898         u16 lsb_mac_addr;
1899         u16 middle_mac_addr;
1900         u16 msb_mac_addr;
1901         u16 flags;
1902 #define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
1903 #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
1904 #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
1905 #define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
1906 #define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
1907 #define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
1908 };
1909
1910 /*
1911  * MAC filtering: CAM target table entry
1912  */
1913 struct tstorm_cam_target_table_entry {
1914         u8 flags;
1915 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
1916 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
1917 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
1918 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
1919 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
1920 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
1921 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
1922 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
1923 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
1924 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
1925         u8 client_id;
1926         u16 vlan_id;
1927 };
1928
1929 /*
1930  * MAC address in list for ramrod
1931  */
1932 struct mac_configuration_entry {
1933         struct tstorm_cam_entry cam_entry;
1934         struct tstorm_cam_target_table_entry target_table_entry;
1935 };
1936
1937 /*
1938  * MAC filtering configuration command
1939  */
1940 struct mac_configuration_cmd {
1941         struct mac_configuration_hdr hdr;
1942         struct mac_configuration_entry config_table[64];
1943 };
1944
1945
1946 /*
1947  * Configuration parameters per client in Tstorm
1948  */
1949 struct tstorm_eth_client_config {
1950 #if defined(__BIG_ENDIAN)
1951         u16 statistics_counter_id;
1952         u16 mtu;
1953 #elif defined(__LITTLE_ENDIAN)
1954         u16 mtu;
1955         u16 statistics_counter_id;
1956 #endif
1957 #if defined(__BIG_ENDIAN)
1958         u16 drop_flags;
1959 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
1960 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
1961 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
1962 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
1963 #define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2)
1964 #define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2
1965 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3)
1966 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3
1967 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4)
1968 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4
1969 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5)
1970 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5
1971         u16 config_flags;
1972 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
1973 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
1974 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
1975 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
1976 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2)
1977 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2
1978 #elif defined(__LITTLE_ENDIAN)
1979         u16 config_flags;
1980 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
1981 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
1982 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
1983 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
1984 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2)
1985 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2
1986         u16 drop_flags;
1987 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
1988 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
1989 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
1990 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
1991 #define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2)
1992 #define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2
1993 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3)
1994 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3
1995 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4)
1996 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4
1997 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5)
1998 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5
1999 #endif
2000 };
2001
2002
2003 /*
2004  * MAC filtering configuration parameters per port in Tstorm
2005  */
2006 struct tstorm_eth_mac_filter_config {
2007         u32 ucast_drop_all;
2008         u32 ucast_accept_all;
2009         u32 mcast_drop_all;
2010         u32 mcast_accept_all;
2011         u32 bcast_drop_all;
2012         u32 bcast_accept_all;
2013         u32 strict_vlan;
2014         u32 __secondary_vlan_clients;
2015 };
2016
2017
2018 struct rate_shaping_per_protocol {
2019 #if defined(__BIG_ENDIAN)
2020         u16 reserved0;
2021         u16 protocol_rate;
2022 #elif defined(__LITTLE_ENDIAN)
2023         u16 protocol_rate;
2024         u16 reserved0;
2025 #endif
2026         u32 protocol_quota;
2027         s32 current_credit;
2028         u32 reserved;
2029 };
2030
2031 struct rate_shaping_vars {
2032         struct rate_shaping_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
2033         u32 pause_mask;
2034         u32 periodic_stop;
2035         u32 rs_periodic_timeout;
2036         u32 rs_threshold;
2037         u32 last_periodic_time;
2038         u32 reserved;
2039 };
2040
2041 struct fairness_per_protocol {
2042         u32 credit_delta;
2043         s32 fair_credit;
2044 #if defined(__BIG_ENDIAN)
2045         u16 reserved0;
2046         u8 state;
2047         u8 weight;
2048 #elif defined(__LITTLE_ENDIAN)
2049         u8 weight;
2050         u8 state;
2051         u16 reserved0;
2052 #endif
2053         u32 reserved1;
2054 };
2055
2056 struct fairness_vars {
2057         struct fairness_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
2058         u32 upper_bound;
2059         u32 port_rate;
2060         u32 pause_mask;
2061         u32 fair_threshold;
2062 };
2063
2064 struct safc_struct {
2065         u32 cur_pause_mask;
2066         u32 expire_time;
2067 #if defined(__BIG_ENDIAN)
2068         u16 reserved0;
2069         u8 cur_cos_types;
2070         u8 safc_timeout_usec;
2071 #elif defined(__LITTLE_ENDIAN)
2072         u8 safc_timeout_usec;
2073         u8 cur_cos_types;
2074         u16 reserved0;
2075 #endif
2076         u32 reserved1;
2077 };
2078
2079 struct demo_struct {
2080         u8 con_number[NUM_OF_PROTOCOLS];
2081 #if defined(__BIG_ENDIAN)
2082         u8 reserved1;
2083         u8 fairness_enable;
2084         u8 rate_shaping_enable;
2085         u8 cmng_enable;
2086 #elif defined(__LITTLE_ENDIAN)
2087         u8 cmng_enable;
2088         u8 rate_shaping_enable;
2089         u8 fairness_enable;
2090         u8 reserved1;
2091 #endif
2092 };
2093
2094 struct cmng_struct {
2095         struct rate_shaping_vars rs_vars;
2096         struct fairness_vars fair_vars;
2097         struct safc_struct safc_vars;
2098         struct demo_struct demo_vars;
2099 };
2100
2101
2102 struct cos_to_protocol {
2103         u8 mask[MAX_COS_NUMBER];
2104 };
2105
2106
2107 /*
2108  * Common statistics collected by the Xstorm (per port)
2109  */
2110 struct xstorm_common_stats {
2111         struct regpair total_sent_bytes;
2112         u32 total_sent_pkts;
2113         u32 unicast_pkts_sent;
2114         struct regpair unicast_bytes_sent;
2115         struct regpair multicast_bytes_sent;
2116         u32 multicast_pkts_sent;
2117         u32 broadcast_pkts_sent;
2118         struct regpair broadcast_bytes_sent;
2119         struct regpair done;
2120 };
2121
2122 /*
2123  * Protocol-common statistics collected by the Tstorm (per client)
2124  */
2125 struct tstorm_per_client_stats {
2126         struct regpair total_rcv_bytes;
2127         struct regpair rcv_unicast_bytes;
2128         struct regpair rcv_broadcast_bytes;
2129         struct regpair rcv_multicast_bytes;
2130         struct regpair rcv_error_bytes;
2131         u32 checksum_discard;
2132         u32 packets_too_big_discard;
2133         u32 total_rcv_pkts;
2134         u32 rcv_unicast_pkts;
2135         u32 rcv_broadcast_pkts;
2136         u32 rcv_multicast_pkts;
2137         u32 no_buff_discard;
2138         u32 ttl0_discard;
2139         u32 mac_discard;
2140         u32 reserved;
2141 };
2142
2143 /*
2144  * Protocol-common statistics collected by the Tstorm (per port)
2145  */
2146 struct tstorm_common_stats {
2147         struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
2148         u32 mac_filter_discard;
2149         u32 xxoverflow_discard;
2150         u32 brb_truncate_discard;
2151         u32 reserved;
2152         struct regpair done;
2153 };
2154
2155 /*
2156  * Eth statistics query sturcture for the eth_stats_quesry ramrod
2157  */
2158 struct eth_stats_query {
2159         struct xstorm_common_stats xstorm_common;
2160         struct tstorm_common_stats tstorm_common;
2161 };
2162
2163
2164 /*
2165  * FW version stored in the Xstorm RAM
2166  */
2167 struct fw_version {
2168 #if defined(__BIG_ENDIAN)
2169         u16 patch;
2170         u8 primary;
2171         u8 client;
2172 #elif defined(__LITTLE_ENDIAN)
2173         u8 client;
2174         u8 primary;
2175         u16 patch;
2176 #endif
2177         u32 flags;
2178 #define FW_VERSION_OPTIMIZED (0x1<<0)
2179 #define FW_VERSION_OPTIMIZED_SHIFT 0
2180 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
2181 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
2182 #define __FW_VERSION_RESERVED (0x3FFFFFFF<<2)
2183 #define __FW_VERSION_RESERVED_SHIFT 2
2184 };
2185
2186
2187 /*
2188  * FW version stored in first line of pram
2189  */
2190 struct pram_fw_version {
2191 #if defined(__BIG_ENDIAN)
2192         u16 patch;
2193         u8 primary;
2194         u8 client;
2195 #elif defined(__LITTLE_ENDIAN)
2196         u8 client;
2197         u8 primary;
2198         u16 patch;
2199 #endif
2200         u8 flags;
2201 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
2202 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
2203 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
2204 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
2205 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
2206 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
2207 #define __PRAM_FW_VERSION_RESERVED0 (0xF<<4)
2208 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 4
2209 };
2210
2211
2212 /*
2213  * The send queue element
2214  */
2215 struct slow_path_element {
2216         struct spe_hdr hdr;
2217         u8 protocol_data[8];
2218 };
2219
2220
2221 /*
2222  * eth/toe flags that indicate if to query
2223  */
2224 struct stats_indication_flags {
2225         u32 collect_eth;
2226         u32 collect_toe;
2227 };
2228
2229