bnx2x: Updating the Maintainer
[linux-2.6.git] / drivers / net / bnx2x.h
1 /* bnx2x.h: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2008 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10  * Written by: Eliezer Tamir
11  * Based on code from Michael Chan's bnx2 driver
12  */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16
17 /* error/debug prints */
18
19 #define DRV_MODULE_NAME         "bnx2x"
20 #define PFX DRV_MODULE_NAME     ": "
21
22 /* for messages that are currently off */
23 #define BNX2X_MSG_OFF                   0
24 #define BNX2X_MSG_MCP                   0x10000 /* was: NETIF_MSG_HW */
25 #define BNX2X_MSG_STATS                 0x20000 /* was: NETIF_MSG_TIMER */
26 #define NETIF_MSG_NVM                   0x40000 /* was: NETIF_MSG_HW */
27 #define NETIF_MSG_DMAE                  0x80000 /* was: NETIF_MSG_HW */
28 #define BNX2X_MSG_SP                    0x100000 /* was: NETIF_MSG_INTR */
29 #define BNX2X_MSG_FP                    0x200000 /* was: NETIF_MSG_INTR */
30
31 #define DP_LEVEL                        KERN_NOTICE     /* was: KERN_DEBUG */
32
33 /* regular debug print */
34 #define DP(__mask, __fmt, __args...) do { \
35         if (bp->msglevel & (__mask)) \
36                 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __FUNCTION__, \
37                 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
38         } while (0)
39
40 /* for errors (never masked) */
41 #define BNX2X_ERR(__fmt, __args...) do { \
42         printk(KERN_ERR "[%s:%d(%s)]" __fmt, __FUNCTION__, \
43                 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
44         } while (0)
45
46 /* for logging (never masked) */
47 #define BNX2X_LOG(__fmt, __args...) do { \
48         printk(KERN_NOTICE "[%s:%d(%s)]" __fmt, __FUNCTION__, \
49                 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
50         } while (0)
51
52 /* before we have a dev->name use dev_info() */
53 #define BNX2X_DEV_INFO(__fmt, __args...) do { \
54         if (bp->msglevel & NETIF_MSG_PROBE) \
55                 dev_info(&bp->pdev->dev, __fmt, ##__args); \
56         } while (0)
57
58
59 #ifdef BNX2X_STOP_ON_ERROR
60 #define bnx2x_panic() do { \
61                 bp->panic = 1; \
62                 BNX2X_ERR("driver assert\n"); \
63                 bnx2x_disable_int(bp); \
64                 bnx2x_panic_dump(bp); \
65         } while (0)
66 #else
67 #define bnx2x_panic() do { \
68                 BNX2X_ERR("driver assert\n"); \
69                 bnx2x_panic_dump(bp); \
70         } while (0)
71 #endif
72
73
74 #define U64_LO(x)                       (((u64)x) & 0xffffffff)
75 #define U64_HI(x)                       (((u64)x) >> 32)
76 #define HILO_U64(hi, lo)                (((u64)hi << 32) + lo)
77
78
79 #define REG_ADDR(bp, offset)            (bp->regview + offset)
80
81 #define REG_RD(bp, offset)              readl(REG_ADDR(bp, offset))
82 #define REG_RD8(bp, offset)             readb(REG_ADDR(bp, offset))
83 #define REG_RD64(bp, offset)            readq(REG_ADDR(bp, offset))
84
85 #define REG_WR(bp, offset, val)         writel((u32)val, REG_ADDR(bp, offset))
86 #define REG_WR8(bp, offset, val)        writeb((u8)val, REG_ADDR(bp, offset))
87 #define REG_WR16(bp, offset, val)       writew((u16)val, REG_ADDR(bp, offset))
88 #define REG_WR32(bp, offset, val)       REG_WR(bp, offset, val)
89
90 #define REG_RD_IND(bp, offset)          bnx2x_reg_rd_ind(bp, offset)
91 #define REG_WR_IND(bp, offset, val)     bnx2x_reg_wr_ind(bp, offset, val)
92
93 #define REG_WR_DMAE(bp, offset, val, len32) \
94         do { \
95                 memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \
96                 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
97                                  offset, len32); \
98         } while (0)
99
100 #define SHMEM_RD(bp, type) \
101         REG_RD(bp, bp->shmem_base + offsetof(struct shmem_region, type))
102 #define SHMEM_WR(bp, type, val) \
103         REG_WR(bp, bp->shmem_base + offsetof(struct shmem_region, type), val)
104
105 #define NIG_WR(reg, val)        REG_WR(bp, reg, val)
106 #define EMAC_WR(reg, val)       REG_WR(bp, emac_base + reg, val)
107 #define BMAC_WR(reg, val)       REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
108
109
110 #define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
111
112 #define for_each_nondefault_queue(bp, var) \
113                                 for (var = 1; var < bp->num_queues; var++)
114 #define is_multi(bp)            (bp->num_queues > 1)
115
116
117 struct regp {
118         u32 lo;
119         u32 hi;
120 };
121
122 struct bmac_stats {
123         struct regp tx_gtpkt;
124         struct regp tx_gtxpf;
125         struct regp tx_gtfcs;
126         struct regp tx_gtmca;
127         struct regp tx_gtgca;
128         struct regp tx_gtfrg;
129         struct regp tx_gtovr;
130         struct regp tx_gt64;
131         struct regp tx_gt127;
132         struct regp tx_gt255;   /* 10 */
133         struct regp tx_gt511;
134         struct regp tx_gt1023;
135         struct regp tx_gt1518;
136         struct regp tx_gt2047;
137         struct regp tx_gt4095;
138         struct regp tx_gt9216;
139         struct regp tx_gt16383;
140         struct regp tx_gtmax;
141         struct regp tx_gtufl;
142         struct regp tx_gterr;   /* 20 */
143         struct regp tx_gtbyt;
144
145         struct regp rx_gr64;
146         struct regp rx_gr127;
147         struct regp rx_gr255;
148         struct regp rx_gr511;
149         struct regp rx_gr1023;
150         struct regp rx_gr1518;
151         struct regp rx_gr2047;
152         struct regp rx_gr4095;
153         struct regp rx_gr9216;  /* 30 */
154         struct regp rx_gr16383;
155         struct regp rx_grmax;
156         struct regp rx_grpkt;
157         struct regp rx_grfcs;
158         struct regp rx_grmca;
159         struct regp rx_grbca;
160         struct regp rx_grxcf;
161         struct regp rx_grxpf;
162         struct regp rx_grxuo;
163         struct regp rx_grjbr;   /* 40 */
164         struct regp rx_grovr;
165         struct regp rx_grflr;
166         struct regp rx_grmeg;
167         struct regp rx_grmeb;
168         struct regp rx_grbyt;
169         struct regp rx_grund;
170         struct regp rx_grfrg;
171         struct regp rx_grerb;
172         struct regp rx_grfre;
173         struct regp rx_gripj;   /* 50 */
174 };
175
176 struct emac_stats {
177         u32 rx_ifhcinoctets                        ;
178         u32 rx_ifhcinbadoctets                     ;
179         u32 rx_etherstatsfragments                 ;
180         u32 rx_ifhcinucastpkts                     ;
181         u32 rx_ifhcinmulticastpkts                 ;
182         u32 rx_ifhcinbroadcastpkts                 ;
183         u32 rx_dot3statsfcserrors                  ;
184         u32 rx_dot3statsalignmenterrors            ;
185         u32 rx_dot3statscarriersenseerrors         ;
186         u32 rx_xonpauseframesreceived              ;    /* 10 */
187         u32 rx_xoffpauseframesreceived             ;
188         u32 rx_maccontrolframesreceived            ;
189         u32 rx_xoffstateentered                    ;
190         u32 rx_dot3statsframestoolong              ;
191         u32 rx_etherstatsjabbers                   ;
192         u32 rx_etherstatsundersizepkts             ;
193         u32 rx_etherstatspkts64octets              ;
194         u32 rx_etherstatspkts65octetsto127octets   ;
195         u32 rx_etherstatspkts128octetsto255octets  ;
196         u32 rx_etherstatspkts256octetsto511octets  ;    /* 20 */
197         u32 rx_etherstatspkts512octetsto1023octets ;
198         u32 rx_etherstatspkts1024octetsto1522octets;
199         u32 rx_etherstatspktsover1522octets        ;
200
201         u32 rx_falsecarriererrors                  ;
202
203         u32 tx_ifhcoutoctets                       ;
204         u32 tx_ifhcoutbadoctets                    ;
205         u32 tx_etherstatscollisions                ;
206         u32 tx_outxonsent                          ;
207         u32 tx_outxoffsent                         ;
208         u32 tx_flowcontroldone                     ;    /* 30 */
209         u32 tx_dot3statssinglecollisionframes      ;
210         u32 tx_dot3statsmultiplecollisionframes    ;
211         u32 tx_dot3statsdeferredtransmissions      ;
212         u32 tx_dot3statsexcessivecollisions        ;
213         u32 tx_dot3statslatecollisions             ;
214         u32 tx_ifhcoutucastpkts                    ;
215         u32 tx_ifhcoutmulticastpkts                ;
216         u32 tx_ifhcoutbroadcastpkts                ;
217         u32 tx_etherstatspkts64octets              ;
218         u32 tx_etherstatspkts65octetsto127octets   ;    /* 40 */
219         u32 tx_etherstatspkts128octetsto255octets  ;
220         u32 tx_etherstatspkts256octetsto511octets  ;
221         u32 tx_etherstatspkts512octetsto1023octets ;
222         u32 tx_etherstatspkts1024octetsto1522octet ;
223         u32 tx_etherstatspktsover1522octets        ;
224         u32 tx_dot3statsinternalmactransmiterrors  ;    /* 46 */
225 };
226
227 union mac_stats {
228         struct emac_stats emac;
229         struct bmac_stats bmac;
230 };
231
232 struct nig_stats {
233         u32 brb_discard;
234         u32 brb_packet;
235         u32 brb_truncate;
236         u32 flow_ctrl_discard;
237         u32 flow_ctrl_octets;
238         u32 flow_ctrl_packet;
239         u32 mng_discard;
240         u32 mng_octet_inp;
241         u32 mng_octet_out;
242         u32 mng_packet_inp;
243         u32 mng_packet_out;
244         u32 pbf_octets;
245         u32 pbf_packet;
246         u32 safc_inp;
247         u32 done;
248         u32 pad;
249 };
250
251 struct bnx2x_eth_stats {
252         u32 pad;        /* to make long counters u64 aligned */
253         u32 mac_stx_start;
254         u32 total_bytes_received_hi;
255         u32 total_bytes_received_lo;
256         u32 total_bytes_transmitted_hi;
257         u32 total_bytes_transmitted_lo;
258         u32 total_unicast_packets_received_hi;
259         u32 total_unicast_packets_received_lo;
260         u32 total_multicast_packets_received_hi;
261         u32 total_multicast_packets_received_lo;
262         u32 total_broadcast_packets_received_hi;
263         u32 total_broadcast_packets_received_lo;
264         u32 total_unicast_packets_transmitted_hi;
265         u32 total_unicast_packets_transmitted_lo;
266         u32 total_multicast_packets_transmitted_hi;
267         u32 total_multicast_packets_transmitted_lo;
268         u32 total_broadcast_packets_transmitted_hi;
269         u32 total_broadcast_packets_transmitted_lo;
270         u32 crc_receive_errors;
271         u32 alignment_errors;
272         u32 false_carrier_detections;
273         u32 runt_packets_received;
274         u32 jabber_packets_received;
275         u32 pause_xon_frames_received;
276         u32 pause_xoff_frames_received;
277         u32 pause_xon_frames_transmitted;
278         u32 pause_xoff_frames_transmitted;
279         u32 single_collision_transmit_frames;
280         u32 multiple_collision_transmit_frames;
281         u32 late_collision_frames;
282         u32 excessive_collision_frames;
283         u32 control_frames_received;
284         u32 frames_received_64_bytes;
285         u32 frames_received_65_127_bytes;
286         u32 frames_received_128_255_bytes;
287         u32 frames_received_256_511_bytes;
288         u32 frames_received_512_1023_bytes;
289         u32 frames_received_1024_1522_bytes;
290         u32 frames_received_1523_9022_bytes;
291         u32 frames_transmitted_64_bytes;
292         u32 frames_transmitted_65_127_bytes;
293         u32 frames_transmitted_128_255_bytes;
294         u32 frames_transmitted_256_511_bytes;
295         u32 frames_transmitted_512_1023_bytes;
296         u32 frames_transmitted_1024_1522_bytes;
297         u32 frames_transmitted_1523_9022_bytes;
298         u32 valid_bytes_received_hi;
299         u32 valid_bytes_received_lo;
300         u32 error_runt_packets_received;
301         u32 error_jabber_packets_received;
302         u32 mac_stx_end;
303
304         u32 pad2;
305         u32 stat_IfHCInBadOctets_hi;
306         u32 stat_IfHCInBadOctets_lo;
307         u32 stat_IfHCOutBadOctets_hi;
308         u32 stat_IfHCOutBadOctets_lo;
309         u32 stat_Dot3statsFramesTooLong;
310         u32 stat_Dot3statsInternalMacTransmitErrors;
311         u32 stat_Dot3StatsCarrierSenseErrors;
312         u32 stat_Dot3StatsDeferredTransmissions;
313         u32 stat_FlowControlDone;
314         u32 stat_XoffStateEntered;
315
316         u32 x_total_sent_bytes_hi;
317         u32 x_total_sent_bytes_lo;
318         u32 x_total_sent_pkts;
319
320         u32 t_rcv_unicast_bytes_hi;
321         u32 t_rcv_unicast_bytes_lo;
322         u32 t_rcv_broadcast_bytes_hi;
323         u32 t_rcv_broadcast_bytes_lo;
324         u32 t_rcv_multicast_bytes_hi;
325         u32 t_rcv_multicast_bytes_lo;
326         u32 t_total_rcv_pkt;
327
328         u32 checksum_discard;
329         u32 packets_too_big_discard;
330         u32 no_buff_discard;
331         u32 ttl0_discard;
332         u32 mac_discard;
333         u32 mac_filter_discard;
334         u32 xxoverflow_discard;
335         u32 brb_truncate_discard;
336
337         u32 brb_discard;
338         u32 brb_packet;
339         u32 brb_truncate;
340         u32 flow_ctrl_discard;
341         u32 flow_ctrl_octets;
342         u32 flow_ctrl_packet;
343         u32 mng_discard;
344         u32 mng_octet_inp;
345         u32 mng_octet_out;
346         u32 mng_packet_inp;
347         u32 mng_packet_out;
348         u32 pbf_octets;
349         u32 pbf_packet;
350         u32 safc_inp;
351         u32 driver_xoff;
352         u32 number_of_bugs_found_in_stats_spec; /* just kidding */
353 };
354
355 #define MAC_STX_NA                      0xffffffff
356
357 #ifdef BNX2X_MULTI
358 #define MAX_CONTEXT                     16
359 #else
360 #define MAX_CONTEXT                     1
361 #endif
362
363 union cdu_context {
364         struct eth_context eth;
365         char pad[1024];
366 };
367
368 #define MAX_DMAE_C                      5
369
370 /* DMA memory not used in fastpath */
371 struct bnx2x_slowpath {
372         union cdu_context               context[MAX_CONTEXT];
373         struct eth_stats_query          fw_stats;
374         struct mac_configuration_cmd    mac_config;
375         struct mac_configuration_cmd    mcast_config;
376
377         /* used by dmae command executer */
378         struct dmae_command             dmae[MAX_DMAE_C];
379
380         union mac_stats                 mac_stats;
381         struct nig_stats                nig;
382         struct bnx2x_eth_stats          eth_stats;
383
384         u32                             wb_comp;
385 #define BNX2X_WB_COMP_VAL               0xe0d0d0ae
386         u32                             wb_data[4];
387 };
388
389 #define bnx2x_sp(bp, var)               (&bp->slowpath->var)
390 #define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : NULL)
391 #define bnx2x_sp_mapping(bp, var) \
392                 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
393
394
395 struct sw_rx_bd {
396         struct sk_buff  *skb;
397         DECLARE_PCI_UNMAP_ADDR(mapping)
398 };
399
400 struct sw_tx_bd {
401         struct sk_buff  *skb;
402         u16             first_bd;
403 };
404
405 struct bnx2x_fastpath {
406
407         struct napi_struct      napi;
408
409         struct host_status_block *status_blk;
410         dma_addr_t              status_blk_mapping;
411
412         struct eth_tx_db_data   *hw_tx_prods;
413         dma_addr_t              tx_prods_mapping;
414
415         struct sw_tx_bd         *tx_buf_ring;
416
417         struct eth_tx_bd        *tx_desc_ring;
418         dma_addr_t              tx_desc_mapping;
419
420         struct sw_rx_bd         *rx_buf_ring;
421
422         struct eth_rx_bd        *rx_desc_ring;
423         dma_addr_t              rx_desc_mapping;
424
425         union eth_rx_cqe        *rx_comp_ring;
426         dma_addr_t              rx_comp_mapping;
427
428         int                     state;
429 #define BNX2X_FP_STATE_CLOSED           0
430 #define BNX2X_FP_STATE_IRQ              0x80000
431 #define BNX2X_FP_STATE_OPENING          0x90000
432 #define BNX2X_FP_STATE_OPEN             0xa0000
433 #define BNX2X_FP_STATE_HALTING          0xb0000
434 #define BNX2X_FP_STATE_HALTED           0xc0000
435
436         int                     index;
437
438         u16                     tx_pkt_prod;
439         u16                     tx_pkt_cons;
440         u16                     tx_bd_prod;
441         u16                     tx_bd_cons;
442         u16                     *tx_cons_sb;
443
444         u16                     fp_c_idx;
445         u16                     fp_u_idx;
446
447         u16                     rx_bd_prod;
448         u16                     rx_bd_cons;
449         u16                     rx_comp_prod;
450         u16                     rx_comp_cons;
451         u16                     *rx_cons_sb;
452
453         unsigned long           tx_pkt,
454                                 rx_pkt,
455                                 rx_calls;
456
457         struct bnx2x            *bp; /* parent */
458 };
459
460 #define bnx2x_fp(bp, nr, var)           (bp->fp[nr].var)
461
462
463 /* attn group wiring */
464 #define MAX_DYNAMIC_ATTN_GRPS           8
465
466 struct attn_route {
467         u32     sig[4];
468 };
469
470 struct bnx2x {
471         /* Fields used in the tx and intr/napi performance paths
472          * are grouped together in the beginning of the structure
473          */
474         struct bnx2x_fastpath   *fp;
475         void __iomem            *regview;
476         void __iomem            *doorbells;
477
478         struct net_device       *dev;
479         struct pci_dev          *pdev;
480
481         atomic_t                intr_sem;
482         struct msix_entry       msix_table[MAX_CONTEXT+1];
483
484         int                     tx_ring_size;
485
486 #ifdef BCM_VLAN
487         struct vlan_group       *vlgrp;
488 #endif
489
490         u32                     rx_csum;
491         u32                     rx_offset;
492         u32                     rx_buf_use_size;        /* useable size */
493         u32                     rx_buf_size;            /* with alignment */
494 #define ETH_OVREHEAD                    (ETH_HLEN + 8)  /* 8 for CRC + VLAN */
495 #define ETH_MIN_PACKET_SIZE             60
496 #define ETH_MAX_PACKET_SIZE             1500
497 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
498
499         struct host_def_status_block *def_status_blk;
500 #define DEF_SB_ID               16
501         u16                     def_c_idx;
502         u16                     def_u_idx;
503         u16                     def_t_idx;
504         u16                     def_x_idx;
505         u16                     def_att_idx;
506         u32                     attn_state;
507         struct attn_route       attn_group[MAX_DYNAMIC_ATTN_GRPS];
508         u32                     aeu_mask;
509         u32                     nig_mask;
510
511         /* slow path ring */
512         struct eth_spe          *spq;
513         dma_addr_t              spq_mapping;
514         u16                     spq_prod_idx;
515         struct eth_spe          *spq_prod_bd;
516         struct eth_spe          *spq_last_bd;
517         u16                     *dsb_sp_prod;
518         u16                     spq_left; /* serialize spq */
519         spinlock_t              spq_lock;
520
521         /* Flag for marking that there is either
522          * STAT_QUERY or CFC DELETE ramrod pending
523          */
524         u8                      stat_pending;
525
526         /* End of fields used in the performance code paths */
527
528         int                     panic;
529         int                     msglevel;
530
531         u32                     flags;
532 #define PCIX_FLAG                       1
533 #define PCI_32BIT_FLAG                  2
534 #define ONE_TDMA_FLAG                   4       /* no longer used */
535 #define NO_WOL_FLAG                     8
536 #define USING_DAC_FLAG                  0x10
537 #define USING_MSIX_FLAG                 0x20
538 #define ASF_ENABLE_FLAG                 0x40
539
540         int                     port;
541
542         int                     pm_cap;
543         int                     pcie_cap;
544
545         /* Used to synchronize phy accesses */
546         spinlock_t              phy_lock;
547
548         struct work_struct      reset_task;
549         struct work_struct      sp_task;
550
551         struct timer_list       timer;
552         int                     timer_interval;
553         int                     current_interval;
554
555         u32                     shmem_base;
556
557         u32                     chip_id;
558 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
559 #define CHIP_ID(bp)                     (((bp)->chip_id) & 0xfffffff0)
560
561 #define CHIP_NUM(bp)                    (((bp)->chip_id) & 0xffff0000)
562
563 #define CHIP_REV(bp)                    (((bp)->chip_id) & 0x0000f000)
564 #define CHIP_REV_Ax                     0x00000000
565 #define CHIP_REV_Bx                     0x00001000
566 #define CHIP_REV_Cx                     0x00002000
567 #define CHIP_REV_EMUL                   0x0000e000
568 #define CHIP_REV_FPGA                   0x0000f000
569 #define CHIP_REV_IS_SLOW(bp)            ((CHIP_REV(bp) == CHIP_REV_EMUL) || \
570                                          (CHIP_REV(bp) == CHIP_REV_FPGA))
571
572 #define CHIP_METAL(bp)                  (((bp)->chip_id) & 0x00000ff0)
573 #define CHIP_BOND_ID(bp)                (((bp)->chip_id) & 0x0000000f)
574
575         u16                     fw_seq;
576         u16                     fw_drv_pulse_wr_seq;
577         u32                     fw_mb;
578
579         u32                     hw_config;
580         u32                     board;
581         u32                     serdes_config;
582         u32                     lane_config;
583         u32                     ext_phy_config;
584 #define XGXS_EXT_PHY_TYPE(bp)           (bp->ext_phy_config & \
585                                          PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
586 #define SERDES_EXT_PHY_TYPE(bp)         (bp->ext_phy_config & \
587                                          PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
588
589         u32                     speed_cap_mask;
590         u32                     link_config;
591 #define SWITCH_CFG_1G                   PORT_FEATURE_CON_SWITCH_1G_SWITCH
592 #define SWITCH_CFG_10G                  PORT_FEATURE_CON_SWITCH_10G_SWITCH
593 #define SWITCH_CFG_AUTO_DETECT          PORT_FEATURE_CON_SWITCH_AUTO_DETECT
594 #define SWITCH_CFG_ONE_TIME_DETECT      \
595                                 PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT
596
597         u8                      ser_lane;
598         u8                      rx_lane_swap;
599         u8                      tx_lane_swap;
600
601         u8                      link_up;
602         u8                      phy_link_up;
603
604         u32                     supported;
605 /* link settings - missing defines */
606 #define SUPPORTED_2500baseT_Full        (1 << 15)
607
608         u32                     phy_flags;
609 /*#define PHY_SERDES_FLAG                       0x1*/
610 #define PHY_BMAC_FLAG                   0x2
611 #define PHY_EMAC_FLAG                   0x4
612 #define PHY_XGXS_FLAG                   0x8
613 #define PHY_SGMII_FLAG                  0x10
614 #define PHY_INT_MODE_MASK_FLAG          0x300
615 #define PHY_INT_MODE_AUTO_POLLING_FLAG  0x100
616 #define PHY_INT_MODE_LINK_READY_FLAG    0x200
617
618         u32                     phy_addr;
619         u32                     phy_id;
620
621         u32                     autoneg;
622 #define AUTONEG_CL37                    SHARED_HW_CFG_AN_ENABLE_CL37
623 #define AUTONEG_CL73                    SHARED_HW_CFG_AN_ENABLE_CL73
624 #define AUTONEG_BAM                     SHARED_HW_CFG_AN_ENABLE_BAM
625 #define AUTONEG_PARALLEL                \
626                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
627 #define AUTONEG_SGMII_FIBER_AUTODET     \
628                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
629 #define AUTONEG_REMOTE_PHY              SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
630
631         u32                     req_autoneg;
632 #define AUTONEG_SPEED                   0x1
633 #define AUTONEG_FLOW_CTRL               0x2
634
635         u32                     req_line_speed;
636 /* link settings - missing defines */
637 #define SPEED_12000                     12000
638 #define SPEED_12500                     12500
639 #define SPEED_13000                     13000
640 #define SPEED_15000                     15000
641 #define SPEED_16000                     16000
642
643         u32                     req_duplex;
644         u32                     req_flow_ctrl;
645 #define FLOW_CTRL_AUTO                  PORT_FEATURE_FLOW_CONTROL_AUTO
646 #define FLOW_CTRL_TX                    PORT_FEATURE_FLOW_CONTROL_TX
647 #define FLOW_CTRL_RX                    PORT_FEATURE_FLOW_CONTROL_RX
648 #define FLOW_CTRL_BOTH                  PORT_FEATURE_FLOW_CONTROL_BOTH
649 #define FLOW_CTRL_NONE                  PORT_FEATURE_FLOW_CONTROL_NONE
650
651         u32                     advertising;
652 /* link settings - missing defines */
653 #define ADVERTISED_2500baseT_Full       (1 << 15)
654
655         u32                     link_status;
656         u32                     line_speed;
657         u32                     duplex;
658         u32                     flow_ctrl;
659
660         u32                     bc_ver;
661
662         int                     flash_size;
663 #define NVRAM_1MB_SIZE                  0x20000 /* 1M bit in bytes */
664 #define NVRAM_TIMEOUT_COUNT             30000
665 #define NVRAM_PAGE_SIZE                 256
666
667         u8                      wol;
668
669         int                     rx_ring_size;
670
671         u16                     tx_quick_cons_trip_int;
672         u16                     tx_quick_cons_trip;
673         u16                     tx_ticks_int;
674         u16                     tx_ticks;
675
676         u16                     rx_quick_cons_trip_int;
677         u16                     rx_quick_cons_trip;
678         u16                     rx_ticks_int;
679         u16                     rx_ticks;
680
681         u32                     stats_ticks;
682
683         int                     state;
684 #define BNX2X_STATE_CLOSED              0x0
685 #define BNX2X_STATE_OPENING_WAIT4_LOAD  0x1000
686 #define BNX2X_STATE_OPENING_WAIT4_PORT  0x2000
687 #define BNX2X_STATE_OPEN                0x3000
688 #define BNX2X_STATE_CLOSING_WAIT4_HALT  0x4000
689 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
690 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
691 #define BNX2X_STATE_ERROR               0xF000
692
693         int                     num_queues;
694
695         u32                     rx_mode;
696 #define BNX2X_RX_MODE_NONE              0
697 #define BNX2X_RX_MODE_NORMAL            1
698 #define BNX2X_RX_MODE_ALLMULTI          2
699 #define BNX2X_RX_MODE_PROMISC           3
700 #define BNX2X_MAX_MULTICAST             64
701 #define BNX2X_MAX_EMUL_MULTI            16
702
703         dma_addr_t              def_status_blk_mapping;
704
705         struct bnx2x_slowpath   *slowpath;
706         dma_addr_t              slowpath_mapping;
707
708 #ifdef BCM_ISCSI
709         void                    *t1;
710         dma_addr_t              t1_mapping;
711         void                    *t2;
712         dma_addr_t              t2_mapping;
713         void                    *timers;
714         dma_addr_t              timers_mapping;
715         void                    *qm;
716         dma_addr_t              qm_mapping;
717 #endif
718
719         char                    *name;
720
721         /* used to synchronize stats collecting */
722         int                     stats_state;
723 #define STATS_STATE_DISABLE             0
724 #define STATS_STATE_ENABLE              1
725 #define STATS_STATE_STOP                2 /* stop stats on next iteration */
726
727         /* used by dmae command loader */
728         struct dmae_command     dmae;
729         int                     executer_idx;
730
731         u32                     old_brb_discard;
732         struct bmac_stats       old_bmac;
733         struct tstorm_per_client_stats old_tclient;
734         struct z_stream_s       *strm;
735         void                    *gunzip_buf;
736         dma_addr_t              gunzip_mapping;
737         int                     gunzip_outlen;
738 #define FW_BUF_SIZE                     0x8000
739
740 };
741
742
743 /* DMAE command defines */
744 #define DMAE_CMD_SRC_PCI                0
745 #define DMAE_CMD_SRC_GRC                DMAE_COMMAND_SRC
746
747 #define DMAE_CMD_DST_PCI                (1 << DMAE_COMMAND_DST_SHIFT)
748 #define DMAE_CMD_DST_GRC                (2 << DMAE_COMMAND_DST_SHIFT)
749
750 #define DMAE_CMD_C_DST_PCI              0
751 #define DMAE_CMD_C_DST_GRC              (1 << DMAE_COMMAND_C_DST_SHIFT)
752
753 #define DMAE_CMD_C_ENABLE               DMAE_COMMAND_C_TYPE_ENABLE
754
755 #define DMAE_CMD_ENDIANITY_NO_SWAP      (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
756 #define DMAE_CMD_ENDIANITY_B_SWAP       (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
757 #define DMAE_CMD_ENDIANITY_DW_SWAP      (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
758 #define DMAE_CMD_ENDIANITY_B_DW_SWAP    (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
759
760 #define DMAE_CMD_PORT_0                 0
761 #define DMAE_CMD_PORT_1                 DMAE_COMMAND_PORT
762
763 #define DMAE_CMD_SRC_RESET              DMAE_COMMAND_SRC_RESET
764 #define DMAE_CMD_DST_RESET              DMAE_COMMAND_DST_RESET
765
766 #define DMAE_LEN32_MAX                  0x400
767
768
769 /* MC hsi */
770 #define RX_COPY_THRESH                  92
771 #define BCM_PAGE_BITS                   12
772 #define BCM_PAGE_SIZE                   (1 << BCM_PAGE_BITS)
773
774 #define NUM_TX_RINGS                    16
775 #define TX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
776 #define MAX_TX_DESC_CNT                 (TX_DESC_CNT - 1)
777 #define NUM_TX_BD                       (TX_DESC_CNT * NUM_TX_RINGS)
778 #define MAX_TX_BD                       (NUM_TX_BD - 1)
779 #define MAX_TX_AVAIL                    (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
780 #define NEXT_TX_IDX(x)          ((((x) & MAX_TX_DESC_CNT) == \
781                                  (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
782 #define TX_BD(x)                        ((x) & MAX_TX_BD)
783 #define TX_BD_POFF(x)                   ((x) & MAX_TX_DESC_CNT)
784
785 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
786 #define NUM_RX_RINGS                    8
787 #define RX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
788 #define MAX_RX_DESC_CNT                 (RX_DESC_CNT - 2)
789 #define RX_DESC_MASK                    (RX_DESC_CNT - 1)
790 #define NUM_RX_BD                       (RX_DESC_CNT * NUM_RX_RINGS)
791 #define MAX_RX_BD                       (NUM_RX_BD - 1)
792 #define MAX_RX_AVAIL                    (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
793 #define NEXT_RX_IDX(x)          ((((x) & RX_DESC_MASK) == \
794                                  (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
795 #define RX_BD(x)                        ((x) & MAX_RX_BD)
796
797 #define NUM_RCQ_RINGS                   (NUM_RX_RINGS * 2)
798 #define RCQ_DESC_CNT            (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
799 #define MAX_RCQ_DESC_CNT                (RCQ_DESC_CNT - 1)
800 #define NUM_RCQ_BD                      (RCQ_DESC_CNT * NUM_RCQ_RINGS)
801 #define MAX_RCQ_BD                      (NUM_RCQ_BD - 1)
802 #define MAX_RCQ_AVAIL                   (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
803 #define NEXT_RCQ_IDX(x)         ((((x) & MAX_RCQ_DESC_CNT) == \
804                                  (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
805 #define RCQ_BD(x)                       ((x) & MAX_RCQ_BD)
806
807
808 /* used on a CID received from the HW */
809 #define SW_CID(x)                       (le32_to_cpu(x) & \
810                                          (COMMON_RAMROD_ETH_RX_CQE_CID >> 1))
811 #define CQE_CMD(x)                      (le32_to_cpu(x) >> \
812                                         COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
813
814 #define BD_UNMAP_ADDR(bd)               HILO_U64(le32_to_cpu((bd)->addr_hi), \
815                                                  le32_to_cpu((bd)->addr_lo))
816 #define BD_UNMAP_LEN(bd)                (le16_to_cpu((bd)->nbytes))
817
818
819 #define STROM_ASSERT_ARRAY_SIZE         50
820
821
822 #define MDIO_INDIRECT_REG_ADDR          0x1f
823 #define MDIO_SET_REG_BANK(bp, reg_bank) \
824                 bnx2x_mdio22_write(bp, MDIO_INDIRECT_REG_ADDR, reg_bank)
825
826 #define MDIO_ACCESS_TIMEOUT             1000
827
828
829 /* must be used on a CID before placing it on a HW ring */
830 #define HW_CID(bp, x)                   (x | (bp->port << 23))
831
832 #define SP_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_spe))
833 #define MAX_SP_DESC_CNT                 (SP_DESC_CNT - 1)
834
835 #define ATTN_NIG_FOR_FUNC               (1L << 8)
836 #define ATTN_SW_TIMER_4_FUNC            (1L << 9)
837 #define GPIO_2_FUNC                     (1L << 10)
838 #define GPIO_3_FUNC                     (1L << 11)
839 #define GPIO_4_FUNC                     (1L << 12)
840 #define ATTN_GENERAL_ATTN_1             (1L << 13)
841 #define ATTN_GENERAL_ATTN_2             (1L << 14)
842 #define ATTN_GENERAL_ATTN_3             (1L << 15)
843 #define ATTN_GENERAL_ATTN_4             (1L << 13)
844 #define ATTN_GENERAL_ATTN_5             (1L << 14)
845 #define ATTN_GENERAL_ATTN_6             (1L << 15)
846
847 #define ATTN_HARD_WIRED_MASK            0xff00
848 #define ATTENTION_ID                    4
849
850
851 #define BNX2X_BTR                       3
852 #define MAX_SPQ_PENDING                 8
853
854
855 #define BNX2X_NUM_STATS                 34
856 #define BNX2X_NUM_TESTS                 1
857
858
859 #define DPM_TRIGER_TYPE                 0x40
860 #define DOORBELL(bp, cid, val) \
861         do { \
862                 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
863                        DPM_TRIGER_TYPE); \
864         } while (0)
865
866 /* PCIE link and speed */
867 #define PCICFG_LINK_WIDTH               0x1f00000
868 #define PCICFG_LINK_WIDTH_SHIFT         20
869 #define PCICFG_LINK_SPEED               0xf0000
870 #define PCICFG_LINK_SPEED_SHIFT         16
871
872 #define BMAC_CONTROL_RX_ENABLE          2
873
874 #define pbd_tcp_flags(skb)      (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
875
876 /* stuff added to make the code fit 80Col */
877
878 #define TPA_TYPE_START                  ETH_FAST_PATH_RX_CQE_START_FLG
879 #define TPA_TYPE_END                    ETH_FAST_PATH_RX_CQE_END_FLG
880 #define TPA_TYPE(cqe)           (cqe->fast_path_cqe.error_type_flags & \
881                                  (TPA_TYPE_START | TPA_TYPE_END))
882 #define BNX2X_RX_SUM_OK(cqe) \
883                         (!(cqe->fast_path_cqe.status_flags & \
884                          (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \
885                           ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))
886
887 #define BNX2X_RX_SUM_FIX(cqe) \
888                         ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
889                           PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
890                          (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
891
892
893 #define MDIO_AN_CL73_OR_37_COMPLETE \
894                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
895                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
896
897 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
898                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
899 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
900                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
901 #define GP_STATUS_SPEED_MASK \
902                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
903 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
904 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
905 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
906 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
907 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
908 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
909 #define GP_STATUS_10G_HIG \
910                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
911 #define GP_STATUS_10G_CX4 \
912                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
913 #define GP_STATUS_12G_HIG \
914                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
915 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
916 #define GP_STATUS_13G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
917 #define GP_STATUS_15G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
918 #define GP_STATUS_16G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
919 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
920 #define GP_STATUS_10G_KX4 \
921                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
922
923 #define LINK_10THD                      LINK_STATUS_SPEED_AND_DUPLEX_10THD
924 #define LINK_10TFD                      LINK_STATUS_SPEED_AND_DUPLEX_10TFD
925 #define LINK_100TXHD                    LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
926 #define LINK_100T4                      LINK_STATUS_SPEED_AND_DUPLEX_100T4
927 #define LINK_100TXFD                    LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
928 #define LINK_1000THD                    LINK_STATUS_SPEED_AND_DUPLEX_1000THD
929 #define LINK_1000TFD                    LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
930 #define LINK_1000XFD                    LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
931 #define LINK_2500THD                    LINK_STATUS_SPEED_AND_DUPLEX_2500THD
932 #define LINK_2500TFD                    LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
933 #define LINK_2500XFD                    LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
934 #define LINK_10GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
935 #define LINK_10GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
936 #define LINK_12GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
937 #define LINK_12GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
938 #define LINK_12_5GTFD                   LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
939 #define LINK_12_5GXFD                   LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
940 #define LINK_13GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
941 #define LINK_13GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
942 #define LINK_15GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
943 #define LINK_15GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
944 #define LINK_16GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
945 #define LINK_16GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
946
947 #define NIG_STATUS_XGXS0_LINK10G \
948                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
949 #define NIG_STATUS_XGXS0_LINK_STATUS \
950                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
951 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
952                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
953 #define NIG_STATUS_SERDES0_LINK_STATUS \
954                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
955 #define NIG_MASK_MI_INT \
956                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
957 #define NIG_MASK_XGXS0_LINK10G \
958                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
959 #define NIG_MASK_XGXS0_LINK_STATUS \
960                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
961 #define NIG_MASK_SERDES0_LINK_STATUS \
962                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
963
964 #define XGXS_RESET_BITS \
965         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
966          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
967          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
968          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
969          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
970
971 #define SERDES_RESET_BITS \
972         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
973          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
974          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
975          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
976
977
978 #define BNX2X_MC_ASSERT_BITS \
979         (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
980          GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
981          GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
982          GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
983
984 #define BNX2X_MCP_ASSERT \
985         GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
986
987 #define BNX2X_DOORQ_ASSERT \
988         AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
989
990 #define HW_INTERRUT_ASSERT_SET_0 \
991                                 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
992                                  AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
993                                  AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
994                                  AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
995 #define HW_PRTY_ASSERT_SET_0    (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
996                                  AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
997                                  AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
998                                  AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
999                                  AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1000 #define HW_INTERRUT_ASSERT_SET_1 \
1001                                 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1002                                  AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1003                                  AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1004                                  AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1005                                  AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1006                                  AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1007                                  AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1008                                  AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1009                                  AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1010                                  AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1011                                  AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1012 #define HW_PRTY_ASSERT_SET_1    (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1013                                  AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1014                                  AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1015                                  AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1016                                 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1017                             AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1018                                  AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1019                                  AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1020                                  AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1021                                  AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1022                                  AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1023 #define HW_INTERRUT_ASSERT_SET_2 \
1024                                 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1025                                  AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1026                                  AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1027                         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1028                                  AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1029 #define HW_PRTY_ASSERT_SET_2    (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1030                                  AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1031                         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1032                                  AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1033                                  AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1034                                  AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1035                                  AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1036
1037
1038 #define ETH_RX_ERROR_FALGS      (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
1039                                  ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
1040                                  ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
1041
1042
1043 #define MULTI_FLAGS \
1044         (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY     | \
1045          TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1046          TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY     | \
1047          TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1048          TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
1049
1050 #define MULTI_MASK      0x7f
1051
1052
1053 #define U_SB_ETH_RX_CQ_INDEX            HC_INDEX_U_ETH_RX_CQ_CONS
1054 #define C_SB_ETH_TX_CQ_INDEX            HC_INDEX_C_ETH_TX_CQ_CONS
1055 #define C_DEF_SB_SP_INDEX               HC_INDEX_DEF_C_ETH_SLOW_PATH
1056
1057 #define BNX2X_RX_SB_INDEX \
1058         &fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]
1059
1060 #define BNX2X_TX_SB_INDEX \
1061         &fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]
1062
1063 #define BNX2X_SP_DSB_INDEX \
1064 &bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]
1065
1066
1067 #define CAM_IS_INVALID(x) \
1068 (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1069
1070 #define CAM_INVALIDATE(x) \
1071 x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE
1072
1073
1074 /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1075
1076 #endif /* bnx2x.h */