bnx2x: Updating the Maintainer
[linux-2.6.git] / drivers / net / bnx2x.c
1 /* bnx2x.c: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2008 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10  * Written by: Eliezer Tamir
11  * Based on code from Michael Chan's bnx2 driver
12  * UDP CSUM errata workaround by Arik Gendelman
13  * Slowpath rework by Vladislav Zolotarov
14  * Statistics and Link management by Yitchak Gertner
15  *
16  */
17
18 /* define this to make the driver freeze on error
19  * to allow getting debug info
20  * (you will need to reboot afterwards)
21  */
22 /*#define BNX2X_STOP_ON_ERROR*/
23
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/kernel.h>
27 #include <linux/device.h>  /* for dev_info() */
28 #include <linux/timer.h>
29 #include <linux/errno.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/vmalloc.h>
33 #include <linux/interrupt.h>
34 #include <linux/pci.h>
35 #include <linux/init.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/bitops.h>
41 #include <linux/irq.h>
42 #include <linux/delay.h>
43 #include <asm/byteorder.h>
44 #include <linux/time.h>
45 #include <linux/ethtool.h>
46 #include <linux/mii.h>
47 #ifdef NETIF_F_HW_VLAN_TX
48         #include <linux/if_vlan.h>
49         #define BCM_VLAN 1
50 #endif
51 #include <net/ip.h>
52 #include <net/tcp.h>
53 #include <net/checksum.h>
54 #include <linux/workqueue.h>
55 #include <linux/crc32.h>
56 #include <linux/prefetch.h>
57 #include <linux/zlib.h>
58 #include <linux/version.h>
59 #include <linux/io.h>
60
61 #include "bnx2x_reg.h"
62 #include "bnx2x_fw_defs.h"
63 #include "bnx2x_hsi.h"
64 #include "bnx2x.h"
65 #include "bnx2x_init.h"
66
67 #define DRV_MODULE_VERSION      "1.42.4"
68 #define DRV_MODULE_RELDATE      "2008/4/9"
69 #define BNX2X_BC_VER            0x040200
70
71 /* Time in jiffies before concluding the transmitter is hung. */
72 #define TX_TIMEOUT              (5*HZ)
73
74 static char version[] __devinitdata =
75         "Broadcom NetXtreme II 5771X 10Gigabit Ethernet Driver "
76         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
77
78 MODULE_AUTHOR("Eliezer Tamir");
79 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710 Driver");
80 MODULE_LICENSE("GPL");
81 MODULE_VERSION(DRV_MODULE_VERSION);
82
83 static int use_inta;
84 static int poll;
85 static int onefunc;
86 static int nomcp;
87 static int debug;
88 static int use_multi;
89
90 module_param(use_inta, int, 0);
91 module_param(poll, int, 0);
92 module_param(onefunc, int, 0);
93 module_param(debug, int, 0);
94 MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X");
95 MODULE_PARM_DESC(poll, "use polling (for debug)");
96 MODULE_PARM_DESC(onefunc, "enable only first function");
97 MODULE_PARM_DESC(nomcp, "ignore management CPU (Implies onefunc)");
98 MODULE_PARM_DESC(debug, "default debug msglevel");
99
100 #ifdef BNX2X_MULTI
101 module_param(use_multi, int, 0);
102 MODULE_PARM_DESC(use_multi, "use per-CPU queues");
103 #endif
104
105 enum bnx2x_board_type {
106         BCM57710 = 0,
107 };
108
109 /* indexed by board_t, above */
110 static struct {
111         char *name;
112 } board_info[] __devinitdata = {
113         { "Broadcom NetXtreme II BCM57710 XGb" }
114 };
115
116 static const struct pci_device_id bnx2x_pci_tbl[] = {
117         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710,
118                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 },
119         { 0 }
120 };
121
122 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
123
124 /****************************************************************************
125 * General service functions
126 ****************************************************************************/
127
128 /* used only at init
129  * locking is done by mcp
130  */
131 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
132 {
133         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
134         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
135         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
136                                PCICFG_VENDOR_ID_OFFSET);
137 }
138
139 #ifdef BNX2X_IND_RD
140 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
141 {
142         u32 val;
143
144         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
145         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
146         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
147                                PCICFG_VENDOR_ID_OFFSET);
148
149         return val;
150 }
151 #endif
152
153 static const u32 dmae_reg_go_c[] = {
154         DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
155         DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
156         DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
157         DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
158 };
159
160 /* copy command into DMAE command memory and set DMAE command go */
161 static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
162                             int idx)
163 {
164         u32 cmd_offset;
165         int i;
166
167         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
168         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
169                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
170
171 /*              DP(NETIF_MSG_DMAE, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
172                    idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); */
173         }
174         REG_WR(bp, dmae_reg_go_c[idx], 1);
175 }
176
177 static void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
178                              u32 dst_addr, u32 len32)
179 {
180         struct dmae_command *dmae = &bp->dmae;
181         int port = bp->port;
182         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
183         int timeout = 200;
184
185         memset(dmae, 0, sizeof(struct dmae_command));
186
187         dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
188                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
189                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
190 #ifdef __BIG_ENDIAN
191                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
192 #else
193                         DMAE_CMD_ENDIANITY_DW_SWAP |
194 #endif
195                         (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
196         dmae->src_addr_lo = U64_LO(dma_addr);
197         dmae->src_addr_hi = U64_HI(dma_addr);
198         dmae->dst_addr_lo = dst_addr >> 2;
199         dmae->dst_addr_hi = 0;
200         dmae->len = len32;
201         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
202         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
203         dmae->comp_val = BNX2X_WB_COMP_VAL;
204
205 /*
206         DP(NETIF_MSG_DMAE, "dmae: opcode 0x%08x\n"
207            DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
208                     "dst_addr [%x:%08x (%08x)]\n"
209            DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
210            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
211            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
212            dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
213 */
214 /*
215         DP(NETIF_MSG_DMAE, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
216            bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
217            bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
218 */
219
220         *wb_comp = 0;
221
222         bnx2x_post_dmae(bp, dmae, port * 8);
223
224         udelay(5);
225         /* adjust timeout for emulation/FPGA */
226         if (CHIP_REV_IS_SLOW(bp))
227                 timeout *= 100;
228         while (*wb_comp != BNX2X_WB_COMP_VAL) {
229 /*              DP(NETIF_MSG_DMAE, "wb_comp 0x%08x\n", *wb_comp); */
230                 udelay(5);
231                 if (!timeout) {
232                         BNX2X_ERR("dmae timeout!\n");
233                         break;
234                 }
235                 timeout--;
236         }
237 }
238
239 #ifdef BNX2X_DMAE_RD
240 static void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
241 {
242         struct dmae_command *dmae = &bp->dmae;
243         int port = bp->port;
244         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
245         int timeout = 200;
246
247         memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
248         memset(dmae, 0, sizeof(struct dmae_command));
249
250         dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
251                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
252                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
253 #ifdef __BIG_ENDIAN
254                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
255 #else
256                         DMAE_CMD_ENDIANITY_DW_SWAP |
257 #endif
258                         (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
259         dmae->src_addr_lo = src_addr >> 2;
260         dmae->src_addr_hi = 0;
261         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
262         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
263         dmae->len = len32;
264         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
265         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
266         dmae->comp_val = BNX2X_WB_COMP_VAL;
267
268 /*
269         DP(NETIF_MSG_DMAE, "dmae: opcode 0x%08x\n"
270            DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
271                     "dst_addr [%x:%08x (%08x)]\n"
272            DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
273            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
274            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
275            dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
276 */
277
278         *wb_comp = 0;
279
280         bnx2x_post_dmae(bp, dmae, port * 8);
281
282         udelay(5);
283         while (*wb_comp != BNX2X_WB_COMP_VAL) {
284                 udelay(5);
285                 if (!timeout) {
286                         BNX2X_ERR("dmae timeout!\n");
287                         break;
288                 }
289                 timeout--;
290         }
291 /*
292         DP(NETIF_MSG_DMAE, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
293            bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
294            bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
295 */
296 }
297 #endif
298
299 static int bnx2x_mc_assert(struct bnx2x *bp)
300 {
301         int i, j, rc = 0;
302         char last_idx;
303         const char storm[] = {"XTCU"};
304         const u32 intmem_base[] = {
305                 BAR_XSTRORM_INTMEM,
306                 BAR_TSTRORM_INTMEM,
307                 BAR_CSTRORM_INTMEM,
308                 BAR_USTRORM_INTMEM
309         };
310
311         /* Go through all instances of all SEMIs */
312         for (i = 0; i < 4; i++) {
313                 last_idx = REG_RD8(bp, XSTORM_ASSERT_LIST_INDEX_OFFSET +
314                                    intmem_base[i]);
315                 if (last_idx)
316                         BNX2X_LOG("DATA %cSTORM_ASSERT_LIST_INDEX 0x%x\n",
317                                   storm[i], last_idx);
318
319                 /* print the asserts */
320                 for (j = 0; j < STROM_ASSERT_ARRAY_SIZE; j++) {
321                         u32 row0, row1, row2, row3;
322
323                         row0 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) +
324                                       intmem_base[i]);
325                         row1 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 4 +
326                                       intmem_base[i]);
327                         row2 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 8 +
328                                       intmem_base[i]);
329                         row3 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 12 +
330                                       intmem_base[i]);
331
332                         if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
333                                 BNX2X_LOG("DATA %cSTORM_ASSERT_INDEX 0x%x ="
334                                           " 0x%08x 0x%08x 0x%08x 0x%08x\n",
335                                           storm[i], j, row3, row2, row1, row0);
336                                 rc++;
337                         } else {
338                                 break;
339                         }
340                 }
341         }
342         return rc;
343 }
344
345 static void bnx2x_fw_dump(struct bnx2x *bp)
346 {
347         u32 mark, offset;
348         u32 data[9];
349         int word;
350
351         mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
352         mark = ((mark + 0x3) & ~0x3);
353         printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n" KERN_ERR, mark);
354
355         for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
356                 for (word = 0; word < 8; word++)
357                         data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
358                                                   offset + 4*word));
359                 data[8] = 0x0;
360                 printk(KERN_CONT "%s", (char *)data);
361         }
362         for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
363                 for (word = 0; word < 8; word++)
364                         data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
365                                                   offset + 4*word));
366                 data[8] = 0x0;
367                 printk(KERN_CONT "%s", (char *)data);
368         }
369         printk("\n" KERN_ERR PFX "end of fw dump\n");
370 }
371
372 static void bnx2x_panic_dump(struct bnx2x *bp)
373 {
374         int i;
375         u16 j, start, end;
376
377         BNX2X_ERR("begin crash dump -----------------\n");
378
379         for_each_queue(bp, i) {
380                 struct bnx2x_fastpath *fp = &bp->fp[i];
381                 struct eth_tx_db_data *hw_prods = fp->hw_tx_prods;
382
383                 BNX2X_ERR("queue[%d]: tx_pkt_prod(%x)  tx_pkt_cons(%x)"
384                           "  tx_bd_prod(%x)  tx_bd_cons(%x)  *tx_cons_sb(%x)"
385                           "  *rx_cons_sb(%x)  rx_comp_prod(%x)"
386                           "  rx_comp_cons(%x)  fp_c_idx(%x)  fp_u_idx(%x)"
387                           "  bd data(%x,%x)\n",
388                           i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
389                           fp->tx_bd_cons, *fp->tx_cons_sb, *fp->rx_cons_sb,
390                           fp->rx_comp_prod, fp->rx_comp_cons, fp->fp_c_idx,
391                           fp->fp_u_idx, hw_prods->packets_prod,
392                           hw_prods->bds_prod);
393
394                 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
395                 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
396                 for (j = start; j < end; j++) {
397                         struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
398
399                         BNX2X_ERR("packet[%x]=[%p,%x]\n", j,
400                                   sw_bd->skb, sw_bd->first_bd);
401                 }
402
403                 start = TX_BD(fp->tx_bd_cons - 10);
404                 end = TX_BD(fp->tx_bd_cons + 254);
405                 for (j = start; j < end; j++) {
406                         u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
407
408                         BNX2X_ERR("tx_bd[%x]=[%x:%x:%x:%x]\n",
409                                   j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
410                 }
411
412                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
413                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
414                 for (j = start; j < end; j++) {
415                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
416                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
417
418                         BNX2X_ERR("rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
419                                   j, rx_bd[0], rx_bd[1], sw_bd->skb);
420                 }
421
422                 start = RCQ_BD(fp->rx_comp_cons - 10);
423                 end = RCQ_BD(fp->rx_comp_cons + 503);
424                 for (j = start; j < end; j++) {
425                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
426
427                         BNX2X_ERR("cqe[%x]=[%x:%x:%x:%x]\n",
428                                   j, cqe[0], cqe[1], cqe[2], cqe[3]);
429                 }
430         }
431
432         BNX2X_ERR("def_c_idx(%u)  def_u_idx(%u)  def_x_idx(%u)"
433                   "  def_t_idx(%u)  def_att_idx(%u)  attn_state(%u)"
434                   "  spq_prod_idx(%u)\n",
435                   bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx,
436                   bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);
437
438
439         bnx2x_mc_assert(bp);
440         BNX2X_ERR("end crash dump -----------------\n");
441
442         bp->stats_state = STATS_STATE_DISABLE;
443         DP(BNX2X_MSG_STATS, "stats_state - DISABLE\n");
444 }
445
446 static void bnx2x_int_enable(struct bnx2x *bp)
447 {
448         int port = bp->port;
449         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
450         u32 val = REG_RD(bp, addr);
451         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
452
453         if (msix) {
454                 val &= ~HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
455                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
456                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
457         } else {
458                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
459                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
460                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
461                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
462
463                 /* Errata A0.158 workaround */
464                 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  MSI-X %d\n",
465                    val, port, addr, msix);
466
467                 REG_WR(bp, addr, val);
468
469                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
470         }
471
472         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  MSI-X %d\n",
473            val, port, addr, msix);
474
475         REG_WR(bp, addr, val);
476 }
477
478 static void bnx2x_int_disable(struct bnx2x *bp)
479 {
480         int port = bp->port;
481         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
482         u32 val = REG_RD(bp, addr);
483
484         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
485                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
486                  HC_CONFIG_0_REG_INT_LINE_EN_0 |
487                  HC_CONFIG_0_REG_ATTN_BIT_EN_0);
488
489         DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
490            val, port, addr);
491
492         REG_WR(bp, addr, val);
493         if (REG_RD(bp, addr) != val)
494                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
495 }
496
497 static void bnx2x_int_disable_sync(struct bnx2x *bp)
498 {
499
500         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
501         int i;
502
503         atomic_inc(&bp->intr_sem);
504         /* prevent the HW from sending interrupts */
505         bnx2x_int_disable(bp);
506
507         /* make sure all ISRs are done */
508         if (msix) {
509                 for_each_queue(bp, i)
510                         synchronize_irq(bp->msix_table[i].vector);
511
512                 /* one more for the Slow Path IRQ */
513                 synchronize_irq(bp->msix_table[i].vector);
514         } else
515                 synchronize_irq(bp->pdev->irq);
516
517         /* make sure sp_task is not running */
518         cancel_work_sync(&bp->sp_task);
519
520 }
521
522 /* fast path code */
523
524 /*
525  * general service functions
526  */
527
528 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 id,
529                                 u8 storm, u16 index, u8 op, u8 update)
530 {
531         u32 igu_addr = (IGU_ADDR_INT_ACK + IGU_PORT_BASE * bp->port) * 8;
532         struct igu_ack_register igu_ack;
533
534         igu_ack.status_block_index = index;
535         igu_ack.sb_id_and_flags =
536                         ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
537                          (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
538                          (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
539                          (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
540
541 /*      DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
542            (*(u32 *)&igu_ack), BAR_IGU_INTMEM + igu_addr); */
543         REG_WR(bp, BAR_IGU_INTMEM + igu_addr, (*(u32 *)&igu_ack));
544 }
545
546 static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
547 {
548         struct host_status_block *fpsb = fp->status_blk;
549         u16 rc = 0;
550
551         barrier(); /* status block is written to by the chip */
552         if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) {
553                 fp->fp_c_idx = fpsb->c_status_block.status_block_index;
554                 rc |= 1;
555         }
556         if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) {
557                 fp->fp_u_idx = fpsb->u_status_block.status_block_index;
558                 rc |= 2;
559         }
560         return rc;
561 }
562
563 static inline int bnx2x_has_work(struct bnx2x_fastpath *fp)
564 {
565         u16 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
566
567         if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
568                 rx_cons_sb++;
569
570         if ((rx_cons_sb != fp->rx_comp_cons) ||
571             (le16_to_cpu(*fp->tx_cons_sb) != fp->tx_pkt_cons))
572                 return 1;
573
574         return 0;
575 }
576
577 static u16 bnx2x_ack_int(struct bnx2x *bp)
578 {
579         u32 igu_addr = (IGU_ADDR_SIMD_MASK + IGU_PORT_BASE * bp->port) * 8;
580         u32 result = REG_RD(bp, BAR_IGU_INTMEM + igu_addr);
581
582 /*      DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
583            result, BAR_IGU_INTMEM + igu_addr); */
584
585 #ifdef IGU_DEBUG
586 #warning IGU_DEBUG active
587         if (result == 0) {
588                 BNX2X_ERR("read %x from IGU\n", result);
589                 REG_WR(bp, TM_REG_TIMER_SOFT_RST, 0);
590         }
591 #endif
592         return result;
593 }
594
595
596 /*
597  * fast path service functions
598  */
599
600 /* free skb in the packet ring at pos idx
601  * return idx of last bd freed
602  */
603 static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
604                              u16 idx)
605 {
606         struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
607         struct eth_tx_bd *tx_bd;
608         struct sk_buff *skb = tx_buf->skb;
609         u16 bd_idx = tx_buf->first_bd;
610         int nbd;
611
612         DP(BNX2X_MSG_OFF, "pkt_idx %d  buff @(%p)->skb %p\n",
613            idx, tx_buf, skb);
614
615         /* unmap first bd */
616         DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
617         tx_bd = &fp->tx_desc_ring[bd_idx];
618         pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd),
619                          BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
620
621         nbd = le16_to_cpu(tx_bd->nbd) - 1;
622 #ifdef BNX2X_STOP_ON_ERROR
623         if (nbd > (MAX_SKB_FRAGS + 2)) {
624                 BNX2X_ERR("bad nbd!\n");
625                 bnx2x_panic();
626         }
627 #endif
628
629         /* Skip a parse bd and the TSO split header bd
630            since they have no mapping */
631         if (nbd)
632                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
633
634         if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM |
635                                            ETH_TX_BD_FLAGS_TCP_CSUM |
636                                            ETH_TX_BD_FLAGS_SW_LSO)) {
637                 if (--nbd)
638                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
639                 tx_bd = &fp->tx_desc_ring[bd_idx];
640                 /* is this a TSO split header bd? */
641                 if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) {
642                         if (--nbd)
643                                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
644                 }
645         }
646
647         /* now free frags */
648         while (nbd > 0) {
649
650                 DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
651                 tx_bd = &fp->tx_desc_ring[bd_idx];
652                 pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd),
653                                BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
654                 if (--nbd)
655                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
656         }
657
658         /* release skb */
659         BUG_TRAP(skb);
660         dev_kfree_skb(skb);
661         tx_buf->first_bd = 0;
662         tx_buf->skb = NULL;
663
664         return bd_idx;
665 }
666
667 static inline u32 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
668 {
669         u16 used;
670         u32 prod;
671         u32 cons;
672
673         /* Tell compiler that prod and cons can change */
674         barrier();
675         prod = fp->tx_bd_prod;
676         cons = fp->tx_bd_cons;
677
678         used = (NUM_TX_BD - NUM_TX_RINGS + prod - cons +
679                 (cons / TX_DESC_CNT) - (prod / TX_DESC_CNT));
680
681         if (prod >= cons) {
682                 /* used = prod - cons - prod/size + cons/size */
683                 used -= NUM_TX_BD - NUM_TX_RINGS;
684         }
685
686         BUG_TRAP(used <= fp->bp->tx_ring_size);
687         BUG_TRAP((fp->bp->tx_ring_size - used) <= MAX_TX_AVAIL);
688
689         return (fp->bp->tx_ring_size - used);
690 }
691
692 static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
693 {
694         struct bnx2x *bp = fp->bp;
695         u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
696         int done = 0;
697
698 #ifdef BNX2X_STOP_ON_ERROR
699         if (unlikely(bp->panic))
700                 return;
701 #endif
702
703         hw_cons = le16_to_cpu(*fp->tx_cons_sb);
704         sw_cons = fp->tx_pkt_cons;
705
706         while (sw_cons != hw_cons) {
707                 u16 pkt_cons;
708
709                 pkt_cons = TX_BD(sw_cons);
710
711                 /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */
712
713                 DP(NETIF_MSG_TX_DONE, "hw_cons %u  sw_cons %u  pkt_cons %d\n",
714                    hw_cons, sw_cons, pkt_cons);
715
716 /*              if (NEXT_TX_IDX(sw_cons) != hw_cons) {
717                         rmb();
718                         prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
719                 }
720 */
721                 bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
722                 sw_cons++;
723                 done++;
724
725                 if (done == work)
726                         break;
727         }
728
729         fp->tx_pkt_cons = sw_cons;
730         fp->tx_bd_cons = bd_cons;
731
732         /* Need to make the tx_cons update visible to start_xmit()
733          * before checking for netif_queue_stopped().  Without the
734          * memory barrier, there is a small possibility that start_xmit()
735          * will miss it and cause the queue to be stopped forever.
736          */
737         smp_mb();
738
739         /* TBD need a thresh? */
740         if (unlikely(netif_queue_stopped(bp->dev))) {
741
742                 netif_tx_lock(bp->dev);
743
744                 if (netif_queue_stopped(bp->dev) &&
745                     (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
746                         netif_wake_queue(bp->dev);
747
748                 netif_tx_unlock(bp->dev);
749
750         }
751 }
752
753 static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
754                            union eth_rx_cqe *rr_cqe)
755 {
756         struct bnx2x *bp = fp->bp;
757         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
758         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
759
760         DP(NETIF_MSG_RX_STATUS,
761            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
762            fp->index, cid, command, bp->state, rr_cqe->ramrod_cqe.type);
763
764         bp->spq_left++;
765
766         if (fp->index) {
767                 switch (command | fp->state) {
768                 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
769                                                 BNX2X_FP_STATE_OPENING):
770                         DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
771                            cid);
772                         fp->state = BNX2X_FP_STATE_OPEN;
773                         break;
774
775                 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
776                         DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
777                            cid);
778                         fp->state = BNX2X_FP_STATE_HALTED;
779                         break;
780
781                 default:
782                         BNX2X_ERR("unexpected MC reply(%d)  state is %x\n",
783                                   command, fp->state);
784                 }
785                 mb(); /* force bnx2x_wait_ramrod to see the change */
786                 return;
787         }
788
789         switch (command | bp->state) {
790         case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
791                 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
792                 bp->state = BNX2X_STATE_OPEN;
793                 break;
794
795         case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
796                 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
797                 bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
798                 fp->state = BNX2X_FP_STATE_HALTED;
799                 break;
800
801         case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
802                 DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n",
803                    cid);
804                 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
805                 break;
806
807         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
808                 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
809                 break;
810
811         case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
812                 DP(NETIF_MSG_IFUP, "got (un)set mac ramrod\n");
813                 break;
814
815         default:
816                 BNX2X_ERR("unexpected ramrod (%d)  state is %x\n",
817                           command, bp->state);
818         }
819
820         mb(); /* force bnx2x_wait_ramrod to see the change */
821 }
822
823 static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
824                                      struct bnx2x_fastpath *fp, u16 index)
825 {
826         struct sk_buff *skb;
827         struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
828         struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
829         dma_addr_t mapping;
830
831         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
832         if (unlikely(skb == NULL))
833                 return -ENOMEM;
834
835         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
836                                  PCI_DMA_FROMDEVICE);
837         if (unlikely(dma_mapping_error(mapping))) {
838
839                 dev_kfree_skb(skb);
840                 return -ENOMEM;
841         }
842
843         rx_buf->skb = skb;
844         pci_unmap_addr_set(rx_buf, mapping, mapping);
845
846         rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
847         rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
848
849         return 0;
850 }
851
852 /* note that we are not allocating a new skb,
853  * we are just moving one from cons to prod
854  * we are not creating a new mapping,
855  * so there is no need to check for dma_mapping_error().
856  */
857 static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
858                                struct sk_buff *skb, u16 cons, u16 prod)
859 {
860         struct bnx2x *bp = fp->bp;
861         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
862         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
863         struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
864         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
865
866         pci_dma_sync_single_for_device(bp->pdev,
867                                        pci_unmap_addr(cons_rx_buf, mapping),
868                                        bp->rx_offset + RX_COPY_THRESH,
869                                        PCI_DMA_FROMDEVICE);
870
871         prod_rx_buf->skb = cons_rx_buf->skb;
872         pci_unmap_addr_set(prod_rx_buf, mapping,
873                            pci_unmap_addr(cons_rx_buf, mapping));
874         *prod_bd = *cons_bd;
875 }
876
877 static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
878 {
879         struct bnx2x *bp = fp->bp;
880         u16 bd_cons, bd_prod, comp_ring_cons;
881         u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
882         int rx_pkt = 0;
883
884 #ifdef BNX2X_STOP_ON_ERROR
885         if (unlikely(bp->panic))
886                 return 0;
887 #endif
888
889         hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
890         if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
891                 hw_comp_cons++;
892
893         bd_cons = fp->rx_bd_cons;
894         bd_prod = fp->rx_bd_prod;
895         sw_comp_cons = fp->rx_comp_cons;
896         sw_comp_prod = fp->rx_comp_prod;
897
898         /* Memory barrier necessary as speculative reads of the rx
899          * buffer can be ahead of the index in the status block
900          */
901         rmb();
902
903         DP(NETIF_MSG_RX_STATUS,
904            "queue[%d]:  hw_comp_cons %u  sw_comp_cons %u\n",
905            fp->index, hw_comp_cons, sw_comp_cons);
906
907         while (sw_comp_cons != hw_comp_cons) {
908                 unsigned int len, pad;
909                 struct sw_rx_bd *rx_buf;
910                 struct sk_buff *skb;
911                 union eth_rx_cqe *cqe;
912
913                 comp_ring_cons = RCQ_BD(sw_comp_cons);
914                 bd_prod = RX_BD(bd_prod);
915                 bd_cons = RX_BD(bd_cons);
916
917                 cqe = &fp->rx_comp_ring[comp_ring_cons];
918
919                 DP(NETIF_MSG_RX_STATUS, "hw_comp_cons %u  sw_comp_cons %u"
920                    "  comp_ring (%u)  bd_ring (%u,%u)\n",
921                    hw_comp_cons, sw_comp_cons,
922                    comp_ring_cons, bd_prod, bd_cons);
923                 DP(NETIF_MSG_RX_STATUS, "CQE type %x  err %x  status %x"
924                    "  queue %x  vlan %x  len %x\n",
925                    cqe->fast_path_cqe.type,
926                    cqe->fast_path_cqe.error_type_flags,
927                    cqe->fast_path_cqe.status_flags,
928                    cqe->fast_path_cqe.rss_hash_result,
929                    cqe->fast_path_cqe.vlan_tag, cqe->fast_path_cqe.pkt_len);
930
931                 /* is this a slowpath msg? */
932                 if (unlikely(cqe->fast_path_cqe.type)) {
933                         bnx2x_sp_event(fp, cqe);
934                         goto next_cqe;
935
936                 /* this is an rx packet */
937                 } else {
938                         rx_buf = &fp->rx_buf_ring[bd_cons];
939                         skb = rx_buf->skb;
940
941                         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
942                         pad = cqe->fast_path_cqe.placement_offset;
943
944                         pci_dma_sync_single_for_device(bp->pdev,
945                                         pci_unmap_addr(rx_buf, mapping),
946                                                        pad + RX_COPY_THRESH,
947                                                        PCI_DMA_FROMDEVICE);
948                         prefetch(skb);
949                         prefetch(((char *)(skb)) + 128);
950
951                         /* is this an error packet? */
952                         if (unlikely(cqe->fast_path_cqe.error_type_flags &
953                                                         ETH_RX_ERROR_FALGS)) {
954                         /* do we sometimes forward error packets anyway? */
955                                 DP(NETIF_MSG_RX_ERR,
956                                    "ERROR flags(%u) Rx packet(%u)\n",
957                                    cqe->fast_path_cqe.error_type_flags,
958                                    sw_comp_cons);
959                                 /* TBD make sure MC counts this as a drop */
960                                 goto reuse_rx;
961                         }
962
963                         /* Since we don't have a jumbo ring
964                          * copy small packets if mtu > 1500
965                          */
966                         if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
967                             (len <= RX_COPY_THRESH)) {
968                                 struct sk_buff *new_skb;
969
970                                 new_skb = netdev_alloc_skb(bp->dev,
971                                                            len + pad);
972                                 if (new_skb == NULL) {
973                                         DP(NETIF_MSG_RX_ERR,
974                                            "ERROR packet dropped "
975                                            "because of alloc failure\n");
976                                         /* TBD count this as a drop? */
977                                         goto reuse_rx;
978                                 }
979
980                                 /* aligned copy */
981                                 skb_copy_from_linear_data_offset(skb, pad,
982                                                     new_skb->data + pad, len);
983                                 skb_reserve(new_skb, pad);
984                                 skb_put(new_skb, len);
985
986                                 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
987
988                                 skb = new_skb;
989
990                         } else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) {
991                                 pci_unmap_single(bp->pdev,
992                                         pci_unmap_addr(rx_buf, mapping),
993                                                  bp->rx_buf_use_size,
994                                                  PCI_DMA_FROMDEVICE);
995                                 skb_reserve(skb, pad);
996                                 skb_put(skb, len);
997
998                         } else {
999                                 DP(NETIF_MSG_RX_ERR,
1000                                    "ERROR packet dropped because "
1001                                    "of alloc failure\n");
1002 reuse_rx:
1003                                 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1004                                 goto next_rx;
1005                         }
1006
1007                         skb->protocol = eth_type_trans(skb, bp->dev);
1008
1009                         skb->ip_summed = CHECKSUM_NONE;
1010                         if (bp->rx_csum && BNX2X_RX_SUM_OK(cqe))
1011                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1012
1013                         /* TBD do we pass bad csum packets in promisc */
1014                 }
1015
1016 #ifdef BCM_VLAN
1017                 if ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags)
1018                                 & PARSING_FLAGS_NUMBER_OF_NESTED_VLANS)
1019                     && (bp->vlgrp != NULL))
1020                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1021                                 le16_to_cpu(cqe->fast_path_cqe.vlan_tag));
1022                 else
1023 #endif
1024                 netif_receive_skb(skb);
1025
1026                 bp->dev->last_rx = jiffies;
1027
1028 next_rx:
1029                 rx_buf->skb = NULL;
1030
1031                 bd_cons = NEXT_RX_IDX(bd_cons);
1032                 bd_prod = NEXT_RX_IDX(bd_prod);
1033 next_cqe:
1034                 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1035                 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1036                 rx_pkt++;
1037
1038                 if ((rx_pkt == budget))
1039                         break;
1040         } /* while */
1041
1042         fp->rx_bd_cons = bd_cons;
1043         fp->rx_bd_prod = bd_prod;
1044         fp->rx_comp_cons = sw_comp_cons;
1045         fp->rx_comp_prod = sw_comp_prod;
1046
1047         REG_WR(bp, BAR_TSTRORM_INTMEM +
1048                TSTORM_RCQ_PROD_OFFSET(bp->port, fp->index), sw_comp_prod);
1049
1050         mmiowb(); /* keep prod updates ordered */
1051
1052         fp->rx_pkt += rx_pkt;
1053         fp->rx_calls++;
1054
1055         return rx_pkt;
1056 }
1057
1058 static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1059 {
1060         struct bnx2x_fastpath *fp = fp_cookie;
1061         struct bnx2x *bp = fp->bp;
1062         struct net_device *dev = bp->dev;
1063         int index = fp->index;
1064
1065         DP(NETIF_MSG_INTR, "got an msix interrupt on [%d]\n", index);
1066         bnx2x_ack_sb(bp, index, USTORM_ID, 0, IGU_INT_DISABLE, 0);
1067
1068 #ifdef BNX2X_STOP_ON_ERROR
1069         if (unlikely(bp->panic))
1070                 return IRQ_HANDLED;
1071 #endif
1072
1073         prefetch(fp->rx_cons_sb);
1074         prefetch(fp->tx_cons_sb);
1075         prefetch(&fp->status_blk->c_status_block.status_block_index);
1076         prefetch(&fp->status_blk->u_status_block.status_block_index);
1077
1078         netif_rx_schedule(dev, &bnx2x_fp(bp, index, napi));
1079         return IRQ_HANDLED;
1080 }
1081
1082 static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1083 {
1084         struct net_device *dev = dev_instance;
1085         struct bnx2x *bp = netdev_priv(dev);
1086         u16 status = bnx2x_ack_int(bp);
1087
1088         if (unlikely(status == 0)) {
1089                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1090                 return IRQ_NONE;
1091         }
1092
1093         DP(NETIF_MSG_INTR, "got an interrupt status is %u\n", status);
1094
1095 #ifdef BNX2X_STOP_ON_ERROR
1096         if (unlikely(bp->panic))
1097                 return IRQ_HANDLED;
1098 #endif
1099
1100         /* Return here if interrupt is shared and is disabled */
1101         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1102                 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1103                 return IRQ_HANDLED;
1104         }
1105
1106         if (status & 0x2) {
1107                 struct bnx2x_fastpath *fp = &bp->fp[0];
1108
1109                 prefetch(fp->rx_cons_sb);
1110                 prefetch(fp->tx_cons_sb);
1111                 prefetch(&fp->status_blk->c_status_block.status_block_index);
1112                 prefetch(&fp->status_blk->u_status_block.status_block_index);
1113
1114                 netif_rx_schedule(dev, &bnx2x_fp(bp, 0, napi));
1115
1116                 status &= ~0x2;
1117                 if (!status)
1118                         return IRQ_HANDLED;
1119         }
1120
1121         if (unlikely(status & 0x1)) {
1122
1123                 schedule_work(&bp->sp_task);
1124
1125                 status &= ~0x1;
1126                 if (!status)
1127                         return IRQ_HANDLED;
1128         }
1129
1130         DP(NETIF_MSG_INTR, "got an unknown interrupt! (status is %u)\n",
1131            status);
1132
1133         return IRQ_HANDLED;
1134 }
1135
1136 /* end of fast path */
1137
1138 /* PHY/MAC */
1139
1140 /*
1141  * General service functions
1142  */
1143
1144 static void bnx2x_leds_set(struct bnx2x *bp, unsigned int speed)
1145 {
1146         int port = bp->port;
1147
1148         NIG_WR(NIG_REG_LED_MODE_P0 + port*4,
1149                ((bp->hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
1150                 SHARED_HW_CFG_LED_MODE_SHIFT));
1151         NIG_WR(NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
1152
1153         /* Set blinking rate to ~15.9Hz */
1154         NIG_WR(NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
1155                LED_BLINK_RATE_VAL);
1156         NIG_WR(NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port*4, 1);
1157
1158         /* On Ax chip versions for speeds less than 10G
1159            LED scheme is different */
1160         if ((CHIP_REV(bp) == CHIP_REV_Ax) && (speed < SPEED_10000)) {
1161                 NIG_WR(NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 1);
1162                 NIG_WR(NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4, 0);
1163                 NIG_WR(NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + port*4, 1);
1164         }
1165 }
1166
1167 static void bnx2x_leds_unset(struct bnx2x *bp)
1168 {
1169         int port = bp->port;
1170
1171         NIG_WR(NIG_REG_LED_10G_P0 + port*4, 0);
1172         NIG_WR(NIG_REG_LED_MODE_P0 + port*4, SHARED_HW_CFG_LED_MAC1);
1173 }
1174
1175 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
1176 {
1177         u32 val = REG_RD(bp, reg);
1178
1179         val |= bits;
1180         REG_WR(bp, reg, val);
1181         return val;
1182 }
1183
1184 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
1185 {
1186         u32 val = REG_RD(bp, reg);
1187
1188         val &= ~bits;
1189         REG_WR(bp, reg, val);
1190         return val;
1191 }
1192
1193 static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1194 {
1195         u32 cnt;
1196         u32 lock_status;
1197         u32 resource_bit = (1 << resource);
1198         u8 func = bp->port;
1199
1200         /* Validating that the resource is within range */
1201         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1202                 DP(NETIF_MSG_HW,
1203                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1204                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1205                 return -EINVAL;
1206         }
1207
1208         /* Validating that the resource is not already taken */
1209         lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8);
1210         if (lock_status & resource_bit) {
1211                 DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
1212                    lock_status, resource_bit);
1213                 return -EEXIST;
1214         }
1215
1216         /* Try for 1 second every 5ms */
1217         for (cnt = 0; cnt < 200; cnt++) {
1218                 /* Try to acquire the lock */
1219                 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + func*8 + 4,
1220                        resource_bit);
1221                 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8);
1222                 if (lock_status & resource_bit)
1223                         return 0;
1224
1225                 msleep(5);
1226         }
1227         DP(NETIF_MSG_HW, "Timeout\n");
1228         return -EAGAIN;
1229 }
1230
1231 static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource)
1232 {
1233         u32 lock_status;
1234         u32 resource_bit = (1 << resource);
1235         u8 func = bp->port;
1236
1237         /* Validating that the resource is within range */
1238         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1239                 DP(NETIF_MSG_HW,
1240                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1241                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1242                 return -EINVAL;
1243         }
1244
1245         /* Validating that the resource is currently taken */
1246         lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8);
1247         if (!(lock_status & resource_bit)) {
1248                 DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
1249                    lock_status, resource_bit);
1250                 return -EFAULT;
1251         }
1252
1253         REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + func*8, resource_bit);
1254         return 0;
1255 }
1256
1257 static int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
1258 {
1259         /* The GPIO should be swapped if swap register is set and active */
1260         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1261                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ bp->port;
1262         int gpio_shift = gpio_num +
1263                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1264         u32 gpio_mask = (1 << gpio_shift);
1265         u32 gpio_reg;
1266
1267         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1268                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1269                 return -EINVAL;
1270         }
1271
1272         bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1273         /* read GPIO and mask except the float bits */
1274         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1275
1276         switch (mode) {
1277         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1278                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1279                    gpio_num, gpio_shift);
1280                 /* clear FLOAT and set CLR */
1281                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1282                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1283                 break;
1284
1285         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1286                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1287                    gpio_num, gpio_shift);
1288                 /* clear FLOAT and set SET */
1289                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1290                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1291                 break;
1292
1293         case MISC_REGISTERS_GPIO_INPUT_HI_Z :
1294                 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1295                    gpio_num, gpio_shift);
1296                 /* set FLOAT */
1297                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1298                 break;
1299
1300         default:
1301                 break;
1302         }
1303
1304         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1305         bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_GPIO);
1306
1307         return 0;
1308 }
1309
1310 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1311 {
1312         u32 spio_mask = (1 << spio_num);
1313         u32 spio_reg;
1314
1315         if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1316             (spio_num > MISC_REGISTERS_SPIO_7)) {
1317                 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1318                 return -EINVAL;
1319         }
1320
1321         bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1322         /* read SPIO and mask except the float bits */
1323         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1324
1325         switch (mode) {
1326         case MISC_REGISTERS_SPIO_OUTPUT_LOW :
1327                 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1328                 /* clear FLOAT and set CLR */
1329                 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1330                 spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1331                 break;
1332
1333         case MISC_REGISTERS_SPIO_OUTPUT_HIGH :
1334                 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1335                 /* clear FLOAT and set SET */
1336                 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1337                 spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1338                 break;
1339
1340         case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1341                 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1342                 /* set FLOAT */
1343                 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1344                 break;
1345
1346         default:
1347                 break;
1348         }
1349
1350         REG_WR(bp, MISC_REG_SPIO, spio_reg);
1351         bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_SPIO);
1352
1353         return 0;
1354 }
1355
1356 static int bnx2x_mdio22_write(struct bnx2x *bp, u32 reg, u32 val)
1357 {
1358         int port = bp->port;
1359         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1360         u32 tmp;
1361         int i, rc;
1362
1363 /*      DP(NETIF_MSG_HW, "phy_addr 0x%x  reg 0x%x  val 0x%08x\n",
1364            bp->phy_addr, reg, val); */
1365
1366         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1367
1368                 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1369                 tmp &= ~EMAC_MDIO_MODE_AUTO_POLL;
1370                 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
1371                 REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1372                 udelay(40);
1373         }
1374
1375         tmp = ((bp->phy_addr << 21) | (reg << 16) |
1376                (val & EMAC_MDIO_COMM_DATA) |
1377                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
1378                EMAC_MDIO_COMM_START_BUSY);
1379         EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, tmp);
1380
1381         for (i = 0; i < 50; i++) {
1382                 udelay(10);
1383
1384                 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM);
1385                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1386                         udelay(5);
1387                         break;
1388                 }
1389         }
1390
1391         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1392                 BNX2X_ERR("write phy register failed\n");
1393
1394                 rc = -EBUSY;
1395         } else {
1396                 rc = 0;
1397         }
1398
1399         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1400
1401                 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1402                 tmp |= EMAC_MDIO_MODE_AUTO_POLL;
1403                 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
1404         }
1405
1406         return rc;
1407 }
1408
1409 static int bnx2x_mdio22_read(struct bnx2x *bp, u32 reg, u32 *ret_val)
1410 {
1411         int port = bp->port;
1412         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1413         u32 val;
1414         int i, rc;
1415
1416         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1417
1418                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1419                 val &= ~EMAC_MDIO_MODE_AUTO_POLL;
1420                 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
1421                 REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1422                 udelay(40);
1423         }
1424
1425         val = ((bp->phy_addr << 21) | (reg << 16) |
1426                EMAC_MDIO_COMM_COMMAND_READ_22 |
1427                EMAC_MDIO_COMM_START_BUSY);
1428         EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, val);
1429
1430         for (i = 0; i < 50; i++) {
1431                 udelay(10);
1432
1433                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM);
1434                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1435                         val &= EMAC_MDIO_COMM_DATA;
1436                         break;
1437                 }
1438         }
1439
1440         if (val & EMAC_MDIO_COMM_START_BUSY) {
1441                 BNX2X_ERR("read phy register failed\n");
1442
1443                 *ret_val = 0x0;
1444                 rc = -EBUSY;
1445         } else {
1446                 *ret_val = val;
1447                 rc = 0;
1448         }
1449
1450         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1451
1452                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1453                 val |= EMAC_MDIO_MODE_AUTO_POLL;
1454                 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
1455         }
1456
1457 /*      DP(NETIF_MSG_HW, "phy_addr 0x%x  reg 0x%x  ret_val 0x%08x\n",
1458            bp->phy_addr, reg, *ret_val); */
1459
1460         return rc;
1461 }
1462
1463 static int bnx2x_mdio45_ctrl_write(struct bnx2x *bp, u32 mdio_ctrl,
1464                                    u32 phy_addr, u32 reg, u32 addr, u32 val)
1465 {
1466         u32 tmp;
1467         int i, rc = 0;
1468
1469         /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
1470          * (a value of 49==0x31) and make sure that the AUTO poll is off
1471          */
1472         tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1473         tmp &= ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1474         tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
1475                 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1476         REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1477         REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1478         udelay(40);
1479
1480         /* address */
1481         tmp = ((phy_addr << 21) | (reg << 16) | addr |
1482                EMAC_MDIO_COMM_COMMAND_ADDRESS |
1483                EMAC_MDIO_COMM_START_BUSY);
1484         REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1485
1486         for (i = 0; i < 50; i++) {
1487                 udelay(10);
1488
1489                 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1490                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1491                         udelay(5);
1492                         break;
1493                 }
1494         }
1495         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1496                 BNX2X_ERR("write phy register failed\n");
1497
1498                 rc = -EBUSY;
1499
1500         } else {
1501                 /* data */
1502                 tmp = ((phy_addr << 21) | (reg << 16) | val |
1503                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
1504                        EMAC_MDIO_COMM_START_BUSY);
1505                 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1506
1507                 for (i = 0; i < 50; i++) {
1508                         udelay(10);
1509
1510                         tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1511                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1512                                 udelay(5);
1513                                 break;
1514                         }
1515                 }
1516
1517                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1518                         BNX2X_ERR("write phy register failed\n");
1519
1520                         rc = -EBUSY;
1521                 }
1522         }
1523
1524         /* unset clause 45 mode, set the MDIO clock to a faster value
1525          * (0x13 => 6.25Mhz) and restore the AUTO poll if needed
1526          */
1527         tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1528         tmp &= ~(EMAC_MDIO_MODE_CLAUSE_45 | EMAC_MDIO_MODE_CLOCK_CNT);
1529         tmp |= (0x13 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1530         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG)
1531                 tmp |= EMAC_MDIO_MODE_AUTO_POLL;
1532         REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1533
1534         return rc;
1535 }
1536
1537 static int bnx2x_mdio45_write(struct bnx2x *bp, u32 phy_addr, u32 reg,
1538                               u32 addr, u32 val)
1539 {
1540         u32 emac_base = bp->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1541
1542         return bnx2x_mdio45_ctrl_write(bp, emac_base, phy_addr,
1543                                        reg, addr, val);
1544 }
1545
1546 static int bnx2x_mdio45_ctrl_read(struct bnx2x *bp, u32 mdio_ctrl,
1547                                   u32 phy_addr, u32 reg, u32 addr,
1548                                   u32 *ret_val)
1549 {
1550         u32 val;
1551         int i, rc = 0;
1552
1553         /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
1554          * (a value of 49==0x31) and make sure that the AUTO poll is off
1555          */
1556         val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1557         val &= ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1558         val |= (EMAC_MDIO_MODE_CLAUSE_45 |
1559                 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1560         REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1561         REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1562         udelay(40);
1563
1564         /* address */
1565         val = ((phy_addr << 21) | (reg << 16) | addr |
1566                EMAC_MDIO_COMM_COMMAND_ADDRESS |
1567                EMAC_MDIO_COMM_START_BUSY);
1568         REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1569
1570         for (i = 0; i < 50; i++) {
1571                 udelay(10);
1572
1573                 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1574                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1575                         udelay(5);
1576                         break;
1577                 }
1578         }
1579         if (val & EMAC_MDIO_COMM_START_BUSY) {
1580                 BNX2X_ERR("read phy register failed\n");
1581
1582                 *ret_val = 0;
1583                 rc = -EBUSY;
1584
1585         } else {
1586                 /* data */
1587                 val = ((phy_addr << 21) | (reg << 16) |
1588                        EMAC_MDIO_COMM_COMMAND_READ_45 |
1589                        EMAC_MDIO_COMM_START_BUSY);
1590                 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1591
1592                 for (i = 0; i < 50; i++) {
1593                         udelay(10);
1594
1595                         val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1596                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1597                                 val &= EMAC_MDIO_COMM_DATA;
1598                                 break;
1599                         }
1600                 }
1601
1602                 if (val & EMAC_MDIO_COMM_START_BUSY) {
1603                         BNX2X_ERR("read phy register failed\n");
1604
1605                         val = 0;
1606                         rc = -EBUSY;
1607                 }
1608
1609                 *ret_val = val;
1610         }
1611
1612         /* unset clause 45 mode, set the MDIO clock to a faster value
1613          * (0x13 => 6.25Mhz) and restore the AUTO poll if needed
1614          */
1615         val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1616         val &= ~(EMAC_MDIO_MODE_CLAUSE_45 | EMAC_MDIO_MODE_CLOCK_CNT);
1617         val |= (0x13 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1618         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG)
1619                 val |= EMAC_MDIO_MODE_AUTO_POLL;
1620         REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1621
1622         return rc;
1623 }
1624
1625 static int bnx2x_mdio45_read(struct bnx2x *bp, u32 phy_addr, u32 reg,
1626                              u32 addr, u32 *ret_val)
1627 {
1628         u32 emac_base = bp->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1629
1630         return bnx2x_mdio45_ctrl_read(bp, emac_base, phy_addr,
1631                                       reg, addr, ret_val);
1632 }
1633
1634 static int bnx2x_mdio45_vwrite(struct bnx2x *bp, u32 phy_addr, u32 reg,
1635                                u32 addr, u32 val)
1636 {
1637         int i;
1638         u32 rd_val;
1639
1640         might_sleep();
1641         for (i = 0; i < 10; i++) {
1642                 bnx2x_mdio45_write(bp, phy_addr, reg, addr, val);
1643                 msleep(5);
1644                 bnx2x_mdio45_read(bp, phy_addr, reg, addr, &rd_val);
1645                 /* if the read value is not the same as the value we wrote,
1646                    we should write it again */
1647                 if (rd_val == val)
1648                         return 0;
1649         }
1650         BNX2X_ERR("MDIO write in CL45 failed\n");
1651         return -EBUSY;
1652 }
1653
1654 /*
1655  * link management
1656  */
1657
1658 static void bnx2x_pause_resolve(struct bnx2x *bp, u32 pause_result)
1659 {
1660         switch (pause_result) {                 /* ASYM P ASYM P */
1661         case 0xb:                               /*   1  0   1  1 */
1662                 bp->flow_ctrl = FLOW_CTRL_TX;
1663                 break;
1664
1665         case 0xe:                               /*   1  1   1  0 */
1666                 bp->flow_ctrl = FLOW_CTRL_RX;
1667                 break;
1668
1669         case 0x5:                               /*   0  1   0  1 */
1670         case 0x7:                               /*   0  1   1  1 */
1671         case 0xd:                               /*   1  1   0  1 */
1672         case 0xf:                               /*   1  1   1  1 */
1673                 bp->flow_ctrl = FLOW_CTRL_BOTH;
1674                 break;
1675
1676         default:
1677                 break;
1678         }
1679 }
1680
1681 static u8 bnx2x_ext_phy_resove_fc(struct bnx2x *bp)
1682 {
1683         u32 ext_phy_addr;
1684         u32 ld_pause;   /* local */
1685         u32 lp_pause;   /* link partner */
1686         u32 an_complete; /* AN complete */
1687         u32 pause_result;
1688         u8 ret = 0;
1689
1690         ext_phy_addr = ((bp->ext_phy_config &
1691                          PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1692                                         PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1693
1694         /* read twice */
1695         bnx2x_mdio45_read(bp, ext_phy_addr,
1696                           EXT_PHY_KR_AUTO_NEG_DEVAD,
1697                           EXT_PHY_KR_STATUS, &an_complete);
1698         bnx2x_mdio45_read(bp, ext_phy_addr,
1699                           EXT_PHY_KR_AUTO_NEG_DEVAD,
1700                           EXT_PHY_KR_STATUS, &an_complete);
1701
1702         if (an_complete & EXT_PHY_KR_AUTO_NEG_COMPLETE) {
1703                 ret = 1;
1704                 bnx2x_mdio45_read(bp, ext_phy_addr,
1705                                   EXT_PHY_KR_AUTO_NEG_DEVAD,
1706                                   EXT_PHY_KR_AUTO_NEG_ADVERT, &ld_pause);
1707                 bnx2x_mdio45_read(bp, ext_phy_addr,
1708                                   EXT_PHY_KR_AUTO_NEG_DEVAD,
1709                                   EXT_PHY_KR_LP_AUTO_NEG, &lp_pause);
1710                 pause_result = (ld_pause &
1711                                 EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK) >> 8;
1712                 pause_result |= (lp_pause &
1713                                  EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK) >> 10;
1714                 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n",
1715                    pause_result);
1716                 bnx2x_pause_resolve(bp, pause_result);
1717         }
1718         return ret;
1719 }
1720
1721 static void bnx2x_flow_ctrl_resolve(struct bnx2x *bp, u32 gp_status)
1722 {
1723         u32 ld_pause;   /* local driver */
1724         u32 lp_pause;   /* link partner */
1725         u32 pause_result;
1726
1727         bp->flow_ctrl = 0;
1728
1729         /* resolve from gp_status in case of AN complete and not sgmii */
1730         if ((bp->req_autoneg & AUTONEG_FLOW_CTRL) &&
1731             (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1732             (!(bp->phy_flags & PHY_SGMII_FLAG)) &&
1733             (XGXS_EXT_PHY_TYPE(bp) == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
1734
1735                 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
1736                 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1737                                   &ld_pause);
1738                 bnx2x_mdio22_read(bp,
1739                         MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1740                                   &lp_pause);
1741                 pause_result = (ld_pause &
1742                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
1743                 pause_result |= (lp_pause &
1744                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
1745                 DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result);
1746                 bnx2x_pause_resolve(bp, pause_result);
1747         } else if (!(bp->req_autoneg & AUTONEG_FLOW_CTRL) ||
1748                    !(bnx2x_ext_phy_resove_fc(bp))) {
1749                 /* forced speed */
1750                 if (bp->req_autoneg & AUTONEG_FLOW_CTRL) {
1751                         switch (bp->req_flow_ctrl) {
1752                         case FLOW_CTRL_AUTO:
1753                                 if (bp->dev->mtu <= 4500)
1754                                         bp->flow_ctrl = FLOW_CTRL_BOTH;
1755                                 else
1756                                         bp->flow_ctrl = FLOW_CTRL_TX;
1757                                 break;
1758
1759                         case FLOW_CTRL_TX:
1760                                 bp->flow_ctrl = FLOW_CTRL_TX;
1761                                 break;
1762
1763                         case FLOW_CTRL_RX:
1764                                 if (bp->dev->mtu <= 4500)
1765                                         bp->flow_ctrl = FLOW_CTRL_RX;
1766                                 break;
1767
1768                         case FLOW_CTRL_BOTH:
1769                                 if (bp->dev->mtu <= 4500)
1770                                         bp->flow_ctrl = FLOW_CTRL_BOTH;
1771                                 else
1772                                         bp->flow_ctrl = FLOW_CTRL_TX;
1773                                 break;
1774
1775                         case FLOW_CTRL_NONE:
1776                         default:
1777                                 break;
1778                         }
1779                 } else { /* forced mode */
1780                         switch (bp->req_flow_ctrl) {
1781                         case FLOW_CTRL_AUTO:
1782                                 DP(NETIF_MSG_LINK, "req_flow_ctrl 0x%x while"
1783                                                    " req_autoneg 0x%x\n",
1784                                    bp->req_flow_ctrl, bp->req_autoneg);
1785                                 break;
1786
1787                         case FLOW_CTRL_TX:
1788                         case FLOW_CTRL_RX:
1789                         case FLOW_CTRL_BOTH:
1790                                 bp->flow_ctrl = bp->req_flow_ctrl;
1791                                 break;
1792
1793                         case FLOW_CTRL_NONE:
1794                         default:
1795                                 break;
1796                         }
1797                 }
1798         }
1799         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", bp->flow_ctrl);
1800 }
1801
1802 static void bnx2x_link_settings_status(struct bnx2x *bp, u32 gp_status)
1803 {
1804         bp->link_status = 0;
1805
1806         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1807                 DP(NETIF_MSG_LINK, "phy link up\n");
1808
1809                 bp->phy_link_up = 1;
1810                 bp->link_status |= LINK_STATUS_LINK_UP;
1811
1812                 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
1813                         bp->duplex = DUPLEX_FULL;
1814                 else
1815                         bp->duplex = DUPLEX_HALF;
1816
1817                 bnx2x_flow_ctrl_resolve(bp, gp_status);
1818
1819                 switch (gp_status & GP_STATUS_SPEED_MASK) {
1820                 case GP_STATUS_10M:
1821                         bp->line_speed = SPEED_10;
1822                         if (bp->duplex == DUPLEX_FULL)
1823                                 bp->link_status |= LINK_10TFD;
1824                         else
1825                                 bp->link_status |= LINK_10THD;
1826                         break;
1827
1828                 case GP_STATUS_100M:
1829                         bp->line_speed = SPEED_100;
1830                         if (bp->duplex == DUPLEX_FULL)
1831                                 bp->link_status |= LINK_100TXFD;
1832                         else
1833                                 bp->link_status |= LINK_100TXHD;
1834                         break;
1835
1836                 case GP_STATUS_1G:
1837                 case GP_STATUS_1G_KX:
1838                         bp->line_speed = SPEED_1000;
1839                         if (bp->duplex == DUPLEX_FULL)
1840                                 bp->link_status |= LINK_1000TFD;
1841                         else
1842                                 bp->link_status |= LINK_1000THD;
1843                         break;
1844
1845                 case GP_STATUS_2_5G:
1846                         bp->line_speed = SPEED_2500;
1847                         if (bp->duplex == DUPLEX_FULL)
1848                                 bp->link_status |= LINK_2500TFD;
1849                         else
1850                                 bp->link_status |= LINK_2500THD;
1851                         break;
1852
1853                 case GP_STATUS_5G:
1854                 case GP_STATUS_6G:
1855                         BNX2X_ERR("link speed unsupported  gp_status 0x%x\n",
1856                                   gp_status);
1857                         break;
1858
1859                 case GP_STATUS_10G_KX4:
1860                 case GP_STATUS_10G_HIG:
1861                 case GP_STATUS_10G_CX4:
1862                         bp->line_speed = SPEED_10000;
1863                         bp->link_status |= LINK_10GTFD;
1864                         break;
1865
1866                 case GP_STATUS_12G_HIG:
1867                         bp->line_speed = SPEED_12000;
1868                         bp->link_status |= LINK_12GTFD;
1869                         break;
1870
1871                 case GP_STATUS_12_5G:
1872                         bp->line_speed = SPEED_12500;
1873                         bp->link_status |= LINK_12_5GTFD;
1874                         break;
1875
1876                 case GP_STATUS_13G:
1877                         bp->line_speed = SPEED_13000;
1878                         bp->link_status |= LINK_13GTFD;
1879                         break;
1880
1881                 case GP_STATUS_15G:
1882                         bp->line_speed = SPEED_15000;
1883                         bp->link_status |= LINK_15GTFD;
1884                         break;
1885
1886                 case GP_STATUS_16G:
1887                         bp->line_speed = SPEED_16000;
1888                         bp->link_status |= LINK_16GTFD;
1889                         break;
1890
1891                 default:
1892                         BNX2X_ERR("link speed unsupported  gp_status 0x%x\n",
1893                                   gp_status);
1894                         break;
1895                 }
1896
1897                 bp->link_status |= LINK_STATUS_SERDES_LINK;
1898
1899                 if (bp->req_autoneg & AUTONEG_SPEED) {
1900                         bp->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
1901
1902                         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
1903                                 bp->link_status |=
1904                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
1905
1906                         if (bp->autoneg & AUTONEG_PARALLEL)
1907                                 bp->link_status |=
1908                                         LINK_STATUS_PARALLEL_DETECTION_USED;
1909                 }
1910
1911                 if (bp->flow_ctrl & FLOW_CTRL_TX)
1912                        bp->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
1913
1914                 if (bp->flow_ctrl & FLOW_CTRL_RX)
1915                        bp->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
1916
1917         } else { /* link_down */
1918                 DP(NETIF_MSG_LINK, "phy link down\n");
1919
1920                 bp->phy_link_up = 0;
1921
1922                 bp->line_speed = 0;
1923                 bp->duplex = DUPLEX_FULL;
1924                 bp->flow_ctrl = 0;
1925         }
1926
1927         DP(NETIF_MSG_LINK, "gp_status 0x%x  phy_link_up %d\n"
1928            DP_LEVEL "  line_speed %d  duplex %d  flow_ctrl 0x%x"
1929                     "  link_status 0x%x\n",
1930            gp_status, bp->phy_link_up, bp->line_speed, bp->duplex,
1931            bp->flow_ctrl, bp->link_status);
1932 }
1933
1934 static void bnx2x_link_int_ack(struct bnx2x *bp, int is_10g)
1935 {
1936         int port = bp->port;
1937
1938         /* first reset all status
1939          * we assume only one line will be change at a time */
1940         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1941                        (NIG_STATUS_XGXS0_LINK10G |
1942                         NIG_STATUS_XGXS0_LINK_STATUS |
1943                         NIG_STATUS_SERDES0_LINK_STATUS));
1944         if (bp->phy_link_up) {
1945                 if (is_10g) {
1946                         /* Disable the 10G link interrupt
1947                          * by writing 1 to the status register
1948                          */
1949                         DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
1950                         bnx2x_bits_en(bp,
1951                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1952                                       NIG_STATUS_XGXS0_LINK10G);
1953
1954                 } else if (bp->phy_flags & PHY_XGXS_FLAG) {
1955                         /* Disable the link interrupt
1956                          * by writing 1 to the relevant lane
1957                          * in the status register
1958                          */
1959                         DP(NETIF_MSG_LINK, "1G XGXS phy link up\n");
1960                         bnx2x_bits_en(bp,
1961                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1962                                       ((1 << bp->ser_lane) <<
1963                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
1964
1965                 } else { /* SerDes */
1966                         DP(NETIF_MSG_LINK, "SerDes phy link up\n");
1967                         /* Disable the link interrupt
1968                          * by writing 1 to the status register
1969                          */
1970                         bnx2x_bits_en(bp,
1971                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1972                                       NIG_STATUS_SERDES0_LINK_STATUS);
1973                 }
1974
1975         } else { /* link_down */
1976         }
1977 }
1978
1979 static int bnx2x_ext_phy_is_link_up(struct bnx2x *bp)
1980 {
1981         u32 ext_phy_type;
1982         u32 ext_phy_addr;
1983         u32 val1 = 0, val2;
1984         u32 rx_sd, pcs_status;
1985
1986         if (bp->phy_flags & PHY_XGXS_FLAG) {
1987                 ext_phy_addr = ((bp->ext_phy_config &
1988                                  PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1989                                 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1990
1991                 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
1992                 switch (ext_phy_type) {
1993                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
1994                         DP(NETIF_MSG_LINK, "XGXS Direct\n");
1995                         val1 = 1;
1996                         break;
1997
1998                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
1999                         DP(NETIF_MSG_LINK, "XGXS 8705\n");
2000                         bnx2x_mdio45_read(bp, ext_phy_addr,
2001                                           EXT_PHY_OPT_WIS_DEVAD,
2002                                           EXT_PHY_OPT_LASI_STATUS, &val1);
2003                         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
2004
2005                         bnx2x_mdio45_read(bp, ext_phy_addr,
2006                                           EXT_PHY_OPT_WIS_DEVAD,
2007                                           EXT_PHY_OPT_LASI_STATUS, &val1);
2008                         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
2009
2010                         bnx2x_mdio45_read(bp, ext_phy_addr,
2011                                           EXT_PHY_OPT_PMA_PMD_DEVAD,
2012                                           EXT_PHY_OPT_PMD_RX_SD, &rx_sd);
2013                         DP(NETIF_MSG_LINK, "8705 rx_sd 0x%x\n", rx_sd);
2014                         val1 = (rx_sd & 0x1);
2015                         break;
2016
2017                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
2018                         DP(NETIF_MSG_LINK, "XGXS 8706\n");
2019                         bnx2x_mdio45_read(bp, ext_phy_addr,
2020                                           EXT_PHY_OPT_PMA_PMD_DEVAD,
2021                                           EXT_PHY_OPT_LASI_STATUS, &val1);
2022                         DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1);
2023
2024                         bnx2x_mdio45_read(bp, ext_phy_addr,
2025                                           EXT_PHY_OPT_PMA_PMD_DEVAD,
2026                                           EXT_PHY_OPT_LASI_STATUS, &val1);
2027                         DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1);
2028
2029                         bnx2x_mdio45_read(bp, ext_phy_addr,
2030                                           EXT_PHY_OPT_PMA_PMD_DEVAD,
2031                                           EXT_PHY_OPT_PMD_RX_SD, &rx_sd);
2032                         bnx2x_mdio45_read(bp, ext_phy_addr,
2033                                           EXT_PHY_OPT_PCS_DEVAD,
2034                                           EXT_PHY_OPT_PCS_STATUS, &pcs_status);
2035                         bnx2x_mdio45_read(bp, ext_phy_addr,
2036                                           EXT_PHY_AUTO_NEG_DEVAD,
2037                                           EXT_PHY_OPT_AN_LINK_STATUS, &val2);
2038
2039                         DP(NETIF_MSG_LINK, "8706 rx_sd 0x%x"
2040                            "  pcs_status 0x%x 1Gbps link_status 0x%x 0x%x\n",
2041                            rx_sd, pcs_status, val2, (val2 & (1<<1)));
2042                         /* link is up if both bit 0 of pmd_rx_sd and
2043                          * bit 0 of pcs_status are set, or if the autoneg bit
2044                            1 is set
2045                          */
2046                         val1 = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
2047                         break;
2048
2049                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
2050                         bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
2051
2052                         /* clear the interrupt LASI status register */
2053                         bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2054                                                ext_phy_addr,
2055                                                EXT_PHY_KR_PCS_DEVAD,
2056                                                EXT_PHY_KR_LASI_STATUS, &val2);
2057                         bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2058                                                ext_phy_addr,
2059                                                EXT_PHY_KR_PCS_DEVAD,
2060                                                EXT_PHY_KR_LASI_STATUS, &val1);
2061                         DP(NETIF_MSG_LINK, "KR LASI status 0x%x->0x%x\n",
2062                            val2, val1);
2063                         /* Check the LASI */
2064                         bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2065                                                ext_phy_addr,
2066                                                EXT_PHY_KR_PMA_PMD_DEVAD,
2067                                                0x9003, &val2);
2068                         bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2069                                                ext_phy_addr,
2070                                                EXT_PHY_KR_PMA_PMD_DEVAD,
2071                                                0x9003, &val1);
2072                         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x->0x%x\n",
2073                            val2, val1);
2074                         /* Check the link status */
2075                         bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2076                                                ext_phy_addr,
2077                                                EXT_PHY_KR_PCS_DEVAD,
2078                                                EXT_PHY_KR_PCS_STATUS, &val2);
2079                         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
2080                         /* Check the link status on 1.1.2 */
2081                         bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2082                                           ext_phy_addr,
2083                                           EXT_PHY_OPT_PMA_PMD_DEVAD,
2084                                           EXT_PHY_KR_STATUS, &val2);
2085                         bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2086                                           ext_phy_addr,
2087                                           EXT_PHY_OPT_PMA_PMD_DEVAD,
2088                                           EXT_PHY_KR_STATUS, &val1);
2089                         DP(NETIF_MSG_LINK,
2090                            "KR PMA status 0x%x->0x%x\n", val2, val1);
2091                         val1 = ((val1 & 4) == 4);
2092                         /* If 1G was requested assume the link is up */
2093                         if (!(bp->req_autoneg & AUTONEG_SPEED) &&
2094                             (bp->req_line_speed == SPEED_1000))
2095                                 val1 = 1;
2096                         bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
2097                         break;
2098
2099                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
2100                         bnx2x_mdio45_read(bp, ext_phy_addr,
2101                                           EXT_PHY_OPT_PMA_PMD_DEVAD,
2102                                           EXT_PHY_OPT_LASI_STATUS, &val2);
2103                         bnx2x_mdio45_read(bp, ext_phy_addr,
2104                                           EXT_PHY_OPT_PMA_PMD_DEVAD,
2105                                           EXT_PHY_OPT_LASI_STATUS, &val1);
2106                         DP(NETIF_MSG_LINK,
2107                            "10G-base-T LASI status 0x%x->0x%x\n", val2, val1);
2108                         bnx2x_mdio45_read(bp, ext_phy_addr,
2109                                           EXT_PHY_OPT_PMA_PMD_DEVAD,
2110                                           EXT_PHY_KR_STATUS, &val2);
2111                         bnx2x_mdio45_read(bp, ext_phy_addr,
2112                                           EXT_PHY_OPT_PMA_PMD_DEVAD,
2113                                           EXT_PHY_KR_STATUS, &val1);
2114                         DP(NETIF_MSG_LINK,
2115                            "10G-base-T PMA status 0x%x->0x%x\n", val2, val1);
2116                         val1 = ((val1 & 4) == 4);
2117                         /* if link is up
2118                          * print the AN outcome of the SFX7101 PHY
2119                          */
2120                         if (val1) {
2121                                 bnx2x_mdio45_read(bp, ext_phy_addr,
2122                                                   EXT_PHY_KR_AUTO_NEG_DEVAD,
2123                                                   0x21, &val2);
2124                                 DP(NETIF_MSG_LINK,
2125                                    "SFX7101 AN status 0x%x->%s\n", val2,
2126                                    (val2 & (1<<14)) ? "Master" : "Slave");
2127                         }
2128                         break;
2129
2130                 default:
2131                         DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
2132                            bp->ext_phy_config);
2133                         val1 = 0;
2134                         break;
2135                 }
2136
2137         } else { /* SerDes */
2138                 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
2139                 switch (ext_phy_type) {
2140                 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
2141                         DP(NETIF_MSG_LINK, "SerDes Direct\n");
2142                         val1 = 1;
2143                         break;
2144
2145                 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
2146                         DP(NETIF_MSG_LINK, "SerDes 5482\n");
2147                         val1 = 1;
2148                         break;
2149
2150                 default:
2151                         DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
2152                            bp->ext_phy_config);
2153                         val1 = 0;
2154                         break;
2155                 }
2156         }
2157
2158         return val1;
2159 }
2160
2161 static void bnx2x_bmac_enable(struct bnx2x *bp, int is_lb)
2162 {
2163         int port = bp->port;
2164         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2165                                NIG_REG_INGRESS_BMAC0_MEM;
2166         u32 wb_write[2];
2167         u32 val;
2168
2169         DP(NETIF_MSG_LINK, "enabling BigMAC\n");
2170         /* reset and unreset the BigMac */
2171         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2172                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2173         msleep(5);
2174         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2175                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2176
2177         /* enable access for bmac registers */
2178         NIG_WR(NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2179
2180         /* XGXS control */
2181         wb_write[0] = 0x3c;
2182         wb_write[1] = 0;
2183         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2184                     wb_write, 2);
2185
2186         /* tx MAC SA */
2187         wb_write[0] = ((bp->dev->dev_addr[2] << 24) |
2188                        (bp->dev->dev_addr[3] << 16) |
2189                        (bp->dev->dev_addr[4] << 8) |
2190                         bp->dev->dev_addr[5]);
2191         wb_write[1] = ((bp->dev->dev_addr[0] << 8) |
2192                         bp->dev->dev_addr[1]);
2193         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
2194                     wb_write, 2);
2195
2196         /* tx control */
2197         val = 0xc0;
2198         if (bp->flow_ctrl & FLOW_CTRL_TX)
2199                 val |= 0x800000;
2200         wb_write[0] = val;
2201         wb_write[1] = 0;
2202         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_write, 2);
2203
2204         /* set tx mtu */
2205         wb_write[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; /* -CRC */
2206         wb_write[1] = 0;
2207         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_write, 2);
2208
2209         /* mac control */
2210         val = 0x3;
2211         if (is_lb) {
2212                 val |= 0x4;
2213                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2214         }
2215         wb_write[0] = val;
2216         wb_write[1] = 0;
2217         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
2218                     wb_write, 2);
2219
2220         /* rx control set to don't strip crc */
2221         val = 0x14;
2222         if (bp->flow_ctrl & FLOW_CTRL_RX)
2223                 val |= 0x20;
2224         wb_write[0] = val;
2225         wb_write[1] = 0;
2226         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_write, 2);
2227
2228         /* set rx mtu */
2229         wb_write[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2230         wb_write[1] = 0;
2231         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_write, 2);
2232
2233         /* set cnt max size */
2234         wb_write[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; /* -VLAN */
2235         wb_write[1] = 0;
2236         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
2237                     wb_write, 2);
2238
2239         /* configure safc */
2240         wb_write[0] = 0x1000200;
2241         wb_write[1] = 0;
2242         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2243                     wb_write, 2);
2244
2245         /* fix for emulation */
2246         if (CHIP_REV(bp) == CHIP_REV_EMUL) {
2247                 wb_write[0] = 0xf000;
2248                 wb_write[1] = 0;
2249                 REG_WR_DMAE(bp,
2250                             bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
2251                             wb_write, 2);
2252         }
2253
2254         /* reset old bmac stats */
2255         memset(&bp->old_bmac, 0, sizeof(struct bmac_stats));
2256
2257         NIG_WR(NIG_REG_XCM0_OUT_EN + port*4, 0x0);
2258
2259         /* select XGXS */
2260         NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2261         NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2262
2263         /* disable the NIG in/out to the emac */
2264         NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2265         NIG_WR(NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2266         NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2267
2268         /* enable the NIG in/out to the bmac */
2269         NIG_WR(NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2270
2271         NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2272         val = 0;
2273         if (bp->flow_ctrl & FLOW_CTRL_TX)
2274                 val = 1;
2275         NIG_WR(NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2276         NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2277
2278         bp->phy_flags |= PHY_BMAC_FLAG;
2279
2280         bp->stats_state = STATS_STATE_ENABLE;
2281 }
2282
2283 static void bnx2x_bmac_rx_disable(struct bnx2x *bp)
2284 {
2285         int port = bp->port;
2286         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2287                                NIG_REG_INGRESS_BMAC0_MEM;
2288         u32 wb_write[2];
2289
2290         /* Only if the bmac is out of reset */
2291         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2292                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)) {
2293                 /* Clear Rx Enable bit in BMAC_CONTROL register */
2294 #ifdef BNX2X_DMAE_RD
2295                 bnx2x_read_dmae(bp, bmac_addr +
2296                                 BIGMAC_REGISTER_BMAC_CONTROL, 2);
2297                 wb_write[0] = *bnx2x_sp(bp, wb_data[0]);
2298                 wb_write[1] = *bnx2x_sp(bp, wb_data[1]);
2299 #else
2300                 wb_write[0] = REG_RD(bp,
2301                                 bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL);
2302                 wb_write[1] = REG_RD(bp,
2303                                 bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL + 4);
2304 #endif
2305                 wb_write[0] &= ~BMAC_CONTROL_RX_ENABLE;
2306                 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
2307                             wb_write, 2);
2308                 msleep(1);
2309         }
2310 }
2311
2312 static void bnx2x_emac_enable(struct bnx2x *bp)
2313 {
2314         int port = bp->port;
2315         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2316         u32 val;
2317         int timeout;
2318
2319         DP(NETIF_MSG_LINK, "enabling EMAC\n");
2320         /* reset and unreset the emac core */
2321         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2322                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2323         msleep(5);
2324         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2325                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2326
2327         /* enable emac and not bmac */
2328         NIG_WR(NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
2329
2330         /* for paladium */
2331         if (CHIP_REV(bp) == CHIP_REV_EMUL) {
2332                 /* Use lane 1 (of lanes 0-3) */
2333                 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2334                 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2335         }
2336         /* for fpga */
2337         else if (CHIP_REV(bp) == CHIP_REV_FPGA) {
2338                 /* Use lane 1 (of lanes 0-3) */
2339                 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2340                 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2341         }
2342         /* ASIC */
2343         else {
2344                 if (bp->phy_flags & PHY_XGXS_FLAG) {
2345                         DP(NETIF_MSG_LINK, "XGXS\n");
2346                         /* select the master lanes (out of 0-3) */
2347                         NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4,
2348                                bp->ser_lane);
2349                         /* select XGXS */
2350                         NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2351
2352                 } else { /* SerDes */
2353                         DP(NETIF_MSG_LINK, "SerDes\n");
2354                         /* select SerDes */
2355                         NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2356                 }
2357         }
2358
2359         /* enable emac */
2360         NIG_WR(NIG_REG_NIG_EMAC0_EN + port*4, 1);
2361
2362         /* init emac - use read-modify-write */
2363         /* self clear reset */
2364         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2365         EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
2366
2367         timeout = 200;
2368         while (val & EMAC_MODE_RESET) {
2369                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2370                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
2371                 if (!timeout) {
2372                         BNX2X_ERR("EMAC timeout!\n");
2373                         break;
2374                 }
2375                 timeout--;
2376         }
2377
2378         /* reset tx part */
2379         EMAC_WR(EMAC_REG_EMAC_TX_MODE, EMAC_TX_MODE_RESET);
2380
2381         timeout = 200;
2382         while (val & EMAC_TX_MODE_RESET) {
2383                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_TX_MODE);
2384                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
2385                 if (!timeout) {
2386                         BNX2X_ERR("EMAC timeout!\n");
2387                         break;
2388                 }
2389                 timeout--;
2390         }
2391
2392         if (CHIP_REV_IS_SLOW(bp)) {
2393                 /* config GMII mode */
2394                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2395                 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
2396
2397         } else { /* ASIC */
2398                 /* pause enable/disable */
2399                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
2400                                EMAC_RX_MODE_FLOW_EN);
2401                 if (bp->flow_ctrl & FLOW_CTRL_RX)
2402                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
2403                                       EMAC_RX_MODE_FLOW_EN);
2404
2405                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
2406                                EMAC_TX_MODE_EXT_PAUSE_EN);
2407                 if (bp->flow_ctrl & FLOW_CTRL_TX)
2408                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
2409                                       EMAC_TX_MODE_EXT_PAUSE_EN);
2410         }
2411
2412         /* KEEP_VLAN_TAG, promiscuous */
2413         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
2414         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
2415         EMAC_WR(EMAC_REG_EMAC_RX_MODE, val);
2416
2417         /* identify magic packets */
2418         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2419         EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_MPKT));
2420
2421         /* enable emac for jumbo packets */
2422         EMAC_WR(EMAC_REG_EMAC_RX_MTU_SIZE,
2423                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
2424                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); /* -VLAN */
2425
2426         /* strip CRC */
2427         NIG_WR(NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
2428
2429         val = ((bp->dev->dev_addr[0] << 8) |
2430                 bp->dev->dev_addr[1]);
2431         EMAC_WR(EMAC_REG_EMAC_MAC_MATCH, val);
2432
2433         val = ((bp->dev->dev_addr[2] << 24) |
2434                (bp->dev->dev_addr[3] << 16) |
2435                (bp->dev->dev_addr[4] << 8) |
2436                 bp->dev->dev_addr[5]);
2437         EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val);
2438
2439         /* disable the NIG in/out to the bmac */
2440         NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0x0);
2441         NIG_WR(NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
2442         NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
2443
2444         /* enable the NIG in/out to the emac */
2445         NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0x1);
2446         val = 0;
2447         if (bp->flow_ctrl & FLOW_CTRL_TX)
2448                 val = 1;
2449         NIG_WR(NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
2450         NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
2451
2452         if (CHIP_REV(bp) == CHIP_REV_FPGA) {
2453                 /* take the BigMac out of reset */
2454                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2455                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2456
2457                 /* enable access for bmac registers */
2458                 NIG_WR(NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2459         }
2460
2461         bp->phy_flags |= PHY_EMAC_FLAG;
2462
2463         bp->stats_state = STATS_STATE_ENABLE;
2464 }
2465
2466 static void bnx2x_emac_program(struct bnx2x *bp)
2467 {
2468         u16 mode = 0;
2469         int port = bp->port;
2470
2471         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2472         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2473                        (EMAC_MODE_25G_MODE |
2474                         EMAC_MODE_PORT_MII_10M |
2475                         EMAC_MODE_HALF_DUPLEX));
2476         switch (bp->line_speed) {
2477         case SPEED_10:
2478                 mode |= EMAC_MODE_PORT_MII_10M;
2479                 break;
2480
2481         case SPEED_100:
2482                 mode |= EMAC_MODE_PORT_MII;
2483                 break;
2484
2485         case SPEED_1000:
2486                 mode |= EMAC_MODE_PORT_GMII;
2487                 break;
2488
2489         case SPEED_2500:
2490                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2491                 break;
2492
2493         default:
2494                 /* 10G not valid for EMAC */
2495                 BNX2X_ERR("Invalid line_speed 0x%x\n", bp->line_speed);
2496                 break;
2497         }
2498
2499         if (bp->duplex == DUPLEX_HALF)
2500                 mode |= EMAC_MODE_HALF_DUPLEX;
2501         bnx2x_bits_en(bp, GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2502                       mode);
2503
2504         bnx2x_leds_set(bp, bp->line_speed);
2505 }
2506
2507 static void bnx2x_set_sgmii_tx_driver(struct bnx2x *bp)
2508 {
2509         u32 lp_up2;
2510         u32 tx_driver;
2511
2512         /* read precomp */
2513         MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_OVER_1G);
2514         bnx2x_mdio22_read(bp, MDIO_OVER_1G_LP_UP2, &lp_up2);
2515
2516         MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_TX0);
2517         bnx2x_mdio22_read(bp, MDIO_TX0_TX_DRIVER, &tx_driver);
2518
2519         /* bits [10:7] at lp_up2, positioned at [15:12] */
2520         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2521                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2522                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2523
2524         if ((lp_up2 != 0) &&
2525             (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK))) {
2526                 /* replace tx_driver bits [15:12] */
2527                 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2528                 tx_driver |= lp_up2;
2529                 bnx2x_mdio22_write(bp, MDIO_TX0_TX_DRIVER, tx_driver);
2530         }
2531 }
2532
2533 static void bnx2x_pbf_update(struct bnx2x *bp)
2534 {
2535         int port = bp->port;
2536         u32 init_crd, crd;
2537         u32 count = 1000;
2538         u32 pause = 0;
2539
2540         /* disable port */
2541         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2542
2543         /* wait for init credit */
2544         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2545         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2546         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2547
2548         while ((init_crd != crd) && count) {
2549                 msleep(5);
2550
2551                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2552                 count--;
2553         }
2554         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2555         if (init_crd != crd)
2556                 BNX2X_ERR("BUG! init_crd 0x%x != crd 0x%x\n", init_crd, crd);
2557
2558         if (bp->flow_ctrl & FLOW_CTRL_RX)
2559                 pause = 1;
2560         REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, pause);
2561         if (pause) {
2562                 /* update threshold */
2563                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2564                 /* update init credit */
2565                 init_crd = 778;         /* (800-18-4) */
2566
2567         } else {
2568                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)/16;
2569
2570                 /* update threshold */
2571                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2572                 /* update init credit */
2573                 switch (bp->line_speed) {
2574                 case SPEED_10:
2575                 case SPEED_100:
2576                 case SPEED_1000:
2577                         init_crd = thresh + 55 - 22;
2578                         break;
2579
2580                 case SPEED_2500:
2581                         init_crd = thresh + 138 - 22;
2582                         break;
2583
2584                 case SPEED_10000:
2585                         init_crd = thresh + 553 - 22;
2586                         break;
2587
2588                 default:
2589                         BNX2X_ERR("Invalid line_speed 0x%x\n",
2590                                   bp->line_speed);
2591                         break;
2592                 }
2593         }
2594         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2595         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2596            bp->line_speed, init_crd);
2597
2598         /* probe the credit changes */
2599         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2600         msleep(5);
2601         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2602
2603         /* enable port */
2604         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2605 }
2606
2607 static void bnx2x_update_mng(struct bnx2x *bp)
2608 {
2609         if (!nomcp)
2610                 SHMEM_WR(bp, port_mb[bp->port].link_status,
2611                          bp->link_status);
2612 }
2613
2614 static void bnx2x_link_report(struct bnx2x *bp)
2615 {
2616         if (bp->link_up) {
2617                 netif_carrier_on(bp->dev);
2618                 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
2619
2620                 printk("%d Mbps ", bp->line_speed);
2621
2622                 if (bp->duplex == DUPLEX_FULL)
2623                         printk("full duplex");
2624                 else
2625                         printk("half duplex");
2626
2627                 if (bp->flow_ctrl) {
2628                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
2629                                 printk(", receive ");
2630                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
2631                                         printk("& transmit ");
2632                         } else {
2633                                 printk(", transmit ");
2634                         }
2635                         printk("flow control ON");
2636                 }
2637                 printk("\n");
2638
2639         } else { /* link_down */
2640                 netif_carrier_off(bp->dev);
2641                 printk(KERN_INFO PFX "%s NIC Link is Down\n", bp->dev->name);
2642         }
2643 }
2644
2645 static void bnx2x_link_up(struct bnx2x *bp)
2646 {
2647         int port = bp->port;
2648
2649         /* PBF - link up */
2650         bnx2x_pbf_update(bp);
2651
2652         /* disable drain */
2653         NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
2654
2655         /* update shared memory */
2656         bnx2x_update_mng(bp);
2657
2658         /* indicate link up */
2659         bnx2x_link_report(bp);
2660 }
2661
2662 static void bnx2x_link_down(struct bnx2x *bp)
2663 {
2664         int port = bp->port;
2665
2666         /* notify stats */
2667         if (bp->stats_state != STATS_STATE_DISABLE) {
2668                 bp->stats_state = STATS_STATE_STOP;
2669                 DP(BNX2X_MSG_STATS, "stats_state - STOP\n");
2670         }
2671
2672         /* indicate no mac active */
2673         bp->phy_flags &= ~(PHY_BMAC_FLAG | PHY_EMAC_FLAG);
2674
2675         /* update shared memory */
2676         bnx2x_update_mng(bp);
2677
2678         /* activate nig drain */
2679         NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
2680
2681         /* reset BigMac */
2682         bnx2x_bmac_rx_disable(bp);
2683         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2684                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2685
2686         /* indicate link down */
2687         bnx2x_link_report(bp);
2688 }
2689
2690 static void bnx2x_init_mac_stats(struct bnx2x *bp);
2691
2692 /* This function is called upon link interrupt */
2693 static void bnx2x_link_update(struct bnx2x *bp)
2694 {
2695         int port = bp->port;
2696         int i;
2697         u32 gp_status;
2698         int link_10g;
2699
2700         DP(NETIF_MSG_LINK, "port %x, %s, int_status 0x%x,"
2701            " int_mask 0x%x, saved_mask 0x%x, MI_INT %x, SERDES_LINK %x,"
2702            " 10G %x, XGXS_LINK %x\n", port,
2703            (bp->phy_flags & PHY_XGXS_FLAG)? "XGXS":"SerDes",
2704            REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4),
2705            REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), bp->nig_mask,
2706            REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2707            REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c),
2708            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2709            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)
2710         );
2711
2712         might_sleep();
2713         MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_GP_STATUS);
2714         /* avoid fast toggling */
2715         for (i = 0; i < 10; i++) {
2716                 msleep(10);
2717                 bnx2x_mdio22_read(bp, MDIO_GP_STATUS_TOP_AN_STATUS1,
2718                                   &gp_status);
2719         }
2720
2721         bnx2x_link_settings_status(bp, gp_status);
2722
2723         /* anything 10 and over uses the bmac */
2724         link_10g = ((bp->line_speed >= SPEED_10000) &&
2725                     (bp->line_speed <= SPEED_16000));
2726
2727         bnx2x_link_int_ack(bp, link_10g);
2728
2729         /* link is up only if both local phy and external phy are up */
2730         bp->link_up = (bp->phy_link_up && bnx2x_ext_phy_is_link_up(bp));
2731         if (bp->link_up) {
2732                 if (link_10g) {
2733                         bnx2x_bmac_enable(bp, 0);
2734                         bnx2x_leds_set(bp, SPEED_10000);
2735
2736                 } else {
2737                         bnx2x_emac_enable(bp);
2738                         bnx2x_emac_program(bp);
2739
2740                         /* AN complete? */
2741                         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
2742                                 if (!(bp->phy_flags & PHY_SGMII_FLAG))
2743                                         bnx2x_set_sgmii_tx_driver(bp);
2744                         }
2745                 }
2746                 bnx2x_link_up(bp);
2747
2748         } else { /* link down */
2749                 bnx2x_leds_unset(bp);
2750                 bnx2x_link_down(bp);
2751         }
2752
2753         bnx2x_init_mac_stats(bp);
2754 }
2755
2756 /*
2757  * Init service functions
2758  */
2759
2760 static void bnx2x_set_aer_mmd(struct bnx2x *bp)
2761 {
2762         u16 offset = (bp->phy_flags & PHY_XGXS_FLAG) ?
2763                                         (bp->phy_addr + bp->ser_lane) : 0;
2764
2765         MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_AER_BLOCK);
2766         bnx2x_mdio22_write(bp, MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
2767 }
2768
2769 static void bnx2x_set_master_ln(struct bnx2x *bp)
2770 {
2771         u32 new_master_ln;
2772
2773         /* set the master_ln for AN */
2774         MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2);
2775         bnx2x_mdio22_read(bp, MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
2776                           &new_master_ln);
2777         bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
2778                            (new_master_ln | bp->ser_lane));
2779 }
2780
2781 static void bnx2x_reset_unicore(struct bnx2x *bp)
2782 {
2783         u32 mii_control;
2784         int i;
2785
2786         MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2787         bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
2788         /* reset the unicore */
2789         bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
2790                            (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET));
2791
2792         /* wait for the reset to self clear */
2793         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
2794                 udelay(5);
2795
2796                 /* the reset erased the previous bank value */
2797                 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2798                 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
2799                                   &mii_control);
2800
2801                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
2802                         udelay(5);
2803                         return;
2804                 }
2805         }
2806
2807         BNX2X_ERR("BUG! %s (0x%x) is still in reset!\n",
2808                   (bp->phy_flags & PHY_XGXS_FLAG)? "XGXS":"SerDes",
2809                   bp->phy_addr);
2810 }
2811
2812 static void bnx2x_set_swap_lanes(struct bnx2x *bp)
2813 {
2814         /* Each two bits represents a lane number:
2815            No swap is 0123 => 0x1b no need to enable the swap */
2816
2817         MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2);
2818         if (bp->rx_lane_swap != 0x1b) {
2819                 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_RX_LN_SWAP,
2820                                    (bp->rx_lane_swap |
2821                                     MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
2822                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
2823         } else {
2824                 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
2825         }
2826
2827         if (bp->tx_lane_swap != 0x1b) {
2828                 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TX_LN_SWAP,
2829                                    (bp->tx_lane_swap |
2830                                     MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
2831         } else {
2832                 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
2833         }
2834 }
2835
2836 static void bnx2x_set_parallel_detection(struct bnx2x *bp)
2837 {
2838         u32 control2;
2839
2840         MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
2841         bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
2842                           &control2);
2843
2844         if (bp->autoneg & AUTONEG_PARALLEL) {
2845                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
2846         } else {
2847                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
2848         }
2849         bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
2850                            control2);
2851
2852         if (bp->phy_flags & PHY_XGXS_FLAG) {
2853                 DP(NETIF_MSG_LINK, "XGXS\n");
2854                 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_10G_PARALLEL_DETECT);
2855
2856                 bnx2x_mdio22_write(bp,
2857                                 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
2858                                MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
2859
2860                 bnx2x_mdio22_read(bp,
2861                                 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
2862                                 &control2);
2863
2864                 if (bp->autoneg & AUTONEG_PARALLEL) {
2865                         control2 |=
2866                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
2867                 } else {
2868                         control2 &=
2869                    ~MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
2870                 }
2871                 bnx2x_mdio22_write(bp,
2872                                 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
2873                                 control2);
2874
2875                 /* Disable parallel detection of HiG */
2876                 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2);
2877                 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
2878                                 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
2879                                 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
2880         }
2881 }
2882
2883 static void bnx2x_set_autoneg(struct bnx2x *bp)
2884 {
2885         u32 reg_val;
2886
2887         /* CL37 Autoneg */
2888         MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2889         bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2890         if ((bp->req_autoneg & AUTONEG_SPEED) &&
2891             (bp->autoneg & AUTONEG_CL37)) {
2892                 /* CL37 Autoneg Enabled */
2893                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
2894         } else {
2895                 /* CL37 Autoneg Disabled */
2896                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2897                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
2898         }
2899         bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2900
2901         /* Enable/Disable Autodetection */
2902         MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
2903         bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
2904         reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN;
2905
2906         if ((bp->req_autoneg & AUTONEG_SPEED) &&
2907             (bp->autoneg & AUTONEG_SGMII_FIBER_AUTODET)) {
2908                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
2909         } else {
2910                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
2911         }
2912         bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
2913
2914         /* Enable TetonII and BAM autoneg */
2915         MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_BAM_NEXT_PAGE);
2916         bnx2x_mdio22_read(bp, MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
2917                           &reg_val);
2918         if ((bp->req_autoneg & AUTONEG_SPEED) &&
2919             (bp->autoneg & AUTONEG_CL37) && (bp->autoneg & AUTONEG_BAM)) {
2920                 /* Enable BAM aneg Mode and TetonII aneg Mode */
2921                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
2922                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
2923         } else {
2924                 /* TetonII and BAM Autoneg Disabled */
2925                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
2926                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
2927         }
2928         bnx2x_mdio22_write(bp, MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
2929                            reg_val);
2930
2931         /* Enable Clause 73 Aneg */
2932         if ((bp->req_autoneg & AUTONEG_SPEED) &&
2933             (bp->autoneg & AUTONEG_CL73)) {
2934                 /* Enable BAM Station Manager */
2935                 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_USERB0);
2936                 bnx2x_mdio22_write(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL1,
2937                                    (MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
2938                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
2939                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN));
2940
2941                 /* Merge CL73 and CL37 aneg resolution */
2942                 bnx2x_mdio22_read(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL3,
2943                                   &reg_val);
2944                 bnx2x_mdio22_write(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL3,
2945                                    (reg_val |
2946                         MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR));
2947
2948                 /* Set the CL73 AN speed */
2949                 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB1);
2950                 bnx2x_mdio22_read(bp, MDIO_CL73_IEEEB1_AN_ADV2, &reg_val);
2951                 /* In the SerDes we support only the 1G.
2952                    In the XGXS we support the 10G KX4
2953                    but we currently do not support the KR */
2954                 if (bp->phy_flags & PHY_XGXS_FLAG) {
2955                         DP(NETIF_MSG_LINK, "XGXS\n");
2956                         /* 10G KX4 */
2957                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
2958                 } else {
2959                         DP(NETIF_MSG_LINK, "SerDes\n");
2960                         /* 1000M KX */
2961                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
2962                 }
2963                 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
2964
2965                 /* CL73 Autoneg Enabled */
2966                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
2967         } else {
2968                 /* CL73 Autoneg Disabled */
2969                 reg_val = 0;
2970         }
2971         MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
2972         bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
2973 }
2974
2975 /* program SerDes, forced speed */
2976 static void bnx2x_program_serdes(struct bnx2x *bp)
2977 {
2978         u32 reg_val;
2979
2980         /* program duplex, disable autoneg */
2981         MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2982         bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2983         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
2984                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN);
2985         if (bp->req_duplex == DUPLEX_FULL)
2986                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2987         bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2988
2989         /* program speed
2990            - needed only if the speed is greater than 1G (2.5G or 10G) */
2991         if (bp->req_line_speed > SPEED_1000) {
2992                 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
2993                 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_MISC1, &reg_val);
2994                 /* clearing the speed value before setting the right speed */
2995                 reg_val &= ~MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK;
2996                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2997                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2998                 if (bp->req_line_speed == SPEED_10000)
2999                         reg_val |=
3000                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
3001                 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_MISC1, reg_val);
3002         }
3003 }
3004
3005 static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x *bp)
3006 {
3007         u32 val = 0;
3008
3009         /* configure the 48 bits for BAM AN */
3010         MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_OVER_1G);
3011
3012         /* set extended capabilities */
3013         if (bp->advertising & ADVERTISED_2500baseX_Full)
3014                 val |= MDIO_OVER_1G_UP1_2_5G;
3015         if (bp->advertising & ADVERTISED_10000baseT_Full)
3016                 val |= MDIO_OVER_1G_UP1_10G;
3017         bnx2x_mdio22_write(bp, MDIO_OVER_1G_UP1, val);
3018
3019         bnx2x_mdio22_write(bp, MDIO_OVER_1G_UP3, 0);
3020 }
3021
3022 static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x *bp)
3023 {
3024         u32 an_adv;
3025
3026         /* for AN, we are always publishing full duplex */
3027         an_adv = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3028
3029         /* resolve pause mode and advertisement
3030          * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
3031         if (bp->req_autoneg & AUTONEG_FLOW_CTRL) {
3032                 switch (bp->req_flow_ctrl) {
3033                 case FLOW_CTRL_AUTO:
3034                         if (bp->dev->mtu <= 4500) {
3035                                 an_adv |=
3036                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3037                                 bp->advertising |= (ADVERTISED_Pause |
3038                                                     ADVERTISED_Asym_Pause);
3039                         } else {
3040                                 an_adv |=
3041                                MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3042                                 bp->advertising |= ADVERTISED_Asym_Pause;
3043                         }
3044                         break;
3045
3046                 case FLOW_CTRL_TX:
3047                         an_adv |=
3048                                MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3049                         bp->advertising |= ADVERTISED_Asym_Pause;
3050                         break;
3051
3052                 case FLOW_CTRL_RX:
3053                         if (bp->dev->mtu <= 4500) {
3054                                 an_adv |=
3055                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3056                                 bp->advertising |= (ADVERTISED_Pause |
3057                                                     ADVERTISED_Asym_Pause);
3058                         } else {
3059                                 an_adv |=
3060                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3061                                 bp->advertising &= ~(ADVERTISED_Pause |
3062                                                      ADVERTISED_Asym_Pause);
3063                         }
3064                         break;
3065
3066                 case FLOW_CTRL_BOTH:
3067                         if (bp->dev->mtu <= 4500) {
3068                                 an_adv |=
3069                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3070                                 bp->advertising |= (ADVERTISED_Pause |
3071                                                     ADVERTISED_Asym_Pause);
3072                         } else {
3073                                 an_adv |=
3074                                MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3075                                 bp->advertising |= ADVERTISED_Asym_Pause;
3076                         }
3077                         break;
3078
3079                 case FLOW_CTRL_NONE:
3080                 default:
3081                         an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3082                         bp->advertising &= ~(ADVERTISED_Pause |
3083                                              ADVERTISED_Asym_Pause);
3084                         break;
3085                 }
3086         } else { /* forced mode */
3087                 switch (bp->req_flow_ctrl) {
3088                 case FLOW_CTRL_AUTO:
3089                         DP(NETIF_MSG_LINK, "req_flow_ctrl 0x%x while"
3090                                            " req_autoneg 0x%x\n",
3091                            bp->req_flow_ctrl, bp->req_autoneg);
3092                         break;
3093
3094                 case FLOW_CTRL_TX:
3095                         an_adv |=
3096                                MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3097                         bp->advertising |= ADVERTISED_Asym_Pause;
3098                         break;
3099
3100                 case FLOW_CTRL_RX:
3101                 case FLOW_CTRL_BOTH:
3102                         an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3103                         bp->advertising |= (ADVERTISED_Pause |
3104                                             ADVERTISED_Asym_Pause);
3105                         break;
3106
3107                 case FLOW_CTRL_NONE:
3108                 default:
3109                         an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3110                         bp->advertising &= ~(ADVERTISED_Pause |
3111                                              ADVERTISED_Asym_Pause);
3112                         break;
3113                 }
3114         }
3115
3116         MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
3117         bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_AUTO_NEG_ADV, an_adv);
3118 }
3119
3120 static void bnx2x_restart_autoneg(struct bnx2x *bp)
3121 {
3122         if (bp->autoneg & AUTONEG_CL73) {
3123                 /* enable and restart clause 73 aneg */
3124                 u32 an_ctrl;
3125
3126                 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
3127                 bnx2x_mdio22_read(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
3128                                   &an_ctrl);
3129                 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
3130                                    (an_ctrl |
3131                                     MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
3132                                 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
3133
3134         } else {
3135                 /* Enable and restart BAM/CL37 aneg */
3136                 u32 mii_control;
3137
3138                 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
3139                 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3140                                   &mii_control);
3141                 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3142                                    (mii_control |
3143                                     MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
3144                                     MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
3145         }
3146 }
3147
3148 static void bnx2x_initialize_sgmii_process(struct bnx2x *bp)
3149 {
3150         u32 control1;
3151
3152         /* in SGMII mode, the unicore is always slave */
3153         MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
3154         bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
3155                           &control1);
3156         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
3157         /* set sgmii mode (and not fiber) */
3158         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
3159                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
3160                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
3161         bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
3162                            control1);
3163
3164         /* if forced speed */
3165         if (!(bp->req_autoneg & AUTONEG_SPEED)) {
3166                 /* set speed, disable autoneg */
3167                 u32 mii_control;
3168
3169                 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
3170                 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3171                                   &mii_control);
3172                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
3173                                MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK |
3174                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
3175
3176                 switch (bp->req_line_speed) {
3177                 case SPEED_100:
3178                         mii_control |=
3179                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
3180                         break;
3181                 case SPEED_1000:
3182                         mii_control |=
3183                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
3184                         break;
3185                 case SPEED_10:
3186                         /* there is nothing to set for 10M */
3187                         break;
3188                 default:
3189                         /* invalid speed for SGMII */
3190                         DP(NETIF_MSG_LINK, "Invalid req_line_speed 0x%x\n",
3191                            bp->req_line_speed);
3192                         break;
3193                 }
3194
3195                 /* setting the full duplex */
3196                 if (bp->req_duplex == DUPLEX_FULL)
3197                         mii_control |=
3198                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
3199                 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3200                                    mii_control);
3201
3202         } else { /* AN mode */
3203                 /* enable and restart AN */
3204                 bnx2x_restart_autoneg(bp);
3205         }
3206 }
3207
3208 static void bnx2x_link_int_enable(struct bnx2x *bp)
3209 {
3210         int port = bp->port;
3211         u32 ext_phy_type;
3212         u32 mask;
3213
3214         /* setting the status to report on link up
3215            for either XGXS or SerDes */
3216         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3217                        (NIG_STATUS_XGXS0_LINK10G |
3218                         NIG_STATUS_XGXS0_LINK_STATUS |
3219                         NIG_STATUS_SERDES0_LINK_STATUS));
3220
3221         if (bp->phy_flags & PHY_XGXS_FLAG) {
3222                 mask = (NIG_MASK_XGXS0_LINK10G |
3223                         NIG_MASK_XGXS0_LINK_STATUS);
3224                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
3225                 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
3226                 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3227                     (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3228                     (ext_phy_type !=
3229                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) {
3230                         mask |= NIG_MASK_MI_INT;
3231                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
3232                 }
3233
3234         } else { /* SerDes */
3235                 mask = NIG_MASK_SERDES0_LINK_STATUS;
3236                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
3237                 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
3238                 if ((ext_phy_type !=
3239                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
3240                     (ext_phy_type !=
3241                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN)) {
3242                         mask |= NIG_MASK_MI_INT;
3243                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
3244                 }
3245         }
3246         bnx2x_bits_en(bp,
3247                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3248                       mask);
3249         DP(NETIF_MSG_LINK, "port %x, %s, int_status 0x%x,"
3250            " int_mask 0x%x, MI_INT %x, SERDES_LINK %x,"
3251            " 10G %x, XGXS_LINK %x\n", port,
3252            (bp->phy_flags & PHY_XGXS_FLAG)? "XGXS":"SerDes",
3253            REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4),
3254            REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3255            REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
3256            REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c),
3257            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3258            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)
3259         );
3260 }
3261
3262 static void bnx2x_bcm8072_external_rom_boot(struct bnx2x *bp)
3263 {
3264         u32 ext_phy_addr = ((bp->ext_phy_config &
3265                              PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3266                             PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3267         u32 fw_ver1, fw_ver2;
3268
3269         /* Need to wait 200ms after reset */
3270         msleep(200);
3271         /* Boot port from external ROM
3272          * Set ser_boot_ctl bit in the MISC_CTRL1 register
3273          */
3274         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3275                                 EXT_PHY_KR_PMA_PMD_DEVAD,
3276                                 EXT_PHY_KR_MISC_CTRL1, 0x0001);
3277
3278         /* Reset internal microprocessor */
3279         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3280                                 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_GEN_CTRL,
3281                                 EXT_PHY_KR_ROM_RESET_INTERNAL_MP);
3282         /* set micro reset = 0 */
3283         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3284                                 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_GEN_CTRL,
3285                                 EXT_PHY_KR_ROM_MICRO_RESET);
3286         /* Reset internal microprocessor */
3287         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3288                                 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_GEN_CTRL,
3289                                 EXT_PHY_KR_ROM_RESET_INTERNAL_MP);
3290         /* wait for 100ms for code download via SPI port */
3291         msleep(100);
3292
3293         /* Clear ser_boot_ctl bit */
3294         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3295                                 EXT_PHY_KR_PMA_PMD_DEVAD,
3296                                 EXT_PHY_KR_MISC_CTRL1, 0x0000);
3297         /* Wait 100ms */
3298         msleep(100);
3299
3300         /* Print the PHY FW version */
3301         bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, ext_phy_addr,
3302                                EXT_PHY_KR_PMA_PMD_DEVAD,
3303                                0xca19, &fw_ver1);
3304         bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, ext_phy_addr,
3305                                EXT_PHY_KR_PMA_PMD_DEVAD,
3306                                0xca1a, &fw_ver2);
3307         DP(NETIF_MSG_LINK,
3308            "8072 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2);
3309 }
3310
3311 static void bnx2x_bcm8072_force_10G(struct bnx2x *bp)
3312 {
3313         u32 ext_phy_addr = ((bp->ext_phy_config &
3314                              PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3315                             PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3316
3317         /* Force KR or KX */
3318         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3319                                 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_CTRL,
3320                                 0x2040);
3321         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3322                                 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_CTRL2,
3323                                 0x000b);
3324         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3325                                 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_PMD_CTRL,
3326                                 0x0000);
3327         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3328                                 EXT_PHY_KR_AUTO_NEG_DEVAD, EXT_PHY_KR_CTRL,
3329                                 0x0000);
3330 }
3331
3332 static void bnx2x_ext_phy_init(struct bnx2x *bp)
3333 {
3334         u32 ext_phy_type;
3335         u32 ext_phy_addr;
3336         u32 cnt;
3337         u32 ctrl;
3338         u32 val = 0;
3339
3340         if (bp->phy_flags & PHY_XGXS_FLAG) {
3341                 ext_phy_addr = ((bp->ext_phy_config &
3342                                  PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3343                                 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3344
3345                 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
3346                 /* Make sure that the soft reset is off (expect for the 8072:
3347                  * due to the lock, it will be done inside the specific
3348                  * handling)
3349                  */
3350                 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3351                     (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3352                    (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) &&
3353                     (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072)) {
3354                         /* Wait for soft reset to get cleared upto 1 sec */
3355                         for (cnt = 0; cnt < 1000; cnt++) {
3356                                 bnx2x_mdio45_read(bp, ext_phy_addr,
3357                                                   EXT_PHY_OPT_PMA_PMD_DEVAD,
3358                                                   EXT_PHY_OPT_CNTL, &ctrl);
3359                                 if (!(ctrl & (1<<15)))
3360                                         break;
3361                                 msleep(1);
3362                         }
3363                         DP(NETIF_MSG_LINK,
3364                            "control reg 0x%x (after %d ms)\n", ctrl, cnt);
3365                 }
3366
3367                 switch (ext_phy_type) {
3368                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
3369                         DP(NETIF_MSG_LINK, "XGXS Direct\n");
3370                         break;
3371
3372                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3373                         DP(NETIF_MSG_LINK, "XGXS 8705\n");
3374
3375                         bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3376                                             EXT_PHY_OPT_PMA_PMD_DEVAD,
3377                                             EXT_PHY_OPT_PMD_MISC_CNTL,
3378                                             0x8288);
3379                         bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3380                                             EXT_PHY_OPT_PMA_PMD_DEVAD,
3381                                             EXT_PHY_OPT_PHY_IDENTIFIER,
3382                                             0x7fbf);
3383                         bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3384                                             EXT_PHY_OPT_PMA_PMD_DEVAD,
3385                                             EXT_PHY_OPT_CMU_PLL_BYPASS,
3386                                             0x0100);
3387                         bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3388                                             EXT_PHY_OPT_WIS_DEVAD,
3389                                             EXT_PHY_OPT_LASI_CNTL, 0x1);
3390                         break;
3391
3392                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
3393                         DP(NETIF_MSG_LINK, "XGXS 8706\n");
3394
3395                         if (!(bp->req_autoneg & AUTONEG_SPEED)) {
3396                                 /* Force speed */
3397                                 if (bp->req_line_speed == SPEED_10000) {
3398                                         DP(NETIF_MSG_LINK,
3399                                            "XGXS 8706 force 10Gbps\n");
3400                                         bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3401                                                 EXT_PHY_OPT_PMA_PMD_DEVAD,
3402                                                 EXT_PHY_OPT_PMD_DIGITAL_CNT,
3403                                                 0x400);
3404                                 } else {
3405                                         /* Force 1Gbps */
3406                                         DP(NETIF_MSG_LINK,
3407                                            "XGXS 8706 force 1Gbps\n");
3408
3409                                         bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3410                                                 EXT_PHY_OPT_PMA_PMD_DEVAD,
3411                                                 EXT_PHY_OPT_CNTL,
3412                                                 0x0040);
3413
3414                                         bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3415                                                 EXT_PHY_OPT_PMA_PMD_DEVAD,
3416                                                 EXT_PHY_OPT_CNTL2,
3417                                                 0x000D);
3418                                 }
3419
3420                                 /* Enable LASI */
3421                                 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3422                                                     EXT_PHY_OPT_PMA_PMD_DEVAD,
3423                                                     EXT_PHY_OPT_LASI_CNTL,
3424                                                     0x1);
3425                         } else {
3426                                 /* AUTONEG */
3427                                 /* Allow CL37 through CL73 */
3428                                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
3429                                 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3430                                                     EXT_PHY_AUTO_NEG_DEVAD,
3431                                                     EXT_PHY_OPT_AN_CL37_CL73,
3432                                                     0x040c);
3433
3434                                 /* Enable Full-Duplex advertisment on CL37 */
3435                                 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3436                                                     EXT_PHY_AUTO_NEG_DEVAD,
3437                                                     EXT_PHY_OPT_AN_CL37_FD,
3438                                                     0x0020);
3439                                 /* Enable CL37 AN */
3440                                 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3441                                                     EXT_PHY_AUTO_NEG_DEVAD,
3442                                                     EXT_PHY_OPT_AN_CL37_AN,
3443                                                     0x1000);
3444                                 /* Advertise 10G/1G support */
3445                                 if (bp->advertising &
3446                                     ADVERTISED_1000baseT_Full)
3447                                         val = (1<<5);
3448                                 if (bp->advertising &
3449                                     ADVERTISED_10000baseT_Full)
3450                                         val |= (1<<7);
3451
3452                                 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3453                                                     EXT_PHY_AUTO_NEG_DEVAD,
3454                                                     EXT_PHY_OPT_AN_ADV, val);
3455                                 /* Enable LASI */
3456                                 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3457                                                     EXT_PHY_OPT_PMA_PMD_DEVAD,
3458                                                     EXT_PHY_OPT_LASI_CNTL,
3459                                                     0x1);
3460
3461                                 /* Enable clause 73 AN */
3462                                 bnx2x_mdio45_write(bp, ext_phy_addr,
3463                                                    EXT_PHY_AUTO_NEG_DEVAD,
3464                                                    EXT_PHY_OPT_CNTL,
3465                                                    0x1200);
3466                         }
3467                         break;
3468
3469                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3470                         bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
3471                         /* Wait for soft reset to get cleared upto 1 sec */
3472                         for (cnt = 0; cnt < 1000; cnt++) {
3473                                 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
3474                                                 ext_phy_addr,
3475                                                 EXT_PHY_OPT_PMA_PMD_DEVAD,
3476                                                 EXT_PHY_OPT_CNTL, &ctrl);
3477                                 if (!(ctrl & (1<<15)))
3478                                         break;
3479                                 msleep(1);
3480                         }
3481                         DP(NETIF_MSG_LINK,
3482                            "8072 control reg 0x%x (after %d ms)\n",
3483                            ctrl, cnt);
3484
3485                         bnx2x_bcm8072_external_rom_boot(bp);
3486                         DP(NETIF_MSG_LINK, "Finshed loading 8072 KR ROM\n");
3487
3488                         /* enable LASI */
3489                         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3490                                                 ext_phy_addr,
3491                                                 EXT_PHY_KR_PMA_PMD_DEVAD,
3492                                                 0x9000, 0x0400);
3493                         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3494                                                 ext_phy_addr,
3495                                                 EXT_PHY_KR_PMA_PMD_DEVAD,
3496                                                 EXT_PHY_KR_LASI_CNTL, 0x0004);
3497
3498                         /* If this is forced speed, set to KR or KX
3499                          * (all other are not supported)
3500                          */
3501                         if (!(bp->req_autoneg & AUTONEG_SPEED)) {
3502                                 if (bp->req_line_speed == SPEED_10000) {
3503                                         bnx2x_bcm8072_force_10G(bp);
3504                                         DP(NETIF_MSG_LINK,
3505                                            "Forced speed 10G on 8072\n");
3506                                         /* unlock */
3507                                         bnx2x_hw_unlock(bp,
3508                                                 HW_LOCK_RESOURCE_8072_MDIO);
3509                                         break;
3510                                 } else
3511                                         val = (1<<5);
3512                         } else {
3513
3514                                 /* Advertise 10G/1G support */
3515                                 if (bp->advertising &
3516                                                 ADVERTISED_1000baseT_Full)
3517                                         val = (1<<5);
3518                                 if (bp->advertising &
3519                                                 ADVERTISED_10000baseT_Full)
3520                                         val |= (1<<7);
3521                         }
3522                         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3523                                         ext_phy_addr,
3524                                         EXT_PHY_KR_AUTO_NEG_DEVAD,
3525                                         0x11, val);
3526                         /* Add support for CL37 ( passive mode ) I */
3527                         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3528                                                 ext_phy_addr,
3529                                                 EXT_PHY_KR_AUTO_NEG_DEVAD,
3530                                                 0x8370, 0x040c);
3531                         /* Add support for CL37 ( passive mode ) II */
3532                         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3533                                                 ext_phy_addr,
3534                                                 EXT_PHY_KR_AUTO_NEG_DEVAD,
3535                                                 0xffe4, 0x20);
3536                         /* Add support for CL37 ( passive mode ) III */
3537                         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3538                                                 ext_phy_addr,
3539                                                 EXT_PHY_KR_AUTO_NEG_DEVAD,
3540                                                 0xffe0, 0x1000);
3541                         /* Restart autoneg */
3542                         msleep(500);
3543                         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3544                                         ext_phy_addr,
3545                                         EXT_PHY_KR_AUTO_NEG_DEVAD,
3546                                         EXT_PHY_KR_CTRL, 0x1200);
3547                         DP(NETIF_MSG_LINK, "8072 Autoneg Restart: "
3548                            "1G %ssupported  10G %ssupported\n",
3549                            (val & (1<<5)) ? "" : "not ",
3550                            (val & (1<<7)) ? "" : "not ");
3551
3552                         /* unlock */
3553                         bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
3554                         break;
3555
3556                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
3557                         DP(NETIF_MSG_LINK,
3558                            "Setting the SFX7101 LASI indication\n");
3559                         bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3560                                             EXT_PHY_OPT_PMA_PMD_DEVAD,
3561                                             EXT_PHY_OPT_LASI_CNTL, 0x1);
3562                         DP(NETIF_MSG_LINK,
3563                            "Setting the SFX7101 LED to blink on traffic\n");
3564                         bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3565                                             EXT_PHY_OPT_PMA_PMD_DEVAD,
3566                                             0xC007, (1<<3));
3567
3568                         /* read modify write pause advertizing */
3569                         bnx2x_mdio45_read(bp, ext_phy_addr,
3570                                           EXT_PHY_KR_AUTO_NEG_DEVAD,
3571                                           EXT_PHY_KR_AUTO_NEG_ADVERT, &val);
3572                         val &= ~EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_BOTH;
3573                         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3574                         if (bp->advertising & ADVERTISED_Pause)
3575                                 val |= EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE;
3576
3577                         if (bp->advertising & ADVERTISED_Asym_Pause) {
3578                                 val |=
3579                                  EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_ASYMMETRIC;
3580                         }
3581                         DP(NETIF_MSG_LINK, "SFX7101 AN advertize 0x%x\n", val);
3582                         bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3583                                             EXT_PHY_KR_AUTO_NEG_DEVAD,
3584                                             EXT_PHY_KR_AUTO_NEG_ADVERT, val);
3585                         /* Restart autoneg */
3586                         bnx2x_mdio45_read(bp, ext_phy_addr,
3587                                           EXT_PHY_KR_AUTO_NEG_DEVAD,
3588                                           EXT_PHY_KR_CTRL, &val);
3589                         val |= 0x200;
3590                         bnx2x_mdio45_write(bp, ext_phy_addr,
3591                                             EXT_PHY_KR_AUTO_NEG_DEVAD,
3592                                             EXT_PHY_KR_CTRL, val);
3593                         break;
3594
3595                 default:
3596                         BNX2X_ERR("BAD XGXS ext_phy_config 0x%x\n",
3597                                   bp->ext_phy_config);
3598                         break;
3599                 }
3600
3601         } else { /* SerDes */
3602 /*              ext_phy_addr = ((bp->ext_phy_config &
3603                                  PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK) >>
3604                                 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT);
3605 */
3606                 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
3607                 switch (ext_phy_type) {
3608                 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
3609                         DP(NETIF_MSG_LINK, "SerDes Direct\n");
3610                         break;
3611
3612                 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
3613                         DP(NETIF_MSG_LINK, "SerDes 5482\n");
3614                         break;
3615
3616                 default:
3617                         DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
3618                            bp->ext_phy_config);
3619                         break;
3620                 }
3621         }
3622 }
3623
3624 static void bnx2x_ext_phy_reset(struct bnx2x *bp)
3625 {
3626         u32 ext_phy_type;
3627         u32 ext_phy_addr = ((bp->ext_phy_config &
3628                              PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3629                             PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3630         u32 board = (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK);
3631
3632         /* The PHY reset is controled by GPIO 1
3633          * Give it 1ms of reset pulse
3634          */
3635         if ((board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G) &&
3636             (board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G)) {
3637                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3638                                MISC_REGISTERS_GPIO_OUTPUT_LOW);
3639                 msleep(1);
3640                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3641                                MISC_REGISTERS_GPIO_OUTPUT_HIGH);
3642         }
3643
3644         if (bp->phy_flags & PHY_XGXS_FLAG) {
3645                 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
3646                 switch (ext_phy_type) {
3647                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
3648                         DP(NETIF_MSG_LINK, "XGXS Direct\n");
3649                         break;
3650
3651                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3652                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
3653                         DP(NETIF_MSG_LINK, "XGXS 8705/8706\n");
3654                         bnx2x_mdio45_write(bp, ext_phy_addr,
3655                                            EXT_PHY_OPT_PMA_PMD_DEVAD,
3656                                            EXT_PHY_OPT_CNTL, 0xa040);
3657                         break;
3658
3659                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3660                         DP(NETIF_MSG_LINK, "XGXS 8072\n");
3661                         bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
3662                         bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3663                                                 ext_phy_addr,
3664                                                 EXT_PHY_KR_PMA_PMD_DEVAD,
3665                                                 0, 1<<15);
3666                         bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
3667                         break;
3668
3669                 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
3670                         DP(NETIF_MSG_LINK, "XGXS SFX7101\n");
3671                         break;
3672
3673                 default:
3674                         DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
3675                            bp->ext_phy_config);
3676                         break;
3677                 }
3678
3679         } else { /* SerDes */
3680                 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
3681                 switch (ext_phy_type) {
3682                 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
3683                         DP(NETIF_MSG_LINK, "SerDes Direct\n");
3684                         break;
3685
3686                 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
3687                         DP(NETIF_MSG_LINK, "SerDes 5482\n");
3688                         break;
3689
3690                 default:
3691                         DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
3692                            bp->ext_phy_config);
3693                         break;
3694                 }
3695         }
3696 }
3697
3698 static void bnx2x_link_initialize(struct bnx2x *bp)
3699 {
3700         int port = bp->port;
3701
3702         /* disable attentions */
3703         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3704                        (NIG_MASK_XGXS0_LINK_STATUS |
3705                         NIG_MASK_XGXS0_LINK10G |
3706                         NIG_MASK_SERDES0_LINK_STATUS |
3707                         NIG_MASK_MI_INT));
3708
3709         /* Activate the external PHY */
3710         bnx2x_ext_phy_reset(bp);
3711
3712         bnx2x_set_aer_mmd(bp);
3713
3714         if (bp->phy_flags & PHY_XGXS_FLAG)
3715                 bnx2x_set_master_ln(bp);
3716
3717         /* reset the SerDes and wait for reset bit return low */
3718         bnx2x_reset_unicore(bp);
3719
3720         bnx2x_set_aer_mmd(bp);
3721
3722         /* setting the masterLn_def again after the reset */
3723         if (bp->phy_flags & PHY_XGXS_FLAG) {
3724                 bnx2x_set_master_ln(bp);
3725                 bnx2x_set_swap_lanes(bp);
3726         }
3727
3728         /* Set Parallel Detect */
3729         if (bp->req_autoneg & AUTONEG_SPEED)
3730                 bnx2x_set_parallel_detection(bp);
3731
3732         if (bp->phy_flags & PHY_XGXS_FLAG) {
3733                 if (bp->req_line_speed &&
3734                     bp->req_line_speed < SPEED_1000) {
3735                         bp->phy_flags |= PHY_SGMII_FLAG;
3736                 } else {
3737                         bp->phy_flags &= ~PHY_SGMII_FLAG;
3738                 }
3739         }
3740
3741         if (!(bp->phy_flags & PHY_SGMII_FLAG)) {
3742                 u16 bank, rx_eq;
3743
3744                 rx_eq = ((bp->serdes_config &
3745                           PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >>
3746                          PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT);
3747
3748                 DP(NETIF_MSG_LINK, "setting rx eq to %d\n", rx_eq);
3749                 for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL;
3750                             bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0)) {
3751                         MDIO_SET_REG_BANK(bp, bank);
3752                         bnx2x_mdio22_write(bp, MDIO_RX0_RX_EQ_BOOST,
3753                                            ((rx_eq &
3754                                 MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) |
3755                                 MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL));
3756                 }
3757
3758                 /* forced speed requested? */
3759                 if (!(bp->req_autoneg & AUTONEG_SPEED)) {
3760                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3761
3762                         /* disable autoneg */
3763                         bnx2x_set_autoneg(bp);
3764
3765                         /* program speed and duplex */
3766                         bnx2x_program_serdes(bp);
3767
3768                 } else { /* AN_mode */
3769                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
3770
3771                         /* AN enabled */
3772                         bnx2x_set_brcm_cl37_advertisment(bp);
3773
3774                         /* program duplex & pause advertisement (for aneg) */
3775                         bnx2x_set_ieee_aneg_advertisment(bp);
3776
3777                         /* enable autoneg */
3778                         bnx2x_set_autoneg(bp);
3779
3780                         /* enable and restart AN */
3781                         bnx2x_restart_autoneg(bp);
3782                 }
3783
3784         } else { /* SGMII mode */
3785                 DP(NETIF_MSG_LINK, "SGMII\n");
3786
3787                 bnx2x_initialize_sgmii_process(bp);
3788         }
3789
3790         /* init ext phy and enable link state int */
3791         bnx2x_ext_phy_init(bp);
3792
3793         /* enable the interrupt */
3794         bnx2x_link_int_enable(bp);
3795 }
3796
3797 static void bnx2x_phy_deassert(struct bnx2x *bp)
3798 {
3799         int port = bp->port;
3800         u32 val;
3801
3802         if (bp->phy_flags & PHY_XGXS_FLAG) {
3803                 DP(NETIF_MSG_LINK, "XGXS\n");
3804                 val = XGXS_RESET_BITS;
3805
3806         } else { /* SerDes */
3807                 DP(NETIF_MSG_LINK, "SerDes\n");
3808                 val = SERDES_RESET_BITS;
3809         }
3810
3811         val = val << (port*16);
3812
3813         /* reset and unreset the SerDes/XGXS */
3814         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3815         msleep(5);
3816         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3817 }
3818
3819 static int bnx2x_phy_init(struct bnx2x *bp)
3820 {
3821         DP(NETIF_MSG_LINK, "started\n");
3822         if (CHIP_REV(bp) == CHIP_REV_FPGA) {
3823                 bp->phy_flags |= PHY_EMAC_FLAG;
3824                 bp->link_up = 1;
3825                 bp->line_speed = SPEED_10000;
3826                 bp->duplex = DUPLEX_FULL;
3827                 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + bp->port*4, 0);
3828                 bnx2x_emac_enable(bp);
3829                 bnx2x_link_report(bp);
3830                 return 0;
3831
3832         } else if (CHIP_REV(bp) == CHIP_REV_EMUL) {
3833                 bp->phy_flags |= PHY_BMAC_FLAG;
3834                 bp->link_up = 1;
3835                 bp->line_speed = SPEED_10000;
3836                 bp->duplex = DUPLEX_FULL;
3837                 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + bp->port*4, 0);
3838                 bnx2x_bmac_enable(bp, 0);
3839                 bnx2x_link_report(bp);
3840                 return 0;
3841
3842         } else {
3843                 bnx2x_phy_deassert(bp);
3844                 bnx2x_link_initialize(bp);
3845         }
3846
3847         return 0;
3848 }
3849
3850 static void bnx2x_link_reset(struct bnx2x *bp)
3851 {
3852         int port = bp->port;
3853         u32 board = (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK);
3854
3855         /* update shared memory */
3856         bp->link_status = 0;
3857         bnx2x_update_mng(bp);
3858
3859         /* disable attentions */
3860         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3861                        (NIG_MASK_XGXS0_LINK_STATUS |
3862                         NIG_MASK_XGXS0_LINK10G |
3863                         NIG_MASK_SERDES0_LINK_STATUS |
3864                         NIG_MASK_MI_INT));
3865
3866         /* activate nig drain */
3867         NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
3868
3869         /* disable nig egress interface */
3870         NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0);
3871         NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
3872
3873         /* Stop BigMac rx */
3874         bnx2x_bmac_rx_disable(bp);
3875
3876         /* disable emac */
3877         NIG_WR(NIG_REG_NIG_EMAC0_EN + port*4, 0);
3878
3879         msleep(10);
3880
3881         /* The PHY reset is controled by GPIO 1
3882          * Hold it as output low
3883          */
3884         if ((board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G) &&
3885             (board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G)) {
3886                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3887                                MISC_REGISTERS_GPIO_OUTPUT_LOW);
3888                 DP(NETIF_MSG_LINK, "reset external PHY\n");
3889         }
3890
3891         /* reset the SerDes/XGXS */
3892         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
3893                (0x1ff << (port*16)));
3894
3895         /* reset BigMac */
3896         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3897                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3898
3899         /* disable nig ingress interface */
3900         NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0);
3901         NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0);
3902
3903         /* set link down */
3904         bp->link_up = 0;
3905 }
3906
3907 #ifdef BNX2X_XGXS_LB
3908 static void bnx2x_set_xgxs_loopback(struct bnx2x *bp, int is_10g)
3909 {
3910         int port = bp->port;
3911
3912         if (is_10g) {
3913                 u32 md_devad;
3914
3915                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3916
3917                 /* change the uni_phy_addr in the nig */
3918                 REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18),
3919                        &md_devad);
3920                 NIG_WR(NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3921
3922                 /* change the aer mmd */
3923                 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_AER_BLOCK);
3924                 bnx2x_mdio22_write(bp, MDIO_AER_BLOCK_AER_REG, 0x2800);
3925
3926                 /* config combo IEEE0 control reg for loopback */
3927                 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
3928                 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
3929                                    0x6041);
3930
3931                 /* set aer mmd back */
3932                 bnx2x_set_aer_mmd(bp);
3933
3934                 /* and md_devad */
3935                 NIG_WR(NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad);
3936
3937         } else {
3938                 u32 mii_control;
3939
3940                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
3941
3942                 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
3943                 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3944                                   &mii_control);
3945                 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3946                                    (mii_control |
3947                                     MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
3948         }
3949 }
3950 #endif
3951
3952 /* end of PHY/MAC */
3953
3954 /* slow path */
3955
3956 /*
3957  * General service functions
3958  */
3959
3960 /* the slow path queue is odd since completions arrive on the fastpath ring */
3961 static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3962                          u32 data_hi, u32 data_lo, int common)
3963 {
3964         int port = bp->port;
3965
3966         DP(NETIF_MSG_TIMER,
3967            "spe (%x:%x)  command %d  hw_cid %x  data (%x:%x)  left %x\n",
3968            (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
3969            (void *)bp->spq_prod_bd - (void *)bp->spq), command,
3970            HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
3971
3972 #ifdef BNX2X_STOP_ON_ERROR
3973         if (unlikely(bp->panic))
3974                 return -EIO;
3975 #endif
3976
3977         spin_lock(&bp->spq_lock);
3978
3979         if (!bp->spq_left) {
3980                 BNX2X_ERR("BUG! SPQ ring full!\n");
3981                 spin_unlock(&bp->spq_lock);
3982                 bnx2x_panic();
3983                 return -EBUSY;
3984         }
3985
3986         /* CID needs port number to be encoded int it */
3987         bp->spq_prod_bd->hdr.conn_and_cmd_data =
3988                         cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) |
3989                                      HW_CID(bp, cid)));
3990         bp->spq_prod_bd->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE);
3991         if (common)
3992                 bp->spq_prod_bd->hdr.type |=
3993                         cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
3994
3995         bp->spq_prod_bd->data.mac_config_addr.hi = cpu_to_le32(data_hi);
3996         bp->spq_prod_bd->data.mac_config_addr.lo = cpu_to_le32(data_lo);
3997
3998         bp->spq_left--;
3999
4000         if (bp->spq_prod_bd == bp->spq_last_bd) {
4001                 bp->spq_prod_bd = bp->spq;
4002                 bp->spq_prod_idx = 0;
4003                 DP(NETIF_MSG_TIMER, "end of spq\n");
4004
4005         } else {
4006                 bp->spq_prod_bd++;
4007                 bp->spq_prod_idx++;
4008         }
4009
4010         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(port),
4011                bp->spq_prod_idx);
4012
4013         spin_unlock(&bp->spq_lock);
4014         return 0;
4015 }
4016
4017 /* acquire split MCP access lock register */
4018 static int bnx2x_lock_alr(struct bnx2x *bp)
4019 {
4020         int rc = 0;
4021         u32 i, j, val;
4022
4023         might_sleep();
4024         i = 100;
4025         for (j = 0; j < i*10; j++) {
4026                 val = (1UL << 31);
4027                 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
4028                 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
4029                 if (val & (1L << 31))
4030                         break;
4031
4032                 msleep(5);
4033         }
4034
4035         if (!(val & (1L << 31))) {
4036                 BNX2X_ERR("Cannot acquire nvram interface\n");
4037
4038                 rc = -EBUSY;
4039         }
4040
4041         return rc;
4042 }
4043
4044 /* Release split MCP access lock register */
4045 static void bnx2x_unlock_alr(struct bnx2x *bp)
4046 {
4047         u32 val = 0;
4048
4049         REG_WR(bp, GRCBASE_MCP + 0x9c, val);
4050 }
4051
4052 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
4053 {
4054         struct host_def_status_block *def_sb = bp->def_status_blk;
4055         u16 rc = 0;
4056
4057         barrier(); /* status block is written to by the chip */
4058
4059         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4060                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4061                 rc |= 1;
4062         }
4063         if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
4064                 bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
4065                 rc |= 2;
4066         }
4067         if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
4068                 bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
4069                 rc |= 4;
4070         }
4071         if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
4072                 bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
4073                 rc |= 8;
4074         }
4075         if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) {
4076                 bp->def_t_idx = def_sb->t_def_status_block.status_block_index;
4077                 rc |= 16;
4078         }
4079         return rc;
4080 }
4081
4082 /*
4083  * slow path service functions
4084  */
4085
4086 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
4087 {
4088         int port = bp->port;
4089         u32 igu_addr = (IGU_ADDR_ATTN_BITS_SET + IGU_PORT_BASE * port) * 8;
4090         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4091                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
4092         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
4093                                        NIG_REG_MASK_INTERRUPT_PORT0;
4094
4095         if (~bp->aeu_mask & (asserted & 0xff))
4096                 BNX2X_ERR("IGU ERROR\n");
4097         if (bp->attn_state & asserted)
4098                 BNX2X_ERR("IGU ERROR\n");
4099
4100         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
4101            bp->aeu_mask, asserted);
4102         bp->aeu_mask &= ~(asserted & 0xff);
4103         DP(NETIF_MSG_HW, "after masking: aeu_mask %x\n", bp->aeu_mask);
4104
4105         REG_WR(bp, aeu_addr, bp->aeu_mask);
4106
4107         bp->attn_state |= asserted;
4108
4109         if (asserted & ATTN_HARD_WIRED_MASK) {
4110                 if (asserted & ATTN_NIG_FOR_FUNC) {
4111
4112                         /* save nig interrupt mask */
4113                         bp->nig_mask = REG_RD(bp, nig_int_mask_addr);
4114                         REG_WR(bp, nig_int_mask_addr, 0);
4115
4116                         bnx2x_link_update(bp);
4117
4118                         /* handle unicore attn? */
4119                 }
4120                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4121                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4122
4123                 if (asserted & GPIO_2_FUNC)
4124                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4125
4126                 if (asserted & GPIO_3_FUNC)
4127                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4128
4129                 if (asserted & GPIO_4_FUNC)
4130                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4131
4132                 if (port == 0) {
4133                         if (asserted & ATTN_GENERAL_ATTN_1) {
4134                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4135                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4136                         }
4137                         if (asserted & ATTN_GENERAL_ATTN_2) {
4138                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4139                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4140                         }
4141                         if (asserted & ATTN_GENERAL_ATTN_3) {
4142                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4143                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4144                         }
4145                 } else {
4146                         if (asserted & ATTN_GENERAL_ATTN_4) {
4147                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4148                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4149                         }
4150                         if (asserted & ATTN_GENERAL_ATTN_5) {
4151                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4152                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4153                         }
4154                         if (asserted & ATTN_GENERAL_ATTN_6) {
4155                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4156                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4157                         }
4158                 }
4159
4160         } /* if hardwired */
4161
4162         DP(NETIF_MSG_HW, "about to mask 0x%08x at IGU addr 0x%x\n",
4163            asserted, BAR_IGU_INTMEM + igu_addr);
4164         REG_WR(bp, BAR_IGU_INTMEM + igu_addr, asserted);
4165
4166         /* now set back the mask */
4167         if (asserted & ATTN_NIG_FOR_FUNC)
4168                 REG_WR(bp, nig_int_mask_addr, bp->nig_mask);
4169 }
4170
4171 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4172 {
4173         int port = bp->port;
4174         int reg_offset;
4175         u32 val;
4176
4177         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4178
4179                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4180                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4181
4182                 val = REG_RD(bp, reg_offset);
4183                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4184                 REG_WR(bp, reg_offset, val);
4185
4186                 BNX2X_ERR("SPIO5 hw attention\n");
4187
4188                 switch (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
4189                 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
4190                         /* Fan failure attention */
4191
4192                         /* The PHY reset is controled by GPIO 1 */
4193                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4194                                        MISC_REGISTERS_GPIO_OUTPUT_LOW);
4195                         /* Low power mode is controled by GPIO 2 */
4196                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4197                                        MISC_REGISTERS_GPIO_OUTPUT_LOW);
4198                         /* mark the failure */
4199                         bp->ext_phy_config &=
4200                                         ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4201                         bp->ext_phy_config |=
4202                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4203                         SHMEM_WR(bp,
4204                                  dev_info.port_hw_config[port].
4205                                                         external_phy_config,
4206                                  bp->ext_phy_config);
4207                         /* log the failure */
4208                         printk(KERN_ERR PFX "Fan Failure on Network"
4209                                " Controller %s has caused the driver to"
4210                                " shutdown the card to prevent permanent"
4211                                " damage.  Please contact Dell Support for"
4212                                " assistance\n", bp->dev->name);
4213                         break;
4214
4215                 default:
4216                         break;
4217                 }
4218         }
4219 }
4220
4221 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4222 {
4223         u32 val;
4224
4225         if (attn & BNX2X_DOORQ_ASSERT) {
4226
4227                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4228                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4229                 /* DORQ discard attention */
4230                 if (val & 0x2)
4231                         BNX2X_ERR("FATAL error from DORQ\n");
4232         }
4233 }
4234
4235 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4236 {
4237         u32 val;
4238
4239         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4240
4241                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4242                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4243                 /* CFC error attention */
4244                 if (val & 0x2)
4245                         BNX2X_ERR("FATAL error from CFC\n");
4246         }
4247
4248         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4249
4250                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4251                 BNX2X_ERR("PXP hw attention 0x%x\n", val);
4252                 /* RQ_USDMDP_FIFO_OVERFLOW */
4253                 if (val & 0x18000)
4254                         BNX2X_ERR("FATAL error from PXP\n");
4255         }
4256 }
4257
4258 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4259 {
4260         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4261
4262                 if (attn & BNX2X_MC_ASSERT_BITS) {
4263
4264                         BNX2X_ERR("MC assert!\n");
4265                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4266                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4267                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4268                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4269                         bnx2x_panic();
4270
4271                 } else if (attn & BNX2X_MCP_ASSERT) {
4272
4273                         BNX2X_ERR("MCP assert!\n");
4274                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4275                         bnx2x_mc_assert(bp);
4276
4277                 } else
4278                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4279         }
4280
4281         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4282
4283                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4284                 BNX2X_ERR("LATCHED attention 0x%x (masked)\n", attn);
4285         }
4286 }
4287
4288 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4289 {
4290         struct attn_route attn;
4291         struct attn_route group_mask;
4292         int port = bp->port;
4293         int index;
4294         u32 reg_addr;
4295         u32 val;
4296
4297         /* need to take HW lock because MCP or other port might also
4298            try to handle this event */
4299         bnx2x_lock_alr(bp);
4300
4301         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4302         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4303         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4304         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4305         DP(NETIF_MSG_HW, "attn %llx\n", (unsigned long long)attn.sig[0]);
4306
4307         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4308                 if (deasserted & (1 << index)) {
4309                         group_mask = bp->attn_group[index];
4310
4311                         DP(NETIF_MSG_HW, "group[%d]: %llx\n", index,
4312                            (unsigned long long)group_mask.sig[0]);
4313
4314                         bnx2x_attn_int_deasserted3(bp,
4315                                         attn.sig[3] & group_mask.sig[3]);
4316                         bnx2x_attn_int_deasserted1(bp,
4317                                         attn.sig[1] & group_mask.sig[1]);
4318                         bnx2x_attn_int_deasserted2(bp,
4319                                         attn.sig[2] & group_mask.sig[2]);
4320                         bnx2x_attn_int_deasserted0(bp,
4321                                         attn.sig[0] & group_mask.sig[0]);
4322
4323                         if ((attn.sig[0] & group_mask.sig[0] &
4324                                                 HW_INTERRUT_ASSERT_SET_0) ||
4325                             (attn.sig[1] & group_mask.sig[1] &
4326                                                 HW_INTERRUT_ASSERT_SET_1) ||
4327                             (attn.sig[2] & group_mask.sig[2] &
4328                                                 HW_INTERRUT_ASSERT_SET_2))
4329                                 BNX2X_ERR("FATAL HW block attention"
4330                                           "  set0 0x%x  set1 0x%x"
4331                                           "  set2 0x%x\n",
4332                                           (attn.sig[0] & group_mask.sig[0] &
4333                                            HW_INTERRUT_ASSERT_SET_0),
4334                                           (attn.sig[1] & group_mask.sig[1] &
4335                                            HW_INTERRUT_ASSERT_SET_1),
4336                                           (attn.sig[2] & group_mask.sig[2] &
4337                                            HW_INTERRUT_ASSERT_SET_2));
4338
4339                         if ((attn.sig[0] & group_mask.sig[0] &
4340                                                 HW_PRTY_ASSERT_SET_0) ||
4341                             (attn.sig[1] & group_mask.sig[1] &
4342                                                 HW_PRTY_ASSERT_SET_1) ||
4343                             (attn.sig[2] & group_mask.sig[2] &
4344                                                 HW_PRTY_ASSERT_SET_2))
4345                                BNX2X_ERR("FATAL HW block parity attention\n");
4346                 }
4347         }
4348
4349         bnx2x_unlock_alr(bp);
4350
4351         reg_addr = (IGU_ADDR_ATTN_BITS_CLR + IGU_PORT_BASE * port) * 8;
4352
4353         val = ~deasserted;
4354 /*      DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
4355            val, BAR_IGU_INTMEM + reg_addr); */
4356         REG_WR(bp, BAR_IGU_INTMEM + reg_addr, val);
4357
4358         if (bp->aeu_mask & (deasserted & 0xff))
4359                 BNX2X_ERR("IGU BUG\n");
4360         if (~bp->attn_state & deasserted)
4361                 BNX2X_ERR("IGU BUG\n");
4362
4363         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4364                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
4365
4366         DP(NETIF_MSG_HW, "aeu_mask %x\n", bp->aeu_mask);
4367         bp->aeu_mask |= (deasserted & 0xff);
4368
4369         DP(NETIF_MSG_HW, "new mask %x\n", bp->aeu_mask);
4370         REG_WR(bp, reg_addr, bp->aeu_mask);
4371
4372         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4373         bp->attn_state &= ~deasserted;
4374         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4375 }
4376
4377 static void bnx2x_attn_int(struct bnx2x *bp)
4378 {
4379         /* read local copy of bits */
4380         u32 attn_bits = bp->def_status_blk->atten_status_block.attn_bits;
4381         u32 attn_ack = bp->def_status_blk->atten_status_block.attn_bits_ack;
4382         u32 attn_state = bp->attn_state;
4383
4384         /* look for changed bits */
4385         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
4386         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
4387
4388         DP(NETIF_MSG_HW,
4389            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
4390            attn_bits, attn_ack, asserted, deasserted);
4391
4392         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4393                 BNX2X_ERR("bad attention state\n");
4394
4395         /* handle bits that were raised */
4396         if (asserted)
4397                 bnx2x_attn_int_asserted(bp, asserted);
4398
4399         if (deasserted)
4400                 bnx2x_attn_int_deasserted(bp, deasserted);
4401 }
4402
4403 static void bnx2x_sp_task(struct work_struct *work)
4404 {
4405         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task);
4406         u16 status;
4407
4408         /* Return here if interrupt is disabled */
4409         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
4410                 DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n");
4411                 return;
4412         }
4413
4414         status = bnx2x_update_dsb_idx(bp);
4415         if (status == 0)
4416                 BNX2X_ERR("spurious slowpath interrupt!\n");
4417
4418         DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status);
4419
4420         /* HW attentions */
4421         if (status & 0x1)
4422                 bnx2x_attn_int(bp);
4423
4424         /* CStorm events: query_stats, port delete ramrod */
4425         if (status & 0x2)
4426                 bp->stat_pending = 0;
4427
4428         bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, bp->def_att_idx,
4429                      IGU_INT_NOP, 1);
4430         bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
4431                      IGU_INT_NOP, 1);
4432         bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
4433                      IGU_INT_NOP, 1);
4434         bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
4435                      IGU_INT_NOP, 1);
4436         bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
4437                      IGU_INT_ENABLE, 1);
4438
4439 }
4440
4441 static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
4442 {
4443         struct net_device *dev = dev_instance;
4444         struct bnx2x *bp = netdev_priv(dev);
4445
4446         /* Return here if interrupt is disabled */
4447         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
4448                 DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n");
4449                 return IRQ_HANDLED;
4450         }
4451
4452         bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, 0, IGU_INT_DISABLE, 0);
4453
4454 #ifdef BNX2X_STOP_ON_ERROR
4455         if (unlikely(bp->panic))
4456                 return IRQ_HANDLED;
4457 #endif
4458
4459         schedule_work(&bp->sp_task);
4460
4461         return IRQ_HANDLED;
4462 }
4463
4464 /* end of slow path */
4465
4466 /* Statistics */
4467
4468 /****************************************************************************
4469 * Macros
4470 ****************************************************************************/
4471
4472 #define UPDATE_STAT(s, t) \
4473         do { \
4474                 estats->t += new->s - old->s; \
4475                 old->s = new->s; \
4476         } while (0)
4477
4478 /* sum[hi:lo] += add[hi:lo] */
4479 #define ADD_64(s_hi, a_hi, s_lo, a_lo) \
4480         do { \
4481                 s_lo += a_lo; \
4482                 s_hi += a_hi + (s_lo < a_lo) ? 1 : 0; \
4483         } while (0)
4484
4485 /* difference = minuend - subtrahend */
4486 #define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
4487         do { \
4488                 if (m_lo < s_lo) {      /* underflow */ \
4489                         d_hi = m_hi - s_hi; \
4490                         if (d_hi > 0) { /* we can 'loan' 1 */ \
4491                                 d_hi--; \
4492                                 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
4493                         } else {        /* m_hi <= s_hi */ \
4494                                 d_hi = 0; \
4495                                 d_lo = 0; \
4496                         } \
4497                 } else {                /* m_lo >= s_lo */ \
4498                         if (m_hi < s_hi) { \
4499                             d_hi = 0; \
4500                             d_lo = 0; \
4501                         } else {        /* m_hi >= s_hi */ \
4502                             d_hi = m_hi - s_hi; \
4503                             d_lo = m_lo - s_lo; \
4504                         } \
4505                 } \
4506         } while (0)
4507
4508 /* minuend -= subtrahend */
4509 #define SUB_64(m_hi, s_hi, m_lo, s_lo) \
4510         do { \
4511                 DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \
4512         } while (0)
4513
4514 #define UPDATE_STAT64(s_hi, t_hi, s_lo, t_lo) \
4515         do { \
4516                 DIFF_64(diff.hi, new->s_hi, old->s_hi, \
4517                         diff.lo, new->s_lo, old->s_lo); \
4518                 old->s_hi = new->s_hi; \
4519                 old->s_lo = new->s_lo; \
4520                 ADD_64(estats->t_hi, diff.hi, \
4521                        estats->t_lo, diff.lo); \
4522         } while (0)
4523
4524 /* sum[hi:lo] += add */
4525 #define ADD_EXTEND_64(s_hi, s_lo, a) \
4526         do { \
4527                 s_lo += a; \
4528                 s_hi += (s_lo < a) ? 1 : 0; \
4529         } while (0)
4530
4531 #define UPDATE_EXTEND_STAT(s, t_hi, t_lo) \
4532         do { \
4533                 ADD_EXTEND_64(estats->t_hi, estats->t_lo, new->s); \
4534         } while (0)
4535
4536 #define UPDATE_EXTEND_TSTAT(s, t_hi, t_lo) \
4537         do { \
4538                 diff = le32_to_cpu(tclient->s) - old_tclient->s; \
4539                 old_tclient->s = le32_to_cpu(tclient->s); \
4540                 ADD_EXTEND_64(estats->t_hi, estats->t_lo, diff); \
4541         } while (0)
4542
4543 /*
4544  * General service functions
4545  */
4546
4547 static inline long bnx2x_hilo(u32 *hiref)
4548 {
4549         u32 lo = *(hiref + 1);
4550 #if (BITS_PER_LONG == 64)
4551         u32 hi = *hiref;
4552
4553         return HILO_U64(hi, lo);
4554 #else
4555         return lo;
4556 #endif
4557 }
4558
4559 /*
4560  * Init service functions
4561  */
4562
4563 static void bnx2x_init_mac_stats(struct bnx2x *bp)
4564 {
4565         struct dmae_command *dmae;
4566         int port = bp->port;
4567         int loader_idx = port * 8;
4568         u32 opcode;
4569         u32 mac_addr;
4570
4571         bp->executer_idx = 0;
4572         if (bp->fw_mb) {
4573                 /* MCP */
4574                 opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
4575                           DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
4576 #ifdef __BIG_ENDIAN
4577                           DMAE_CMD_ENDIANITY_B_DW_SWAP |
4578 #else
4579                           DMAE_CMD_ENDIANITY_DW_SWAP |
4580 #endif
4581                           (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
4582
4583                 if (bp->link_up)
4584                         opcode |= (DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE);
4585
4586                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4587                 dmae->opcode = opcode;
4588                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, eth_stats) +
4589                                            sizeof(u32));
4590                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, eth_stats) +
4591                                            sizeof(u32));
4592                 dmae->dst_addr_lo = bp->fw_mb >> 2;
4593                 dmae->dst_addr_hi = 0;
4594                 dmae->len = (offsetof(struct bnx2x_eth_stats, mac_stx_end) -
4595                              sizeof(u32)) >> 2;
4596                 if (bp->link_up) {
4597                         dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4598                         dmae->comp_addr_hi = 0;
4599                         dmae->comp_val = 1;
4600                 } else {
4601                         dmae->comp_addr_lo = 0;
4602                         dmae->comp_addr_hi = 0;
4603                         dmae->comp_val = 0;
4604                 }
4605         }
4606
4607         if (!bp->link_up) {
4608                 /* no need to collect statistics in link down */
4609                 return;
4610         }
4611
4612         opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
4613                   DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
4614                   DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
4615 #ifdef __BIG_ENDIAN
4616                   DMAE_CMD_ENDIANITY_B_DW_SWAP |
4617 #else
4618                   DMAE_CMD_ENDIANITY_DW_SWAP |
4619 #endif
4620                   (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
4621
4622         if (bp->phy_flags & PHY_BMAC_FLAG) {
4623
4624                 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
4625                                    NIG_REG_INGRESS_BMAC0_MEM);
4626
4627                 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
4628                    BIGMAC_REGISTER_TX_STAT_GTBYT */
4629                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4630                 dmae->opcode = opcode;
4631                 dmae->src_addr_lo = (mac_addr +
4632                                      BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
4633                 dmae->src_addr_hi = 0;
4634                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
4635                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
4636                 dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
4637                              BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
4638                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4639                 dmae->comp_addr_hi = 0;
4640                 dmae->comp_val = 1;
4641
4642                 /* BIGMAC_REGISTER_RX_STAT_GR64 ..
4643                    BIGMAC_REGISTER_RX_STAT_GRIPJ */
4644                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4645                 dmae->opcode = opcode;
4646                 dmae->src_addr_lo = (mac_addr +
4647                                      BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
4648                 dmae->src_addr_hi = 0;
4649                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
4650                                         offsetof(struct bmac_stats, rx_gr64));
4651                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
4652                                         offsetof(struct bmac_stats, rx_gr64));
4653                 dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
4654                              BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
4655                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4656                 dmae->comp_addr_hi = 0;
4657                 dmae->comp_val = 1;
4658
4659         } else if (bp->phy_flags & PHY_EMAC_FLAG) {
4660
4661                 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
4662
4663                 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
4664                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4665                 dmae->opcode = opcode;
4666                 dmae->src_addr_lo = (mac_addr +
4667                                      EMAC_REG_EMAC_RX_STAT_AC) >> 2;
4668                 dmae->src_addr_hi = 0;
4669                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
4670                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
4671                 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
4672                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4673                 dmae->comp_addr_hi = 0;
4674                 dmae->comp_val = 1;
4675
4676                 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
4677                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4678                 dmae->opcode = opcode;
4679                 dmae->src_addr_lo = (mac_addr +
4680                                      EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
4681                 dmae->src_addr_hi = 0;
4682                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
4683                                            offsetof(struct emac_stats,
4684                                                     rx_falsecarriererrors));
4685                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
4686                                            offsetof(struct emac_stats,
4687                                                     rx_falsecarriererrors));
4688                 dmae->len = 1;
4689                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4690                 dmae->comp_addr_hi = 0;
4691                 dmae->comp_val = 1;
4692
4693                 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
4694                 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4695                 dmae->opcode = opcode;
4696                 dmae->src_addr_lo = (mac_addr +
4697                                      EMAC_REG_EMAC_TX_STAT_AC) >> 2;
4698                 dmae->src_addr_hi = 0;
4699                 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
4700                                            offsetof(struct emac_stats,
4701                                                     tx_ifhcoutoctets));
4702                 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
4703                                            offsetof(struct emac_stats,
4704                                                     tx_ifhcoutoctets));
4705                 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
4706                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4707                 dmae->comp_addr_hi = 0;
4708                 dmae->comp_val = 1;
4709         }
4710
4711         /* NIG */
4712         dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4713         dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
4714                         DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
4715                         DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
4716 #ifdef __BIG_ENDIAN
4717                         DMAE_CMD_ENDIANITY_B_DW_SWAP |
4718 #else
4719                         DMAE_CMD_ENDIANITY_DW_SWAP |
4720 #endif
4721                         (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
4722         dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
4723                                     NIG_REG_STAT0_BRB_DISCARD) >> 2;
4724         dmae->src_addr_hi = 0;
4725         dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig));
4726         dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig));
4727         dmae->len = (sizeof(struct nig_stats) - 2*sizeof(u32)) >> 2;
4728         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig) +
4729                                     offsetof(struct nig_stats, done));
4730         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig) +
4731                                     offsetof(struct nig_stats, done));
4732         dmae->comp_val = 0xffffffff;
4733 }
4734
4735 static void bnx2x_init_stats(struct bnx2x *bp)
4736 {
4737         int port = bp->port;
4738
4739         bp->stats_state = STATS_STATE_DISABLE;
4740         bp->executer_idx = 0;
4741
4742         bp->old_brb_discard = REG_RD(bp,
4743                                      NIG_REG_STAT0_BRB_DISCARD + port*0x38);
4744
4745         memset(&bp->old_bmac, 0, sizeof(struct bmac_stats));
4746         memset(&bp->old_tclient, 0, sizeof(struct tstorm_per_client_stats));
4747         memset(&bp->dev->stats, 0, sizeof(struct net_device_stats));
4748
4749         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port), 1);
4750         REG_WR(bp, BAR_XSTRORM_INTMEM +
4751                XSTORM_STATS_FLAGS_OFFSET(port) + 4, 0);
4752
4753         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(port), 1);
4754         REG_WR(bp, BAR_TSTRORM_INTMEM +
4755                TSTORM_STATS_FLAGS_OFFSET(port) + 4, 0);
4756
4757         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(port), 0);
4758         REG_WR(bp, BAR_CSTRORM_INTMEM +
4759                CSTORM_STATS_FLAGS_OFFSET(port) + 4, 0);
4760
4761         REG_WR(bp, BAR_XSTRORM_INTMEM +
4762                XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port),
4763                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4764         REG_WR(bp, BAR_XSTRORM_INTMEM +
4765                XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port) + 4,
4766                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4767
4768         REG_WR(bp, BAR_TSTRORM_INTMEM +
4769                TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port),
4770                U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4771         REG_WR(bp, BAR_TSTRORM_INTMEM +
4772                TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port) + 4,
4773                U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4774 }
4775
4776 static void bnx2x_stop_stats(struct bnx2x *bp)
4777 {
4778         might_sleep();
4779         if (bp->stats_state != STATS_STATE_DISABLE) {
4780                 int timeout = 10;
4781
4782                 bp->stats_state = STATS_STATE_STOP;
4783                 DP(BNX2X_MSG_STATS, "stats_state - STOP\n");
4784
4785                 while (bp->stats_state != STATS_STATE_DISABLE) {
4786                         if (!timeout) {
4787                                 BNX2X_ERR("timeout waiting for stats stop\n");
4788                                 break;
4789                         }
4790                         timeout--;
4791                         msleep(100);
4792                 }
4793         }
4794         DP(BNX2X_MSG_STATS, "stats_state - DISABLE\n");
4795 }
4796
4797 /*
4798  * Statistics service functions
4799  */
4800
4801 static void bnx2x_update_bmac_stats(struct bnx2x *bp)
4802 {
4803         struct regp diff;
4804         struct regp sum;
4805         struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac);
4806         struct bmac_stats *old = &bp->old_bmac;
4807         struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
4808
4809         sum.hi = 0;
4810         sum.lo = 0;
4811
4812         UPDATE_STAT64(tx_gtbyt.hi, total_bytes_transmitted_hi,
4813                       tx_gtbyt.lo, total_bytes_transmitted_lo);
4814
4815         UPDATE_STAT64(tx_gtmca.hi, total_multicast_packets_transmitted_hi,
4816                       tx_gtmca.lo, total_multicast_packets_transmitted_lo);
4817         ADD_64(sum.hi, diff.hi, sum.lo, diff.lo);
4818
4819         UPDATE_STAT64(tx_gtgca.hi, total_broadcast_packets_transmitted_hi,
4820                       tx_gtgca.lo, total_broadcast_packets_transmitted_lo);
4821         ADD_64(sum.hi, diff.hi, sum.lo, diff.lo);
4822
4823         UPDATE_STAT64(tx_gtpkt.hi, total_unicast_packets_transmitted_hi,
4824                       tx_gtpkt.lo, total_unicast_packets_transmitted_lo);
4825         SUB_64(estats->total_unicast_packets_transmitted_hi, sum.hi,
4826                estats->total_unicast_packets_transmitted_lo, sum.lo);
4827
4828         UPDATE_STAT(tx_gtxpf.lo, pause_xoff_frames_transmitted);
4829         UPDATE_STAT(tx_gt64.lo, frames_transmitted_64_bytes);
4830         UPDATE_STAT(tx_gt127.lo, frames_transmitted_65_127_bytes);
4831         UPDATE_STAT(tx_gt255.lo, frames_transmitted_128_255_bytes);
4832         UPDATE_STAT(tx_gt511.lo, frames_transmitted_256_511_bytes);
4833         UPDATE_STAT(tx_gt1023.lo, frames_transmitted_512_1023_bytes);
4834         UPDATE_STAT(tx_gt1518.lo, frames_transmitted_1024_1522_bytes);
4835         UPDATE_STAT(tx_gt2047.lo, frames_transmitted_1523_9022_bytes);
4836         UPDATE_STAT(tx_gt4095.lo, frames_transmitted_1523_9022_bytes);
4837         UPDATE_STAT(tx_gt9216.lo, frames_transmitted_1523_9022_bytes);
4838         UPDATE_STAT(tx_gt16383.lo, frames_transmitted_1523_9022_bytes);
4839
4840         UPDATE_STAT(rx_grfcs.lo, crc_receive_errors);
4841         UPDATE_STAT(rx_grund.lo, runt_packets_received);
4842         UPDATE_STAT(rx_grovr.lo, stat_Dot3statsFramesTooLong);
4843         UPDATE_STAT(rx_grxpf.lo, pause_xoff_frames_received);
4844         UPDATE_STAT(rx_grxcf.lo, control_frames_received);
4845         /* UPDATE_STAT(rx_grxpf.lo, control_frames_received); */
4846         UPDATE_STAT(rx_grfrg.lo, error_runt_packets_received);
4847         UPDATE_STAT(rx_grjbr.lo, error_jabber_packets_received);
4848
4849         UPDATE_STAT64(rx_grerb.hi, stat_IfHCInBadOctets_hi,
4850                       rx_grerb.lo, stat_IfHCInBadOctets_lo);
4851         UPDATE_STAT64(tx_gtufl.hi, stat_IfHCOutBadOctets_hi,
4852                       tx_gtufl.lo, stat_IfHCOutBadOctets_lo);
4853         UPDATE_STAT(tx_gterr.lo, stat_Dot3statsInternalMacTransmitErrors);
4854         /* UPDATE_STAT(rx_grxpf.lo, stat_XoffStateEntered); */
4855         estats->stat_XoffStateEntered = estats->pause_xoff_frames_received;
4856 }
4857
4858 static void bnx2x_update_emac_stats(struct bnx2x *bp)
4859 {
4860         struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac);
4861         struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
4862
4863         UPDATE_EXTEND_STAT(tx_ifhcoutoctets, total_bytes_transmitted_hi,
4864                                              total_bytes_transmitted_lo);
4865         UPDATE_EXTEND_STAT(tx_ifhcoutucastpkts,
4866                                         total_unicast_packets_transmitted_hi,
4867                                         total_unicast_packets_transmitted_lo);
4868         UPDATE_EXTEND_STAT(tx_ifhcoutmulticastpkts,
4869                                       total_multicast_packets_transmitted_hi,
4870                                       total_multicast_packets_transmitted_lo);
4871         UPDATE_EXTEND_STAT(tx_ifhcoutbroadcastpkts,
4872                                       total_broadcast_packets_transmitted_hi,
4873                                       total_broadcast_packets_transmitted_lo);
4874
4875         estats->pause_xon_frames_transmitted += new->tx_outxonsent;
4876         estats->pause_xoff_frames_transmitted += new->tx_outxoffsent;
4877         estats->single_collision_transmit_frames +=
4878                                 new->tx_dot3statssinglecollisionframes;
4879         estats->multiple_collision_transmit_frames +=
4880                                 new->tx_dot3statsmultiplecollisionframes;
4881         estats->late_collision_frames += new->tx_dot3statslatecollisions;
4882         estats->excessive_collision_frames +=
4883                                 new->tx_dot3statsexcessivecollisions;
4884         estats->frames_transmitted_64_bytes += new->tx_etherstatspkts64octets;
4885         estats->frames_transmitted_65_127_bytes +=
4886                                 new->tx_etherstatspkts65octetsto127octets;
4887         estats->frames_transmitted_128_255_bytes +=
4888                                 new->tx_etherstatspkts128octetsto255octets;
4889         estats->frames_transmitted_256_511_bytes +=
4890                                 new->tx_etherstatspkts256octetsto511octets;
4891         estats->frames_transmitted_512_1023_bytes +=
4892                                 new->tx_etherstatspkts512octetsto1023octets;
4893         estats->frames_transmitted_1024_1522_bytes +=
4894                                 new->tx_etherstatspkts1024octetsto1522octet;
4895         estats->frames_transmitted_1523_9022_bytes +=
4896                                 new->tx_etherstatspktsover1522octets;
4897
4898         estats->crc_receive_errors += new->rx_dot3statsfcserrors;
4899         estats->alignment_errors += new->rx_dot3statsalignmenterrors;
4900         estats->false_carrier_detections += new->rx_falsecarriererrors;
4901         estats->runt_packets_received += new->rx_etherstatsundersizepkts;
4902         estats->stat_Dot3statsFramesTooLong += new->rx_dot3statsframestoolong;
4903         estats->pause_xon_frames_received += new->rx_xonpauseframesreceived;
4904         estats->pause_xoff_frames_received += new->rx_xoffpauseframesreceived;
4905         estats->control_frames_received += new->rx_maccontrolframesreceived;
4906         estats->error_runt_packets_received += new->rx_etherstatsfragments;
4907         estats->error_jabber_packets_received += new->rx_etherstatsjabbers;
4908
4909         UPDATE_EXTEND_STAT(rx_ifhcinbadoctets, stat_IfHCInBadOctets_hi,
4910                                                stat_IfHCInBadOctets_lo);
4911         UPDATE_EXTEND_STAT(tx_ifhcoutbadoctets, stat_IfHCOutBadOctets_hi,
4912                                                 stat_IfHCOutBadOctets_lo);
4913         estats->stat_Dot3statsInternalMacTransmitErrors +=
4914                                 new->tx_dot3statsinternalmactransmiterrors;
4915         estats->stat_Dot3StatsCarrierSenseErrors +=
4916                                 new->rx_dot3statscarriersenseerrors;
4917         estats->stat_Dot3StatsDeferredTransmissions +=
4918                                 new->tx_dot3statsdeferredtransmissions;
4919         estats->stat_FlowControlDone += new->tx_flowcontroldone;
4920         estats->stat_XoffStateEntered += new->rx_xoffstateentered;
4921 }
4922
4923 static int bnx2x_update_storm_stats(struct bnx2x *bp)
4924 {
4925         struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
4926         struct tstorm_common_stats *tstats = &stats->tstorm_common;
4927         struct tstorm_per_client_stats *tclient =
4928                                                 &tstats->client_statistics[0];
4929         struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
4930         struct xstorm_common_stats *xstats = &stats->xstorm_common;
4931         struct nig_stats *nstats = bnx2x_sp(bp, nig);
4932         struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
4933         u32 diff;
4934
4935         /* are DMAE stats valid? */
4936         if (nstats->done != 0xffffffff) {
4937                 DP(BNX2X_MSG_STATS, "stats not updated by dmae\n");
4938                 return -1;
4939         }
4940
4941         /* are storm stats valid? */
4942         if (tstats->done.hi != 0xffffffff) {
4943                 DP(BNX2X_MSG_STATS, "stats not updated by tstorm\n");
4944                 return -2;
4945         }
4946         if (xstats->done.hi != 0xffffffff) {
4947                 DP(BNX2X_MSG_STATS, "stats not updated by xstorm\n");
4948                 return -3;
4949         }
4950
4951         estats->total_bytes_received_hi =
4952         estats->valid_bytes_received_hi =
4953                                 le32_to_cpu(tclient->total_rcv_bytes.hi);
4954         estats->total_bytes_received_lo =
4955         estats->valid_bytes_received_lo =
4956                                 le32_to_cpu(tclient->total_rcv_bytes.lo);
4957         ADD_64(estats->total_bytes_received_hi,
4958                le32_to_cpu(tclient->rcv_error_bytes.hi),
4959                estats->total_bytes_received_lo,
4960                le32_to_cpu(tclient->rcv_error_bytes.lo));
4961
4962         UPDATE_EXTEND_TSTAT(rcv_unicast_pkts,
4963                                         total_unicast_packets_received_hi,
4964                                         total_unicast_packets_received_lo);
4965         UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
4966                                         total_multicast_packets_received_hi,
4967                                         total_multicast_packets_received_lo);
4968         UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
4969                                         total_broadcast_packets_received_hi,
4970                                         total_broadcast_packets_received_lo);
4971
4972         estats->frames_received_64_bytes = MAC_STX_NA;
4973         estats->frames_received_65_127_bytes = MAC_STX_NA;
4974         estats->frames_received_128_255_bytes = MAC_STX_NA;
4975         estats->frames_received_256_511_bytes = MAC_STX_NA;
4976         estats->frames_received_512_1023_bytes = MAC_STX_NA;
4977         estats->frames_received_1024_1522_bytes = MAC_STX_NA;
4978         estats->frames_received_1523_9022_bytes = MAC_STX_NA;
4979
4980         estats->x_total_sent_bytes_hi =
4981                                 le32_to_cpu(xstats->total_sent_bytes.hi);
4982         estats->x_total_sent_bytes_lo =
4983                                 le32_to_cpu(xstats->total_sent_bytes.lo);
4984         estats->x_total_sent_pkts = le32_to_cpu(xstats->total_sent_pkts);
4985
4986         estats->t_rcv_unicast_bytes_hi =
4987                                 le32_to_cpu(tclient->rcv_unicast_bytes.hi);
4988         estats->t_rcv_unicast_bytes_lo =
4989                                 le32_to_cpu(tclient->rcv_unicast_bytes.lo);
4990         estats->t_rcv_broadcast_bytes_hi =
4991                                 le32_to_cpu(tclient->rcv_broadcast_bytes.hi);
4992         estats->t_rcv_broadcast_bytes_lo =
4993                                 le32_to_cpu(tclient->rcv_broadcast_bytes.lo);
4994         estats->t_rcv_multicast_bytes_hi =
4995                                 le32_to_cpu(tclient->rcv_multicast_bytes.hi);
4996         estats->t_rcv_multicast_bytes_lo =
4997                                 le32_to_cpu(tclient->rcv_multicast_bytes.lo);
4998         estats->t_total_rcv_pkt = le32_to_cpu(tclient->total_rcv_pkts);
4999
5000         estats->checksum_discard = le32_to_cpu(tclient->checksum_discard);
5001         estats->packets_too_big_discard =
5002                                 le32_to_cpu(tclient->packets_too_big_discard);
5003         estats->jabber_packets_received = estats->packets_too_big_discard +
5004                                           estats->stat_Dot3statsFramesTooLong;
5005         estats->no_buff_discard = le32_to_cpu(tclient->no_buff_discard);
5006         estats->ttl0_discard = le32_to_cpu(tclient->ttl0_discard);
5007         estats->mac_discard = le32_to_cpu(tclient->mac_discard);
5008         estats->mac_filter_discard = le32_to_cpu(tstats->mac_filter_discard);
5009         estats->xxoverflow_discard = le32_to_cpu(tstats->xxoverflow_discard);
5010         estats->brb_truncate_discard =
5011                                 le32_to_cpu(tstats->brb_truncate_discard);
5012
5013         estats->brb_discard += nstats->brb_discard - bp->old_brb_discard;
5014         bp->old_brb_discard = nstats->brb_discard;
5015
5016         estats->brb_packet = nstats->brb_packet;
5017         estats->brb_truncate = nstats->brb_truncate;
5018         estats->flow_ctrl_discard = nstats->flow_ctrl_discard;
5019         estats->flow_ctrl_octets = nstats->flow_ctrl_octets;
5020         estats->flow_ctrl_packet = nstats->flow_ctrl_packet;
5021         estats->mng_discard = nstats->mng_discard;
5022         estats->mng_octet_inp = nstats->mng_octet_inp;
5023         estats->mng_octet_out = nstats->mng_octet_out;
5024         estats->mng_packet_inp = nstats->mng_packet_inp;
5025         estats->mng_packet_out = nstats->mng_packet_out;
5026         estats->pbf_octets = nstats->pbf_octets;
5027         estats->pbf_packet = nstats->pbf_packet;
5028         estats->safc_inp = nstats->safc_inp;
5029
5030         xstats->done.hi = 0;
5031         tstats->done.hi = 0;
5032         nstats->done = 0;
5033
5034         return 0;
5035 }
5036
5037 static void bnx2x_update_net_stats(struct bnx2x *bp)
5038 {
5039         struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
5040         struct net_device_stats *nstats = &bp->dev->stats;
5041
5042         nstats->rx_packets =
5043                 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
5044                 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
5045                 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
5046
5047         nstats->tx_packets =
5048                 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
5049                 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
5050                 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
5051
5052         nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
5053
5054         nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
5055
5056         nstats->rx_dropped = estats->checksum_discard + estats->mac_discard;
5057         nstats->tx_dropped = 0;
5058
5059         nstats->multicast =
5060                 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi);
5061
5062         nstats->collisions = estats->single_collision_transmit_frames +
5063                              estats->multiple_collision_transmit_frames +
5064                              estats->late_collision_frames +
5065                              estats->excessive_collision_frames;
5066
5067         nstats->rx_length_errors = estats->runt_packets_received +
5068                                    estats->jabber_packets_received;
5069         nstats->rx_over_errors = estats->brb_discard +
5070                                  estats->brb_truncate_discard;
5071         nstats->rx_crc_errors = estats->crc_receive_errors;
5072         nstats->rx_frame_errors = estats->alignment_errors;
5073         nstats->rx_fifo_errors = estats->no_buff_discard;
5074         nstats->rx_missed_errors = estats->xxoverflow_discard;
5075
5076         nstats->rx_errors = nstats->rx_length_errors +
5077                             nstats->rx_over_errors +
5078                             nstats->rx_crc_errors +
5079                             nstats->rx_frame_errors +
5080                             nstats->rx_fifo_errors +
5081                             nstats->rx_missed_errors;
5082
5083         nstats->tx_aborted_errors = estats->late_collision_frames +
5084                                     estats->excessive_collision_frames;
5085         nstats->tx_carrier_errors = estats->false_carrier_detections;
5086         nstats->tx_fifo_errors = 0;
5087         nstats->tx_heartbeat_errors = 0;
5088         nstats->tx_window_errors = 0;
5089
5090         nstats->tx_errors = nstats->tx_aborted_errors +
5091                             nstats->tx_carrier_errors;
5092
5093         estats->mac_stx_start = ++estats->mac_stx_end;
5094 }
5095
5096 static void bnx2x_update_stats(struct bnx2x *bp)
5097 {
5098         int i;
5099
5100         if (!bnx2x_update_storm_stats(bp)) {
5101
5102                 if (bp->phy_flags & PHY_BMAC_FLAG) {
5103                         bnx2x_update_bmac_stats(bp);
5104
5105                 } else if (bp->phy_flags & PHY_EMAC_FLAG) {
5106                         bnx2x_update_emac_stats(bp);
5107
5108                 } else { /* unreached */
5109                         BNX2X_ERR("no MAC active\n");
5110                         return;
5111                 }
5112
5113                 bnx2x_update_net_stats(bp);
5114         }
5115
5116         if (bp->msglevel & NETIF_MSG_TIMER) {
5117                 struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
5118                 struct net_device_stats *nstats = &bp->dev->stats;
5119
5120                 printk(KERN_DEBUG "%s:\n", bp->dev->name);
5121                 printk(KERN_DEBUG "  tx avail (%4x)  tx hc idx (%x)"
5122                                   "  tx pkt (%lx)\n",
5123                        bnx2x_tx_avail(bp->fp),
5124                        *bp->fp->tx_cons_sb, nstats->tx_packets);
5125                 printk(KERN_DEBUG "  rx usage (%4x)  rx hc idx (%x)"
5126                                   "  rx pkt (%lx)\n",
5127                        (u16)(*bp->fp->rx_cons_sb - bp->fp->rx_comp_cons),
5128                        *bp->fp->rx_cons_sb, nstats->rx_packets);
5129                 printk(KERN_DEBUG "  %s (Xoff events %u)  brb drops %u\n",
5130                        netif_queue_stopped(bp->dev)? "Xoff" : "Xon",
5131                        estats->driver_xoff, estats->brb_discard);
5132                 printk(KERN_DEBUG "tstats: checksum_discard %u  "
5133                         "packets_too_big_discard %u  no_buff_discard %u  "
5134                         "mac_discard %u  mac_filter_discard %u  "
5135                         "xxovrflow_discard %u  brb_truncate_discard %u  "
5136                         "ttl0_discard %u\n",
5137                        estats->checksum_discard,
5138                        estats->packets_too_big_discard,
5139                        estats->no_buff_discard, estats->mac_discard,
5140                        estats->mac_filter_discard, estats->xxoverflow_discard,
5141                        estats->brb_truncate_discard, estats->ttl0_discard);
5142
5143                 for_each_queue(bp, i) {
5144                         printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i,
5145                                bnx2x_fp(bp, i, tx_pkt),
5146                                bnx2x_fp(bp, i, rx_pkt),
5147                                bnx2x_fp(bp, i, rx_calls));
5148                 }
5149         }
5150
5151         if (bp->state != BNX2X_STATE_OPEN) {
5152                 DP(BNX2X_MSG_STATS, "state is %x, returning\n", bp->state);
5153                 return;
5154         }
5155
5156 #ifdef BNX2X_STOP_ON_ERROR
5157         if (unlikely(bp->panic))
5158                 return;
5159 #endif
5160
5161         /* loader */
5162         if (bp->executer_idx) {
5163                 struct dmae_command *dmae = &bp->dmae;
5164                 int port = bp->port;
5165                 int loader_idx = port * 8;
5166
5167                 memset(dmae, 0, sizeof(struct dmae_command));
5168
5169                 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
5170                                 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
5171                                 DMAE_CMD_DST_RESET |
5172 #ifdef __BIG_ENDIAN
5173                                 DMAE_CMD_ENDIANITY_B_DW_SWAP |
5174 #else
5175                                 DMAE_CMD_ENDIANITY_DW_SWAP |
5176 #endif
5177                                 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
5178                 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
5179                 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
5180                 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
5181                                      sizeof(struct dmae_command) *
5182                                      (loader_idx + 1)) >> 2;
5183                 dmae->dst_addr_hi = 0;
5184                 dmae->len = sizeof(struct dmae_command) >> 2;
5185                 dmae->len--;    /* !!! for A0/1 only */
5186                 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
5187                 dmae->comp_addr_hi = 0;
5188                 dmae->comp_val = 1;
5189
5190                 bnx2x_post_dmae(bp, dmae, loader_idx);
5191         }
5192
5193         if (bp->stats_state != STATS_STATE_ENABLE) {
5194                 bp->stats_state = STATS_STATE_DISABLE;
5195                 return;
5196         }
5197
5198         if (bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0, 0, 0, 0) == 0) {
5199                 /* stats ramrod has it's own slot on the spe */
5200                 bp->spq_left++;
5201                 bp->stat_pending = 1;
5202         }
5203 }
5204
5205 static void bnx2x_timer(unsigned long data)
5206 {
5207         struct bnx2x *bp = (struct bnx2x *) data;
5208
5209         if (!netif_running(bp->dev))
5210                 return;
5211
5212         if (atomic_read(&bp->intr_sem) != 0)
5213                 goto timer_restart;
5214
5215         if (poll) {
5216                 struct bnx2x_fastpath *fp = &bp->fp[0];
5217                 int rc;
5218
5219                 bnx2x_tx_int(fp, 1000);
5220                 rc = bnx2x_rx_int(fp, 1000);
5221         }
5222
5223         if (!nomcp) {
5224                 int port = bp->port;
5225                 u32 drv_pulse;
5226                 u32 mcp_pulse;
5227
5228                 ++bp->fw_drv_pulse_wr_seq;
5229                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5230                 /* TBD - add SYSTEM_TIME */
5231                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5232                 SHMEM_WR(bp, func_mb[port].drv_pulse_mb, drv_pulse);
5233
5234                 mcp_pulse = (SHMEM_RD(bp, func_mb[port].mcp_pulse_mb) &
5235                              MCP_PULSE_SEQ_MASK);
5236                 /* The delta between driver pulse and mcp response
5237                  * should be 1 (before mcp response) or 0 (after mcp response)
5238                  */
5239                 if ((drv_pulse != mcp_pulse) &&
5240                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5241                         /* someone lost a heartbeat... */
5242                         BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5243                                   drv_pulse, mcp_pulse);
5244                 }
5245         }
5246
5247         if (bp->stats_state == STATS_STATE_DISABLE)
5248                 goto timer_restart;
5249
5250         bnx2x_update_stats(bp);
5251
5252 timer_restart:
5253         mod_timer(&bp->timer, jiffies + bp->current_interval);
5254 }
5255
5256 /* end of Statistics */
5257
5258 /* nic init */
5259
5260 /*
5261  * nic init service functions
5262  */
5263
5264 static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
5265                           dma_addr_t mapping, int id)
5266 {
5267         int port = bp->port;
5268         u64 section;
5269         int index;
5270
5271         /* USTORM */
5272         section = ((u64)mapping) + offsetof(struct host_status_block,
5273                                             u_status_block);
5274         sb->u_status_block.status_block_id = id;
5275
5276         REG_WR(bp, BAR_USTRORM_INTMEM +
5277                USTORM_SB_HOST_SB_ADDR_OFFSET(port, id), U64_LO(section));
5278         REG_WR(bp, BAR_USTRORM_INTMEM +
5279                ((USTORM_SB_HOST_SB_ADDR_OFFSET(port, id)) + 4),
5280                U64_HI(section));
5281
5282         for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
5283                 REG_WR16(bp, BAR_USTRORM_INTMEM +
5284                          USTORM_SB_HC_DISABLE_OFFSET(port, id, index), 0x1);
5285
5286         /* CSTORM */
5287         section = ((u64)mapping) + offsetof(struct host_status_block,
5288                                             c_status_block);
5289         sb->c_status_block.status_block_id = id;
5290
5291         REG_WR(bp, BAR_CSTRORM_INTMEM +
5292                CSTORM_SB_HOST_SB_ADDR_OFFSET(port, id), U64_LO(section));
5293         REG_WR(bp, BAR_CSTRORM_INTMEM +
5294                ((CSTORM_SB_HOST_SB_ADDR_OFFSET(port, id)) + 4),
5295                U64_HI(section));
5296
5297         for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
5298                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
5299                          CSTORM_SB_HC_DISABLE_OFFSET(port, id, index), 0x1);
5300
5301         bnx2x_ack_sb(bp, id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
5302 }
5303
5304 static void bnx2x_init_def_sb(struct bnx2x *bp,
5305                               struct host_def_status_block *def_sb,
5306                               dma_addr_t mapping, int id)
5307 {
5308         int port = bp->port;
5309         int index, val, reg_offset;
5310         u64 section;
5311
5312         /* ATTN */
5313         section = ((u64)mapping) + offsetof(struct host_def_status_block,
5314                                             atten_status_block);
5315         def_sb->atten_status_block.status_block_id = id;
5316
5317         bp->def_att_idx = 0;
5318         bp->attn_state = 0;
5319
5320         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5321                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5322
5323         for (index = 0; index < 3; index++) {
5324                 bp->attn_group[index].sig[0] = REG_RD(bp,
5325                                                      reg_offset + 0x10*index);
5326                 bp->attn_group[index].sig[1] = REG_RD(bp,
5327                                                reg_offset + 0x4 + 0x10*index);
5328                 bp->attn_group[index].sig[2] = REG_RD(bp,
5329                                                reg_offset + 0x8 + 0x10*index);
5330                 bp->attn_group[index].sig[3] = REG_RD(bp,
5331                                                reg_offset + 0xc + 0x10*index);
5332         }
5333
5334         bp->aeu_mask = REG_RD(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5335                                           MISC_REG_AEU_MASK_ATTN_FUNC_0));
5336
5337         reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5338                              HC_REG_ATTN_MSG0_ADDR_L);
5339
5340         REG_WR(bp, reg_offset, U64_LO(section));
5341         REG_WR(bp, reg_offset + 4, U64_HI(section));
5342
5343         reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);
5344
5345         val = REG_RD(bp, reg_offset);
5346         val |= id;
5347         REG_WR(bp, reg_offset, val);
5348
5349         /* USTORM */
5350         section = ((u64)mapping) + offsetof(struct host_def_status_block,
5351                                             u_def_status_block);
5352         def_sb->u_def_status_block.status_block_id = id;
5353
5354         bp->def_u_idx = 0;
5355
5356         REG_WR(bp, BAR_USTRORM_INTMEM +
5357                USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section));
5358         REG_WR(bp, BAR_USTRORM_INTMEM +
5359                ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)) + 4),
5360                U64_HI(section));
5361         REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port),
5362                BNX2X_BTR);
5363
5364         for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
5365                 REG_WR16(bp, BAR_USTRORM_INTMEM +
5366                          USTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1);
5367
5368         /* CSTORM */
5369         section = ((u64)mapping) + offsetof(struct host_def_status_block,
5370                                             c_def_status_block);
5371         def_sb->c_def_status_block.status_block_id = id;
5372
5373         bp->def_c_idx = 0;
5374
5375         REG_WR(bp, BAR_CSTRORM_INTMEM +
5376                CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section));
5377         REG_WR(bp, BAR_CSTRORM_INTMEM +
5378                ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)) + 4),
5379                U64_HI(section));
5380         REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port),
5381                BNX2X_BTR);
5382
5383         for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
5384                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
5385                          CSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1);
5386
5387         /* TSTORM */
5388         section = ((u64)mapping) + offsetof(struct host_def_status_block,
5389                                             t_def_status_block);
5390         def_sb->t_def_status_block.status_block_id = id;
5391
5392         bp->def_t_idx = 0;
5393
5394         REG_WR(bp, BAR_TSTRORM_INTMEM +
5395                TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section));
5396         REG_WR(bp, BAR_TSTRORM_INTMEM +
5397                ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)) + 4),
5398                U64_HI(section));
5399         REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port),
5400                BNX2X_BTR);
5401
5402         for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
5403                 REG_WR16(bp, BAR_TSTRORM_INTMEM +
5404                          TSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1);
5405
5406         /* XSTORM */
5407         section = ((u64)mapping) + offsetof(struct host_def_status_block,
5408                                             x_def_status_block);
5409         def_sb->x_def_status_block.status_block_id = id;
5410
5411         bp->def_x_idx = 0;
5412
5413         REG_WR(bp, BAR_XSTRORM_INTMEM +
5414                XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section));
5415         REG_WR(bp, BAR_XSTRORM_INTMEM +
5416                ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)) + 4),
5417                U64_HI(section));
5418         REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port),
5419                BNX2X_BTR);
5420
5421         for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
5422                 REG_WR16(bp, BAR_XSTRORM_INTMEM +
5423                          XSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1);
5424
5425         bp->stat_pending = 0;
5426
5427         bnx2x_ack_sb(bp, id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
5428 }
5429
5430 static void bnx2x_update_coalesce(struct bnx2x *bp)
5431 {
5432         int port = bp->port;
5433         int i;
5434
5435         for_each_queue(bp, i) {
5436
5437                 /* HC_INDEX_U_ETH_RX_CQ_CONS */
5438                 REG_WR8(bp, BAR_USTRORM_INTMEM +
5439                         USTORM_SB_HC_TIMEOUT_OFFSET(port, i,
5440                                                    HC_INDEX_U_ETH_RX_CQ_CONS),
5441                         bp->rx_ticks_int/12);
5442                 REG_WR16(bp, BAR_USTRORM_INTMEM +
5443                          USTORM_SB_HC_DISABLE_OFFSET(port, i,
5444                                                    HC_INDEX_U_ETH_RX_CQ_CONS),
5445                          bp->rx_ticks_int ? 0 : 1);
5446
5447                 /* HC_INDEX_C_ETH_TX_CQ_CONS */
5448                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
5449                         CSTORM_SB_HC_TIMEOUT_OFFSET(port, i,
5450                                                    HC_INDEX_C_ETH_TX_CQ_CONS),
5451                         bp->tx_ticks_int/12);
5452                 REG_WR16(bp, BAR_CSTRORM_INTMEM +
5453                          CSTORM_SB_HC_DISABLE_OFFSET(port, i,
5454                                                    HC_INDEX_C_ETH_TX_CQ_CONS),
5455                          bp->tx_ticks_int ? 0 : 1);
5456         }
5457 }
5458
5459 static void bnx2x_init_rx_rings(struct bnx2x *bp)
5460 {
5461         u16 ring_prod;
5462         int i, j;
5463         int port = bp->port;
5464
5465         bp->rx_buf_use_size = bp->dev->mtu;
5466
5467         bp->rx_buf_use_size += bp->rx_offset + ETH_OVREHEAD;
5468         bp->rx_buf_size = bp->rx_buf_use_size + 64;
5469
5470         for_each_queue(bp, j) {
5471                 struct bnx2x_fastpath *fp = &bp->fp[j];
5472
5473                 fp->rx_bd_cons = 0;
5474                 fp->rx_cons_sb = BNX