c0fa9c9edf089c1a039ded475fb13740cfa52d1f
[linux-2.6.git] / drivers / mtd / nand / pxa3xx_nand.c
1 /*
2  * drivers/mtd/nand/pxa3xx_nand.c
3  *
4  * Copyright © 2005 Intel Corporation
5  * Copyright © 2006 Marvell International Ltd.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/delay.h>
17 #include <linux/clk.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/io.h>
22 #include <linux/irq.h>
23 #include <asm/dma.h>
24
25 #include <mach/pxa-regs.h>
26 #include <mach/pxa3xx_nand.h>
27
28 #define CHIP_DELAY_TIMEOUT      (2 * HZ/10)
29
30 /* registers and bit definitions */
31 #define NDCR            (0x00) /* Control register */
32 #define NDTR0CS0        (0x04) /* Timing Parameter 0 for CS0 */
33 #define NDTR1CS0        (0x0C) /* Timing Parameter 1 for CS0 */
34 #define NDSR            (0x14) /* Status Register */
35 #define NDPCR           (0x18) /* Page Count Register */
36 #define NDBDR0          (0x1C) /* Bad Block Register 0 */
37 #define NDBDR1          (0x20) /* Bad Block Register 1 */
38 #define NDDB            (0x40) /* Data Buffer */
39 #define NDCB0           (0x48) /* Command Buffer0 */
40 #define NDCB1           (0x4C) /* Command Buffer1 */
41 #define NDCB2           (0x50) /* Command Buffer2 */
42
43 #define NDCR_SPARE_EN           (0x1 << 31)
44 #define NDCR_ECC_EN             (0x1 << 30)
45 #define NDCR_DMA_EN             (0x1 << 29)
46 #define NDCR_ND_RUN             (0x1 << 28)
47 #define NDCR_DWIDTH_C           (0x1 << 27)
48 #define NDCR_DWIDTH_M           (0x1 << 26)
49 #define NDCR_PAGE_SZ            (0x1 << 24)
50 #define NDCR_NCSX               (0x1 << 23)
51 #define NDCR_ND_MODE            (0x3 << 21)
52 #define NDCR_NAND_MODE          (0x0)
53 #define NDCR_CLR_PG_CNT         (0x1 << 20)
54 #define NDCR_CLR_ECC            (0x1 << 19)
55 #define NDCR_RD_ID_CNT_MASK     (0x7 << 16)
56 #define NDCR_RD_ID_CNT(x)       (((x) << 16) & NDCR_RD_ID_CNT_MASK)
57
58 #define NDCR_RA_START           (0x1 << 15)
59 #define NDCR_PG_PER_BLK         (0x1 << 14)
60 #define NDCR_ND_ARB_EN          (0x1 << 12)
61
62 #define NDSR_MASK               (0xfff)
63 #define NDSR_RDY                (0x1 << 11)
64 #define NDSR_CS0_PAGED          (0x1 << 10)
65 #define NDSR_CS1_PAGED          (0x1 << 9)
66 #define NDSR_CS0_CMDD           (0x1 << 8)
67 #define NDSR_CS1_CMDD           (0x1 << 7)
68 #define NDSR_CS0_BBD            (0x1 << 6)
69 #define NDSR_CS1_BBD            (0x1 << 5)
70 #define NDSR_DBERR              (0x1 << 4)
71 #define NDSR_SBERR              (0x1 << 3)
72 #define NDSR_WRDREQ             (0x1 << 2)
73 #define NDSR_RDDREQ             (0x1 << 1)
74 #define NDSR_WRCMDREQ           (0x1)
75
76 #define NDCB0_AUTO_RS           (0x1 << 25)
77 #define NDCB0_CSEL              (0x1 << 24)
78 #define NDCB0_CMD_TYPE_MASK     (0x7 << 21)
79 #define NDCB0_CMD_TYPE(x)       (((x) << 21) & NDCB0_CMD_TYPE_MASK)
80 #define NDCB0_NC                (0x1 << 20)
81 #define NDCB0_DBC               (0x1 << 19)
82 #define NDCB0_ADDR_CYC_MASK     (0x7 << 16)
83 #define NDCB0_ADDR_CYC(x)       (((x) << 16) & NDCB0_ADDR_CYC_MASK)
84 #define NDCB0_CMD2_MASK         (0xff << 8)
85 #define NDCB0_CMD1_MASK         (0xff)
86 #define NDCB0_ADDR_CYC_SHIFT    (16)
87
88 /* dma-able I/O address for the NAND data and commands */
89 #define NDCB0_DMA_ADDR          (0x43100048)
90 #define NDDB_DMA_ADDR           (0x43100040)
91
92 /* macros for registers read/write */
93 #define nand_writel(info, off, val)     \
94         __raw_writel((val), (info)->mmio_base + (off))
95
96 #define nand_readl(info, off)           \
97         __raw_readl((info)->mmio_base + (off))
98
99 /* error code and state */
100 enum {
101         ERR_NONE        = 0,
102         ERR_DMABUSERR   = -1,
103         ERR_SENDCMD     = -2,
104         ERR_DBERR       = -3,
105         ERR_BBERR       = -4,
106 };
107
108 enum {
109         STATE_READY     = 0,
110         STATE_CMD_HANDLE,
111         STATE_DMA_READING,
112         STATE_DMA_WRITING,
113         STATE_DMA_DONE,
114         STATE_PIO_READING,
115         STATE_PIO_WRITING,
116 };
117
118 struct pxa3xx_nand_info {
119         struct nand_chip        nand_chip;
120
121         struct platform_device   *pdev;
122         const struct pxa3xx_nand_flash *flash_info;
123
124         struct clk              *clk;
125         void __iomem            *mmio_base;
126
127         unsigned int            buf_start;
128         unsigned int            buf_count;
129
130         /* DMA information */
131         int                     drcmr_dat;
132         int                     drcmr_cmd;
133
134         unsigned char           *data_buff;
135         dma_addr_t              data_buff_phys;
136         size_t                  data_buff_size;
137         int                     data_dma_ch;
138         struct pxa_dma_desc     *data_desc;
139         dma_addr_t              data_desc_addr;
140
141         uint32_t                reg_ndcr;
142
143         /* saved column/page_addr during CMD_SEQIN */
144         int                     seqin_column;
145         int                     seqin_page_addr;
146
147         /* relate to the command */
148         unsigned int            state;
149
150         int                     use_ecc;        /* use HW ECC ? */
151         int                     use_dma;        /* use DMA ? */
152
153         size_t                  data_size;      /* data size in FIFO */
154         int                     retcode;
155         struct completion       cmd_complete;
156
157         /* generated NDCBx register values */
158         uint32_t                ndcb0;
159         uint32_t                ndcb1;
160         uint32_t                ndcb2;
161
162         /* calculated from pxa3xx_nand_flash data */
163         size_t          oob_size;
164         size_t          read_id_bytes;
165
166         unsigned int    col_addr_cycles;
167         unsigned int    row_addr_cycles;
168 };
169
170 static int use_dma = 1;
171 module_param(use_dma, bool, 0444);
172 MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
173
174 #ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
175 static struct pxa3xx_nand_cmdset smallpage_cmdset = {
176         .read1          = 0x0000,
177         .read2          = 0x0050,
178         .program        = 0x1080,
179         .read_status    = 0x0070,
180         .read_id        = 0x0090,
181         .erase          = 0xD060,
182         .reset          = 0x00FF,
183         .lock           = 0x002A,
184         .unlock         = 0x2423,
185         .lock_status    = 0x007A,
186 };
187
188 static struct pxa3xx_nand_cmdset largepage_cmdset = {
189         .read1          = 0x3000,
190         .read2          = 0x0050,
191         .program        = 0x1080,
192         .read_status    = 0x0070,
193         .read_id        = 0x0090,
194         .erase          = 0xD060,
195         .reset          = 0x00FF,
196         .lock           = 0x002A,
197         .unlock         = 0x2423,
198         .lock_status    = 0x007A,
199 };
200
201 static struct pxa3xx_nand_timing samsung512MbX16_timing = {
202         .tCH    = 10,
203         .tCS    = 0,
204         .tWH    = 20,
205         .tWP    = 40,
206         .tRH    = 30,
207         .tRP    = 40,
208         .tR     = 11123,
209         .tWHR   = 110,
210         .tAR    = 10,
211 };
212
213 static struct pxa3xx_nand_flash samsung512MbX16 = {
214         .timing         = &samsung512MbX16_timing,
215         .cmdset         = &smallpage_cmdset,
216         .page_per_block = 32,
217         .page_size      = 512,
218         .flash_width    = 16,
219         .dfc_width      = 16,
220         .num_blocks     = 4096,
221         .chip_id        = 0x46ec,
222 };
223
224 static struct pxa3xx_nand_timing micron_timing = {
225         .tCH    = 10,
226         .tCS    = 25,
227         .tWH    = 15,
228         .tWP    = 25,
229         .tRH    = 15,
230         .tRP    = 25,
231         .tR     = 25000,
232         .tWHR   = 60,
233         .tAR    = 10,
234 };
235
236 static struct pxa3xx_nand_flash micron1GbX8 = {
237         .timing         = &micron_timing,
238         .cmdset         = &largepage_cmdset,
239         .page_per_block = 64,
240         .page_size      = 2048,
241         .flash_width    = 8,
242         .dfc_width      = 8,
243         .num_blocks     = 1024,
244         .chip_id        = 0xa12c,
245 };
246
247 static struct pxa3xx_nand_flash micron1GbX16 = {
248         .timing         = &micron_timing,
249         .cmdset         = &largepage_cmdset,
250         .page_per_block = 64,
251         .page_size      = 2048,
252         .flash_width    = 16,
253         .dfc_width      = 16,
254         .num_blocks     = 1024,
255         .chip_id        = 0xb12c,
256 };
257
258 static struct pxa3xx_nand_timing stm2GbX16_timing = {
259         .tCH = 10,
260         .tCS = 35,
261         .tWH = 15,
262         .tWP = 25,
263         .tRH = 15,
264         .tRP = 25,
265         .tR = 25000,
266         .tWHR = 60,
267         .tAR = 10,
268 };
269
270 static struct pxa3xx_nand_flash stm2GbX16 = {
271         .timing = &stm2GbX16_timing,
272         .page_per_block = 64,
273         .page_size = 2048,
274         .flash_width = 16,
275         .dfc_width = 16,
276         .num_blocks = 2048,
277         .chip_id = 0xba20,
278 };
279
280 static struct pxa3xx_nand_flash *builtin_flash_types[] = {
281         &samsung512MbX16,
282         &micron1GbX8,
283         &micron1GbX16,
284         &stm2GbX16,
285 };
286 #endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */
287
288 #define NDTR0_tCH(c)    (min((c), 7) << 19)
289 #define NDTR0_tCS(c)    (min((c), 7) << 16)
290 #define NDTR0_tWH(c)    (min((c), 7) << 11)
291 #define NDTR0_tWP(c)    (min((c), 7) << 8)
292 #define NDTR0_tRH(c)    (min((c), 7) << 3)
293 #define NDTR0_tRP(c)    (min((c), 7) << 0)
294
295 #define NDTR1_tR(c)     (min((c), 65535) << 16)
296 #define NDTR1_tWHR(c)   (min((c), 15) << 4)
297 #define NDTR1_tAR(c)    (min((c), 15) << 0)
298
299 /* convert nano-seconds to nand flash controller clock cycles */
300 #define ns2cycle(ns, clk)       (int)(((ns) * (clk / 1000000) / 1000) + 1)
301
302 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
303                                    const struct pxa3xx_nand_timing *t)
304 {
305         unsigned long nand_clk = clk_get_rate(info->clk);
306         uint32_t ndtr0, ndtr1;
307
308         ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
309                 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
310                 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
311                 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
312                 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
313                 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
314
315         ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
316                 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
317                 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
318
319         nand_writel(info, NDTR0CS0, ndtr0);
320         nand_writel(info, NDTR1CS0, ndtr1);
321 }
322
323 #define WAIT_EVENT_TIMEOUT      10
324
325 static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event)
326 {
327         int timeout = WAIT_EVENT_TIMEOUT;
328         uint32_t ndsr;
329
330         while (timeout--) {
331                 ndsr = nand_readl(info, NDSR) & NDSR_MASK;
332                 if (ndsr & event) {
333                         nand_writel(info, NDSR, ndsr);
334                         return 0;
335                 }
336                 udelay(10);
337         }
338
339         return -ETIMEDOUT;
340 }
341
342 static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
343                         uint16_t cmd, int column, int page_addr)
344 {
345         const struct pxa3xx_nand_flash *f = info->flash_info;
346         const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
347
348         /* calculate data size */
349         switch (f->page_size) {
350         case 2048:
351                 info->data_size = (info->use_ecc) ? 2088 : 2112;
352                 break;
353         case 512:
354                 info->data_size = (info->use_ecc) ? 520 : 528;
355                 break;
356         default:
357                 return -EINVAL;
358         }
359
360         /* generate values for NDCBx registers */
361         info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
362         info->ndcb1 = 0;
363         info->ndcb2 = 0;
364         info->ndcb0 |= NDCB0_ADDR_CYC(info->row_addr_cycles + info->col_addr_cycles);
365
366         if (info->col_addr_cycles == 2) {
367                 /* large block, 2 cycles for column address
368                  * row address starts from 3rd cycle
369                  */
370                 info->ndcb1 |= (page_addr << 16) | (column & 0xffff);
371                 if (info->row_addr_cycles == 3)
372                         info->ndcb2 = (page_addr >> 16) & 0xff;
373         } else
374                 /* small block, 1 cycles for column address
375                  * row address starts from 2nd cycle
376                  */
377                 info->ndcb1 = (page_addr << 8) | (column & 0xff);
378
379         if (cmd == cmdset->program)
380                 info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;
381
382         return 0;
383 }
384
385 static int prepare_erase_cmd(struct pxa3xx_nand_info *info,
386                         uint16_t cmd, int page_addr)
387 {
388         info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
389         info->ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS | NDCB0_ADDR_CYC(3);
390         info->ndcb1 = page_addr;
391         info->ndcb2 = 0;
392         return 0;
393 }
394
395 static int prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
396 {
397         const struct pxa3xx_nand_cmdset *cmdset = info->flash_info->cmdset;
398
399         info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
400         info->ndcb1 = 0;
401         info->ndcb2 = 0;
402
403         if (cmd == cmdset->read_id) {
404                 info->ndcb0 |= NDCB0_CMD_TYPE(3);
405                 info->data_size = 8;
406         } else if (cmd == cmdset->read_status) {
407                 info->ndcb0 |= NDCB0_CMD_TYPE(4);
408                 info->data_size = 8;
409         } else if (cmd == cmdset->reset || cmd == cmdset->lock ||
410                    cmd == cmdset->unlock) {
411                 info->ndcb0 |= NDCB0_CMD_TYPE(5);
412         } else
413                 return -EINVAL;
414
415         return 0;
416 }
417
418 static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
419 {
420         uint32_t ndcr;
421
422         ndcr = nand_readl(info, NDCR);
423         nand_writel(info, NDCR, ndcr & ~int_mask);
424 }
425
426 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
427 {
428         uint32_t ndcr;
429
430         ndcr = nand_readl(info, NDCR);
431         nand_writel(info, NDCR, ndcr | int_mask);
432 }
433
434 /* NOTE: it is a must to set ND_RUN firstly, then write command buffer
435  * otherwise, it does not work
436  */
437 static int write_cmd(struct pxa3xx_nand_info *info)
438 {
439         uint32_t ndcr;
440
441         /* clear status bits and run */
442         nand_writel(info, NDSR, NDSR_MASK);
443
444         ndcr = info->reg_ndcr;
445
446         ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
447         ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
448         ndcr |= NDCR_ND_RUN;
449
450         nand_writel(info, NDCR, ndcr);
451
452         if (wait_for_event(info, NDSR_WRCMDREQ)) {
453                 printk(KERN_ERR "timed out writing command\n");
454                 return -ETIMEDOUT;
455         }
456
457         nand_writel(info, NDCB0, info->ndcb0);
458         nand_writel(info, NDCB0, info->ndcb1);
459         nand_writel(info, NDCB0, info->ndcb2);
460         return 0;
461 }
462
463 static int handle_data_pio(struct pxa3xx_nand_info *info)
464 {
465         int ret, timeout = CHIP_DELAY_TIMEOUT;
466
467         switch (info->state) {
468         case STATE_PIO_WRITING:
469                 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
470                                 info->data_size << 2);
471
472                 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
473
474                 ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
475                 if (!ret) {
476                         printk(KERN_ERR "program command time out\n");
477                         return -1;
478                 }
479                 break;
480         case STATE_PIO_READING:
481                 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
482                                 info->data_size << 2);
483                 break;
484         default:
485                 printk(KERN_ERR "%s: invalid state %d\n", __func__,
486                                 info->state);
487                 return -EINVAL;
488         }
489
490         info->state = STATE_READY;
491         return 0;
492 }
493
494 static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
495 {
496         struct pxa_dma_desc *desc = info->data_desc;
497         int dma_len = ALIGN(info->data_size, 32);
498
499         desc->ddadr = DDADR_STOP;
500         desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
501
502         if (dir_out) {
503                 desc->dsadr = info->data_buff_phys;
504                 desc->dtadr = NDDB_DMA_ADDR;
505                 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
506         } else {
507                 desc->dtadr = info->data_buff_phys;
508                 desc->dsadr = NDDB_DMA_ADDR;
509                 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
510         }
511
512         DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
513         DDADR(info->data_dma_ch) = info->data_desc_addr;
514         DCSR(info->data_dma_ch) |= DCSR_RUN;
515 }
516
517 static void pxa3xx_nand_data_dma_irq(int channel, void *data)
518 {
519         struct pxa3xx_nand_info *info = data;
520         uint32_t dcsr;
521
522         dcsr = DCSR(channel);
523         DCSR(channel) = dcsr;
524
525         if (dcsr & DCSR_BUSERR) {
526                 info->retcode = ERR_DMABUSERR;
527                 complete(&info->cmd_complete);
528         }
529
530         if (info->state == STATE_DMA_WRITING) {
531                 info->state = STATE_DMA_DONE;
532                 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
533         } else {
534                 info->state = STATE_READY;
535                 complete(&info->cmd_complete);
536         }
537 }
538
539 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
540 {
541         struct pxa3xx_nand_info *info = devid;
542         unsigned int status;
543
544         status = nand_readl(info, NDSR);
545
546         if (status & (NDSR_RDDREQ | NDSR_DBERR)) {
547                 if (status & NDSR_DBERR)
548                         info->retcode = ERR_DBERR;
549
550                 disable_int(info, NDSR_RDDREQ | NDSR_DBERR);
551
552                 if (info->use_dma) {
553                         info->state = STATE_DMA_READING;
554                         start_data_dma(info, 0);
555                 } else {
556                         info->state = STATE_PIO_READING;
557                         complete(&info->cmd_complete);
558                 }
559         } else if (status & NDSR_WRDREQ) {
560                 disable_int(info, NDSR_WRDREQ);
561                 if (info->use_dma) {
562                         info->state = STATE_DMA_WRITING;
563                         start_data_dma(info, 1);
564                 } else {
565                         info->state = STATE_PIO_WRITING;
566                         complete(&info->cmd_complete);
567                 }
568         } else if (status & (NDSR_CS0_BBD | NDSR_CS0_CMDD)) {
569                 if (status & NDSR_CS0_BBD)
570                         info->retcode = ERR_BBERR;
571
572                 disable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
573                 info->state = STATE_READY;
574                 complete(&info->cmd_complete);
575         }
576         nand_writel(info, NDSR, status);
577         return IRQ_HANDLED;
578 }
579
580 static int pxa3xx_nand_do_cmd(struct pxa3xx_nand_info *info, uint32_t event)
581 {
582         uint32_t ndcr;
583         int ret, timeout = CHIP_DELAY_TIMEOUT;
584
585         if (write_cmd(info)) {
586                 info->retcode = ERR_SENDCMD;
587                 goto fail_stop;
588         }
589
590         info->state = STATE_CMD_HANDLE;
591
592         enable_int(info, event);
593
594         ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
595         if (!ret) {
596                 printk(KERN_ERR "command execution timed out\n");
597                 info->retcode = ERR_SENDCMD;
598                 goto fail_stop;
599         }
600
601         if (info->use_dma == 0 && info->data_size > 0)
602                 if (handle_data_pio(info))
603                         goto fail_stop;
604
605         return 0;
606
607 fail_stop:
608         ndcr = nand_readl(info, NDCR);
609         nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
610         udelay(10);
611         return -ETIMEDOUT;
612 }
613
614 static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
615 {
616         struct pxa3xx_nand_info *info = mtd->priv;
617         return (nand_readl(info, NDSR) & NDSR_RDY) ? 1 : 0;
618 }
619
620 static inline int is_buf_blank(uint8_t *buf, size_t len)
621 {
622         for (; len > 0; len--)
623                 if (*buf++ != 0xff)
624                         return 0;
625         return 1;
626 }
627
628 static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
629                                 int column, int page_addr)
630 {
631         struct pxa3xx_nand_info *info = mtd->priv;
632         const struct pxa3xx_nand_flash *flash_info = info->flash_info;
633         const struct pxa3xx_nand_cmdset *cmdset = flash_info->cmdset;
634         int ret;
635
636         info->use_dma = (use_dma) ? 1 : 0;
637         info->use_ecc = 0;
638         info->data_size = 0;
639         info->state = STATE_READY;
640
641         init_completion(&info->cmd_complete);
642
643         switch (command) {
644         case NAND_CMD_READOOB:
645                 /* disable HW ECC to get all the OOB data */
646                 info->buf_count = mtd->writesize + mtd->oobsize;
647                 info->buf_start = mtd->writesize + column;
648
649                 if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
650                         break;
651
652                 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR);
653
654                 /* We only are OOB, so if the data has error, does not matter */
655                 if (info->retcode == ERR_DBERR)
656                         info->retcode = ERR_NONE;
657                 break;
658
659         case NAND_CMD_READ0:
660                 info->use_ecc = 1;
661                 info->retcode = ERR_NONE;
662                 info->buf_start = column;
663                 info->buf_count = mtd->writesize + mtd->oobsize;
664                 memset(info->data_buff, 0xFF, info->buf_count);
665
666                 if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
667                         break;
668
669                 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR);
670
671                 if (info->retcode == ERR_DBERR) {
672                         /* for blank page (all 0xff), HW will calculate its ECC as
673                          * 0, which is different from the ECC information within
674                          * OOB, ignore such double bit errors
675                          */
676                         if (is_buf_blank(info->data_buff, mtd->writesize))
677                                 info->retcode = ERR_NONE;
678                 }
679                 break;
680         case NAND_CMD_SEQIN:
681                 info->buf_start = column;
682                 info->buf_count = mtd->writesize + mtd->oobsize;
683                 memset(info->data_buff, 0xff, info->buf_count);
684
685                 /* save column/page_addr for next CMD_PAGEPROG */
686                 info->seqin_column = column;
687                 info->seqin_page_addr = page_addr;
688                 break;
689         case NAND_CMD_PAGEPROG:
690                 info->use_ecc = (info->seqin_column >= mtd->writesize) ? 0 : 1;
691
692                 if (prepare_read_prog_cmd(info, cmdset->program,
693                                 info->seqin_column, info->seqin_page_addr))
694                         break;
695
696                 pxa3xx_nand_do_cmd(info, NDSR_WRDREQ);
697                 break;
698         case NAND_CMD_ERASE1:
699                 if (prepare_erase_cmd(info, cmdset->erase, page_addr))
700                         break;
701
702                 pxa3xx_nand_do_cmd(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
703                 break;
704         case NAND_CMD_ERASE2:
705                 break;
706         case NAND_CMD_READID:
707         case NAND_CMD_STATUS:
708                 info->use_dma = 0;      /* force PIO read */
709                 info->buf_start = 0;
710                 info->buf_count = (command == NAND_CMD_READID) ?
711                                 info->read_id_bytes : 1;
712
713                 if (prepare_other_cmd(info, (command == NAND_CMD_READID) ?
714                                 cmdset->read_id : cmdset->read_status))
715                         break;
716
717                 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ);
718                 break;
719         case NAND_CMD_RESET:
720                 if (prepare_other_cmd(info, cmdset->reset))
721                         break;
722
723                 ret = pxa3xx_nand_do_cmd(info, NDSR_CS0_CMDD);
724                 if (ret == 0) {
725                         int timeout = 2;
726                         uint32_t ndcr;
727
728                         while (timeout--) {
729                                 if (nand_readl(info, NDSR) & NDSR_RDY)
730                                         break;
731                                 msleep(10);
732                         }
733
734                         ndcr = nand_readl(info, NDCR);
735                         nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
736                 }
737                 break;
738         default:
739                 printk(KERN_ERR "non-supported command.\n");
740                 break;
741         }
742
743         if (info->retcode == ERR_DBERR) {
744                 printk(KERN_ERR "double bit error @ page %08x\n", page_addr);
745                 info->retcode = ERR_NONE;
746         }
747 }
748
749 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
750 {
751         struct pxa3xx_nand_info *info = mtd->priv;
752         char retval = 0xFF;
753
754         if (info->buf_start < info->buf_count)
755                 /* Has just send a new command? */
756                 retval = info->data_buff[info->buf_start++];
757
758         return retval;
759 }
760
761 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
762 {
763         struct pxa3xx_nand_info *info = mtd->priv;
764         u16 retval = 0xFFFF;
765
766         if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
767                 retval = *((u16 *)(info->data_buff+info->buf_start));
768                 info->buf_start += 2;
769         }
770         return retval;
771 }
772
773 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
774 {
775         struct pxa3xx_nand_info *info = mtd->priv;
776         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
777
778         memcpy(buf, info->data_buff + info->buf_start, real_len);
779         info->buf_start += real_len;
780 }
781
782 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
783                 const uint8_t *buf, int len)
784 {
785         struct pxa3xx_nand_info *info = mtd->priv;
786         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
787
788         memcpy(info->data_buff + info->buf_start, buf, real_len);
789         info->buf_start += real_len;
790 }
791
792 static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
793                 const uint8_t *buf, int len)
794 {
795         return 0;
796 }
797
798 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
799 {
800         return;
801 }
802
803 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
804 {
805         struct pxa3xx_nand_info *info = mtd->priv;
806
807         /* pxa3xx_nand_send_command has waited for command complete */
808         if (this->state == FL_WRITING || this->state == FL_ERASING) {
809                 if (info->retcode == ERR_NONE)
810                         return 0;
811                 else {
812                         /*
813                          * any error make it return 0x01 which will tell
814                          * the caller the erase and write fail
815                          */
816                         return 0x01;
817                 }
818         }
819
820         return 0;
821 }
822
823 static void pxa3xx_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
824 {
825         return;
826 }
827
828 static int pxa3xx_nand_ecc_calculate(struct mtd_info *mtd,
829                 const uint8_t *dat, uint8_t *ecc_code)
830 {
831         return 0;
832 }
833
834 static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
835                 uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc)
836 {
837         struct pxa3xx_nand_info *info = mtd->priv;
838         /*
839          * Any error include ERR_SEND_CMD, ERR_DBERR, ERR_BUSERR, we
840          * consider it as a ecc error which will tell the caller the
841          * read fail We have distinguish all the errors, but the
842          * nand_read_ecc only check this function return value
843          */
844         if (info->retcode != ERR_NONE)
845                 return -1;
846
847         return 0;
848 }
849
850 static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
851 {
852         const struct pxa3xx_nand_flash *f = info->flash_info;
853         const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
854         uint32_t ndcr;
855         uint8_t  id_buff[8];
856
857         if (prepare_other_cmd(info, cmdset->read_id)) {
858                 printk(KERN_ERR "failed to prepare command\n");
859                 return -EINVAL;
860         }
861
862         /* Send command */
863         if (write_cmd(info))
864                 goto fail_timeout;
865
866         /* Wait for CMDDM(command done successfully) */
867         if (wait_for_event(info, NDSR_RDDREQ))
868                 goto fail_timeout;
869
870         __raw_readsl(info->mmio_base + NDDB, id_buff, 2);
871         *id = id_buff[0] | (id_buff[1] << 8);
872         return 0;
873
874 fail_timeout:
875         ndcr = nand_readl(info, NDCR);
876         nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
877         udelay(10);
878         return -ETIMEDOUT;
879 }
880
881 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
882                                     const struct pxa3xx_nand_flash *f)
883 {
884         struct platform_device *pdev = info->pdev;
885         struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
886         uint32_t ndcr = 0x00000FFF; /* disable all interrupts */
887
888         if (f->page_size != 2048 && f->page_size != 512)
889                 return -EINVAL;
890
891         if (f->flash_width != 16 && f->flash_width != 8)
892                 return -EINVAL;
893
894         /* calculate flash information */
895         info->oob_size = (f->page_size == 2048) ? 64 : 16;
896         info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
897
898         /* calculate addressing information */
899         info->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
900
901         if (f->num_blocks * f->page_per_block > 65536)
902                 info->row_addr_cycles = 3;
903         else
904                 info->row_addr_cycles = 2;
905
906         ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
907         ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0;
908         ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
909         ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
910         ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
911         ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
912
913         ndcr |= NDCR_RD_ID_CNT(info->read_id_bytes);
914         ndcr |= NDCR_SPARE_EN; /* enable spare by default */
915
916         info->reg_ndcr = ndcr;
917
918         pxa3xx_nand_set_timing(info, f->timing);
919         info->flash_info = f;
920         return 0;
921 }
922
923 static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
924                                     const struct pxa3xx_nand_platform_data *pdata)
925 {
926         const struct pxa3xx_nand_flash *f;
927         uint32_t id = -1;
928         int i;
929
930         for (i = 0; i<pdata->num_flash; ++i) {
931                 f = pdata->flash + i;
932
933                 if (pxa3xx_nand_config_flash(info, f))
934                         continue;
935
936                 if (__readid(info, &id))
937                         continue;
938
939                 if (id == f->chip_id)
940                         return 0;
941         }
942
943 #ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
944         for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {
945
946                 f = builtin_flash_types[i];
947
948                 if (pxa3xx_nand_config_flash(info, f))
949                         continue;
950
951                 if (__readid(info, &id))
952                         continue;
953
954                 if (id == f->chip_id)
955                         return 0;
956         }
957 #endif
958
959         dev_warn(&info->pdev->dev,
960                  "failed to detect configured nand flash; found %04x instead of\n",
961                  id);
962         return -ENODEV;
963 }
964
965 /* the maximum possible buffer size for large page with OOB data
966  * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
967  * data buffer and the DMA descriptor
968  */
969 #define MAX_BUFF_SIZE   PAGE_SIZE
970
971 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
972 {
973         struct platform_device *pdev = info->pdev;
974         int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
975
976         if (use_dma == 0) {
977                 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
978                 if (info->data_buff == NULL)
979                         return -ENOMEM;
980                 return 0;
981         }
982
983         info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
984                                 &info->data_buff_phys, GFP_KERNEL);
985         if (info->data_buff == NULL) {
986                 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
987                 return -ENOMEM;
988         }
989
990         info->data_buff_size = MAX_BUFF_SIZE;
991         info->data_desc = (void *)info->data_buff + data_desc_offset;
992         info->data_desc_addr = info->data_buff_phys + data_desc_offset;
993
994         info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
995                                 pxa3xx_nand_data_dma_irq, info);
996         if (info->data_dma_ch < 0) {
997                 dev_err(&pdev->dev, "failed to request data dma\n");
998                 dma_free_coherent(&pdev->dev, info->data_buff_size,
999                                 info->data_buff, info->data_buff_phys);
1000                 return info->data_dma_ch;
1001         }
1002
1003         return 0;
1004 }
1005
1006 static struct nand_ecclayout hw_smallpage_ecclayout = {
1007         .eccbytes = 6,
1008         .eccpos = {8, 9, 10, 11, 12, 13 },
1009         .oobfree = { {2, 6} }
1010 };
1011
1012 static struct nand_ecclayout hw_largepage_ecclayout = {
1013         .eccbytes = 24,
1014         .eccpos = {
1015                 40, 41, 42, 43, 44, 45, 46, 47,
1016                 48, 49, 50, 51, 52, 53, 54, 55,
1017                 56, 57, 58, 59, 60, 61, 62, 63},
1018         .oobfree = { {2, 38} }
1019 };
1020
1021 static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
1022                                  struct pxa3xx_nand_info *info)
1023 {
1024         const struct pxa3xx_nand_flash *f = info->flash_info;
1025         struct nand_chip *this = &info->nand_chip;
1026
1027         this->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
1028
1029         this->waitfunc          = pxa3xx_nand_waitfunc;
1030         this->select_chip       = pxa3xx_nand_select_chip;
1031         this->dev_ready         = pxa3xx_nand_dev_ready;
1032         this->cmdfunc           = pxa3xx_nand_cmdfunc;
1033         this->read_word         = pxa3xx_nand_read_word;
1034         this->read_byte         = pxa3xx_nand_read_byte;
1035         this->read_buf          = pxa3xx_nand_read_buf;
1036         this->write_buf         = pxa3xx_nand_write_buf;
1037         this->verify_buf        = pxa3xx_nand_verify_buf;
1038
1039         this->ecc.mode          = NAND_ECC_HW;
1040         this->ecc.hwctl         = pxa3xx_nand_ecc_hwctl;
1041         this->ecc.calculate     = pxa3xx_nand_ecc_calculate;
1042         this->ecc.correct       = pxa3xx_nand_ecc_correct;
1043         this->ecc.size          = f->page_size;
1044
1045         if (f->page_size == 2048)
1046                 this->ecc.layout = &hw_largepage_ecclayout;
1047         else
1048                 this->ecc.layout = &hw_smallpage_ecclayout;
1049
1050         this->chip_delay = 25;
1051 }
1052
1053 static int pxa3xx_nand_probe(struct platform_device *pdev)
1054 {
1055         struct pxa3xx_nand_platform_data *pdata;
1056         struct pxa3xx_nand_info *info;
1057         struct nand_chip *this;
1058         struct mtd_info *mtd;
1059         struct resource *r;
1060         int ret = 0, irq;
1061
1062         pdata = pdev->dev.platform_data;
1063
1064         if (!pdata) {
1065                 dev_err(&pdev->dev, "no platform data defined\n");
1066                 return -ENODEV;
1067         }
1068
1069         mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
1070                         GFP_KERNEL);
1071         if (!mtd) {
1072                 dev_err(&pdev->dev, "failed to allocate memory\n");
1073                 return -ENOMEM;
1074         }
1075
1076         info = (struct pxa3xx_nand_info *)(&mtd[1]);
1077         info->pdev = pdev;
1078
1079         this = &info->nand_chip;
1080         mtd->priv = info;
1081
1082         info->clk = clk_get(&pdev->dev, "NANDCLK");
1083         if (IS_ERR(info->clk)) {
1084                 dev_err(&pdev->dev, "failed to get nand clock\n");
1085                 ret = PTR_ERR(info->clk);
1086                 goto fail_free_mtd;
1087         }
1088         clk_enable(info->clk);
1089
1090         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1091         if (r == NULL) {
1092                 dev_err(&pdev->dev, "no resource defined for data DMA\n");
1093                 ret = -ENXIO;
1094                 goto fail_put_clk;
1095         }
1096         info->drcmr_dat = r->start;
1097
1098         r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1099         if (r == NULL) {
1100                 dev_err(&pdev->dev, "no resource defined for command DMA\n");
1101                 ret = -ENXIO;
1102                 goto fail_put_clk;
1103         }
1104         info->drcmr_cmd = r->start;
1105
1106         irq = platform_get_irq(pdev, 0);
1107         if (irq < 0) {
1108                 dev_err(&pdev->dev, "no IRQ resource defined\n");
1109                 ret = -ENXIO;
1110                 goto fail_put_clk;
1111         }
1112
1113         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1114         if (r == NULL) {
1115                 dev_err(&pdev->dev, "no IO memory resource defined\n");
1116                 ret = -ENODEV;
1117                 goto fail_put_clk;
1118         }
1119
1120         r = request_mem_region(r->start, r->end - r->start + 1, pdev->name);
1121         if (r == NULL) {
1122                 dev_err(&pdev->dev, "failed to request memory resource\n");
1123                 ret = -EBUSY;
1124                 goto fail_put_clk;
1125         }
1126
1127         info->mmio_base = ioremap(r->start, r->end - r->start + 1);
1128         if (info->mmio_base == NULL) {
1129                 dev_err(&pdev->dev, "ioremap() failed\n");
1130                 ret = -ENODEV;
1131                 goto fail_free_res;
1132         }
1133
1134         ret = pxa3xx_nand_init_buff(info);
1135         if (ret)
1136                 goto fail_free_io;
1137
1138         ret = request_irq(IRQ_NAND, pxa3xx_nand_irq, IRQF_DISABLED,
1139                                 pdev->name, info);
1140         if (ret < 0) {
1141                 dev_err(&pdev->dev, "failed to request IRQ\n");
1142                 goto fail_free_buf;
1143         }
1144
1145         ret = pxa3xx_nand_detect_flash(info, pdata);
1146         if (ret) {
1147                 dev_err(&pdev->dev, "failed to detect flash\n");
1148                 ret = -ENODEV;
1149                 goto fail_free_irq;
1150         }
1151
1152         pxa3xx_nand_init_mtd(mtd, info);
1153
1154         platform_set_drvdata(pdev, mtd);
1155
1156         if (nand_scan(mtd, 1)) {
1157                 dev_err(&pdev->dev, "failed to scan nand\n");
1158                 ret = -ENXIO;
1159                 goto fail_free_irq;
1160         }
1161
1162         return add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
1163
1164 fail_free_irq:
1165         free_irq(IRQ_NAND, info);
1166 fail_free_buf:
1167         if (use_dma) {
1168                 pxa_free_dma(info->data_dma_ch);
1169                 dma_free_coherent(&pdev->dev, info->data_buff_size,
1170                         info->data_buff, info->data_buff_phys);
1171         } else
1172                 kfree(info->data_buff);
1173 fail_free_io:
1174         iounmap(info->mmio_base);
1175 fail_free_res:
1176         release_mem_region(r->start, r->end - r->start + 1);
1177 fail_put_clk:
1178         clk_disable(info->clk);
1179         clk_put(info->clk);
1180 fail_free_mtd:
1181         kfree(mtd);
1182         return ret;
1183 }
1184
1185 static int pxa3xx_nand_remove(struct platform_device *pdev)
1186 {
1187         struct mtd_info *mtd = platform_get_drvdata(pdev);
1188         struct pxa3xx_nand_info *info = mtd->priv;
1189
1190         platform_set_drvdata(pdev, NULL);
1191
1192         del_mtd_device(mtd);
1193         del_mtd_partitions(mtd);
1194         free_irq(IRQ_NAND, info);
1195         if (use_dma) {
1196                 pxa_free_dma(info->data_dma_ch);
1197                 dma_free_writecombine(&pdev->dev, info->data_buff_size,
1198                                 info->data_buff, info->data_buff_phys);
1199         } else
1200                 kfree(info->data_buff);
1201         kfree(mtd);
1202         return 0;
1203 }
1204
1205 #ifdef CONFIG_PM
1206 static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1207 {
1208         struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1209         struct pxa3xx_nand_info *info = mtd->priv;
1210
1211         if (info->state != STATE_READY) {
1212                 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1213                 return -EAGAIN;
1214         }
1215
1216         return 0;
1217 }
1218
1219 static int pxa3xx_nand_resume(struct platform_device *pdev)
1220 {
1221         struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1222         struct pxa3xx_nand_info *info = mtd->priv;
1223
1224         clk_enable(info->clk);
1225
1226         return pxa3xx_nand_config_flash(info, info->flash_info);
1227 }
1228 #else
1229 #define pxa3xx_nand_suspend     NULL
1230 #define pxa3xx_nand_resume      NULL
1231 #endif
1232
1233 static struct platform_driver pxa3xx_nand_driver = {
1234         .driver = {
1235                 .name   = "pxa3xx-nand",
1236         },
1237         .probe          = pxa3xx_nand_probe,
1238         .remove         = pxa3xx_nand_remove,
1239         .suspend        = pxa3xx_nand_suspend,
1240         .resume         = pxa3xx_nand_resume,
1241 };
1242
1243 static int __init pxa3xx_nand_init(void)
1244 {
1245         return platform_driver_register(&pxa3xx_nand_driver);
1246 }
1247 module_init(pxa3xx_nand_init);
1248
1249 static void __exit pxa3xx_nand_exit(void)
1250 {
1251         platform_driver_unregister(&pxa3xx_nand_driver);
1252 }
1253 module_exit(pxa3xx_nand_exit);
1254
1255 MODULE_LICENSE("GPL");
1256 MODULE_DESCRIPTION("PXA3xx NAND controller driver");