9e485459f63b389c0a63a7139dcb18bbab6bba2e
[linux-2.6.git] / drivers / mfd / asic3.c
1 /*
2  * driver/mfd/asic3.c
3  *
4  * Compaq ASIC3 support.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * Copyright 2001 Compaq Computer Corporation.
11  * Copyright 2004-2005 Phil Blundell
12  * Copyright 2007-2008 OpenedHand Ltd.
13  *
14  * Authors: Phil Blundell <pb@handhelds.org>,
15  *          Samuel Ortiz <sameo@openedhand.com>
16  *
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/irq.h>
21 #include <linux/gpio.h>
22 #include <linux/io.h>
23 #include <linux/spinlock.h>
24 #include <linux/platform_device.h>
25
26 #include <linux/mfd/asic3.h>
27
28 struct asic3 {
29         void __iomem *mapping;
30         unsigned int bus_shift;
31         unsigned int irq_nr;
32         unsigned int irq_base;
33         spinlock_t lock;
34         u16 irq_bothedge[4];
35         struct gpio_chip gpio;
36         struct device *dev;
37 };
38
39 static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
40
41 static inline void asic3_write_register(struct asic3 *asic,
42                                  unsigned int reg, u32 value)
43 {
44         iowrite16(value, asic->mapping +
45                   (reg >> asic->bus_shift));
46 }
47
48 static inline u32 asic3_read_register(struct asic3 *asic,
49                                unsigned int reg)
50 {
51         return ioread16(asic->mapping +
52                         (reg >> asic->bus_shift));
53 }
54
55 /* IRQs */
56 #define MAX_ASIC_ISR_LOOPS    20
57 #define ASIC3_GPIO_BASE_INCR \
58         (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
59
60 static void asic3_irq_flip_edge(struct asic3 *asic,
61                                 u32 base, int bit)
62 {
63         u16 edge;
64         unsigned long flags;
65
66         spin_lock_irqsave(&asic->lock, flags);
67         edge = asic3_read_register(asic,
68                                    base + ASIC3_GPIO_EDGE_TRIGGER);
69         edge ^= bit;
70         asic3_write_register(asic,
71                              base + ASIC3_GPIO_EDGE_TRIGGER, edge);
72         spin_unlock_irqrestore(&asic->lock, flags);
73 }
74
75 static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
76 {
77         int iter, i;
78         unsigned long flags;
79         struct asic3 *asic;
80
81         desc->chip->ack(irq);
82
83         asic = desc->handler_data;
84
85         for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
86                 u32 status;
87                 int bank;
88
89                 spin_lock_irqsave(&asic->lock, flags);
90                 status = asic3_read_register(asic,
91                                              ASIC3_OFFSET(INTR, P_INT_STAT));
92                 spin_unlock_irqrestore(&asic->lock, flags);
93
94                 /* Check all ten register bits */
95                 if ((status & 0x3ff) == 0)
96                         break;
97
98                 /* Handle GPIO IRQs */
99                 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
100                         if (status & (1 << bank)) {
101                                 unsigned long base, istat;
102
103                                 base = ASIC3_GPIO_A_BASE
104                                        + bank * ASIC3_GPIO_BASE_INCR;
105
106                                 spin_lock_irqsave(&asic->lock, flags);
107                                 istat = asic3_read_register(asic,
108                                                             base +
109                                                             ASIC3_GPIO_INT_STATUS);
110                                 /* Clearing IntStatus */
111                                 asic3_write_register(asic,
112                                                      base +
113                                                      ASIC3_GPIO_INT_STATUS, 0);
114                                 spin_unlock_irqrestore(&asic->lock, flags);
115
116                                 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
117                                         int bit = (1 << i);
118                                         unsigned int irqnr;
119
120                                         if (!(istat & bit))
121                                                 continue;
122
123                                         irqnr = asic->irq_base +
124                                                 (ASIC3_GPIOS_PER_BANK * bank)
125                                                 + i;
126                                         desc = irq_to_desc(irqnr);
127                                         desc->handle_irq(irqnr, desc);
128                                         if (asic->irq_bothedge[bank] & bit)
129                                                 asic3_irq_flip_edge(asic, base,
130                                                                     bit);
131                                 }
132                         }
133                 }
134
135                 /* Handle remaining IRQs in the status register */
136                 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
137                         /* They start at bit 4 and go up */
138                         if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
139                                 desc = irq_to_desc(asic->irq_base + i);
140                                 desc->handle_irq(asic->irq_base + i,
141                                                  desc);
142                         }
143                 }
144         }
145
146         if (iter >= MAX_ASIC_ISR_LOOPS)
147                 dev_err(asic->dev, "interrupt processing overrun\n");
148 }
149
150 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
151 {
152         int n;
153
154         n = (irq - asic->irq_base) >> 4;
155
156         return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
157 }
158
159 static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
160 {
161         return (irq - asic->irq_base) & 0xf;
162 }
163
164 static void asic3_mask_gpio_irq(unsigned int irq)
165 {
166         struct asic3 *asic = get_irq_chip_data(irq);
167         u32 val, bank, index;
168         unsigned long flags;
169
170         bank = asic3_irq_to_bank(asic, irq);
171         index = asic3_irq_to_index(asic, irq);
172
173         spin_lock_irqsave(&asic->lock, flags);
174         val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
175         val |= 1 << index;
176         asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
177         spin_unlock_irqrestore(&asic->lock, flags);
178 }
179
180 static void asic3_mask_irq(unsigned int irq)
181 {
182         struct asic3 *asic = get_irq_chip_data(irq);
183         int regval;
184         unsigned long flags;
185
186         spin_lock_irqsave(&asic->lock, flags);
187         regval = asic3_read_register(asic,
188                                      ASIC3_INTR_BASE +
189                                      ASIC3_INTR_INT_MASK);
190
191         regval &= ~(ASIC3_INTMASK_MASK0 <<
192                     (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
193
194         asic3_write_register(asic,
195                              ASIC3_INTR_BASE +
196                              ASIC3_INTR_INT_MASK,
197                              regval);
198         spin_unlock_irqrestore(&asic->lock, flags);
199 }
200
201 static void asic3_unmask_gpio_irq(unsigned int irq)
202 {
203         struct asic3 *asic = get_irq_chip_data(irq);
204         u32 val, bank, index;
205         unsigned long flags;
206
207         bank = asic3_irq_to_bank(asic, irq);
208         index = asic3_irq_to_index(asic, irq);
209
210         spin_lock_irqsave(&asic->lock, flags);
211         val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
212         val &= ~(1 << index);
213         asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
214         spin_unlock_irqrestore(&asic->lock, flags);
215 }
216
217 static void asic3_unmask_irq(unsigned int irq)
218 {
219         struct asic3 *asic = get_irq_chip_data(irq);
220         int regval;
221         unsigned long flags;
222
223         spin_lock_irqsave(&asic->lock, flags);
224         regval = asic3_read_register(asic,
225                                      ASIC3_INTR_BASE +
226                                      ASIC3_INTR_INT_MASK);
227
228         regval |= (ASIC3_INTMASK_MASK0 <<
229                    (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
230
231         asic3_write_register(asic,
232                              ASIC3_INTR_BASE +
233                              ASIC3_INTR_INT_MASK,
234                              regval);
235         spin_unlock_irqrestore(&asic->lock, flags);
236 }
237
238 static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
239 {
240         struct asic3 *asic = get_irq_chip_data(irq);
241         u32 bank, index;
242         u16 trigger, level, edge, bit;
243         unsigned long flags;
244
245         bank = asic3_irq_to_bank(asic, irq);
246         index = asic3_irq_to_index(asic, irq);
247         bit = 1<<index;
248
249         spin_lock_irqsave(&asic->lock, flags);
250         level = asic3_read_register(asic,
251                                     bank + ASIC3_GPIO_LEVEL_TRIGGER);
252         edge = asic3_read_register(asic,
253                                    bank + ASIC3_GPIO_EDGE_TRIGGER);
254         trigger = asic3_read_register(asic,
255                                       bank + ASIC3_GPIO_TRIGGER_TYPE);
256         asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
257
258         if (type == IRQ_TYPE_EDGE_RISING) {
259                 trigger |= bit;
260                 edge |= bit;
261         } else if (type == IRQ_TYPE_EDGE_FALLING) {
262                 trigger |= bit;
263                 edge &= ~bit;
264         } else if (type == IRQ_TYPE_EDGE_BOTH) {
265                 trigger |= bit;
266                 if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
267                         edge &= ~bit;
268                 else
269                         edge |= bit;
270                 asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
271         } else if (type == IRQ_TYPE_LEVEL_LOW) {
272                 trigger &= ~bit;
273                 level &= ~bit;
274         } else if (type == IRQ_TYPE_LEVEL_HIGH) {
275                 trigger &= ~bit;
276                 level |= bit;
277         } else {
278                 /*
279                  * if type == IRQ_TYPE_NONE, we should mask interrupts, but
280                  * be careful to not unmask them if mask was also called.
281                  * Probably need internal state for mask.
282                  */
283                 dev_notice(asic->dev, "irq type not changed\n");
284         }
285         asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
286                              level);
287         asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
288                              edge);
289         asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
290                              trigger);
291         spin_unlock_irqrestore(&asic->lock, flags);
292         return 0;
293 }
294
295 static struct irq_chip asic3_gpio_irq_chip = {
296         .name           = "ASIC3-GPIO",
297         .ack            = asic3_mask_gpio_irq,
298         .mask           = asic3_mask_gpio_irq,
299         .unmask         = asic3_unmask_gpio_irq,
300         .set_type       = asic3_gpio_irq_type,
301 };
302
303 static struct irq_chip asic3_irq_chip = {
304         .name           = "ASIC3",
305         .ack            = asic3_mask_irq,
306         .mask           = asic3_mask_irq,
307         .unmask         = asic3_unmask_irq,
308 };
309
310 static int __init asic3_irq_probe(struct platform_device *pdev)
311 {
312         struct asic3 *asic = platform_get_drvdata(pdev);
313         unsigned long clksel = 0;
314         unsigned int irq, irq_base;
315         int ret;
316
317         ret = platform_get_irq(pdev, 0);
318         if (ret < 0)
319                 return ret;
320         asic->irq_nr = ret;
321
322         /* turn on clock to IRQ controller */
323         clksel |= CLOCK_SEL_CX;
324         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
325                              clksel);
326
327         irq_base = asic->irq_base;
328
329         for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
330                 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
331                         set_irq_chip(irq, &asic3_gpio_irq_chip);
332                 else
333                         set_irq_chip(irq, &asic3_irq_chip);
334
335                 set_irq_chip_data(irq, asic);
336                 set_irq_handler(irq, handle_level_irq);
337                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
338         }
339
340         asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
341                              ASIC3_INTMASK_GINTMASK);
342
343         set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
344         set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
345         set_irq_data(asic->irq_nr, asic);
346
347         return 0;
348 }
349
350 static void asic3_irq_remove(struct platform_device *pdev)
351 {
352         struct asic3 *asic = platform_get_drvdata(pdev);
353         unsigned int irq, irq_base;
354
355         irq_base = asic->irq_base;
356
357         for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
358                 set_irq_flags(irq, 0);
359                 set_irq_handler(irq, NULL);
360                 set_irq_chip(irq, NULL);
361                 set_irq_chip_data(irq, NULL);
362         }
363         set_irq_chained_handler(asic->irq_nr, NULL);
364 }
365
366 /* GPIOs */
367 static int asic3_gpio_direction(struct gpio_chip *chip,
368                                 unsigned offset, int out)
369 {
370         u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
371         unsigned int gpio_base;
372         unsigned long flags;
373         struct asic3 *asic;
374
375         asic = container_of(chip, struct asic3, gpio);
376         gpio_base = ASIC3_GPIO_TO_BASE(offset);
377
378         if (gpio_base > ASIC3_GPIO_D_BASE) {
379                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
380                         gpio_base, offset);
381                 return -EINVAL;
382         }
383
384         spin_lock_irqsave(&asic->lock, flags);
385
386         out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
387
388         /* Input is 0, Output is 1 */
389         if (out)
390                 out_reg |= mask;
391         else
392                 out_reg &= ~mask;
393
394         asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
395
396         spin_unlock_irqrestore(&asic->lock, flags);
397
398         return 0;
399
400 }
401
402 static int asic3_gpio_direction_input(struct gpio_chip *chip,
403                                       unsigned offset)
404 {
405         return asic3_gpio_direction(chip, offset, 0);
406 }
407
408 static int asic3_gpio_direction_output(struct gpio_chip *chip,
409                                        unsigned offset, int value)
410 {
411         return asic3_gpio_direction(chip, offset, 1);
412 }
413
414 static int asic3_gpio_get(struct gpio_chip *chip,
415                           unsigned offset)
416 {
417         unsigned int gpio_base;
418         u32 mask = ASIC3_GPIO_TO_MASK(offset);
419         struct asic3 *asic;
420
421         asic = container_of(chip, struct asic3, gpio);
422         gpio_base = ASIC3_GPIO_TO_BASE(offset);
423
424         if (gpio_base > ASIC3_GPIO_D_BASE) {
425                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
426                         gpio_base, offset);
427                 return -EINVAL;
428         }
429
430         return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
431 }
432
433 static void asic3_gpio_set(struct gpio_chip *chip,
434                            unsigned offset, int value)
435 {
436         u32 mask, out_reg;
437         unsigned int gpio_base;
438         unsigned long flags;
439         struct asic3 *asic;
440
441         asic = container_of(chip, struct asic3, gpio);
442         gpio_base = ASIC3_GPIO_TO_BASE(offset);
443
444         if (gpio_base > ASIC3_GPIO_D_BASE) {
445                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
446                         gpio_base, offset);
447                 return;
448         }
449
450         mask = ASIC3_GPIO_TO_MASK(offset);
451
452         spin_lock_irqsave(&asic->lock, flags);
453
454         out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
455
456         if (value)
457                 out_reg |= mask;
458         else
459                 out_reg &= ~mask;
460
461         asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
462
463         spin_unlock_irqrestore(&asic->lock, flags);
464
465         return;
466 }
467
468 static __init int asic3_gpio_probe(struct platform_device *pdev,
469                                    u16 *gpio_config, int num)
470 {
471         struct asic3 *asic = platform_get_drvdata(pdev);
472         u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
473         u16 out_reg[ASIC3_NUM_GPIO_BANKS];
474         u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
475         int i;
476
477         memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
478         memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
479         memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
480
481         /* Enable all GPIOs */
482         asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
483         asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
484         asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
485         asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
486
487         for (i = 0; i < num; i++) {
488                 u8 alt, pin, dir, init, bank_num, bit_num;
489                 u16 config = gpio_config[i];
490
491                 pin = ASIC3_CONFIG_GPIO_PIN(config);
492                 alt = ASIC3_CONFIG_GPIO_ALT(config);
493                 dir = ASIC3_CONFIG_GPIO_DIR(config);
494                 init = ASIC3_CONFIG_GPIO_INIT(config);
495
496                 bank_num = ASIC3_GPIO_TO_BANK(pin);
497                 bit_num = ASIC3_GPIO_TO_BIT(pin);
498
499                 alt_reg[bank_num] |= (alt << bit_num);
500                 out_reg[bank_num] |= (init << bit_num);
501                 dir_reg[bank_num] |= (dir << bit_num);
502         }
503
504         for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
505                 asic3_write_register(asic,
506                                      ASIC3_BANK_TO_BASE(i) +
507                                      ASIC3_GPIO_DIRECTION,
508                                      dir_reg[i]);
509                 asic3_write_register(asic,
510                                      ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
511                                      out_reg[i]);
512                 asic3_write_register(asic,
513                                      ASIC3_BANK_TO_BASE(i) +
514                                      ASIC3_GPIO_ALT_FUNCTION,
515                                      alt_reg[i]);
516         }
517
518         return gpiochip_add(&asic->gpio);
519 }
520
521 static int asic3_gpio_remove(struct platform_device *pdev)
522 {
523         struct asic3 *asic = platform_get_drvdata(pdev);
524
525         return gpiochip_remove(&asic->gpio);
526 }
527
528
529 /* Core */
530 static int __init asic3_probe(struct platform_device *pdev)
531 {
532         struct asic3_platform_data *pdata = pdev->dev.platform_data;
533         struct asic3 *asic;
534         struct resource *mem;
535         unsigned long clksel;
536         int map_size;
537         int ret = 0;
538
539         asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
540         if (asic == NULL) {
541                 printk(KERN_ERR "kzalloc failed\n");
542                 return -ENOMEM;
543         }
544
545         spin_lock_init(&asic->lock);
546         platform_set_drvdata(pdev, asic);
547         asic->dev = &pdev->dev;
548
549         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
550         if (!mem) {
551                 ret = -ENOMEM;
552                 dev_err(asic->dev, "no MEM resource\n");
553                 goto out_free;
554         }
555
556         map_size = mem->end - mem->start + 1;
557         asic->mapping = ioremap(mem->start, map_size);
558         if (!asic->mapping) {
559                 ret = -ENOMEM;
560                 dev_err(asic->dev, "Couldn't ioremap\n");
561                 goto out_free;
562         }
563
564         asic->irq_base = pdata->irq_base;
565
566         /* calculate bus shift from mem resource */
567         asic->bus_shift = 2 - (map_size >> 12);
568
569         clksel = 0;
570         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
571
572         ret = asic3_irq_probe(pdev);
573         if (ret < 0) {
574                 dev_err(asic->dev, "Couldn't probe IRQs\n");
575                 goto out_unmap;
576         }
577
578         asic->gpio.base = pdata->gpio_base;
579         asic->gpio.ngpio = ASIC3_NUM_GPIOS;
580         asic->gpio.get = asic3_gpio_get;
581         asic->gpio.set = asic3_gpio_set;
582         asic->gpio.direction_input = asic3_gpio_direction_input;
583         asic->gpio.direction_output = asic3_gpio_direction_output;
584
585         ret = asic3_gpio_probe(pdev,
586                                pdata->gpio_config,
587                                pdata->gpio_config_num);
588         if (ret < 0) {
589                 dev_err(asic->dev, "GPIO probe failed\n");
590                 goto out_irq;
591         }
592
593         dev_info(asic->dev, "ASIC3 Core driver\n");
594
595         return 0;
596
597  out_irq:
598         asic3_irq_remove(pdev);
599
600  out_unmap:
601         iounmap(asic->mapping);
602
603  out_free:
604         kfree(asic);
605
606         return ret;
607 }
608
609 static int asic3_remove(struct platform_device *pdev)
610 {
611         int ret;
612         struct asic3 *asic = platform_get_drvdata(pdev);
613
614         ret = asic3_gpio_remove(pdev);
615         if (ret < 0)
616                 return ret;
617         asic3_irq_remove(pdev);
618
619         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
620
621         iounmap(asic->mapping);
622
623         kfree(asic);
624
625         return 0;
626 }
627
628 static void asic3_shutdown(struct platform_device *pdev)
629 {
630 }
631
632 static struct platform_driver asic3_device_driver = {
633         .driver         = {
634                 .name   = "asic3",
635         },
636         .remove         = __devexit_p(asic3_remove),
637         .shutdown       = asic3_shutdown,
638 };
639
640 static int __init asic3_init(void)
641 {
642         int retval = 0;
643         retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
644         return retval;
645 }
646
647 subsys_initcall(asic3_init);