8355068b0696e65f6975ac08b0bc0bb9edb8e713
[linux-2.6.git] / drivers / ieee1394 / ohci1394.c
1 /*
2  * ohci1394.c - driver for OHCI 1394 boards
3  * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
4  *                        Gord Peters <GordPeters@smarttech.com>
5  *              2001      Ben Collins <bcollins@debian.org>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software Foundation,
19  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20  */
21
22 /*
23  * Things known to be working:
24  * . Async Request Transmit
25  * . Async Response Receive
26  * . Async Request Receive
27  * . Async Response Transmit
28  * . Iso Receive
29  * . DMA mmap for iso receive
30  * . Config ROM generation
31  *
32  * Things implemented, but still in test phase:
33  * . Iso Transmit
34  * . Async Stream Packets Transmit (Receive done via Iso interface)
35  *
36  * Things not implemented:
37  * . DMA error recovery
38  *
39  * Known bugs:
40  * . devctl BUS_RESET arg confusion (reset type or root holdoff?)
41  *   added LONG_RESET_ROOT and SHORT_RESET_ROOT for root holdoff --kk
42  */
43
44 /*
45  * Acknowledgments:
46  *
47  * Adam J Richter <adam@yggdrasil.com>
48  *  . Use of pci_class to find device
49  *
50  * Emilie Chung <emilie.chung@axis.com>
51  *  . Tip on Async Request Filter
52  *
53  * Pascal Drolet <pascal.drolet@informission.ca>
54  *  . Various tips for optimization and functionnalities
55  *
56  * Robert Ficklin <rficklin@westengineering.com>
57  *  . Loop in irq_handler
58  *
59  * James Goodwin <jamesg@Filanet.com>
60  *  . Various tips on initialization, self-id reception, etc.
61  *
62  * Albrecht Dress <ad@mpifr-bonn.mpg.de>
63  *  . Apple PowerBook detection
64  *
65  * Daniel Kobras <daniel.kobras@student.uni-tuebingen.de>
66  *  . Reset the board properly before leaving + misc cleanups
67  *
68  * Leon van Stuivenberg <leonvs@iae.nl>
69  *  . Bug fixes
70  *
71  * Ben Collins <bcollins@debian.org>
72  *  . Working big-endian support
73  *  . Updated to 2.4.x module scheme (PCI aswell)
74  *  . Config ROM generation
75  *
76  * Manfred Weihs <weihs@ict.tuwien.ac.at>
77  *  . Reworked code for initiating bus resets
78  *    (long, short, with or without hold-off)
79  *
80  * Nandu Santhi <contactnandu@users.sourceforge.net>
81  *  . Added support for nVidia nForce2 onboard Firewire chipset
82  *
83  */
84
85 #include <linux/config.h>
86 #include <linux/kernel.h>
87 #include <linux/list.h>
88 #include <linux/slab.h>
89 #include <linux/interrupt.h>
90 #include <linux/wait.h>
91 #include <linux/errno.h>
92 #include <linux/module.h>
93 #include <linux/moduleparam.h>
94 #include <linux/pci.h>
95 #include <linux/fs.h>
96 #include <linux/poll.h>
97 #include <asm/byteorder.h>
98 #include <asm/atomic.h>
99 #include <asm/uaccess.h>
100 #include <linux/delay.h>
101 #include <linux/spinlock.h>
102
103 #include <asm/pgtable.h>
104 #include <asm/page.h>
105 #include <asm/irq.h>
106 #include <linux/sched.h>
107 #include <linux/types.h>
108 #include <linux/vmalloc.h>
109 #include <linux/init.h>
110
111 #ifdef CONFIG_PPC_PMAC
112 #include <asm/machdep.h>
113 #include <asm/pmac_feature.h>
114 #include <asm/prom.h>
115 #include <asm/pci-bridge.h>
116 #endif
117
118 #include "csr1212.h"
119 #include "ieee1394.h"
120 #include "ieee1394_types.h"
121 #include "hosts.h"
122 #include "dma.h"
123 #include "iso.h"
124 #include "ieee1394_core.h"
125 #include "highlevel.h"
126 #include "ohci1394.h"
127
128 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
129 #define OHCI1394_DEBUG
130 #endif
131
132 #ifdef DBGMSG
133 #undef DBGMSG
134 #endif
135
136 #ifdef OHCI1394_DEBUG
137 #define DBGMSG(fmt, args...) \
138 printk(KERN_INFO "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args)
139 #else
140 #define DBGMSG(fmt, args...)
141 #endif
142
143 #ifdef CONFIG_IEEE1394_OHCI_DMA_DEBUG
144 #define OHCI_DMA_ALLOC(fmt, args...) \
145         HPSB_ERR("%s(%s)alloc(%d): "fmt, OHCI1394_DRIVER_NAME, __FUNCTION__, \
146                 ++global_outstanding_dmas, ## args)
147 #define OHCI_DMA_FREE(fmt, args...) \
148         HPSB_ERR("%s(%s)free(%d): "fmt, OHCI1394_DRIVER_NAME, __FUNCTION__, \
149                 --global_outstanding_dmas, ## args)
150 static int global_outstanding_dmas = 0;
151 #else
152 #define OHCI_DMA_ALLOC(fmt, args...)
153 #define OHCI_DMA_FREE(fmt, args...)
154 #endif
155
156 /* print general (card independent) information */
157 #define PRINT_G(level, fmt, args...) \
158 printk(level "%s: " fmt "\n" , OHCI1394_DRIVER_NAME , ## args)
159
160 /* print card specific information */
161 #define PRINT(level, fmt, args...) \
162 printk(level "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args)
163
164 /* Module Parameters */
165 static int phys_dma = 1;
166 module_param(phys_dma, int, 0644);
167 MODULE_PARM_DESC(phys_dma, "Enable physical dma (default = 1).");
168
169 static void dma_trm_tasklet(unsigned long data);
170 static void dma_trm_reset(struct dma_trm_ctx *d);
171
172 static int alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d,
173                              enum context_type type, int ctx, int num_desc,
174                              int buf_size, int split_buf_size, int context_base);
175 static void stop_dma_rcv_ctx(struct dma_rcv_ctx *d);
176 static void free_dma_rcv_ctx(struct dma_rcv_ctx *d);
177
178 static int alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d,
179                              enum context_type type, int ctx, int num_desc,
180                              int context_base);
181
182 static void ohci1394_pci_remove(struct pci_dev *pdev);
183
184 #ifndef __LITTLE_ENDIAN
185 static unsigned hdr_sizes[] =
186 {
187         3,      /* TCODE_WRITEQ */
188         4,      /* TCODE_WRITEB */
189         3,      /* TCODE_WRITE_RESPONSE */
190         0,      /* ??? */
191         3,      /* TCODE_READQ */
192         4,      /* TCODE_READB */
193         3,      /* TCODE_READQ_RESPONSE */
194         4,      /* TCODE_READB_RESPONSE */
195         1,      /* TCODE_CYCLE_START (???) */
196         4,      /* TCODE_LOCK_REQUEST */
197         2,      /* TCODE_ISO_DATA */
198         4,      /* TCODE_LOCK_RESPONSE */
199 };
200
201 /* Swap headers */
202 static inline void packet_swab(quadlet_t *data, int tcode)
203 {
204         size_t size = hdr_sizes[tcode];
205
206         if (tcode > TCODE_LOCK_RESPONSE || hdr_sizes[tcode] == 0)
207                 return;
208
209         while (size--)
210                 data[size] = swab32(data[size]);
211 }
212 #else
213 /* Don't waste cycles on same sex byte swaps */
214 #define packet_swab(w,x)
215 #endif /* !LITTLE_ENDIAN */
216
217 /***********************************
218  * IEEE-1394 functionality section *
219  ***********************************/
220
221 static u8 get_phy_reg(struct ti_ohci *ohci, u8 addr)
222 {
223         int i;
224         unsigned long flags;
225         quadlet_t r;
226
227         spin_lock_irqsave (&ohci->phy_reg_lock, flags);
228
229         reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000);
230
231         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
232                 if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000)
233                         break;
234
235                 mdelay(1);
236         }
237
238         r = reg_read(ohci, OHCI1394_PhyControl);
239
240         if (i >= OHCI_LOOP_COUNT)
241                 PRINT (KERN_ERR, "Get PHY Reg timeout [0x%08x/0x%08x/%d]",
242                        r, r & 0x80000000, i);
243
244         spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
245
246         return (r & 0x00ff0000) >> 16;
247 }
248
249 static void set_phy_reg(struct ti_ohci *ohci, u8 addr, u8 data)
250 {
251         int i;
252         unsigned long flags;
253         u32 r = 0;
254
255         spin_lock_irqsave (&ohci->phy_reg_lock, flags);
256
257         reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000);
258
259         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
260                 r = reg_read(ohci, OHCI1394_PhyControl);
261                 if (!(r & 0x00004000))
262                         break;
263
264                 mdelay(1);
265         }
266
267         if (i == OHCI_LOOP_COUNT)
268                 PRINT (KERN_ERR, "Set PHY Reg timeout [0x%08x/0x%08x/%d]",
269                        r, r & 0x00004000, i);
270
271         spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
272
273         return;
274 }
275
276 /* Or's our value into the current value */
277 static void set_phy_reg_mask(struct ti_ohci *ohci, u8 addr, u8 data)
278 {
279         u8 old;
280
281         old = get_phy_reg (ohci, addr);
282         old |= data;
283         set_phy_reg (ohci, addr, old);
284
285         return;
286 }
287
288 static void handle_selfid(struct ti_ohci *ohci, struct hpsb_host *host,
289                                 int phyid, int isroot)
290 {
291         quadlet_t *q = ohci->selfid_buf_cpu;
292         quadlet_t self_id_count=reg_read(ohci, OHCI1394_SelfIDCount);
293         size_t size;
294         quadlet_t q0, q1;
295
296         /* Check status of self-id reception */
297
298         if (ohci->selfid_swap)
299                 q0 = le32_to_cpu(q[0]);
300         else
301                 q0 = q[0];
302
303         if ((self_id_count & 0x80000000) ||
304             ((self_id_count & 0x00FF0000) != (q0 & 0x00FF0000))) {
305                 PRINT(KERN_ERR,
306                       "Error in reception of SelfID packets [0x%08x/0x%08x] (count: %d)",
307                       self_id_count, q0, ohci->self_id_errors);
308
309                 /* Tip by James Goodwin <jamesg@Filanet.com>:
310                  * We had an error, generate another bus reset in response.  */
311                 if (ohci->self_id_errors<OHCI1394_MAX_SELF_ID_ERRORS) {
312                         set_phy_reg_mask (ohci, 1, 0x40);
313                         ohci->self_id_errors++;
314                 } else {
315                         PRINT(KERN_ERR,
316                               "Too many errors on SelfID error reception, giving up!");
317                 }
318                 return;
319         }
320
321         /* SelfID Ok, reset error counter. */
322         ohci->self_id_errors = 0;
323
324         size = ((self_id_count & 0x00001FFC) >> 2) - 1;
325         q++;
326
327         while (size > 0) {
328                 if (ohci->selfid_swap) {
329                         q0 = le32_to_cpu(q[0]);
330                         q1 = le32_to_cpu(q[1]);
331                 } else {
332                         q0 = q[0];
333                         q1 = q[1];
334                 }
335
336                 if (q0 == ~q1) {
337                         DBGMSG ("SelfID packet 0x%x received", q0);
338                         hpsb_selfid_received(host, cpu_to_be32(q0));
339                         if (((q0 & 0x3f000000) >> 24) == phyid)
340                                 DBGMSG ("SelfID for this node is 0x%08x", q0);
341                 } else {
342                         PRINT(KERN_ERR,
343                               "SelfID is inconsistent [0x%08x/0x%08x]", q0, q1);
344                 }
345                 q += 2;
346                 size -= 2;
347         }
348
349         DBGMSG("SelfID complete");
350
351         return;
352 }
353
354 static void ohci_soft_reset(struct ti_ohci *ohci) {
355         int i;
356
357         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
358
359         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
360                 if (!(reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_softReset))
361                         break;
362                 mdelay(1);
363         }
364         DBGMSG ("Soft reset finished");
365 }
366
367
368 /* Generate the dma receive prgs and start the context */
369 static void initialize_dma_rcv_ctx(struct dma_rcv_ctx *d, int generate_irq)
370 {
371         struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
372         int i;
373
374         ohci1394_stop_context(ohci, d->ctrlClear, NULL);
375
376         for (i=0; i<d->num_desc; i++) {
377                 u32 c;
378
379                 c = DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | DMA_CTL_BRANCH;
380                 if (generate_irq)
381                         c |= DMA_CTL_IRQ;
382
383                 d->prg_cpu[i]->control = cpu_to_le32(c | d->buf_size);
384
385                 /* End of descriptor list? */
386                 if (i + 1 < d->num_desc) {
387                         d->prg_cpu[i]->branchAddress =
388                                 cpu_to_le32((d->prg_bus[i+1] & 0xfffffff0) | 0x1);
389                 } else {
390                         d->prg_cpu[i]->branchAddress =
391                                 cpu_to_le32((d->prg_bus[0] & 0xfffffff0));
392                 }
393
394                 d->prg_cpu[i]->address = cpu_to_le32(d->buf_bus[i]);
395                 d->prg_cpu[i]->status = cpu_to_le32(d->buf_size);
396         }
397
398         d->buf_ind = 0;
399         d->buf_offset = 0;
400
401         if (d->type == DMA_CTX_ISO) {
402                 /* Clear contextControl */
403                 reg_write(ohci, d->ctrlClear, 0xffffffff);
404
405                 /* Set bufferFill, isochHeader, multichannel for IR context */
406                 reg_write(ohci, d->ctrlSet, 0xd0000000);
407
408                 /* Set the context match register to match on all tags */
409                 reg_write(ohci, d->ctxtMatch, 0xf0000000);
410
411                 /* Clear the multi channel mask high and low registers */
412                 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, 0xffffffff);
413                 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, 0xffffffff);
414
415                 /* Set up isoRecvIntMask to generate interrupts */
416                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << d->ctx);
417         }
418
419         /* Tell the controller where the first AR program is */
420         reg_write(ohci, d->cmdPtr, d->prg_bus[0] | 0x1);
421
422         /* Run context */
423         reg_write(ohci, d->ctrlSet, 0x00008000);
424
425         DBGMSG("Receive DMA ctx=%d initialized", d->ctx);
426 }
427
428 /* Initialize the dma transmit context */
429 static void initialize_dma_trm_ctx(struct dma_trm_ctx *d)
430 {
431         struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
432
433         /* Stop the context */
434         ohci1394_stop_context(ohci, d->ctrlClear, NULL);
435
436         d->prg_ind = 0;
437         d->sent_ind = 0;
438         d->free_prgs = d->num_desc;
439         d->branchAddrPtr = NULL;
440         INIT_LIST_HEAD(&d->fifo_list);
441         INIT_LIST_HEAD(&d->pending_list);
442
443         if (d->type == DMA_CTX_ISO) {
444                 /* enable interrupts */
445                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << d->ctx);
446         }
447
448         DBGMSG("Transmit DMA ctx=%d initialized", d->ctx);
449 }
450
451 /* Count the number of available iso contexts */
452 static int get_nb_iso_ctx(struct ti_ohci *ohci, int reg)
453 {
454         int i,ctx=0;
455         u32 tmp;
456
457         reg_write(ohci, reg, 0xffffffff);
458         tmp = reg_read(ohci, reg);
459
460         DBGMSG("Iso contexts reg: %08x implemented: %08x", reg, tmp);
461
462         /* Count the number of contexts */
463         for (i=0; i<32; i++) {
464                 if (tmp & 1) ctx++;
465                 tmp >>= 1;
466         }
467         return ctx;
468 }
469
470 /* Global initialization */
471 static void ohci_initialize(struct ti_ohci *ohci)
472 {
473         char irq_buf[16];
474         quadlet_t buf;
475         int num_ports, i;
476
477         spin_lock_init(&ohci->phy_reg_lock);
478
479         /* Put some defaults to these undefined bus options */
480         buf = reg_read(ohci, OHCI1394_BusOptions);
481         buf |=  0x60000000; /* Enable CMC and ISC */
482         if (hpsb_disable_irm)
483                 buf &= ~0x80000000;
484         else
485                 buf |=  0x80000000; /* Enable IRMC */
486         buf &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */
487         buf &= ~0x18000000; /* Disable PMC and BMC */
488         reg_write(ohci, OHCI1394_BusOptions, buf);
489
490         /* Set the bus number */
491         reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
492
493         /* Enable posted writes */
494         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_postedWriteEnable);
495
496         /* Clear link control register */
497         reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
498
499         /* Enable cycle timer and cycle master and set the IRM
500          * contender bit in our self ID packets if appropriate. */
501         reg_write(ohci, OHCI1394_LinkControlSet,
502                   OHCI1394_LinkControl_CycleTimerEnable |
503                   OHCI1394_LinkControl_CycleMaster);
504         i = get_phy_reg(ohci, 4) | PHY_04_LCTRL;
505         if (hpsb_disable_irm)
506                 i &= ~PHY_04_CONTENDER;
507         else
508                 i |= PHY_04_CONTENDER;
509         set_phy_reg(ohci, 4, i);
510
511         /* Set up self-id dma buffer */
512         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus);
513
514         /* enable self-id and phys */
515         reg_write(ohci, OHCI1394_LinkControlSet, OHCI1394_LinkControl_RcvSelfID |
516                   OHCI1394_LinkControl_RcvPhyPkt);
517
518         /* Set the Config ROM mapping register */
519         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->csr_config_rom_bus);
520
521         /* Now get our max packet size */
522         ohci->max_packet_size =
523                 1<<(((reg_read(ohci, OHCI1394_BusOptions)>>12)&0xf)+1);
524                 
525         /* Don't accept phy packets into AR request context */
526         reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400);
527
528         /* Clear the interrupt mask */
529         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
530         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
531
532         /* Clear the interrupt mask */
533         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
534         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
535
536         /* Initialize AR dma */
537         initialize_dma_rcv_ctx(&ohci->ar_req_context, 0);
538         initialize_dma_rcv_ctx(&ohci->ar_resp_context, 0);
539
540         /* Initialize AT dma */
541         initialize_dma_trm_ctx(&ohci->at_req_context);
542         initialize_dma_trm_ctx(&ohci->at_resp_context);
543         
544         /* Initialize IR Legacy DMA channel mask */
545         ohci->ir_legacy_channels = 0;
546
547         /*
548          * Accept AT requests from all nodes. This probably
549          * will have to be controlled from the subsystem
550          * on a per node basis.
551          */
552         reg_write(ohci,OHCI1394_AsReqFilterHiSet, 0x80000000);
553
554         /* Specify AT retries */
555         reg_write(ohci, OHCI1394_ATRetries,
556                   OHCI1394_MAX_AT_REQ_RETRIES |
557                   (OHCI1394_MAX_AT_RESP_RETRIES<<4) |
558                   (OHCI1394_MAX_PHYS_RESP_RETRIES<<8));
559
560         /* We don't want hardware swapping */
561         reg_write(ohci, OHCI1394_HCControlClear, OHCI1394_HCControl_noByteSwap);
562
563         /* Enable interrupts */
564         reg_write(ohci, OHCI1394_IntMaskSet,
565                   OHCI1394_unrecoverableError |
566                   OHCI1394_masterIntEnable |
567                   OHCI1394_busReset |
568                   OHCI1394_selfIDComplete |
569                   OHCI1394_RSPkt |
570                   OHCI1394_RQPkt |
571                   OHCI1394_respTxComplete |
572                   OHCI1394_reqTxComplete |
573                   OHCI1394_isochRx |
574                   OHCI1394_isochTx |
575                   OHCI1394_cycleInconsistent);
576
577         /* Enable link */
578         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);
579
580         buf = reg_read(ohci, OHCI1394_Version);
581 #ifndef __sparc__
582         sprintf (irq_buf, "%d", ohci->dev->irq);
583 #else
584         sprintf (irq_buf, "%s", __irq_itoa(ohci->dev->irq));
585 #endif
586         PRINT(KERN_INFO, "OHCI-1394 %d.%d (PCI): IRQ=[%s]  "
587               "MMIO=[%lx-%lx]  Max Packet=[%d]",
588               ((((buf) >> 16) & 0xf) + (((buf) >> 20) & 0xf) * 10),
589               ((((buf) >> 4) & 0xf) + ((buf) & 0xf) * 10), irq_buf,
590               pci_resource_start(ohci->dev, 0),
591               pci_resource_start(ohci->dev, 0) + OHCI1394_REGISTER_SIZE - 1,
592               ohci->max_packet_size);
593
594         /* Check all of our ports to make sure that if anything is
595          * connected, we enable that port. */
596         num_ports = get_phy_reg(ohci, 2) & 0xf;
597         for (i = 0; i < num_ports; i++) {
598                 unsigned int status;
599
600                 set_phy_reg(ohci, 7, i);
601                 status = get_phy_reg(ohci, 8);
602
603                 if (status & 0x20)
604                         set_phy_reg(ohci, 8, status & ~1);
605         }
606
607         /* Serial EEPROM Sanity check. */
608         if ((ohci->max_packet_size < 512) ||
609             (ohci->max_packet_size > 4096)) {
610                 /* Serial EEPROM contents are suspect, set a sane max packet
611                  * size and print the raw contents for bug reports if verbose
612                  * debug is enabled. */
613 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
614                 int i;
615 #endif
616
617                 PRINT(KERN_DEBUG, "Serial EEPROM has suspicious values, "
618                       "attempting to setting max_packet_size to 512 bytes");
619                 reg_write(ohci, OHCI1394_BusOptions,
620                           (reg_read(ohci, OHCI1394_BusOptions) & 0xf007) | 0x8002);
621                 ohci->max_packet_size = 512;
622 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
623                 PRINT(KERN_DEBUG, "    EEPROM Present: %d",
624                       (reg_read(ohci, OHCI1394_Version) >> 24) & 0x1);
625                 reg_write(ohci, OHCI1394_GUID_ROM, 0x80000000);
626
627                 for (i = 0;
628                      ((i < 1000) &&
629                       (reg_read(ohci, OHCI1394_GUID_ROM) & 0x80000000)); i++)
630                         udelay(10);
631
632                 for (i = 0; i < 0x20; i++) {
633                         reg_write(ohci, OHCI1394_GUID_ROM, 0x02000000);
634                         PRINT(KERN_DEBUG, "    EEPROM %02x: %02x", i,
635                               (reg_read(ohci, OHCI1394_GUID_ROM) >> 16) & 0xff);
636                 }
637 #endif
638         }
639 }
640
641 /*
642  * Insert a packet in the DMA fifo and generate the DMA prg
643  * FIXME: rewrite the program in order to accept packets crossing
644  *        page boundaries.
645  *        check also that a single dma descriptor doesn't cross a
646  *        page boundary.
647  */
648 static void insert_packet(struct ti_ohci *ohci,
649                           struct dma_trm_ctx *d, struct hpsb_packet *packet)
650 {
651         u32 cycleTimer;
652         int idx = d->prg_ind;
653
654         DBGMSG("Inserting packet for node " NODE_BUS_FMT
655                ", tlabel=%d, tcode=0x%x, speed=%d",
656                NODE_BUS_ARGS(ohci->host, packet->node_id), packet->tlabel,
657                packet->tcode, packet->speed_code);
658
659         d->prg_cpu[idx]->begin.address = 0;
660         d->prg_cpu[idx]->begin.branchAddress = 0;
661
662         if (d->type == DMA_CTX_ASYNC_RESP) {
663                 /*
664                  * For response packets, we need to put a timeout value in
665                  * the 16 lower bits of the status... let's try 1 sec timeout
666                  */
667                 cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
668                 d->prg_cpu[idx]->begin.status = cpu_to_le32(
669                         (((((cycleTimer>>25)&0x7)+1)&0x7)<<13) |
670                         ((cycleTimer&0x01fff000)>>12));
671
672                 DBGMSG("cycleTimer: %08x timeStamp: %08x",
673                        cycleTimer, d->prg_cpu[idx]->begin.status);
674         } else 
675                 d->prg_cpu[idx]->begin.status = 0;
676
677         if ( (packet->type == hpsb_async) || (packet->type == hpsb_raw) ) {
678
679                 if (packet->type == hpsb_raw) {
680                         d->prg_cpu[idx]->data[0] = cpu_to_le32(OHCI1394_TCODE_PHY<<4);
681                         d->prg_cpu[idx]->data[1] = cpu_to_le32(packet->header[0]);
682                         d->prg_cpu[idx]->data[2] = cpu_to_le32(packet->header[1]);
683                 } else {
684                         d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
685                                 (packet->header[0] & 0xFFFF);
686
687                         if (packet->tcode == TCODE_ISO_DATA) {
688                                 /* Sending an async stream packet */
689                                 d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000;
690                         } else {
691                                 /* Sending a normal async request or response */
692                                 d->prg_cpu[idx]->data[1] =
693                                         (packet->header[1] & 0xFFFF) |
694                                         (packet->header[0] & 0xFFFF0000);
695                                 d->prg_cpu[idx]->data[2] = packet->header[2];
696                                 d->prg_cpu[idx]->data[3] = packet->header[3];
697                         }
698                         packet_swab(d->prg_cpu[idx]->data, packet->tcode);
699                 }
700
701                 if (packet->data_size) { /* block transmit */
702                         if (packet->tcode == TCODE_STREAM_DATA){
703                                 d->prg_cpu[idx]->begin.control =
704                                         cpu_to_le32(DMA_CTL_OUTPUT_MORE |
705                                                     DMA_CTL_IMMEDIATE | 0x8);
706                         } else {
707                                 d->prg_cpu[idx]->begin.control =
708                                         cpu_to_le32(DMA_CTL_OUTPUT_MORE |
709                                                     DMA_CTL_IMMEDIATE | 0x10);
710                         }
711                         d->prg_cpu[idx]->end.control =
712                                 cpu_to_le32(DMA_CTL_OUTPUT_LAST |
713                                             DMA_CTL_IRQ |
714                                             DMA_CTL_BRANCH |
715                                             packet->data_size);
716                         /*
717                          * Check that the packet data buffer
718                          * does not cross a page boundary.
719                          *
720                          * XXX Fix this some day. eth1394 seems to trigger
721                          * it, but ignoring it doesn't seem to cause a
722                          * problem.
723                          */
724 #if 0
725                         if (cross_bound((unsigned long)packet->data,
726                                         packet->data_size)>0) {
727                                 /* FIXME: do something about it */
728                                 PRINT(KERN_ERR,
729                                       "%s: packet data addr: %p size %Zd bytes "
730                                       "cross page boundary", __FUNCTION__,
731                                       packet->data, packet->data_size);
732                         }
733 #endif
734                         d->prg_cpu[idx]->end.address = cpu_to_le32(
735                                 pci_map_single(ohci->dev, packet->data,
736                                                packet->data_size,
737                                                PCI_DMA_TODEVICE));
738                         OHCI_DMA_ALLOC("single, block transmit packet");
739
740                         d->prg_cpu[idx]->end.branchAddress = 0;
741                         d->prg_cpu[idx]->end.status = 0;
742                         if (d->branchAddrPtr)
743                                 *(d->branchAddrPtr) =
744                                         cpu_to_le32(d->prg_bus[idx] | 0x3);
745                         d->branchAddrPtr =
746                                 &(d->prg_cpu[idx]->end.branchAddress);
747                 } else { /* quadlet transmit */
748                         if (packet->type == hpsb_raw)
749                                 d->prg_cpu[idx]->begin.control =
750                                         cpu_to_le32(DMA_CTL_OUTPUT_LAST |
751                                                     DMA_CTL_IMMEDIATE |
752                                                     DMA_CTL_IRQ |
753                                                     DMA_CTL_BRANCH |
754                                                     (packet->header_size + 4));
755                         else
756                                 d->prg_cpu[idx]->begin.control =
757                                         cpu_to_le32(DMA_CTL_OUTPUT_LAST |
758                                                     DMA_CTL_IMMEDIATE |
759                                                     DMA_CTL_IRQ |
760                                                     DMA_CTL_BRANCH |
761                                                     packet->header_size);
762
763                         if (d->branchAddrPtr)
764                                 *(d->branchAddrPtr) =
765                                         cpu_to_le32(d->prg_bus[idx] | 0x2);
766                         d->branchAddrPtr =
767                                 &(d->prg_cpu[idx]->begin.branchAddress);
768                 }
769
770         } else { /* iso packet */
771                 d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
772                         (packet->header[0] & 0xFFFF);
773                 d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000;
774                 packet_swab(d->prg_cpu[idx]->data, packet->tcode);
775
776                 d->prg_cpu[idx]->begin.control =
777                         cpu_to_le32(DMA_CTL_OUTPUT_MORE |
778                                     DMA_CTL_IMMEDIATE | 0x8);
779                 d->prg_cpu[idx]->end.control =
780                         cpu_to_le32(DMA_CTL_OUTPUT_LAST |
781                                     DMA_CTL_UPDATE |
782                                     DMA_CTL_IRQ |
783                                     DMA_CTL_BRANCH |
784                                     packet->data_size);
785                 d->prg_cpu[idx]->end.address = cpu_to_le32(
786                                 pci_map_single(ohci->dev, packet->data,
787                                 packet->data_size, PCI_DMA_TODEVICE));
788                 OHCI_DMA_ALLOC("single, iso transmit packet");
789
790                 d->prg_cpu[idx]->end.branchAddress = 0;
791                 d->prg_cpu[idx]->end.status = 0;
792                 DBGMSG("Iso xmit context info: header[%08x %08x]\n"
793                        "                       begin=%08x %08x %08x %08x\n"
794                        "                             %08x %08x %08x %08x\n"
795                        "                       end  =%08x %08x %08x %08x",
796                        d->prg_cpu[idx]->data[0], d->prg_cpu[idx]->data[1],
797                        d->prg_cpu[idx]->begin.control,
798                        d->prg_cpu[idx]->begin.address,
799                        d->prg_cpu[idx]->begin.branchAddress,
800                        d->prg_cpu[idx]->begin.status,
801                        d->prg_cpu[idx]->data[0],
802                        d->prg_cpu[idx]->data[1],
803                        d->prg_cpu[idx]->data[2],
804                        d->prg_cpu[idx]->data[3],
805                        d->prg_cpu[idx]->end.control,
806                        d->prg_cpu[idx]->end.address,
807                        d->prg_cpu[idx]->end.branchAddress,
808                        d->prg_cpu[idx]->end.status);
809                 if (d->branchAddrPtr)
810                         *(d->branchAddrPtr) = cpu_to_le32(d->prg_bus[idx] | 0x3);
811                 d->branchAddrPtr = &(d->prg_cpu[idx]->end.branchAddress);
812         }
813         d->free_prgs--;
814
815         /* queue the packet in the appropriate context queue */
816         list_add_tail(&packet->driver_list, &d->fifo_list);
817         d->prg_ind = (d->prg_ind + 1) % d->num_desc;
818 }
819
820 /*
821  * This function fills the FIFO with the (eventual) pending packets
822  * and runs or wakes up the DMA prg if necessary.
823  *
824  * The function MUST be called with the d->lock held.
825  */
826 static void dma_trm_flush(struct ti_ohci *ohci, struct dma_trm_ctx *d)
827 {
828         struct hpsb_packet *packet, *ptmp;
829         int idx = d->prg_ind;
830         int z = 0;
831
832         /* insert the packets into the dma fifo */
833         list_for_each_entry_safe(packet, ptmp, &d->pending_list, driver_list) {
834                 if (!d->free_prgs)
835                         break;
836
837                 /* For the first packet only */
838                 if (!z)
839                         z = (packet->data_size) ? 3 : 2;
840
841                 /* Insert the packet */
842                 list_del_init(&packet->driver_list);
843                 insert_packet(ohci, d, packet);
844         }
845
846         /* Nothing must have been done, either no free_prgs or no packets */
847         if (z == 0)
848                 return;
849
850         /* Is the context running ? (should be unless it is
851            the first packet to be sent in this context) */
852         if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) {
853                 u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
854
855                 DBGMSG("Starting transmit DMA ctx=%d",d->ctx);
856                 reg_write(ohci, d->cmdPtr, d->prg_bus[idx] | z);
857
858                 /* Check that the node id is valid, and not 63 */
859                 if (!(nodeId & 0x80000000) || (nodeId & 0x3f) == 63)
860                         PRINT(KERN_ERR, "Running dma failed because Node ID is not valid");
861                 else
862                         reg_write(ohci, d->ctrlSet, 0x8000);
863         } else {
864                 /* Wake up the dma context if necessary */
865                 if (!(reg_read(ohci, d->ctrlSet) & 0x400))
866                         DBGMSG("Waking transmit DMA ctx=%d",d->ctx);
867
868                 /* do this always, to avoid race condition */
869                 reg_write(ohci, d->ctrlSet, 0x1000);
870         }
871
872         return;
873 }
874
875 /* Transmission of an async or iso packet */
876 static int ohci_transmit(struct hpsb_host *host, struct hpsb_packet *packet)
877 {
878         struct ti_ohci *ohci = host->hostdata;
879         struct dma_trm_ctx *d;
880         unsigned long flags;
881
882         if (packet->data_size > ohci->max_packet_size) {
883                 PRINT(KERN_ERR,
884                       "Transmit packet size %Zd is too big",
885                       packet->data_size);
886                 return -EOVERFLOW;
887         }
888
889         /* Decide whether we have an iso, a request, or a response packet */
890         if (packet->type == hpsb_raw)
891                 d = &ohci->at_req_context;
892         else if ((packet->tcode == TCODE_ISO_DATA) && (packet->type == hpsb_iso)) {
893                 /* The legacy IT DMA context is initialized on first
894                  * use.  However, the alloc cannot be run from
895                  * interrupt context, so we bail out if that is the
896                  * case. I don't see anyone sending ISO packets from
897                  * interrupt context anyway... */
898
899                 if (ohci->it_legacy_context.ohci == NULL) {
900                         if (in_interrupt()) {
901                                 PRINT(KERN_ERR,
902                                       "legacy IT context cannot be initialized during interrupt");
903                                 return -EINVAL;
904                         }
905
906                         if (alloc_dma_trm_ctx(ohci, &ohci->it_legacy_context,
907                                               DMA_CTX_ISO, 0, IT_NUM_DESC,
908                                               OHCI1394_IsoXmitContextBase) < 0) {
909                                 PRINT(KERN_ERR,
910                                       "error initializing legacy IT context");
911                                 return -ENOMEM;
912                         }
913
914                         initialize_dma_trm_ctx(&ohci->it_legacy_context);
915                 }
916
917                 d = &ohci->it_legacy_context;
918         } else if ((packet->tcode & 0x02) && (packet->tcode != TCODE_ISO_DATA))
919                 d = &ohci->at_resp_context;
920         else
921                 d = &ohci->at_req_context;
922
923         spin_lock_irqsave(&d->lock,flags);
924
925         list_add_tail(&packet->driver_list, &d->pending_list);
926
927         dma_trm_flush(ohci, d);
928
929         spin_unlock_irqrestore(&d->lock,flags);
930
931         return 0;
932 }
933
934 static int ohci_devctl(struct hpsb_host *host, enum devctl_cmd cmd, int arg)
935 {
936         struct ti_ohci *ohci = host->hostdata;
937         int retval = 0;
938         unsigned long flags;
939         int phy_reg;
940
941         switch (cmd) {
942         case RESET_BUS:
943                 switch (arg) {
944                 case SHORT_RESET:
945                         phy_reg = get_phy_reg(ohci, 5);
946                         phy_reg |= 0x40;
947                         set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
948                         break;
949                 case LONG_RESET:
950                         phy_reg = get_phy_reg(ohci, 1);
951                         phy_reg |= 0x40;
952                         set_phy_reg(ohci, 1, phy_reg); /* set IBR */
953                         break;
954                 case SHORT_RESET_NO_FORCE_ROOT:
955                         phy_reg = get_phy_reg(ohci, 1);
956                         if (phy_reg & 0x80) {
957                                 phy_reg &= ~0x80;
958                                 set_phy_reg(ohci, 1, phy_reg); /* clear RHB */
959                         }
960
961                         phy_reg = get_phy_reg(ohci, 5);
962                         phy_reg |= 0x40;
963                         set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
964                         break;
965                 case LONG_RESET_NO_FORCE_ROOT:
966                         phy_reg = get_phy_reg(ohci, 1);
967                         phy_reg &= ~0x80;
968                         phy_reg |= 0x40;
969                         set_phy_reg(ohci, 1, phy_reg); /* clear RHB, set IBR */
970                         break;
971                 case SHORT_RESET_FORCE_ROOT:
972                         phy_reg = get_phy_reg(ohci, 1);
973                         if (!(phy_reg & 0x80)) {
974                                 phy_reg |= 0x80;
975                                 set_phy_reg(ohci, 1, phy_reg); /* set RHB */
976                         }
977
978                         phy_reg = get_phy_reg(ohci, 5);
979                         phy_reg |= 0x40;
980                         set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
981                         break;
982                 case LONG_RESET_FORCE_ROOT:
983                         phy_reg = get_phy_reg(ohci, 1);
984                         phy_reg |= 0xc0;
985                         set_phy_reg(ohci, 1, phy_reg); /* set RHB and IBR */
986                         break;
987                 default:
988                         retval = -1;
989                 }
990                 break;
991
992         case GET_CYCLE_COUNTER:
993                 retval = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
994                 break;
995
996         case SET_CYCLE_COUNTER:
997                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, arg);
998                 break;
999
1000         case SET_BUS_ID:
1001                 PRINT(KERN_ERR, "devctl command SET_BUS_ID err");
1002                 break;
1003
1004         case ACT_CYCLE_MASTER:
1005                 if (arg) {
1006                         /* check if we are root and other nodes are present */
1007                         u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
1008                         if ((nodeId & (1<<30)) && (nodeId & 0x3f)) {
1009                                 /*
1010                                  * enable cycleTimer, cycleMaster
1011                                  */
1012                                 DBGMSG("Cycle master enabled");
1013                                 reg_write(ohci, OHCI1394_LinkControlSet,
1014                                           OHCI1394_LinkControl_CycleTimerEnable |
1015                                           OHCI1394_LinkControl_CycleMaster);
1016                         }
1017                 } else {
1018                         /* disable cycleTimer, cycleMaster, cycleSource */
1019                         reg_write(ohci, OHCI1394_LinkControlClear,
1020                                   OHCI1394_LinkControl_CycleTimerEnable |
1021                                   OHCI1394_LinkControl_CycleMaster |
1022                                   OHCI1394_LinkControl_CycleSource);
1023                 }
1024                 break;
1025
1026         case CANCEL_REQUESTS:
1027                 DBGMSG("Cancel request received");
1028                 dma_trm_reset(&ohci->at_req_context);
1029                 dma_trm_reset(&ohci->at_resp_context);
1030                 break;
1031
1032         case ISO_LISTEN_CHANNEL:
1033         {
1034                 u64 mask;
1035                 struct dma_rcv_ctx *d = &ohci->ir_legacy_context;
1036                 int ir_legacy_active;
1037
1038                 if (arg<0 || arg>63) {
1039                         PRINT(KERN_ERR,
1040                               "%s: IS0 listen channel %d is out of range",
1041                               __FUNCTION__, arg);
1042                         return -EFAULT;
1043                 }
1044
1045                 mask = (u64)0x1<<arg;
1046
1047                 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
1048
1049                 if (ohci->ISO_channel_usage & mask) {
1050                         PRINT(KERN_ERR,
1051                               "%s: IS0 listen channel %d is already used",
1052                               __FUNCTION__, arg);
1053                         spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1054                         return -EFAULT;
1055                 }
1056
1057                 ir_legacy_active = ohci->ir_legacy_channels;
1058
1059                 ohci->ISO_channel_usage |= mask;
1060                 ohci->ir_legacy_channels |= mask;
1061
1062                 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1063
1064                 if (!ir_legacy_active) {
1065                         if (ohci1394_register_iso_tasklet(ohci,
1066                                           &ohci->ir_legacy_tasklet) < 0) {
1067                                 PRINT(KERN_ERR, "No IR DMA context available");
1068                                 return -EBUSY;
1069                         }
1070
1071                         /* the IR context can be assigned to any DMA context
1072                          * by ohci1394_register_iso_tasklet */
1073                         d->ctx = ohci->ir_legacy_tasklet.context;
1074                         d->ctrlSet = OHCI1394_IsoRcvContextControlSet +
1075                                 32*d->ctx;
1076                         d->ctrlClear = OHCI1394_IsoRcvContextControlClear +
1077                                 32*d->ctx;
1078                         d->cmdPtr = OHCI1394_IsoRcvCommandPtr + 32*d->ctx;
1079                         d->ctxtMatch = OHCI1394_IsoRcvContextMatch + 32*d->ctx;
1080
1081                         initialize_dma_rcv_ctx(&ohci->ir_legacy_context, 1);
1082
1083                         if (printk_ratelimit())
1084                                 DBGMSG("IR legacy activated");
1085                 }
1086
1087                 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
1088
1089                 if (arg>31)
1090                         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet,
1091                                   1<<(arg-32));
1092                 else
1093                         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet,
1094                                   1<<arg);
1095
1096                 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1097                 DBGMSG("Listening enabled on channel %d", arg);
1098                 break;
1099         }
1100         case ISO_UNLISTEN_CHANNEL:
1101         {
1102                 u64 mask;
1103
1104                 if (arg<0 || arg>63) {
1105                         PRINT(KERN_ERR,
1106                               "%s: IS0 unlisten channel %d is out of range",
1107                               __FUNCTION__, arg);
1108                         return -EFAULT;
1109                 }
1110
1111                 mask = (u64)0x1<<arg;
1112
1113                 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
1114
1115                 if (!(ohci->ISO_channel_usage & mask)) {
1116                         PRINT(KERN_ERR,
1117                               "%s: IS0 unlisten channel %d is not used",
1118                               __FUNCTION__, arg);
1119                         spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1120                         return -EFAULT;
1121                 }
1122
1123                 ohci->ISO_channel_usage &= ~mask;
1124                 ohci->ir_legacy_channels &= ~mask;
1125
1126                 if (arg>31)
1127                         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear,
1128                                   1<<(arg-32));
1129                 else
1130                         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear,
1131                                   1<<arg);
1132
1133                 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1134                 DBGMSG("Listening disabled on channel %d", arg);
1135
1136                 if (ohci->ir_legacy_channels == 0) {
1137                         stop_dma_rcv_ctx(&ohci->ir_legacy_context);
1138                         DBGMSG("ISO legacy receive context stopped");
1139                 }
1140
1141                 break;
1142         }
1143         default:
1144                 PRINT_G(KERN_ERR, "ohci_devctl cmd %d not implemented yet",
1145                         cmd);
1146                 break;
1147         }
1148         return retval;
1149 }
1150
1151 /***********************************
1152  * rawiso ISO reception            *
1153  ***********************************/
1154
1155 /*
1156   We use either buffer-fill or packet-per-buffer DMA mode. The DMA
1157   buffer is split into "blocks" (regions described by one DMA
1158   descriptor). Each block must be one page or less in size, and
1159   must not cross a page boundary.
1160
1161   There is one little wrinkle with buffer-fill mode: a packet that
1162   starts in the final block may wrap around into the first block. But
1163   the user API expects all packets to be contiguous. Our solution is
1164   to keep the very last page of the DMA buffer in reserve - if a
1165   packet spans the gap, we copy its tail into this page.
1166 */
1167
1168 struct ohci_iso_recv {
1169         struct ti_ohci *ohci;
1170
1171         struct ohci1394_iso_tasklet task;
1172         int task_active;
1173
1174         enum { BUFFER_FILL_MODE = 0,
1175                PACKET_PER_BUFFER_MODE = 1 } dma_mode;
1176
1177         /* memory and PCI mapping for the DMA descriptors */
1178         struct dma_prog_region prog;
1179         struct dma_cmd *block; /* = (struct dma_cmd*) prog.virt */
1180
1181         /* how many DMA blocks fit in the buffer */
1182         unsigned int nblocks;
1183
1184         /* stride of DMA blocks */
1185         unsigned int buf_stride;
1186
1187         /* number of blocks to batch between interrupts */
1188         int block_irq_interval;
1189
1190         /* block that DMA will finish next */
1191         int block_dma;
1192
1193         /* (buffer-fill only) block that the reader will release next */
1194         int block_reader;
1195
1196         /* (buffer-fill only) bytes of buffer the reader has released,
1197            less than one block */
1198         int released_bytes;
1199
1200         /* (buffer-fill only) buffer offset at which the next packet will appear */
1201         int dma_offset;
1202
1203         /* OHCI DMA context control registers */
1204         u32 ContextControlSet;
1205         u32 ContextControlClear;
1206         u32 CommandPtr;
1207         u32 ContextMatch;
1208 };
1209
1210 static void ohci_iso_recv_task(unsigned long data);
1211 static void ohci_iso_recv_stop(struct hpsb_iso *iso);
1212 static void ohci_iso_recv_shutdown(struct hpsb_iso *iso);
1213 static int  ohci_iso_recv_start(struct hpsb_iso *iso, int cycle, int tag_mask, int sync);
1214 static void ohci_iso_recv_program(struct hpsb_iso *iso);
1215
1216 static int ohci_iso_recv_init(struct hpsb_iso *iso)
1217 {
1218         struct ti_ohci *ohci = iso->host->hostdata;
1219         struct ohci_iso_recv *recv;
1220         int ctx;
1221         int ret = -ENOMEM;
1222
1223         recv = kmalloc(sizeof(*recv), SLAB_KERNEL);
1224         if (!recv)
1225                 return -ENOMEM;
1226
1227         iso->hostdata = recv;
1228         recv->ohci = ohci;
1229         recv->task_active = 0;
1230         dma_prog_region_init(&recv->prog);
1231         recv->block = NULL;
1232
1233         /* use buffer-fill mode, unless irq_interval is 1
1234            (note: multichannel requires buffer-fill) */
1235
1236         if (((iso->irq_interval == 1 && iso->dma_mode == HPSB_ISO_DMA_OLD_ABI) ||
1237              iso->dma_mode == HPSB_ISO_DMA_PACKET_PER_BUFFER) && iso->channel != -1) {
1238                 recv->dma_mode = PACKET_PER_BUFFER_MODE;
1239         } else {
1240                 recv->dma_mode = BUFFER_FILL_MODE;
1241         }
1242
1243         /* set nblocks, buf_stride, block_irq_interval */
1244
1245         if (recv->dma_mode == BUFFER_FILL_MODE) {
1246                 recv->buf_stride = PAGE_SIZE;
1247
1248                 /* one block per page of data in the DMA buffer, minus the final guard page */
1249                 recv->nblocks = iso->buf_size/PAGE_SIZE - 1;
1250                 if (recv->nblocks < 3) {
1251                         DBGMSG("ohci_iso_recv_init: DMA buffer too small");
1252                         goto err;
1253                 }
1254
1255                 /* iso->irq_interval is in packets - translate that to blocks */
1256                 if (iso->irq_interval == 1)
1257                         recv->block_irq_interval = 1;
1258                 else
1259                         recv->block_irq_interval = iso->irq_interval *
1260                                                         ((recv->nblocks+1)/iso->buf_packets);
1261                 if (recv->block_irq_interval*4 > recv->nblocks)
1262                         recv->block_irq_interval = recv->nblocks/4;
1263                 if (recv->block_irq_interval < 1)
1264                         recv->block_irq_interval = 1;
1265
1266         } else {
1267                 int max_packet_size;
1268
1269                 recv->nblocks = iso->buf_packets;
1270                 recv->block_irq_interval = iso->irq_interval;
1271                 if (recv->block_irq_interval * 4 > iso->buf_packets)
1272                         recv->block_irq_interval = iso->buf_packets / 4;
1273                 if (recv->block_irq_interval < 1)
1274                 recv->block_irq_interval = 1;
1275
1276                 /* choose a buffer stride */
1277                 /* must be a power of 2, and <= PAGE_SIZE */
1278
1279                 max_packet_size = iso->buf_size / iso->buf_packets;
1280
1281                 for (recv->buf_stride = 8; recv->buf_stride < max_packet_size;
1282                     recv->buf_stride *= 2);
1283
1284                 if (recv->buf_stride*iso->buf_packets > iso->buf_size ||
1285                    recv->buf_stride > PAGE_SIZE) {
1286                         /* this shouldn't happen, but anyway... */
1287                         DBGMSG("ohci_iso_recv_init: problem choosing a buffer stride");
1288                         goto err;
1289                 }
1290         }
1291
1292         recv->block_reader = 0;
1293         recv->released_bytes = 0;
1294         recv->block_dma = 0;
1295         recv->dma_offset = 0;
1296
1297         /* size of DMA program = one descriptor per block */
1298         if (dma_prog_region_alloc(&recv->prog,
1299                                  sizeof(struct dma_cmd) * recv->nblocks,
1300                                  recv->ohci->dev))
1301                 goto err;
1302
1303         recv->block = (struct dma_cmd*) recv->prog.kvirt;
1304
1305         ohci1394_init_iso_tasklet(&recv->task,
1306                                   iso->channel == -1 ? OHCI_ISO_MULTICHANNEL_RECEIVE :
1307                                                        OHCI_ISO_RECEIVE,
1308                                   ohci_iso_recv_task, (unsigned long) iso);
1309
1310         if (ohci1394_register_iso_tasklet(recv->ohci, &recv->task) < 0) {
1311                 ret = -EBUSY;
1312                 goto err;
1313         }
1314
1315         recv->task_active = 1;
1316
1317         /* recv context registers are spaced 32 bytes apart */
1318         ctx = recv->task.context;
1319         recv->ContextControlSet = OHCI1394_IsoRcvContextControlSet + 32 * ctx;
1320         recv->ContextControlClear = OHCI1394_IsoRcvContextControlClear + 32 * ctx;
1321         recv->CommandPtr = OHCI1394_IsoRcvCommandPtr + 32 * ctx;
1322         recv->ContextMatch = OHCI1394_IsoRcvContextMatch + 32 * ctx;
1323
1324         if (iso->channel == -1) {
1325                 /* clear multi-channel selection mask */
1326                 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, 0xFFFFFFFF);
1327                 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, 0xFFFFFFFF);
1328         }
1329
1330         /* write the DMA program */
1331         ohci_iso_recv_program(iso);
1332
1333         DBGMSG("ohci_iso_recv_init: %s mode, DMA buffer is %lu pages"
1334                " (%u bytes), using %u blocks, buf_stride %u, block_irq_interval %d",
1335                recv->dma_mode == BUFFER_FILL_MODE ?
1336                "buffer-fill" : "packet-per-buffer",
1337                iso->buf_size/PAGE_SIZE, iso->buf_size,
1338                recv->nblocks, recv->buf_stride, recv->block_irq_interval);
1339
1340         return 0;
1341
1342 err:
1343         ohci_iso_recv_shutdown(iso);
1344         return ret;
1345 }
1346
1347 static void ohci_iso_recv_stop(struct hpsb_iso *iso)
1348 {
1349         struct ohci_iso_recv *recv = iso->hostdata;
1350
1351         /* disable interrupts */
1352         reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskClear, 1 << recv->task.context);
1353
1354         /* halt DMA */
1355         ohci1394_stop_context(recv->ohci, recv->ContextControlClear, NULL);
1356 }
1357
1358 static void ohci_iso_recv_shutdown(struct hpsb_iso *iso)
1359 {
1360         struct ohci_iso_recv *recv = iso->hostdata;
1361
1362         if (recv->task_active) {
1363                 ohci_iso_recv_stop(iso);
1364                 ohci1394_unregister_iso_tasklet(recv->ohci, &recv->task);
1365                 recv->task_active = 0;
1366         }
1367
1368         dma_prog_region_free(&recv->prog);
1369         kfree(recv);
1370         iso->hostdata = NULL;
1371 }
1372
1373 /* set up a "gapped" ring buffer DMA program */
1374 static void ohci_iso_recv_program(struct hpsb_iso *iso)
1375 {
1376         struct ohci_iso_recv *recv = iso->hostdata;
1377         int blk;
1378
1379         /* address of 'branch' field in previous DMA descriptor */
1380         u32 *prev_branch = NULL;
1381
1382         for (blk = 0; blk < recv->nblocks; blk++) {
1383                 u32 control;
1384
1385                 /* the DMA descriptor */
1386                 struct dma_cmd *cmd = &recv->block[blk];
1387
1388                 /* offset of the DMA descriptor relative to the DMA prog buffer */
1389                 unsigned long prog_offset = blk * sizeof(struct dma_cmd);
1390
1391                 /* offset of this packet's data within the DMA buffer */
1392                 unsigned long buf_offset = blk * recv->buf_stride;
1393
1394                 if (recv->dma_mode == BUFFER_FILL_MODE) {
1395                         control = 2 << 28; /* INPUT_MORE */
1396                 } else {
1397                         control = 3 << 28; /* INPUT_LAST */
1398                 }
1399
1400                 control |= 8 << 24; /* s = 1, update xferStatus and resCount */
1401
1402                 /* interrupt on last block, and at intervals */
1403                 if (blk == recv->nblocks-1 || (blk % recv->block_irq_interval) == 0) {
1404                         control |= 3 << 20; /* want interrupt */
1405                 }
1406
1407                 control |= 3 << 18; /* enable branch to address */
1408                 control |= recv->buf_stride;
1409
1410                 cmd->control = cpu_to_le32(control);
1411                 cmd->address = cpu_to_le32(dma_region_offset_to_bus(&iso->data_buf, buf_offset));
1412                 cmd->branchAddress = 0; /* filled in on next loop */
1413                 cmd->status = cpu_to_le32(recv->buf_stride);
1414
1415                 /* link the previous descriptor to this one */
1416                 if (prev_branch) {
1417                         *prev_branch = cpu_to_le32(dma_prog_region_offset_to_bus(&recv->prog, prog_offset) | 1);
1418                 }
1419
1420                 prev_branch = &cmd->branchAddress;
1421         }
1422
1423         /* the final descriptor's branch address and Z should be left at 0 */
1424 }
1425
1426 /* listen or unlisten to a specific channel (multi-channel mode only) */
1427 static void ohci_iso_recv_change_channel(struct hpsb_iso *iso, unsigned char channel, int listen)
1428 {
1429         struct ohci_iso_recv *recv = iso->hostdata;
1430         int reg, i;
1431
1432         if (channel < 32) {
1433                 reg = listen ? OHCI1394_IRMultiChanMaskLoSet : OHCI1394_IRMultiChanMaskLoClear;
1434                 i = channel;
1435         } else {
1436                 reg = listen ? OHCI1394_IRMultiChanMaskHiSet : OHCI1394_IRMultiChanMaskHiClear;
1437                 i = channel - 32;
1438         }
1439
1440         reg_write(recv->ohci, reg, (1 << i));
1441
1442         /* issue a dummy read to force all PCI writes to be posted immediately */
1443         mb();
1444         reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1445 }
1446
1447 static void ohci_iso_recv_set_channel_mask(struct hpsb_iso *iso, u64 mask)
1448 {
1449         struct ohci_iso_recv *recv = iso->hostdata;
1450         int i;
1451
1452         for (i = 0; i < 64; i++) {
1453                 if (mask & (1ULL << i)) {
1454                         if (i < 32)
1455                                 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoSet, (1 << i));
1456                         else
1457                                 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiSet, (1 << (i-32)));
1458                 } else {
1459                         if (i < 32)
1460                                 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, (1 << i));
1461                         else
1462                                 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, (1 << (i-32)));
1463                 }
1464         }
1465
1466         /* issue a dummy read to force all PCI writes to be posted immediately */
1467         mb();
1468         reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1469 }
1470
1471 static int ohci_iso_recv_start(struct hpsb_iso *iso, int cycle, int tag_mask, int sync)
1472 {
1473         struct ohci_iso_recv *recv = iso->hostdata;
1474         struct ti_ohci *ohci = recv->ohci;
1475         u32 command, contextMatch;
1476
1477         reg_write(recv->ohci, recv->ContextControlClear, 0xFFFFFFFF);
1478         wmb();
1479
1480         /* always keep ISO headers */
1481         command = (1 << 30);
1482
1483         if (recv->dma_mode == BUFFER_FILL_MODE)
1484                 command |= (1 << 31);
1485
1486         reg_write(recv->ohci, recv->ContextControlSet, command);
1487
1488         /* match on specified tags */
1489         contextMatch = tag_mask << 28;
1490
1491         if (iso->channel == -1) {
1492                 /* enable multichannel reception */
1493                 reg_write(recv->ohci, recv->ContextControlSet, (1 << 28));
1494         } else {
1495                 /* listen on channel */
1496                 contextMatch |= iso->channel;
1497         }
1498
1499         if (cycle != -1) {
1500                 u32 seconds;
1501
1502                 /* enable cycleMatch */
1503                 reg_write(recv->ohci, recv->ContextControlSet, (1 << 29));
1504
1505                 /* set starting cycle */
1506                 cycle &= 0x1FFF;
1507
1508                 /* 'cycle' is only mod 8000, but we also need two 'seconds' bits -
1509                    just snarf them from the current time */
1510                 seconds = reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer) >> 25;
1511
1512                 /* advance one second to give some extra time for DMA to start */
1513                 seconds += 1;
1514
1515                 cycle |= (seconds & 3) << 13;
1516
1517                 contextMatch |= cycle << 12;
1518         }
1519
1520         if (sync != -1) {
1521                 /* set sync flag on first DMA descriptor */
1522                 struct dma_cmd *cmd = &recv->block[recv->block_dma];
1523                 cmd->control |= cpu_to_le32(DMA_CTL_WAIT);
1524
1525                 /* match sync field */
1526                 contextMatch |= (sync&0xf)<<8;
1527         }
1528
1529         reg_write(recv->ohci, recv->ContextMatch, contextMatch);
1530
1531         /* address of first descriptor block */
1532         command = dma_prog_region_offset_to_bus(&recv->prog,
1533                                                 recv->block_dma * sizeof(struct dma_cmd));
1534         command |= 1; /* Z=1 */
1535
1536         reg_write(recv->ohci, recv->CommandPtr, command);
1537
1538         /* enable interrupts */
1539         reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskSet, 1 << recv->task.context);
1540
1541         wmb();
1542
1543         /* run */
1544         reg_write(recv->ohci, recv->ContextControlSet, 0x8000);
1545
1546         /* issue a dummy read of the cycle timer register to force
1547            all PCI writes to be posted immediately */
1548         mb();
1549         reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1550
1551         /* check RUN */
1552         if (!(reg_read(recv->ohci, recv->ContextControlSet) & 0x8000)) {
1553                 PRINT(KERN_ERR,
1554                       "Error starting IR DMA (ContextControl 0x%08x)\n",
1555                       reg_read(recv->ohci, recv->ContextControlSet));
1556                 return -1;
1557         }
1558
1559         return 0;
1560 }
1561
1562 static void ohci_iso_recv_release_block(struct ohci_iso_recv *recv, int block)
1563 {
1564         /* re-use the DMA descriptor for the block */
1565         /* by linking the previous descriptor to it */
1566
1567         int next_i = block;
1568         int prev_i = (next_i == 0) ? (recv->nblocks - 1) : (next_i - 1);
1569
1570         struct dma_cmd *next = &recv->block[next_i];
1571         struct dma_cmd *prev = &recv->block[prev_i];
1572         
1573         /* ignore out-of-range requests */
1574         if ((block < 0) || (block > recv->nblocks))
1575                 return;
1576
1577         /* 'next' becomes the new end of the DMA chain,
1578            so disable branch and enable interrupt */
1579         next->branchAddress = 0;
1580         next->control |= cpu_to_le32(3 << 20);
1581         next->status = cpu_to_le32(recv->buf_stride);
1582
1583         /* link prev to next */
1584         prev->branchAddress = cpu_to_le32(dma_prog_region_offset_to_bus(&recv->prog,
1585                                                                         sizeof(struct dma_cmd) * next_i)
1586                                           | 1); /* Z=1 */
1587
1588         /* disable interrupt on previous DMA descriptor, except at intervals */
1589         if ((prev_i % recv->block_irq_interval) == 0) {
1590                 prev->control |= cpu_to_le32(3 << 20); /* enable interrupt */
1591         } else {
1592                 prev->control &= cpu_to_le32(~(3<<20)); /* disable interrupt */
1593         }
1594         wmb();
1595
1596         /* wake up DMA in case it fell asleep */
1597         reg_write(recv->ohci, recv->ContextControlSet, (1 << 12));
1598 }
1599
1600 static void ohci_iso_recv_bufferfill_release(struct ohci_iso_recv *recv,
1601                                              struct hpsb_iso_packet_info *info)
1602 {
1603         /* release the memory where the packet was */
1604         recv->released_bytes += info->total_len;
1605
1606         /* have we released enough memory for one block? */
1607         while (recv->released_bytes > recv->buf_stride) {
1608                 ohci_iso_recv_release_block(recv, recv->block_reader);
1609                 recv->block_reader = (recv->block_reader + 1) % recv->nblocks;
1610                 recv->released_bytes -= recv->buf_stride;
1611         }
1612 }
1613
1614 static inline void ohci_iso_recv_release(struct hpsb_iso *iso, struct hpsb_iso_packet_info *info)
1615 {
1616         struct ohci_iso_recv *recv = iso->hostdata;
1617         if (recv->dma_mode == BUFFER_FILL_MODE) {
1618                 ohci_iso_recv_bufferfill_release(recv, info);
1619         } else {
1620                 ohci_iso_recv_release_block(recv, info - iso->infos);
1621         }
1622 }
1623
1624 /* parse all packets from blocks that have been fully received */
1625 static void ohci_iso_recv_bufferfill_parse(struct hpsb_iso *iso, struct ohci_iso_recv *recv)
1626 {
1627         int wake = 0;
1628         int runaway = 0;
1629         struct ti_ohci *ohci = recv->ohci;
1630
1631         while (1) {
1632                 /* we expect the next parsable packet to begin at recv->dma_offset */
1633                 /* note: packet layout is as shown in section 10.6.1.1 of the OHCI spec */
1634
1635                 unsigned int offset;
1636                 unsigned short len, cycle, total_len;
1637                 unsigned char channel, tag, sy;
1638
1639                 unsigned char *p = iso->data_buf.kvirt;
1640
1641                 unsigned int this_block = recv->dma_offset/recv->buf_stride;
1642
1643                 /* don't loop indefinitely */
1644                 if (runaway++ > 100000) {
1645                         atomic_inc(&iso->overflows);
1646                         PRINT(KERN_ERR,
1647                               "IR DMA error - Runaway during buffer parsing!\n");
1648                         break;
1649                 }
1650
1651                 /* stop parsing once we arrive at block_dma (i.e. don't get ahead of DMA) */
1652                 if (this_block == recv->block_dma)
1653                         break;
1654
1655                 wake = 1;
1656
1657                 /* parse data length, tag, channel, and sy */
1658
1659                 /* note: we keep our own local copies of 'len' and 'offset'
1660                    so the user can't mess with them by poking in the mmap area */
1661
1662                 len = p[recv->dma_offset+2] | (p[recv->dma_offset+3] << 8);
1663
1664                 if (len > 4096) {
1665                         PRINT(KERN_ERR,
1666                               "IR DMA error - bogus 'len' value %u\n", len);
1667                 }
1668
1669                 channel = p[recv->dma_offset+1] & 0x3F;
1670                 tag = p[recv->dma_offset+1] >> 6;
1671                 sy = p[recv->dma_offset+0] & 0xF;
1672
1673                 /* advance to data payload */
1674                 recv->dma_offset += 4;
1675
1676                 /* check for wrap-around */
1677                 if (recv->dma_offset >= recv->buf_stride*recv->nblocks) {
1678                         recv->dma_offset -= recv->buf_stride*recv->nblocks;
1679                 }
1680
1681                 /* dma_offset now points to the first byte of the data payload */
1682                 offset = recv->dma_offset;
1683
1684                 /* advance to xferStatus/timeStamp */
1685                 recv->dma_offset += len;
1686
1687                 total_len = len + 8; /* 8 bytes header+trailer in OHCI packet */
1688                 /* payload is padded to 4 bytes */
1689                 if (len % 4) {
1690                         recv->dma_offset += 4 - (len%4);
1691                         total_len += 4 - (len%4);
1692                 }
1693
1694                 /* check for wrap-around */
1695                 if (recv->dma_offset >= recv->buf_stride*recv->nblocks) {
1696                         /* uh oh, the packet data wraps from the last
1697                            to the first DMA block - make the packet
1698                            contiguous by copying its "tail" into the
1699                            guard page */
1700
1701                         int guard_off = recv->buf_stride*recv->nblocks;
1702                         int tail_len = len - (guard_off - offset);
1703
1704                         if (tail_len > 0  && tail_len < recv->buf_stride) {
1705                                 memcpy(iso->data_buf.kvirt + guard_off,
1706                                        iso->data_buf.kvirt,
1707                                        tail_len);
1708                         }
1709
1710                         recv->dma_offset -= recv->buf_stride*recv->nblocks;
1711                 }
1712
1713                 /* parse timestamp */
1714                 cycle = p[recv->dma_offset+0] | (p[recv->dma_offset+1]<<8);
1715                 cycle &= 0x1FFF;
1716
1717                 /* advance to next packet */
1718                 recv->dma_offset += 4;
1719
1720                 /* check for wrap-around */
1721                 if (recv->dma_offset >= recv->buf_stride*recv->nblocks) {
1722                         recv->dma_offset -= recv->buf_stride*recv->nblocks;
1723                 }
1724
1725                 hpsb_iso_packet_received(iso, offset, len, total_len, cycle, channel, tag, sy);
1726         }
1727
1728         if (wake)
1729                 hpsb_iso_wake(iso);
1730 }
1731
1732 static void ohci_iso_recv_bufferfill_task(struct hpsb_iso *iso, struct ohci_iso_recv *recv)
1733 {
1734         int loop;
1735         struct ti_ohci *ohci = recv->ohci;
1736
1737         /* loop over all blocks */
1738         for (loop = 0; loop < recv->nblocks; loop++) {
1739
1740                 /* check block_dma to see if it's done */
1741                 struct dma_cmd *im = &recv->block[recv->block_dma];
1742
1743                 /* check the DMA descriptor for new writes to xferStatus */
1744                 u16 xferstatus = le32_to_cpu(im->status) >> 16;
1745
1746                 /* rescount is the number of bytes *remaining to be written* in the block */
1747                 u16 rescount = le32_to_cpu(im->status) & 0xFFFF;
1748
1749                 unsigned char event = xferstatus & 0x1F;
1750
1751                 if (!event) {
1752                         /* nothing has happened to this block yet */
1753                         break;
1754                 }
1755
1756                 if (event != 0x11) {
1757                         atomic_inc(&iso->overflows);
1758                         PRINT(KERN_ERR,
1759                               "IR DMA error - OHCI error code 0x%02x\n", event);
1760                 }
1761
1762                 if (rescount != 0) {
1763                         /* the card is still writing to this block;
1764                            we can't touch it until it's done */
1765                         break;
1766                 }
1767
1768                 /* OK, the block is finished... */
1769
1770                 /* sync our view of the block */
1771                 dma_region_sync_for_cpu(&iso->data_buf, recv->block_dma*recv->buf_stride, recv->buf_stride);
1772
1773                 /* reset the DMA descriptor */
1774                 im->status = recv->buf_stride;
1775
1776                 /* advance block_dma */
1777                 recv->block_dma = (recv->block_dma + 1) % recv->nblocks;
1778
1779                 if ((recv->block_dma+1) % recv->nblocks == recv->block_reader) {
1780                         atomic_inc(&iso->overflows);
1781                         DBGMSG("ISO reception overflow - "
1782                                "ran out of DMA blocks");
1783                 }
1784         }
1785
1786         /* parse any packets that have arrived */
1787         ohci_iso_recv_bufferfill_parse(iso, recv);
1788 }
1789
1790 static void ohci_iso_recv_packetperbuf_task(struct hpsb_iso *iso, struct ohci_iso_recv *recv)
1791 {
1792         int count;
1793         int wake = 0;
1794         struct ti_ohci *ohci = recv->ohci;
1795
1796         /* loop over the entire buffer */
1797         for (count = 0; count < recv->nblocks; count++) {
1798                 u32 packet_len = 0;
1799
1800                 /* pointer to the DMA descriptor */
1801                 struct dma_cmd *il = ((struct dma_cmd*) recv->prog.kvirt) + iso->pkt_dma;
1802
1803                 /* check the DMA descriptor for new writes to xferStatus */
1804                 u16 xferstatus = le32_to_cpu(il->status) >> 16;
1805                 u16 rescount = le32_to_cpu(il->status) & 0xFFFF;
1806
1807                 unsigned char event = xferstatus & 0x1F;
1808
1809                 if (!event) {
1810                         /* this packet hasn't come in yet; we are done for now */
1811                         goto out;
1812                 }
1813
1814                 if (event == 0x11) {
1815                         /* packet received successfully! */
1816
1817                         /* rescount is the number of bytes *remaining* in the packet buffer,
1818                            after the packet was written */
1819                         packet_len = recv->buf_stride - rescount;
1820
1821                 } else if (event == 0x02) {
1822                         PRINT(KERN_ERR, "IR DMA error - packet too long for buffer\n");
1823                 } else if (event) {
1824                         PRINT(KERN_ERR, "IR DMA error - OHCI error code 0x%02x\n", event);
1825                 }
1826
1827                 /* sync our view of the buffer */
1828                 dma_region_sync_for_cpu(&iso->data_buf, iso->pkt_dma * recv->buf_stride, recv->buf_stride);
1829
1830                 /* record the per-packet info */
1831                 {
1832                         /* iso header is 8 bytes ahead of the data payload */
1833                         unsigned char *hdr;
1834
1835                         unsigned int offset;
1836                         unsigned short cycle;
1837                         unsigned char channel, tag, sy;
1838
1839                         offset = iso->pkt_dma * recv->buf_stride;
1840                         hdr = iso->data_buf.kvirt + offset;
1841
1842                         /* skip iso header */
1843                         offset += 8;
1844                         packet_len -= 8;
1845
1846                         cycle = (hdr[0] | (hdr[1] << 8)) & 0x1FFF;
1847                         channel = hdr[5] & 0x3F;
1848                         tag = hdr[5] >> 6;
1849                         sy = hdr[4] & 0xF;
1850
1851                         hpsb_iso_packet_received(iso, offset, packet_len,
1852                                         recv->buf_stride, cycle, channel, tag, sy);
1853                 }
1854
1855                 /* reset the DMA descriptor */
1856                 il->status = recv->buf_stride;
1857
1858                 wake = 1;
1859                 recv->block_dma = iso->pkt_dma;
1860         }
1861
1862 out:
1863         if (wake)
1864                 hpsb_iso_wake(iso);
1865 }
1866
1867 static void ohci_iso_recv_task(unsigned long data)
1868 {
1869         struct hpsb_iso *iso = (struct hpsb_iso*) data;
1870         struct ohci_iso_recv *recv = iso->hostdata;
1871
1872         if (recv->dma_mode == BUFFER_FILL_MODE)
1873                 ohci_iso_recv_bufferfill_task(iso, recv);
1874         else
1875                 ohci_iso_recv_packetperbuf_task(iso, recv);
1876 }
1877
1878 /***********************************
1879  * rawiso ISO transmission         *
1880  ***********************************/
1881
1882 struct ohci_iso_xmit {
1883         struct ti_ohci *ohci;
1884         struct dma_prog_region prog;
1885         struct ohci1394_iso_tasklet task;
1886         int task_active;
1887
1888         u32 ContextControlSet;
1889         u32 ContextControlClear;
1890         u32 CommandPtr;
1891 };
1892
1893 /* transmission DMA program:
1894    one OUTPUT_MORE_IMMEDIATE for the IT header
1895    one OUTPUT_LAST for the buffer data */
1896
1897 struct iso_xmit_cmd {
1898         struct dma_cmd output_more_immediate;
1899         u8 iso_hdr[8];
1900         u32 unused[2];
1901         struct dma_cmd output_last;
1902 };
1903
1904 static int ohci_iso_xmit_init(struct hpsb_iso *iso);
1905 static int ohci_iso_xmit_start(struct hpsb_iso *iso, int cycle);
1906 static void ohci_iso_xmit_shutdown(struct hpsb_iso *iso);
1907 static void ohci_iso_xmit_task(unsigned long data);
1908
1909 static int ohci_iso_xmit_init(struct hpsb_iso *iso)
1910 {
1911         struct ohci_iso_xmit *xmit;
1912         unsigned int prog_size;
1913         int ctx;
1914         int ret = -ENOMEM;
1915
1916         xmit = kmalloc(sizeof(*xmit), SLAB_KERNEL);
1917         if (!xmit)
1918                 return -ENOMEM;
1919
1920         iso->hostdata = xmit;
1921         xmit->ohci = iso->host->hostdata;
1922         xmit->task_active = 0;
1923
1924         dma_prog_region_init(&xmit->prog);
1925
1926         prog_size = sizeof(struct iso_xmit_cmd) * iso->buf_packets;
1927
1928         if (dma_prog_region_alloc(&xmit->prog, prog_size, xmit->ohci->dev))
1929                 goto err;
1930
1931         ohci1394_init_iso_tasklet(&xmit->task, OHCI_ISO_TRANSMIT,
1932                                   ohci_iso_xmit_task, (unsigned long) iso);
1933
1934         if (ohci1394_register_iso_tasklet(xmit->ohci, &xmit->task) < 0) {
1935                 ret = -EBUSY;
1936                 goto err;
1937         }
1938
1939         xmit->task_active = 1;
1940
1941         /* xmit context registers are spaced 16 bytes apart */
1942         ctx = xmit->task.context;
1943         xmit->ContextControlSet = OHCI1394_IsoXmitContextControlSet + 16 * ctx;
1944         xmit->ContextControlClear = OHCI1394_IsoXmitContextControlClear + 16 * ctx;
1945         xmit->CommandPtr = OHCI1394_IsoXmitCommandPtr + 16 * ctx;
1946
1947         return 0;
1948
1949 err:
1950         ohci_iso_xmit_shutdown(iso);
1951         return ret;
1952 }
1953
1954 static void ohci_iso_xmit_stop(struct hpsb_iso *iso)
1955 {
1956         struct ohci_iso_xmit *xmit = iso->hostdata;
1957         struct ti_ohci *ohci = xmit->ohci;
1958
1959         /* disable interrupts */
1960         reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskClear, 1 << xmit->task.context);
1961
1962         /* halt DMA */
1963         if (ohci1394_stop_context(xmit->ohci, xmit->ContextControlClear, NULL)) {
1964                 /* XXX the DMA context will lock up if you try to send too much data! */
1965                 PRINT(KERN_ERR,
1966                       "you probably exceeded the OHCI card's bandwidth limit - "
1967                       "reload the module and reduce xmit bandwidth");
1968         }
1969 }
1970
1971 static void ohci_iso_xmit_shutdown(struct hpsb_iso *iso)
1972 {
1973         struct ohci_iso_xmit *xmit = iso->hostdata;
1974
1975         if (xmit->task_active) {
1976                 ohci_iso_xmit_stop(iso);
1977                 ohci1394_unregister_iso_tasklet(xmit->ohci, &xmit->task);
1978                 xmit->task_active = 0;
1979         }
1980
1981         dma_prog_region_free(&xmit->prog);
1982         kfree(xmit);
1983         iso->hostdata = NULL;
1984 }
1985
1986 static void ohci_iso_xmit_task(unsigned long data)
1987 {
1988         struct hpsb_iso *iso = (struct hpsb_iso*) data;
1989         struct ohci_iso_xmit *xmit = iso->hostdata;
1990         struct ti_ohci *ohci = xmit->ohci;
1991         int wake = 0;
1992         int count;
1993
1994         /* check the whole buffer if necessary, starting at pkt_dma */
1995         for (count = 0; count < iso->buf_packets; count++) {
1996                 int cycle;
1997
1998                 /* DMA descriptor */
1999                 struct iso_xmit_cmd *cmd = dma_region_i(&xmit->prog, struct iso_xmit_cmd, iso->pkt_dma);
2000
2001                 /* check for new writes to xferStatus */
2002                 u16 xferstatus = le32_to_cpu(cmd->output_last.status) >> 16;
2003                 u8  event = xferstatus & 0x1F;
2004
2005                 if (!event) {
2006                         /* packet hasn't been sent yet; we are done for now */
2007                         break;
2008                 }
2009
2010                 if (event != 0x11)
2011                         PRINT(KERN_ERR,
2012                               "IT DMA error - OHCI error code 0x%02x\n", event);
2013
2014                 /* at least one packet went out, so wake up the writer */
2015                 wake = 1;
2016
2017                 /* parse cycle */
2018                 cycle = le32_to_cpu(cmd->output_last.status) & 0x1FFF;
2019
2020                 /* tell the subsystem the packet has gone out */
2021                 hpsb_iso_packet_sent(iso, cycle, event != 0x11);
2022
2023                 /* reset the DMA descriptor for next time */
2024                 cmd->output_last.status = 0;
2025         }
2026
2027         if (wake)
2028                 hpsb_iso_wake(iso);
2029 }
2030
2031 static int ohci_iso_xmit_queue(struct hpsb_iso *iso, struct hpsb_iso_packet_info *info)
2032 {
2033         struct ohci_iso_xmit *xmit = iso->hostdata;
2034         struct ti_ohci *ohci = xmit->ohci;
2035
2036         int next_i, prev_i;
2037         struct iso_xmit_cmd *next, *prev;
2038
2039         unsigned int offset;
2040         unsigned short len;
2041         unsigned char tag, sy;
2042
2043         /* check that the packet doesn't cross a page boundary
2044            (we could allow this if we added OUTPUT_MORE descriptor support) */
2045         if (cross_bound(info->offset, info->len)) {
2046                 PRINT(KERN_ERR,
2047                       "rawiso xmit: packet %u crosses a page boundary",
2048                       iso->first_packet);
2049                 return -EINVAL;
2050         }
2051
2052         offset = info->offset;
2053         len = info->len;
2054         tag = info->tag;
2055         sy = info->sy;
2056
2057         /* sync up the card's view of the buffer */
2058         dma_region_sync_for_device(&iso->data_buf, offset, len);
2059
2060         /* append first_packet to the DMA chain */
2061         /* by linking the previous descriptor to it */
2062         /* (next will become the new end of the DMA chain) */
2063
2064         next_i = iso->first_packet;
2065         prev_i = (next_i == 0) ? (iso->buf_packets - 1) : (next_i - 1);
2066
2067         next = dma_region_i(&xmit->prog, struct iso_xmit_cmd, next_i);
2068         prev = dma_region_i(&xmit->prog, struct iso_xmit_cmd, prev_i);
2069
2070         /* set up the OUTPUT_MORE_IMMEDIATE descriptor */
2071         memset(next, 0, sizeof(struct iso_xmit_cmd));
2072         next->output_more_immediate.control = cpu_to_le32(0x02000008);
2073
2074         /* ISO packet header is embedded in the OUTPUT_MORE_IMMEDIATE */
2075
2076         /* tcode = 0xA, and sy */
2077         next->iso_hdr[0] = 0xA0 | (sy & 0xF);
2078
2079         /* tag and channel number */
2080         next->iso_hdr[1] = (tag << 6) | (iso->channel & 0x3F);
2081
2082         /* transmission speed */
2083         next->iso_hdr[2] = iso->speed & 0x7;
2084
2085         /* payload size */
2086         next->iso_hdr[6] = len & 0xFF;
2087         next->iso_hdr[7] = len >> 8;
2088
2089         /* set up the OUTPUT_LAST */
2090         next->output_last.control = cpu_to_le32(1 << 28);
2091         next->output_last.control |= cpu_to_le32(1 << 27); /* update timeStamp */
2092         next->output_last.control |= cpu_to_le32(3 << 20); /* want interrupt */
2093         next->output_last.control |= cpu_to_le32(3 << 18); /* enable branch */
2094         next->output_last.control |= cpu_to_le32(len);
2095
2096         /* payload bus address */
2097         next->output_last.address = cpu_to_le32(dma_region_offset_to_bus(&iso->data_buf, offset));
2098
2099         /* leave branchAddress at zero for now */
2100
2101         /* re-write the previous DMA descriptor to chain to this one */
2102
2103         /* set prev branch address to point to next (Z=3) */
2104         prev->output_last.branchAddress = cpu_to_le32(
2105                 dma_prog_region_offset_to_bus(&xmit->prog, sizeof(struct iso_xmit_cmd) * next_i) | 3);
2106
2107         /* disable interrupt, unless required by the IRQ interval */
2108         if (prev_i % iso->irq_interval) {
2109                 prev->output_last.control &= cpu_to_le32(~(3 << 20)); /* no interrupt */
2110         } else {
2111                 prev->output_last.control |= cpu_to_le32(3 << 20); /* enable interrupt */
2112         }
2113
2114         wmb();
2115
2116         /* wake DMA in case it is sleeping */
2117         reg_write(xmit->ohci, xmit->ContextControlSet, 1 << 12);
2118
2119         /* issue a dummy read of the cycle timer to force all PCI
2120            writes to be posted immediately */
2121         mb();
2122         reg_read(xmit->ohci, OHCI1394_IsochronousCycleTimer);
2123
2124         return 0;
2125 }
2126
2127 static int ohci_iso_xmit_start(struct hpsb_iso *iso, int cycle)
2128 {
2129         struct ohci_iso_xmit *xmit = iso->hostdata;
2130         struct ti_ohci *ohci = xmit->ohci;
2131
2132         /* clear out the control register */
2133         reg_write(xmit->ohci, xmit->ContextControlClear, 0xFFFFFFFF);
2134         wmb();
2135
2136         /* address and length of first descriptor block (Z=3) */
2137         reg_write(xmit->ohci, xmit->CommandPtr,
2138                   dma_prog_region_offset_to_bus(&xmit->prog, iso->pkt_dma * sizeof(struct iso_xmit_cmd)) | 3);
2139
2140         /* cycle match */
2141         if (cycle != -1) {
2142                 u32 start = cycle & 0x1FFF;
2143
2144                 /* 'cycle' is only mod 8000, but we also need two 'seconds' bits -
2145                    just snarf them from the current time */
2146                 u32 seconds = reg_read(xmit->ohci, OHCI1394_IsochronousCycleTimer) >> 25;
2147
2148                 /* advance one second to give some extra time for DMA to start */
2149                 seconds += 1;
2150
2151                 start |= (seconds & 3) << 13;
2152
2153                 reg_write(xmit->ohci, xmit->ContextControlSet, 0x80000000 | (start << 16));
2154         }
2155
2156         /* enable interrupts */
2157         reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskSet, 1 << xmit->task.context);
2158
2159         /* run */
2160         reg_write(xmit->ohci, xmit->ContextControlSet, 0x8000);
2161         mb();
2162
2163         /* wait 100 usec to give the card time to go active */
2164         udelay(100);
2165
2166         /* check the RUN bit */
2167         if (!(reg_read(xmit->ohci, xmit->ContextControlSet) & 0x8000)) {
2168                 PRINT(KERN_ERR, "Error starting IT DMA (ContextControl 0x%08x)\n",
2169                       reg_read(xmit->ohci, xmit->ContextControlSet));
2170                 return -1;
2171         }
2172
2173         return 0;
2174 }
2175
2176 static int ohci_isoctl(struct hpsb_iso *iso, enum isoctl_cmd cmd, unsigned long arg)
2177 {
2178
2179         switch(cmd) {
2180         case XMIT_INIT:
2181                 return ohci_iso_xmit_init(iso);
2182         case XMIT_START:
2183                 return ohci_iso_xmit_start(iso, arg);
2184         case XMIT_STOP:
2185                 ohci_iso_xmit_stop(iso);
2186                 return 0;
2187         case XMIT_QUEUE:
2188                 return ohci_iso_xmit_queue(iso, (struct hpsb_iso_packet_info*) arg);
2189         case XMIT_SHUTDOWN:
2190                 ohci_iso_xmit_shutdown(iso);
2191                 return 0;
2192
2193         case RECV_INIT:
2194                 return ohci_iso_recv_init(iso);
2195         case RECV_START: {
2196                 int *args = (int*) arg;
2197                 return ohci_iso_recv_start(iso, args[0], args[1], args[2]);
2198         }
2199         case RECV_STOP:
2200                 ohci_iso_recv_stop(iso);
2201                 return 0;
2202         case RECV_RELEASE:
2203                 ohci_iso_recv_release(iso, (struct hpsb_iso_packet_info*) arg);
2204                 return 0;
2205         case RECV_FLUSH:
2206                 ohci_iso_recv_task((unsigned long) iso);
2207                 return 0;
2208         case RECV_SHUTDOWN:
2209                 ohci_iso_recv_shutdown(iso);
2210                 return 0;
2211         case RECV_LISTEN_CHANNEL:
2212                 ohci_iso_recv_change_channel(iso, arg, 1);
2213                 return 0;
2214         case RECV_UNLISTEN_CHANNEL:
2215                 ohci_iso_recv_change_channel(iso, arg, 0);
2216                 return 0;
2217         case RECV_SET_CHANNEL_MASK:
2218                 ohci_iso_recv_set_channel_mask(iso, *((u64*) arg));
2219                 return 0;
2220
2221         default:
2222                 PRINT_G(KERN_ERR, "ohci_isoctl cmd %d not implemented yet",
2223                         cmd);
2224                 break;
2225         }
2226         return -EINVAL;
2227 }
2228
2229 /***************************************
2230  * IEEE-1394 functionality section END *
2231  ***************************************/
2232
2233
2234 /********************************************************
2235  * Global stuff (interrupt handler, init/shutdown code) *
2236  ********************************************************/
2237
2238 static void dma_trm_reset(struct dma_trm_ctx *d)
2239 {
2240         unsigned long flags;
2241         LIST_HEAD(packet_list);
2242         struct ti_ohci *ohci = d->ohci;
2243         struct hpsb_packet *packet, *ptmp;
2244
2245         ohci1394_stop_context(ohci, d->ctrlClear, NULL);
2246
2247         /* Lock the context, reset it and release it. Move the packets
2248          * that were pending in the context to packet_list and free
2249          * them after releasing the lock. */
2250
2251         spin_lock_irqsave(&d->lock, flags);
2252
2253         list_splice(&d->fifo_list, &packet_list);
2254         list_splice(&d->pending_list, &packet_list);
2255         INIT_LIST_HEAD(&d->fifo_list);
2256         INIT_LIST_HEAD(&d->pending_list);
2257
2258         d->branchAddrPtr = NULL;
2259         d->sent_ind = d->prg_ind;
2260         d->free_prgs = d->num_desc;
2261
2262         spin_unlock_irqrestore(&d->lock, flags);
2263
2264         if (list_empty(&packet_list))
2265                 return;
2266
2267         PRINT(KERN_INFO, "AT dma reset ctx=%d, aborting transmission", d->ctx);
2268
2269         /* Now process subsystem callbacks for the packets from this
2270          * context. */
2271         list_for_each_entry_safe(packet, ptmp, &packet_list, driver_list) {
2272                 list_del_init(&packet->driver_list);
2273                 hpsb_packet_sent(ohci->host, packet, ACKX_ABORTED);
2274         }
2275 }
2276
2277 static void ohci_schedule_iso_tasklets(struct ti_ohci *ohci,
2278                                        quadlet_t rx_event,
2279                                        quadlet_t tx_event)
2280 {
2281         struct ohci1394_iso_tasklet *t;
2282         unsigned long mask;
2283         unsigned long flags;
2284
2285         spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
2286
2287         list_for_each_entry(t, &ohci->iso_tasklet_list, link) {
2288                 mask = 1 << t->context;
2289
2290                 if (t->type == OHCI_ISO_TRANSMIT && tx_event & mask)
2291                         tasklet_schedule(&t->tasklet);
2292                 else if (rx_event & mask)
2293                         tasklet_schedule(&t->tasklet);
2294         }
2295
2296         spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);
2297 }
2298
2299 static irqreturn_t ohci_irq_handler(int irq, void *dev_id,
2300                              struct pt_regs *regs_are_unused)
2301 {
2302         quadlet_t event, node_id;
2303         struct ti_ohci *ohci = (struct ti_ohci *)dev_id;
2304         struct hpsb_host *host = ohci->host;
2305         int phyid = -1, isroot = 0;
2306         unsigned long flags;
2307
2308         /* Read and clear the interrupt event register.  Don't clear
2309          * the busReset event, though. This is done when we get the
2310          * selfIDComplete interrupt. */
2311         spin_lock_irqsave(&ohci->event_lock, flags);
2312         event = reg_read(ohci, OHCI1394_IntEventClear);
2313         reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
2314         spin_unlock_irqrestore(&ohci->event_lock, flags);
2315
2316         if (!event)
2317                 return IRQ_NONE;
2318
2319         /* If event is ~(u32)0 cardbus card was ejected.  In this case
2320          * we just return, and clean up in the ohci1394_pci_remove
2321          * function. */
2322         if (event == ~(u32) 0) {
2323                 DBGMSG("Device removed.");
2324                 return IRQ_NONE;
2325         }
2326
2327         DBGMSG("IntEvent: %08x", event);
2328
2329         if (event & OHCI1394_unrecoverableError) {
2330                 int ctx;
2331                 PRINT(KERN_ERR, "Unrecoverable error!");
2332
2333                 if (reg_read(ohci, OHCI1394_AsReqTrContextControlSet) & 0x800)
2334                         PRINT(KERN_ERR, "Async Req Tx Context died: "
2335                                 "ctrl[%08x] cmdptr[%08x]",
2336                                 reg_read(ohci, OHCI1394_AsReqTrContextControlSet),
2337                                 reg_read(ohci, OHCI1394_AsReqTrCommandPtr));
2338
2339                 if (reg_read(ohci, OHCI1394_AsRspTrContextControlSet) & 0x800)
2340                         PRINT(KERN_ERR, "Async Rsp Tx Context died: "
2341                                 "ctrl[%08x] cmdptr[%08x]",
2342                                 reg_read(ohci, OHCI1394_AsRspTrContextControlSet),
2343                                 reg_read(ohci, OHCI1394_AsRspTrCommandPtr));
2344
2345                 if (reg_read(ohci, OHCI1394_AsReqRcvContextControlSet) & 0x800)
2346                         PRINT(KERN_ERR, "Async Req Rcv Context died: "
2347                                 "ctrl[%08x] cmdptr[%08x]",
2348                                 reg_read(ohci, OHCI1394_AsReqRcvContextControlSet),
2349                                 reg_read(ohci, OHCI1394_AsReqRcvCommandPtr));
2350
2351                 if (reg_read(ohci, OHCI1394_AsRspRcvContextControlSet) & 0x800)
2352                         PRINT(KERN_ERR, "Async Rsp Rcv Context died: "
2353                                 "ctrl[%08x] cmdptr[%08x]",
2354                                 reg_read(ohci, OHCI1394_AsRspRcvContextControlSet),
2355                                 reg_read(ohci, OHCI1394_AsRspRcvCommandPtr));
2356
2357                 for (ctx = 0; ctx < ohci->nb_iso_xmit_ctx; ctx++) {
2358                         if (reg_read(ohci, OHCI1394_IsoXmitContextControlSet + (16 * ctx)) & 0x800)
2359                                 PRINT(KERN_ERR, "Iso Xmit %d Context died: "
2360                                         "ctrl[%08x] cmdptr[%08x]", ctx,
2361                                         reg_read(ohci, OHCI1394_IsoXmitContextControlSet + (16 * ctx)),
2362                                         reg_read(ohci, OHCI1394_IsoXmitCommandPtr + (16 * ctx)));
2363                 }
2364
2365                 for (ctx = 0; ctx < ohci->nb_iso_rcv_ctx; ctx++) {
2366                         if (reg_read(ohci, OHCI1394_IsoRcvContextControlSet + (32 * ctx)) & 0x800)
2367                                 PRINT(KERN_ERR, "Iso Recv %d Context died: "
2368                                         "ctrl[%08x] cmdptr[%08x] match[%08x]", ctx,
2369                                         reg_read(ohci, OHCI1394_IsoRcvContextControlSet + (32 * ctx)),
2370                                         reg_read(ohci, OHCI1394_IsoRcvCommandPtr + (32 * ctx)),
2371                                         reg_read(ohci, OHCI1394_IsoRcvContextMatch + (32 * ctx)));
2372                 }
2373
2374                 event &= ~OHCI1394_unrecoverableError;
2375         }
2376
2377         if (event & OHCI1394_cycleInconsistent) {
2378                 /* We subscribe to the cycleInconsistent event only to
2379                  * clear the corresponding event bit... otherwise,
2380                  * isochronous cycleMatch DMA won't work. */
2381                 DBGMSG("OHCI1394_cycleInconsistent");
2382                 event &= ~OHCI1394_cycleInconsistent;
2383         }
2384
2385         if (event & OHCI1394_busReset) {
2386                 /* The busReset event bit can't be cleared during the
2387                  * selfID phase, so we disable busReset interrupts, to
2388                  * avoid burying the cpu in interrupt requests. */
2389                 spin_lock_irqsave(&ohci->event_lock, flags);
2390                 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset);
2391
2392                 if (ohci->check_busreset) {
2393                         int loop_count = 0;
2394
2395                         udelay(10);
2396
2397                         while (reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
2398                                 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2399
2400                                 spin_unlock_irqrestore(&ohci->event_lock, flags);
2401                                 udelay(10);
2402                                 spin_lock_irqsave(&ohci->event_lock, flags);
2403
2404                                 /* The loop counter check is to prevent the driver
2405                                  * from remaining in this state forever. For the
2406                                  * initial bus reset, the loop continues for ever
2407                                  * and the system hangs, until some device is plugged-in
2408                                  * or out manually into a port! The forced reset seems
2409                                  * to solve this problem. This mainly effects nForce2. */
2410                                 if (loop_count > 10000) {
2411                                         ohci_devctl(host, RESET_BUS, LONG_RESET);
2412                                         DBGMSG("Detected bus-reset loop. Forced a bus reset!");
2413                                         loop_count = 0;
2414                                 }
2415
2416                                 loop_count++;
2417                         }
2418                 }
2419                 spin_unlock_irqrestore(&ohci->event_lock, flags);
2420                 if (!host->in_bus_reset) {
2421                         DBGMSG("irq_handler: Bus reset requested");
2422
2423                         /* Subsystem call */
2424                         hpsb_bus_reset(ohci->host);
2425                 }
2426                 event &= ~OHCI1394_busReset;
2427         }
2428
2429         if (event & OHCI1394_reqTxComplete) {
2430                 struct dma_trm_ctx *d = &ohci->at_req_context;
2431                 DBGMSG("Got reqTxComplete interrupt "
2432                        "status=0x%08X", reg_read(ohci, d->ctrlSet));
2433                 if (reg_read(ohci, d->ctrlSet) & 0x800)
2434                         ohci1394_stop_context(ohci, d->ctrlClear,
2435                                               "reqTxComplete");
2436                 else
2437                         dma_trm_tasklet((unsigned long)d);
2438                         //tasklet_schedule(&d->task);
2439                 event &= ~OHCI1394_reqTxComplete;
2440         }
2441         if (event & OHCI1394_respTxComplete) {
2442                 struct dma_trm_ctx *d = &ohci->at_resp_context;
2443                 DBGMSG("Got respTxComplete interrupt "
2444                        "status=0x%08X", reg_read(ohci, d->ctrlSet));
2445                 if (reg_read(ohci, d->ctrlSet) & 0x800)
2446                         ohci1394_stop_context(ohci, d->ctrlClear,
2447                                               "respTxComplete");
2448                 else
2449                         tasklet_schedule(&d->task);
2450                 event &= ~OHCI1394_respTxComplete;
2451         }
2452         if (event & OHCI1394_RQPkt) {
2453                 struct dma_rcv_ctx *d = &ohci->ar_req_context;
2454                 DBGMSG("Got RQPkt interrupt status=0x%08X",
2455                        reg_read(ohci, d->ctrlSet));
2456                 if (reg_read(ohci, d->ctrlSet) & 0x800)
2457                         ohci1394_stop_context(ohci, d->ctrlClear, "RQPkt");
2458                 else
2459                         tasklet_schedule(&d->task);
2460                 event &= ~OHCI1394_RQPkt;
2461         }
2462         if (event & OHCI1394_RSPkt) {
2463                 struct dma_rcv_ctx *d = &ohci->ar_resp_context;
2464                 DBGMSG("Got RSPkt interrupt status=0x%08X",
2465                        reg_read(ohci, d->ctrlSet));
2466                 if (reg_read(ohci, d->ctrlSet) & 0x800)
2467                         ohci1394_stop_context(ohci, d->ctrlClear, "RSPkt");
2468                 else
2469                         tasklet_schedule(&d->task);
2470                 event &= ~OHCI1394_RSPkt;
2471         }
2472         if (event & OHCI1394_isochRx) {
2473                 quadlet_t rx_event;
2474
2475                 rx_event = reg_read(ohci, OHCI1394_IsoRecvIntEventSet);
2476                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, rx_event);
2477                 ohci_schedule_iso_tasklets(ohci, rx_event, 0);
2478                 event &= ~OHCI1394_isochRx;
2479         }
2480         if (event & OHCI1394_isochTx) {
2481                 quadlet_t tx_event;
2482
2483                 tx_event = reg_read(ohci, OHCI1394_IsoXmitIntEventSet);
2484                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, tx_event);
2485                 ohci_schedule_iso_tasklets(ohci, 0, tx_event);
2486                 event &= ~OHCI1394_isochTx;
2487         }
2488         if (event & OHCI1394_selfIDComplete) {
2489                 if (host->in_bus_reset) {
2490                         node_id = reg_read(ohci, OHCI1394_NodeID);
2491
2492                         if (!(node_id & 0x80000000)) {
2493                                 PRINT(KERN_ERR,
2494                                       "SelfID received, but NodeID invalid "
2495                                       "(probably new bus reset occurred): %08X",
2496                                       node_id);
2497                                 goto selfid_not_valid;
2498                         }
2499
2500                         phyid =  node_id & 0x0000003f;
2501                         isroot = (node_id & 0x40000000) != 0;
2502
2503                         DBGMSG("SelfID interrupt received "
2504                               "(phyid %d, %s)", phyid,
2505                               (isroot ? "root" : "not root"));
2506
2507                         handle_selfid(ohci, host, phyid, isroot);
2508
2509                         /* Clear the bus reset event and re-enable the
2510                          * busReset interrupt.  */
2511                         spin_lock_irqsave(&ohci->event_lock, flags);
2512                         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2513                         reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
2514                         spin_unlock_irqrestore(&ohci->event_lock, flags);
2515
2516                         /* Accept Physical requests from all nodes. */
2517                         reg_write(ohci,OHCI1394_AsReqFilterHiSet, 0xffffffff);
2518                         reg_write(ohci,OHCI1394_AsReqFilterLoSet, 0xffffffff);
2519
2520                         /* Turn on phys dma reception.
2521                          *
2522                          * TODO: Enable some sort of filtering management.
2523                          */
2524                         if (phys_dma) {
2525                                 reg_write(ohci,OHCI1394_PhyReqFilterHiSet, 0xffffffff);
2526                                 reg_write(ohci,OHCI1394_PhyReqFilterLoSet, 0xffffffff);
2527                                 reg_write(ohci,OHCI1394_PhyUpperBound, 0xffff0000);
2528                         } else {
2529                                 reg_write(ohci,OHCI1394_PhyReqFilterHiSet, 0x00000000);
2530                                 reg_write(ohci,OHCI1394_PhyReqFilterLoSet, 0x00000000);
2531                         }
2532
2533                         DBGMSG("PhyReqFilter=%08x%08x",
2534                                reg_read(ohci,OHCI1394_PhyReqFilterHiSet),
2535                                reg_read(ohci,OHCI1394_PhyReqFilterLoSet));
2536
2537                         hpsb_selfid_complete(host, phyid, isroot);
2538                 } else
2539                         PRINT(KERN_ERR,
2540                               "SelfID received outside of bus reset sequence");
2541
2542 selfid_not_valid:
2543                 event &= ~OHCI1394_selfIDComplete;
2544         }
2545
2546         /* Make sure we handle everything, just in case we accidentally
2547          * enabled an interrupt that we didn't write a handler for.  */
2548         if (event)
2549                 PRINT(KERN_ERR, "Unhandled interrupt(s) 0x%08x",
2550                       event);
2551
2552         return IRQ_HANDLED;
2553 }
2554
2555 /* Put the buffer back into the dma context */
2556 static void insert_dma_buffer(struct dma_rcv_ctx *d, int idx)
2557 {
2558         struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2559         DBGMSG("Inserting dma buf ctx=%d idx=%d", d->ctx, idx);
2560
2561         d->prg_cpu[idx]->status = cpu_to_le32(d->buf_size);
2562         d->prg_cpu[idx]->branchAddress &= le32_to_cpu(0xfffffff0);
2563         idx = (idx + d->num_desc - 1 ) % d->num_desc;
2564         d->prg_cpu[idx]->branchAddress |= le32_to_cpu(0x00000001);
2565
2566         /* To avoid a race, ensure 1394 interface hardware sees the inserted
2567          * context program descriptors before it sees the wakeup bit set. */
2568         wmb();
2569         
2570         /* wake up the dma context if necessary */
2571         if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
2572                 PRINT(KERN_INFO,
2573                       "Waking dma ctx=%d ... processing is probably too slow",
2574                       d->ctx);
2575         }
2576
2577         /* do this always, to avoid race condition */
2578         reg_write(ohci, d->ctrlSet, 0x1000);
2579 }
2580
2581 #define cond_le32_to_cpu(data, noswap) \
2582         (noswap ? data : le32_to_cpu(data))
2583
2584 static const int TCODE_SIZE[16] = {20, 0, 16, -1, 16, 20, 20, 0,
2585                             -1, 0, -1, 0, -1, -1, 16, -1};
2586
2587 /*
2588  * Determine the length of a packet in the buffer
2589  * Optimization suggested by Pascal Drolet <pascal.drolet@informission.ca>
2590  */
2591 static __inline__ int packet_length(struct dma_rcv_ctx *d, int idx, quadlet_t *buf_ptr,
2592                          int offset, unsigned char tcode, int noswap)
2593 {
2594         int length = -1;
2595
2596         if (d->type == DMA_CTX_ASYNC_REQ || d->type == DMA_CTX_ASYNC_RESP) {
2597                 length = TCODE_SIZE[tcode];
2598                 if (length == 0) {
2599                         if (offset + 12 >= d->buf_size) {
2600                                 length = (cond_le32_to_cpu(d->buf_cpu[(idx + 1) % d->num_desc]
2601                                                 [3 - ((d->buf_size - offset) >> 2)], noswap) >> 16);
2602                         } else {
2603                                 length = (cond_le32_to_cpu(buf_ptr[3], noswap) >> 16);
2604                         }
2605                         length += 20;
2606                 }
2607         } else if (d->type == DMA_CTX_ISO) {
2608                 /* Assumption: buffer fill mode with header/trailer */
2609                 length = (cond_le32_to_cpu(buf_ptr[0], noswap) >> 16) + 8;
2610         }
2611
2612         if (length > 0 && length % 4)
2613                 length += 4 - (length % 4);
2614
2615         return length;
2616 }
2617
2618 /* Tasklet that processes dma receive buffers */
2619 static void dma_rcv_tasklet (unsigned long data)
2620 {
2621         struct dma_rcv_ctx *d = (struct dma_rcv_ctx*)data;
2622         struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2623         unsigned int split_left, idx, offset, rescount;
2624         unsigned char tcode;
2625         int length, bytes_left, ack;
2626         unsigned long flags;
2627         quadlet_t *buf_ptr;
2628         char *split_ptr;
2629         char msg[256];
2630
2631         spin_lock_irqsave(&d->lock, flags);
2632
2633         idx = d->buf_ind;
2634         offset = d->buf_offset;
2635         buf_ptr = d->buf_cpu[idx] + offset/4;
2636
2637         rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff;
2638         bytes_left = d->buf_size - rescount - offset;
2639
2640         while (bytes_left > 0) {
2641                 tcode = (cond_le32_to_cpu(buf_ptr[0], ohci->no_swap_incoming) >> 4) & 0xf;
2642
2643                 /* packet_length() will return < 4 for an error */
2644                 length = packet_length(d, idx, buf_ptr, offset, tcode, ohci->no_swap_incoming);
2645
2646                 if (length < 4) { /* something is wrong */
2647                         sprintf(msg,"Unexpected tcode 0x%x(0x%08x) in AR ctx=%d, length=%d",
2648                                 tcode, cond_le32_to_cpu(buf_ptr[0], ohci->no_swap_incoming),
2649                                 d->ctx, length);
2650                         ohci1394_stop_context(ohci, d->ctrlClear, msg);
2651                         spin_unlock_irqrestore(&d->lock, flags);
2652                         return;
2653                 }
2654
2655                 /* The first case is where we have a packet that crosses
2656                  * over more than one descriptor. The next case is where
2657                  * it's all in the first descriptor.  */
2658                 if ((offset + length) > d->buf_size) {
2659                         DBGMSG("Split packet rcv'd");
2660                         if (length > d->split_buf_size) {
2661                                 ohci1394_stop_context(ohci, d->ctrlClear,
2662                                              "Split packet size exceeded");
2663                                 d->buf_ind = idx;
2664                                 d->buf_offset = offset;
2665                                 spin_unlock_irqrestore(&d->lock, flags);
2666                                 return;
2667                         }
2668
2669                         if (le32_to_cpu(d->prg_cpu[(idx+1)%d->num_desc]->status)
2670                             == d->buf_size) {
2671                                 /* Other part of packet not written yet.
2672                                  * this should never happen I think
2673                                  * anyway we'll get it on the next call.  */
2674                                 PRINT(KERN_INFO,
2675                                       "Got only half a packet!");
2676                                 d->buf_ind = idx;
2677                                 d->buf_offset = offset;
2678                                 spin_unlock_irqrestore(&d->lock, flags);
2679                                 return;
2680                         }
2681
2682                         split_left = length;
2683                         split_ptr = (char *)d->spb;
2684                         memcpy(split_ptr,buf_ptr,d->buf_size-offset);
2685                         split_left -= d->buf_size-offset;
2686                         split_ptr += d->buf_size-offset;
2687                         insert_dma_buffer(d, idx);
2688                         idx = (idx+1) % d->num_desc;
2689                         buf_ptr = d->buf_cpu[idx];
2690                         offset=0;
2691
2692                         while (split_left >= d->buf_size) {
2693                                 memcpy(split_ptr,buf_ptr,d->buf_size);
2694                                 split_ptr += d->buf_size;
2695                                 split_left -= d->buf_size;
2696                                 insert_dma_buffer(d, idx);
2697                                 idx = (idx+1) % d->num_desc;
2698                                 buf_ptr = d->buf_cpu[idx];
2699                         }
2700
2701                         if (split_left > 0) {
2702                                 memcpy(split_ptr, buf_ptr, split_left);
2703                                 offset = split_left;
2704                                 buf_ptr += offset/4;
2705                         }
2706                 } else {
2707                         DBGMSG("Single packet rcv'd");
2708                         memcpy(d->spb, buf_ptr, length);
2709                         offset += length;
2710                         buf_ptr += length/4;
2711                         if (offset==d->buf_size) {
2712                                 insert_dma_buffer(d, idx);
2713                                 idx = (idx+1) % d->num_desc;
2714                                 buf_ptr = d->buf_cpu[idx];
2715                                 offset=0;
2716                         }
2717                 }
2718
2719                 /* We get one phy packet to the async descriptor for each
2720                  * bus reset. We always ignore it.  */
2721                 if (tcode != OHCI1394_TCODE_PHY) {
2722                         if (!ohci->no_swap_incoming)
2723                                 packet_swab(d->spb, tcode);
2724                         DBGMSG("Packet received from node"
2725                                 " %d ack=0x%02X spd=%d tcode=0x%X"
2726                                 " length=%d ctx=%d tlabel=%d",
2727                                 (d->spb[1]>>16)&0x3f,
2728                                 (cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>16)&0x1f,
2729                                 (cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>21)&0x3,
2730                                 tcode, length, d->ctx,
2731                                 (cond_le32_to_cpu(d->spb[0], ohci->no_swap_incoming)>>10)&0x3f);
2732
2733                         ack = (((cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>16)&0x1f)
2734                                 == 0x11) ? 1 : 0;
2735
2736                         hpsb_packet_received(ohci->host, d->spb,
2737                                              length-4, ack);
2738                 }
2739 #ifdef OHCI1394_DEBUG
2740                 else
2741                         PRINT (KERN_DEBUG, "Got phy packet ctx=%d ... discarded",
2742                                d->ctx);
2743 #endif
2744
2745                 rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff;
2746
2747                 bytes_left = d->buf_size - rescount - offset;
2748
2749         }
2750
2751         d->buf_ind = idx;
2752         d->buf_offset = offset;
2753
2754         spin_unlock_irqrestore(&d->lock, flags);
2755 }
2756
2757 /* Bottom half that processes sent packets */
2758 static void dma_trm_tasklet (unsigned long data)
2759 {
2760         struct dma_trm_ctx *d = (struct dma_trm_ctx*)data;
2761         struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2762         struct hpsb_packet *packet, *ptmp;
2763         unsigned long flags;
2764         u32 status, ack;
2765         size_t datasize;
2766
2767         spin_lock_irqsave(&d->lock, flags);
2768
2769         list_for_each_entry_safe(packet, ptmp, &d->fifo_list, driver_list) {
2770                 datasize = packet->data_size;
2771                 if (datasize && packet->type != hpsb_raw)
2772                         status = le32_to_cpu(
2773                                 d->prg_cpu[d->sent_ind]->end.status) >> 16;
2774                 else
2775                         status = le32_to_cpu(
2776                                 d->prg_cpu[d->sent_ind]->begin.status) >> 16;
2777
2778                 if (status == 0)
2779                         /* this packet hasn't been sent yet*/
2780                         break;
2781
2782 #ifdef OHCI1394_DEBUG
2783                 if (datasize)
2784                         if (((le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf) == 0xa)
2785                                 DBGMSG("Stream packet sent to channel %d tcode=0x%X "
2786                                        "ack=0x%X spd=%d dataLength=%d ctx=%d",
2787                                        (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>8)&0x3f,
2788                                        (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf,
2789                                        status&0x1f, (status>>5)&0x3,
2790                                        le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])>>16,
2791                                        d->ctx);
2792                         else
2793                                 DBGMSG("Packet sent to node %d tcode=0x%X tLabel="
2794                                        "%d ack=0x%X spd=%d dataLength=%d ctx=%d",
2795                                        (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])>>16)&0x3f,
2796                                        (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf,
2797                                        (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>10)&0x3f,
2798                                        status&0x1f, (status>>5)&0x3,
2799                                        le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3])>>16,
2800                                        d->ctx);
2801                 else
2802                         DBGMSG("Packet sent to node %d tcode=0x%X tLabel="
2803                                "%d ack=0x%X spd=%d data=0x%08X ctx=%d",
2804                                 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])
2805                                         >>16)&0x3f,
2806                                 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
2807                                         >>4)&0xf,
2808                                 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
2809                                         >>10)&0x3f,
2810                                 status&0x1f, (status>>5)&0x3,
2811                                 le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3]),
2812                                 d->ctx);
2813 #endif
2814
2815                 if (status & 0x10) {
2816                         ack = status & 0xf;
2817                 } else {
2818                         switch (status & 0x1f) {
2819                         case EVT_NO_STATUS: /* that should never happen */
2820                         case EVT_RESERVED_A: /* that should never happen */
2821                         case EVT_LONG_PACKET: /* that should never happen */
2822                                 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2823                                 ack = ACKX_SEND_ERROR;
2824                                 break;
2825                         case EVT_MISSING_ACK:
2826                                 ack = ACKX_TIMEOUT;
2827                                 break;
2828                         case EVT_UNDERRUN:
2829                                 ack = ACKX_SEND_ERROR;
2830                                 break;
2831                         case EVT_OVERRUN: /* that should never happen */
2832                                 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2833                                 ack = ACKX_SEND_ERROR;
2834                                 break;
2835                         case EVT_DESCRIPTOR_READ:
2836                         case EVT_DATA_READ:
2837                         case EVT_DATA_WRITE:
2838                                 ack = ACKX_SEND_ERROR;
2839                                 break;
2840                         case EVT_BUS_RESET: /* that should never happen */
2841                                 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2842                                 ack = ACKX_SEND_ERROR;
2843                                 break;
2844                         case EVT_TIMEOUT:
2845                                 ack = ACKX_TIMEOUT;
2846                                 break;
2847                         case EVT_TCODE_ERR:
2848                                 ack = ACKX_SEND_ERROR;
2849                                 break;
2850                         case EVT_RESERVED_B: /* that should never happen */
2851                         case EVT_RESERVED_C: /* that should never happen */
2852                                 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2853                                 ack = ACKX_SEND_ERROR;
2854                                 break;
2855                         case EVT_UNKNOWN:
2856                         case EVT_FLUSHED:
2857                                 ack = ACKX_SEND_ERROR;
2858                                 break;
2859                         default:
2860                                 PRINT(KERN_ERR, "Unhandled OHCI evt_* error 0x%x", status & 0x1f);
2861                                 ack = ACKX_SEND_ERROR;
2862                                 BUG();
2863                         }
2864                 }
2865
2866                 list_del_init(&packet->driver_list);
2867                 hpsb_packet_sent(ohci->host, packet, ack);
2868
2869                 if (datasize) {
2870                         pci_unmap_single(ohci->dev,
2871                                          cpu_to_le32(d->prg_cpu[d->sent_ind]->end.address),
2872                                          datasize, PCI_DMA_TODEVICE);
2873                         OHCI_DMA_FREE("single Xmit data packet");
2874                 }
2875
2876                 d->sent_ind = (d->sent_ind+1)%d->num_desc;
2877                 d->free_prgs++;
2878         }
2879
2880         dma_trm_flush(ohci, d);
2881
2882         spin_unlock_irqrestore(&d->lock, flags);
2883 }
2884
2885 static void stop_dma_rcv_ctx(struct dma_rcv_ctx *d)
2886 {
2887         if (d->ctrlClear) {
2888                 ohci1394_stop_context(d->ohci, d->ctrlClear, NULL);
2889
2890                 if (d->type == DMA_CTX_ISO) {
2891                         /* disable interrupts */
2892                         reg_write(d->ohci, OHCI1394_IsoRecvIntMaskClear, 1 << d->ctx);
2893                         ohci1394_unregister_iso_tasklet(d->ohci, &d->ohci->ir_legacy_tasklet);
2894                 } else {
2895                         tasklet_kill(&d->task);
2896                 }
2897         }
2898 }
2899
2900
2901 static void free_dma_rcv_ctx(struct dma_rcv_ctx *d)
2902 {
2903         int i;
2904         struct ti_ohci *ohci = d->ohci;
2905
2906         if (ohci == NULL)
2907                 return;
2908
2909         DBGMSG("Freeing dma_rcv_ctx %d", d->ctx);
2910
2911         if (d->buf_cpu) {
2912                 for (i=0; i<d->num_desc; i++)
2913                         if (d->buf_cpu[i] && d->buf_bus[i]) {
2914                                 pci_free_consistent(
2915                                         ohci->dev, d->buf_size,
2916                                         d->buf_cpu[i], d->buf_bus[i]);
2917                                 OHCI_DMA_FREE("consistent dma_rcv buf[%d]", i);
2918                         }
2919                 kfree(d->buf_cpu);
2920                 kfree(d->buf_bus);
2921         }
2922         if (d->prg_cpu) {
2923                 for (i=0; i<d->num_desc; i++)
2924                         if (d->prg_cpu[i] && d->prg_bus[i]) {
2925                                 pci_pool_free(d->prg_pool, d->prg_cpu[i], d->prg_bus[i]);
2926                                 OHCI_DMA_FREE("consistent dma_rcv prg[%d]", i);
2927                         }
2928                 pci_pool_destroy(d->prg_pool);
2929                 OHCI_DMA_FREE("dma_rcv prg pool");
2930                 kfree(d->prg_cpu);
2931                 kfree(d->prg_bus);
2932         }
2933         kfree(d->spb);
2934
2935         /* Mark this context as freed. */
2936         d->ohci = NULL;
2937 }
2938
2939 static int
2940 alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d,
2941                   enum context_type type, int ctx, int num_desc,
2942                   int buf_size, int split_buf_size, int context_base)
2943 {
2944         int i, len;
2945         static int num_allocs;
2946         static char pool_name[20];
2947
2948         d->ohci = ohci;
2949         d->type = type;
2950         d->ctx = ctx;
2951
2952         d->num_desc = num_desc;
2953         d->buf_size = buf_size;
2954         d->split_buf_size = split_buf_size;
2955
2956         d->ctrlSet = 0;
2957         d->ctrlClear = 0;
2958         d->cmdPtr = 0;
2959
2960         d->buf_cpu = kmalloc(d->num_desc * sizeof(quadlet_t*), GFP_ATOMIC);
2961         d->buf_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_ATOMIC);
2962
2963         if (d->buf_cpu == NULL || d->buf_bus == NULL) {
2964                 PRINT(KERN_ERR, "Failed to allocate dma buffer");
2965                 free_dma_rcv_ctx(d);
2966                 return -ENOMEM;
2967         }
2968         memset(d->buf_cpu, 0, d->num_desc * sizeof(quadlet_t*));
2969         memset(d->buf_bus, 0, d->num_desc * sizeof(dma_addr_t));
2970
2971         d->prg_cpu = kmalloc(d->num_desc * sizeof(struct dma_cmd*),
2972                                 GFP_ATOMIC);
2973         d->prg_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_ATOMIC);
2974
2975         if (d->prg_cpu == NULL || d->prg_bus == NULL) {
2976                 PRINT(KERN_ERR, "Failed to allocate dma prg");
2977                 free_dma_rcv_ctx(d);
2978                 return -ENOMEM;
2979         }
2980         memset(d->prg_cpu, 0, d->num_desc * sizeof(struct dma_cmd*));
2981         memset(d->prg_bus, 0, d->num_desc * sizeof(dma_addr_t));
2982
2983         d->spb = kmalloc(d->split_buf_size, GFP_ATOMIC);
2984
2985         if (d->spb == NULL) {
2986                 PRINT(KERN_ERR, "Failed to allocate split buffer");
2987                 free_dma_rcv_ctx(d);
2988                 return -ENOMEM;
2989         }
2990         
2991         len = sprintf(pool_name, "ohci1394_rcv_prg");
2992         sprintf(pool_name+len, "%d", num_allocs);
2993         d->prg_pool = pci_pool_create(pool_name, ohci->dev,
2994                                 sizeof(struct dma_cmd), 4, 0);
2995         if(d->prg_pool == NULL)
2996         {
2997                 PRINT(KERN_ERR, "pci_pool_create failed for %s", pool_name);
2998                 free_dma_rcv_ctx(d);
2999                 return -ENOMEM;
3000         }
3001         num_allocs++;
3002
3003         OHCI_DMA_ALLOC("dma_rcv prg pool");
3004
3005         for (i=0; i<d->num_desc; i++) {
3006                 d->buf_cpu[i] = pci_alloc_consistent(ohci->dev,
3007                                                      d->buf_size,
3008                                                      d->buf_bus+i);
3009                 OHCI_DMA_ALLOC("consistent dma_rcv buf[%d]", i);
3010
3011                 if (d->buf_cpu[i] != NULL) {
3012                         memset(d->buf_cpu[i], 0, d->buf_size);
3013                 } else {
3014                         PRINT(KERN_ERR,
3015                               "Failed to allocate dma buffer");
3016                         free_dma_rcv_ctx(d);
3017                         return -ENOMEM;
3018                 }
3019
3020                 d->prg_cpu[i] = pci_pool_alloc(d->prg_pool, SLAB_KERNEL, d->prg_bus+i);
3021                 OHCI_DMA_ALLOC("pool dma_rcv prg[%d]", i);
3022
3023                 if (d->prg_cpu[i] != NULL) {
3024                         memset(d->prg_cpu[i], 0, sizeof(struct dma_cmd));
3025                 } else {
3026                         PRINT(KERN_ERR,
3027                               "Failed to allocate dma prg");
3028                         free_dma_rcv_ctx(d);
3029                         return -ENOMEM;
3030                 }
3031         }
3032
3033         spin_lock_init(&d->lock);
3034
3035         if (type == DMA_CTX_ISO) {
3036                 ohci1394_init_iso_tasklet(&ohci->ir_legacy_tasklet,
3037                                           OHCI_ISO_MULTICHANNEL_RECEIVE,
3038                                           dma_rcv_tasklet, (unsigned long) d);
3039         } else {
3040                 d->ctrlSet = context_base + OHCI1394_ContextControlSet;
3041                 d->ctrlClear = context_base + OHCI1394_ContextControlClear;
3042                 d->cmdPtr = context_base + OHCI1394_ContextCommandPtr;
3043
3044                 tasklet_init (&d->task, dma_rcv_tasklet, (unsigned long) d);
3045         }
3046
3047         return 0;
3048 }
3049
3050 static void free_dma_trm_ctx(struct dma_trm_ctx *d)
3051 {
3052         int i;
3053         struct ti_ohci *ohci = d->ohci;
3054
3055         if (ohci == NULL)
3056                 return;
3057
3058         DBGMSG("Freeing dma_trm_ctx %d", d->ctx);
3059
3060         if (d->prg_cpu) {
3061                 for (i=0; i<d->num_desc; i++)
3062                         if (d->prg_cpu[i] && d->prg_bus[i]) {
3063                                 pci_pool_free(d->prg_pool, d->prg_cpu[i], d->prg_bus[i]);
3064                                 OHCI_DMA_FREE("pool dma_trm prg[%d]", i);
3065                         }
3066                 pci_pool_destroy(d->prg_pool);
3067                 OHCI_DMA_FREE("dma_trm prg pool");
3068                 kfree(d->prg_cpu);
3069                 kfree(d->prg_bus);
3070         }
3071
3072         /* Mark this context as freed. */
3073         d->ohci = NULL;
3074 }
3075
3076 static int
3077 alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d,
3078                   enum context_type type, int ctx, int num_desc,
3079                   int context_base)
3080 {
3081         int i, len;
3082         static char pool_name[20];
3083         static int num_allocs=0;
3084
3085         d->ohci = ohci;
3086         d->type = type;
3087         d->ctx = ctx;
3088         d->num_desc = num_desc;
3089         d->ctrlSet = 0;
3090         d->ctrlClear = 0;
3091         d->cmdPtr = 0;
3092
3093         d->prg_cpu = kmalloc(d->num_desc * sizeof(struct at_dma_prg*),
3094                              GFP_KERNEL);
3095         d->prg_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_KERNEL);
3096
3097         if (d->prg_cpu == NULL || d->prg_bus == NULL) {
3098                 PRINT(KERN_ERR, "Failed to allocate at dma prg");
3099                 free_dma_trm_ctx(d);
3100                 return -ENOMEM;
3101         }
3102         memset(d->prg_cpu, 0, d->num_desc * sizeof(struct at_dma_prg*));
3103         memset(d->prg_bus, 0, d->num_desc * sizeof(dma_addr_t));
3104
3105         len = sprintf(pool_name, "ohci1394_trm_prg");
3106         sprintf(pool_name+len, "%d", num_allocs);
3107         d->prg_pool = pci_pool_create(pool_name, ohci->dev,
3108                                 sizeof(struct at_dma_prg), 4, 0);
3109         if (d->prg_pool == NULL) {
3110                 PRINT(KERN_ERR, "pci_pool_create failed for %s", pool_name);
3111                 free_dma_trm_ctx(d);
3112                 return -ENOMEM;
3113         }
3114         num_allocs++;
3115
3116         OHCI_DMA_ALLOC("dma_rcv prg pool");
3117
3118         for (i = 0; i < d->num_desc; i++) {
3119                 d->prg_cpu[i] = pci_pool_alloc(d->prg_pool, SLAB_KERNEL, d->prg_bus+i);
3120                 OHCI_DMA_ALLOC("pool dma_trm prg[%d]", i);
3121
3122                 if (d->prg_cpu[i] != NULL) {
3123                         memset(d->prg_cpu[i], 0, sizeof(struct at_dma_prg));
3124                 } else {
3125                         PRINT(KERN_ERR,
3126                               "Failed to allocate at dma prg");
3127                         free_dma_trm_ctx(d);
3128                         return -ENOMEM;
3129                 }
3130         }
3131
3132         spin_lock_init(&d->lock);
3133
3134         /* initialize tasklet */
3135         if (type == DMA_CTX_ISO) {
3136                 ohci1394_init_iso_tasklet(&ohci->it_legacy_tasklet, OHCI_ISO_TRANSMIT,
3137                                           dma_trm_tasklet, (unsigned long) d);
3138                 if (ohci1394_register_iso_tasklet(ohci,
3139                                                   &ohci->it_legacy_tasklet) < 0) {
3140                         PRINT(KERN_ERR, "No IT DMA context available");
3141                         free_dma_trm_ctx(d);
3142                         return -EBUSY;
3143                 }
3144
3145                 /* IT can be assigned to any context by register_iso_tasklet */
3146                 d->ctx = ohci->it_legacy_tasklet.context;
3147                 d->ctrlSet = OHCI1394_IsoXmitContextControlSet + 16 * d->ctx;
3148                 d->ctrlClear = OHCI1394_IsoXmitContextControlClear + 16 * d->ctx;
3149                 d->cmdPtr = OHCI1394_IsoXmitCommandPtr + 16 * d->ctx;
3150         } else {
3151                 d->ctrlSet = context_base + OHCI1394_ContextControlSet;
3152                 d->ctrlClear = context_base + OHCI1394_ContextControlClear;
3153                 d->cmdPtr = context_base + OHCI1394_ContextCommandPtr;
3154                 tasklet_init (&d->task, dma_trm_tasklet, (unsigned long)d);
3155         }
3156
3157         return 0;
3158 }
3159
3160 static void ohci_set_hw_config_rom(struct hpsb_host *host, quadlet_t *config_rom)
3161 {
3162         struct ti_ohci *ohci = host->hostdata;
3163
3164         reg_write(ohci, OHCI1394_ConfigROMhdr, be32_to_cpu(config_rom[0]));
3165         reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(config_rom[2]));
3166
3167         memcpy(ohci->csr_config_rom_cpu, config_rom, OHCI_CONFIG_ROM_LEN);
3168 }
3169
3170
3171 static quadlet_t ohci_hw_csr_reg(struct hpsb_host *host, int reg,
3172                                  quadlet_t data, quadlet_t compare)
3173 {
3174         struct ti_ohci *ohci = host->hostdata;
3175         int i;
3176
3177         reg_write(ohci, OHCI1394_CSRData, data);
3178         reg_write(ohci, OHCI1394_CSRCompareData, compare);
3179         reg_write(ohci, OHCI1394_CSRControl, reg & 0x3);
3180
3181         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
3182                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
3183                         break;
3184
3185                 mdelay(1);
3186         }
3187
3188         return reg_read(ohci, OHCI1394_CSRData);
3189 }
3190
3191 static struct hpsb_host_driver ohci1394_driver = {
3192         .owner =                THIS_MODULE,
3193         .name =                 OHCI1394_DRIVER_NAME,
3194         .set_hw_config_rom =    ohci_set_hw_config_rom,
3195         .transmit_packet =      ohci_transmit,
3196         .devctl =               ohci_devctl,
3197         .isoctl =               ohci_isoctl,
3198         .hw_csr_reg =           ohci_hw_csr_reg,
3199 };
3200
3201 /***********************************
3202  * PCI Driver Interface functions  *
3203  ***********************************/
3204
3205 #define FAIL(err, fmt, args...)                 \
3206 do {                                            \
3207         PRINT_G(KERN_ERR, fmt , ## args);       \
3208         ohci1394_pci_remove(dev);               \
3209         return err;                             \
3210 } while (0)
3211
3212 static int __devinit ohci1394_pci_probe(struct pci_dev *dev,
3213                                         const struct pci_device_id *ent)
3214 {
3215         struct hpsb_host *host;
3216         struct ti_ohci *ohci;   /* shortcut to currently handled device */
3217         unsigned long ohci_base;
3218
3219         if (pci_enable_device(dev))
3220                 FAIL(-ENXIO, "Failed to enable OHCI hardware");
3221         pci_set_master(dev);
3222
3223         host = hpsb_alloc_host(&ohci1394_driver, sizeof(struct ti_ohci), &dev->dev);
3224         if (!host) FAIL(-ENOMEM, "Failed to allocate host structure");
3225
3226         ohci = host->hostdata;
3227         ohci->dev = dev;
3228         ohci->host = host;
3229         ohci->init_state = OHCI_INIT_ALLOC_HOST;
3230         host->pdev = dev;
3231         pci_set_drvdata(dev, ohci);
3232
3233         /* We don't want hardware swapping */
3234         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3235
3236         /* Some oddball Apple controllers do not order the selfid
3237          * properly, so we make up for it here.  */
3238 #ifndef __LITTLE_ENDIAN
3239         /* XXX: Need a better way to check this. I'm wondering if we can
3240          * read the values of the OHCI1394_PCI_HCI_Control and the
3241          * noByteSwapData registers to see if they were not cleared to
3242          * zero. Should this work? Obviously it's not defined what these
3243          * registers will read when they aren't supported. Bleh! */
3244         if (dev->vendor == PCI_VENDOR_ID_APPLE &&
3245             dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW) {
3246                 ohci->no_swap_incoming = 1;
3247                 ohci->selfid_swap = 0;
3248         } else
3249                 ohci->selfid_swap = 1;
3250 #endif
3251
3252
3253 #ifndef PCI_DEVICE_ID_NVIDIA_NFORCE2_FW
3254 #define PCI_DEVICE_ID_NVIDIA_NFORCE2_FW 0x006e
3255 #endif
3256
3257         /* These chipsets require a bit of extra care when checking after
3258          * a busreset.  */
3259         if ((dev->vendor == PCI_VENDOR_ID_APPLE &&
3260              dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW) ||
3261             (dev->vendor ==  PCI_VENDOR_ID_NVIDIA &&
3262              dev->device == PCI_DEVICE_ID_NVIDIA_NFORCE2_FW))
3263                 ohci->check_busreset = 1;
3264
3265         /* We hardwire the MMIO length, since some CardBus adaptors
3266          * fail to report the right length.  Anyway, the ohci spec
3267          * clearly says it's 2kb, so this shouldn't be a problem. */
3268         ohci_base = pci_resource_start(dev, 0);
3269         if (pci_resource_len(dev, 0) != OHCI1394_REGISTER_SIZE)
3270                 PRINT(KERN_WARNING, "Unexpected PCI resource length of %lx!",
3271                       pci_resource_len(dev, 0));
3272
3273         /* Seems PCMCIA handles this internally. Not sure why. Seems
3274          * pretty bogus to force a driver to special case this.  */
3275 #ifndef PCMCIA
3276         if (!request_mem_region (ohci_base, OHCI1394_REGISTER_SIZE, OHCI1394_DRIVER_NAME))
3277                 FAIL(-ENOMEM, "MMIO resource (0x%lx - 0x%lx) unavailable",
3278                      ohci_base, ohci_base + OHCI1394_REGISTER_SIZE);
3279 #endif
3280         ohci->init_state = OHCI_INIT_HAVE_MEM_REGION;
3281
3282         ohci->registers = ioremap(ohci_base, OHCI1394_REGISTER_SIZE);
3283         if (ohci->registers == NULL)
3284                 FAIL(-ENXIO, "Failed to remap registers - card not accessible");
3285         ohci->init_state = OHCI_INIT_HAVE_IOMAPPING;
3286         DBGMSG("Remapped memory spaces reg 0x%p", ohci->registers);
3287
3288         /* csr_config rom allocation */
3289         ohci->csr_config_rom_cpu =
3290                 pci_alloc_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN,
3291                                      &ohci->csr_config_rom_bus);
3292         OHCI_DMA_ALLOC("consistent csr_config_rom");
3293         if (ohci->csr_config_rom_cpu == NULL)
3294                 FAIL(-ENOMEM, "Failed to allocate buffer config rom");
3295         ohci->init_state = OHCI_INIT_HAVE_CONFIG_ROM_BUFFER;
3296
3297         /* self-id dma buffer allocation */
3298         ohci->selfid_buf_cpu =
3299                 pci_alloc_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE,
3300                       &ohci->selfid_buf_bus);
3301         OHCI_DMA_ALLOC("consistent selfid_buf");
3302
3303         if (ohci->selfid_buf_cpu == NULL)
3304                 FAIL(-ENOMEM, "Failed to allocate DMA buffer for self-id packets");
3305         ohci->init_state = OHCI_INIT_HAVE_SELFID_BUFFER;
3306
3307         if ((unsigned long)ohci->selfid_buf_cpu & 0x1fff)
3308                 PRINT(KERN_INFO, "SelfID buffer %p is not aligned on "
3309                       "8Kb boundary... may cause problems on some CXD3222 chip",
3310                       ohci->selfid_buf_cpu);
3311
3312         /* No self-id errors at startup */
3313         ohci->self_id_errors = 0;
3314
3315         ohci->init_state = OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE;
3316         /* AR DMA request context allocation */
3317         if (alloc_dma_rcv_ctx(ohci, &ohci->ar_req_context,
3318                               DMA_CTX_ASYNC_REQ, 0, AR_REQ_NUM_DESC,
3319                               AR_REQ_BUF_SIZE, AR_REQ_SPLIT_BUF_SIZE,
3320                               OHCI1394_AsReqRcvContextBase) < 0)
3321                 FAIL(-ENOMEM, "Failed to allocate AR Req context");
3322
3323         /* AR DMA response context allocation */
3324         if (alloc_dma_rcv_ctx(ohci, &ohci->ar_resp_context,
3325                               DMA_CTX_ASYNC_RESP, 0, AR_RESP_NUM_DESC,
3326                               AR_RESP_BUF_SIZE, AR_RESP_SPLIT_BUF_SIZE,
3327                               OHCI1394_AsRspRcvContextBase) < 0)
3328                 FAIL(-ENOMEM, "Failed to allocate AR Resp context");
3329
3330         /* AT DMA request context */
3331         if (alloc_dma_trm_ctx(ohci, &ohci->at_req_context,
3332                               DMA_CTX_ASYNC_REQ, 0, AT_REQ_NUM_DESC,
3333                               OHCI1394_AsReqTrContextBase) < 0)
3334                 FAIL(-ENOMEM, "Failed to allocate AT Req context");
3335
3336         /* AT DMA response context */
3337         if (alloc_dma_trm_ctx(ohci, &ohci->at_resp_context,
3338                               DMA_CTX_ASYNC_RESP, 1, AT_RESP_NUM_DESC,
3339                               OHCI1394_AsRspTrContextBase) < 0)
3340                 FAIL(-ENOMEM, "Failed to allocate AT Resp context");
3341
3342         /* Start off with a soft reset, to clear everything to a sane
3343          * state. */
3344         ohci_soft_reset(ohci);
3345
3346         /* Now enable LPS, which we need in order to start accessing
3347          * most of the registers.  In fact, on some cards (ALI M5251),
3348          * accessing registers in the SClk domain without LPS enabled
3349          * will lock up the machine.  Wait 50msec to make sure we have
3350          * full link enabled.  */
3351         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
3352
3353         /* Disable and clear interrupts */
3354         reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3355         reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3356
3357         mdelay(50);
3358
3359         /* Determine the number of available IR and IT contexts. */
3360         ohci->nb_iso_rcv_ctx =
3361                 get_nb_iso_ctx(ohci, OHCI1394_IsoRecvIntMaskSet);
3362         DBGMSG("%d iso receive contexts available",
3363                ohci->nb_iso_rcv_ctx);
3364
3365         ohci->nb_iso_xmit_ctx =
3366                 get_nb_iso_ctx(ohci, OHCI1394_IsoXmitIntMaskSet);
3367         DBGMSG("%d iso transmit contexts available",
3368                ohci->nb_iso_xmit_ctx);
3369
3370         /* Set the usage bits for non-existent contexts so they can't
3371          * be allocated */
3372         ohci->ir_ctx_usage = ~0 << ohci->nb_iso_rcv_ctx;
3373         ohci->it_ctx_usage = ~0 << ohci->nb_iso_xmit_ctx;
3374
3375         INIT_LIST_HEAD(&ohci->iso_tasklet_list);
3376         spin_lock_init(&ohci->iso_tasklet_list_lock);
3377         ohci->ISO_channel_usage = 0;
3378         spin_lock_init(&ohci->IR_channel_lock);
3379
3380         /* Allocate the IR DMA context right here so we don't have
3381          * to do it in interrupt path - note that this doesn't
3382          * waste much memory and avoids the jugglery required to
3383          * allocate it in IRQ path. */
3384         if (alloc_dma_rcv_ctx(ohci, &ohci->ir_legacy_context,
3385                               DMA_CTX_ISO, 0, IR_NUM_DESC,
3386                               IR_BUF_SIZE, IR_SPLIT_BUF_SIZE,
3387                               OHCI1394_IsoRcvContextBase) < 0) {
3388                 FAIL(-ENOMEM, "Cannot allocate IR Legacy DMA context");
3389         }
3390
3391         /* We hopefully don't have to pre-allocate IT DMA like we did
3392          * for IR DMA above. Allocate it on-demand and mark inactive. */
3393         ohci->it_legacy_context.ohci = NULL;
3394         spin_lock_init(&ohci->event_lock);
3395
3396         /*
3397          * interrupts are disabled, all right, but... due to SA_SHIRQ we
3398          * might get called anyway.  We'll see no event, of course, but
3399          * we need to get to that "no event", so enough should be initialized
3400          * by that point.
3401          */
3402         if (request_irq(dev->irq, ohci_irq_handler, SA_SHIRQ,
3403                          OHCI1394_DRIVER_NAME, ohci))
3404                 FAIL(-ENOMEM, "Failed to allocate shared interrupt %d", dev->irq);
3405
3406         ohci->init_state = OHCI_INIT_HAVE_IRQ;
3407         ohci_initialize(ohci);
3408
3409         /* Set certain csr values */
3410         host->csr.guid_hi = reg_read(ohci, OHCI1394_GUIDHi);
3411         host->csr.guid_lo = reg_read(ohci, OHCI1394_GUIDLo);
3412         host->csr.cyc_clk_acc = 100;  /* how do we determine clk accuracy? */
3413         host->csr.max_rec = (reg_read(ohci, OHCI1394_BusOptions) >> 12) & 0xf;
3414         host->csr.lnk_spd = reg_read(ohci, OHCI1394_BusOptions) & 0x7;
3415
3416         /* Tell the highlevel this host is ready */
3417         if (hpsb_add_host(host))
3418                 FAIL(-ENOMEM, "Failed to register host with highlevel");
3419
3420         ohci->init_state = OHCI_INIT_DONE;
3421
3422         return 0;
3423 #undef FAIL
3424 }
3425
3426 static void ohci1394_pci_remove(struct pci_dev *pdev)
3427 {
3428         struct ti_ohci *ohci;
3429         struct device *dev;
3430
3431         ohci = pci_get_drvdata(pdev);
3432         if (!ohci)
3433                 return;
3434
3435         dev = get_device(&ohci->host->device);
3436
3437         switch (ohci->init_state) {
3438         case OHCI_INIT_DONE:
3439                 hpsb_remove_host(ohci->host);
3440
3441                 /* Clear out BUS Options */
3442                 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
3443                 reg_write(ohci, OHCI1394_BusOptions,
3444                           (reg_read(ohci, OHCI1394_BusOptions) & 0x0000f007) |
3445                           0x00ff0000);
3446                 memset(ohci->csr_config_rom_cpu, 0, OHCI_CONFIG_ROM_LEN);
3447
3448         case OHCI_INIT_HAVE_IRQ:
3449                 /* Clear interrupt registers */
3450                 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3451                 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3452                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
3453                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
3454                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
3455                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
3456
3457                 /* Disable IRM Contender */
3458                 set_phy_reg(ohci, 4, ~0xc0 & get_phy_reg(ohci, 4));
3459
3460                 /* Clear link control register */
3461                 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
3462
3463                 /* Let all other nodes know to ignore us */
3464                 ohci_devctl(ohci->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT);
3465
3466                 /* Soft reset before we start - this disables
3467                  * interrupts and clears linkEnable and LPS. */
3468                 ohci_soft_reset(ohci);
3469                 free_irq(ohci->dev->irq, ohci);
3470
3471         case OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE:
3472                 /* The ohci_soft_reset() stops all DMA contexts, so we
3473                  * dont need to do this.  */
3474                 /* Free AR dma */
3475                 free_dma_rcv_ctx(&ohci->ar_req_context);
3476                 free_dma_rcv_ctx(&ohci->ar_resp_context);
3477
3478                 /* Free AT dma */
3479                 free_dma_trm_ctx(&ohci->at_req_context);
3480                 free_dma_trm_ctx(&ohci->at_resp_context);
3481
3482                 /* Free IR dma */
3483                 free_dma_rcv_ctx(&ohci->ir_legacy_context);
3484
3485                 /* Free IT dma */
3486                 free_dma_trm_ctx(&ohci->it_legacy_context);
3487
3488                 /* Free IR legacy dma */
3489                 free_dma_rcv_ctx(&ohci->ir_legacy_context);
3490
3491
3492         case OHCI_INIT_HAVE_SELFID_BUFFER:
3493                 pci_free_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE,
3494                                     ohci->selfid_buf_cpu,
3495                                     ohci->selfid_buf_bus);
3496                 OHCI_DMA_FREE("consistent selfid_buf");
3497
3498         case OHCI_INIT_HAVE_CONFIG_ROM_BUFFER:
3499                 pci_free_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN,
3500                                     ohci->csr_config_rom_cpu,
3501                                     ohci->csr_config_rom_bus);
3502                 OHCI_DMA_FREE("consistent csr_config_rom");
3503
3504         case OHCI_INIT_HAVE_IOMAPPING:
3505                 iounmap(ohci->registers);
3506
3507         case OHCI_INIT_HAVE_MEM_REGION:
3508 #ifndef PCMCIA
3509                 release_mem_region(pci_resource_start(ohci->dev, 0),
3510                                    OHCI1394_REGISTER_SIZE);
3511 #endif
3512
3513 #ifdef CONFIG_PPC_PMAC
3514         /* On UniNorth, power down the cable and turn off the chip
3515          * clock when the module is removed to save power on
3516          * laptops. Turning it back ON is done by the arch code when
3517          * pci_enable_device() is called */
3518         {
3519                 struct device_node* of_node;
3520
3521                 of_node = pci_device_to_OF_node(ohci->dev);
3522                 if (of_node) {
3523                         pmac_call_feature(PMAC_FTR_1394_ENABLE, of_node, 0, 0);
3524                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, of_node, 0, 0);
3525                 }
3526         }
3527 #endif /* CONFIG_PPC_PMAC */
3528
3529         case OHCI_INIT_ALLOC_HOST:
3530                 pci_set_drvdata(ohci->dev, NULL);
3531         }
3532
3533         if (dev)
3534                 put_device(dev);
3535 }
3536
3537
3538 static int ohci1394_pci_resume (struct pci_dev *pdev)
3539 {
3540 #ifdef CONFIG_PPC_PMAC
3541         if (_machine == _MACH_Pmac) {
3542                 struct device_node *of_node;
3543
3544                 /* Re-enable 1394 */
3545                 of_node = pci_device_to_OF_node (pdev);
3546                 if (of_node)
3547                         pmac_call_feature (PMAC_FTR_1394_ENABLE, of_node, 0, 1);
3548         }
3549 #endif /* CONFIG_PPC_PMAC */
3550
3551         pci_enable_device(pdev);
3552
3553         return 0;
3554 }
3555
3556
3557 static int ohci1394_pci_suspend (struct pci_dev *pdev, pm_message_t state)
3558 {
3559 #ifdef CONFIG_PPC_PMAC
3560         if (_machine == _MACH_Pmac) {
3561                 struct device_node *of_node;
3562
3563                 /* Disable 1394 */
3564                 of_node = pci_device_to_OF_node (pdev);
3565                 if (of_node)
3566                         pmac_call_feature(PMAC_FTR_1394_ENABLE, of_node, 0, 0);
3567         }
3568 #endif
3569
3570         return 0;
3571 }
3572
3573
3574 #define PCI_CLASS_FIREWIRE_OHCI     ((PCI_CLASS_SERIAL_FIREWIRE << 8) | 0x10)
3575
3576 static struct pci_device_id ohci1394_pci_tbl[] = {
3577         {
3578                 .class =        PCI_CLASS_FIREWIRE_OHCI,
3579                 .class_mask =   PCI_ANY_ID,
3580                 .vendor =       PCI_ANY_ID,
3581                 .device =       PCI_ANY_ID,
3582                 .subvendor =    PCI_ANY_ID,
3583                 .subdevice =    PCI_ANY_ID,
3584         },
3585         { 0, },
3586 };
3587
3588 MODULE_DEVICE_TABLE(pci, ohci1394_pci_tbl);
3589
3590 static struct pci_driver ohci1394_pci_driver = {
3591         .name =         OHCI1394_DRIVER_NAME,
3592         .id_table =     ohci1394_pci_tbl,
3593         .probe =        ohci1394_pci_probe,
3594         .remove =       ohci1394_pci_remove,
3595         .resume =       ohci1394_pci_resume,
3596         .suspend =      ohci1394_pci_suspend,
3597 };
3598
3599 /***********************************
3600  * OHCI1394 Video Interface        *
3601  ***********************************/
3602
3603 /* essentially the only purpose of this code is to allow another
3604    module to hook into ohci's interrupt handler */
3605
3606 int ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg)
3607 {
3608         int i=0;
3609
3610         /* stop the channel program if it's still running */
3611         reg_write(ohci, reg, 0x8000);
3612
3613         /* Wait until it effectively stops */
3614         while (reg_read(ohci, reg) & 0x400) {
3615                 i++;
3616                 if (i>5000) {
3617                         PRINT(KERN_ERR,
3618                               "Runaway loop while stopping context: %s...", msg ? msg : "");
3619                         return 1;
3620                 }
3621
3622                 mb();
3623                 udelay(10);
3624         }
3625         if (msg) PRINT(KERN_ERR, "%s: dma prg stopped", msg);
3626         return 0;
3627 }
3628
3629 void ohci1394_init_iso_tasklet(struct ohci1394_iso_tasklet *tasklet, int type,
3630                                void (*func)(unsigned long), unsigned long data)
3631 {
3632         tasklet_init(&tasklet->tasklet, func, data);
3633         tasklet->type = type;
3634         /* We init the tasklet->link field, so we can list_del() it
3635          * without worrying whether it was added to the list or not. */
3636         INIT_LIST_HEAD(&tasklet->link);
3637 }
3638
3639 int ohci1394_register_iso_tasklet(struct ti_ohci *ohci,
3640                                   struct ohci1394_iso_tasklet *tasklet)
3641 {
3642         unsigned long flags, *usage;
3643         int n, i, r = -EBUSY;
3644
3645         if (tasklet->type == OHCI_ISO_TRANSMIT) {
3646                 n = ohci->nb_iso_xmit_ctx;
3647                 usage = &ohci->it_ctx_usage;
3648         }
3649         else {
3650                 n = ohci->nb_iso_rcv_ctx;
3651                 usage = &ohci->ir_ctx_usage;
3652
3653                 /* only one receive context can be multichannel (OHCI sec 10.4.1) */
3654                 if (tasklet->type == OHCI_ISO_MULTICHANNEL_RECEIVE) {
3655                         if (test_and_set_bit(0, &ohci->ir_multichannel_used)) {
3656                                 return r;
3657                         }
3658                 }
3659         }
3660
3661         spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
3662
3663         for (i = 0; i < n; i++)
3664                 if (!test_and_set_bit(i, usage)) {
3665                         tasklet->context = i;
3666                         list_add_tail(&tasklet->link, &ohci->iso_tasklet_list);
3667                         r = 0;
3668                         break;
3669                 }
3670
3671         spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);
3672
3673         return r;
3674 }
3675
3676 void ohci1394_unregister_iso_tasklet(struct ti_ohci *ohci,
3677                                      struct ohci1394_iso_tasklet *tasklet)
3678 {
3679         unsigned long flags;
3680
3681         tasklet_kill(&tasklet->tasklet);
3682
3683         spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
3684
3685         if (tasklet->type == OHCI_ISO_TRANSMIT)
3686                 clear_bit(tasklet->context, &ohci->it_ctx_usage);
3687         else {
3688                 clear_bit(tasklet->context, &ohci->ir_ctx_usage);
3689
3690                 if (tasklet->type == OHCI_ISO_MULTICHANNEL_RECEIVE) {
3691                         clear_bit(0, &ohci->ir_multichannel_used);
3692                 }
3693         }
3694
3695         list_del(&tasklet->link);
3696
3697         spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);
3698 }
3699
3700 EXPORT_SYMBOL(ohci1394_stop_context);
3701 EXPORT_SYMBOL(ohci1394_init_iso_tasklet);
3702 EXPORT_SYMBOL(ohci1394_register_iso_tasklet);
3703 EXPORT_SYMBOL(ohci1394_unregister_iso_tasklet);
3704
3705 /***********************************
3706  * General module initialization   *
3707  ***********************************/
3708
3709 MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
3710 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE-1394 controllers");
3711 MODULE_LICENSE("GPL");
3712
3713 static void __exit ohci1394_cleanup (void)
3714 {
3715         pci_unregister_driver(&ohci1394_pci_driver);
3716 }
3717
3718 static int __init ohci1394_init(void)
3719 {
3720         return pci_register_driver(&ohci1394_pci_driver);
3721 }
3722
3723 module_init(ohci1394_init);
3724 module_exit(ohci1394_cleanup);