3838bc4acabac07b01b2c7b2488d07d825aa28ae
[linux-2.6.git] / drivers / ieee1394 / dv1394.c
1 /*
2  * dv1394.c - DV input/output over IEEE 1394 on OHCI chips
3  *   Copyright (C)2001 Daniel Maas <dmaas@dcine.com>
4  *     receive by Dan Dennedy <dan@dennedy.org>
5  *
6  * based on:
7  *  video1394.c - video driver for OHCI 1394 boards
8  *  Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software Foundation,
22  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23  */
24
25 /*
26   OVERVIEW
27
28   I designed dv1394 as a "pipe" that you can use to shoot DV onto a
29   FireWire bus. In transmission mode, dv1394 does the following:
30
31    1. accepts contiguous frames of DV data from user-space, via write()
32       or mmap() (see dv1394.h for the complete API)
33    2. wraps IEC 61883 packets around the DV data, inserting
34       empty synchronization packets as necessary
35    3. assigns accurate SYT timestamps to the outgoing packets
36    4. shoots them out using the OHCI card's IT DMA engine
37
38    Thanks to Dan Dennedy, we now have a receive mode that does the following:
39
40    1. accepts raw IEC 61883 packets from the OHCI card
41    2. re-assembles the DV data payloads into contiguous frames,
42       discarding empty packets
43    3. sends the DV data to user-space via read() or mmap()
44 */
45
46 /*
47   TODO:
48
49   - tunable frame-drop behavior: either loop last frame, or halt transmission
50
51   - use a scatter/gather buffer for DMA programs (f->descriptor_pool)
52     so that we don't rely on allocating 64KB of contiguous kernel memory
53     via pci_alloc_consistent()
54
55   DONE:
56   - during reception, better handling of dropped frames and continuity errors
57   - during reception, prevent DMA from bypassing the irq tasklets
58   - reduce irq rate during reception (1/250 packets).
59   - add many more internal buffers during reception with scatter/gather dma.
60   - add dbc (continuity) checking on receive, increment status.dropped_frames
61     if not continuous.
62   - restart IT DMA after a bus reset
63   - safely obtain and release ISO Tx channels in cooperation with OHCI driver
64   - map received DIF blocks to their proper location in DV frame (ensure
65     recovery if dropped packet)
66   - handle bus resets gracefully (OHCI card seems to take care of this itself(!))
67   - do not allow resizing the user_buf once allocated; eliminate nuke_buffer_mappings
68   - eliminated #ifdef DV1394_DEBUG_LEVEL by inventing macros debug_printk and irq_printk
69   - added wmb() and mb() to places where PCI read/write ordering needs to be enforced
70   - set video->id correctly
71   - store video_cards in an array indexed by OHCI card ID, rather than a list
72   - implement DMA context allocation to cooperate with other users of the OHCI
73   - fix all XXX showstoppers
74   - disable IR/IT DMA interrupts on shutdown
75   - flush pci writes to the card by issuing a read
76   - character device dispatching
77   - switch over to the new kernel DMA API (pci_map_*()) (* needs testing on platforms with IOMMU!)
78   - keep all video_cards in a list (for open() via chardev), set file->private_data = video
79   - dv1394_poll should indicate POLLIN when receiving buffers are available
80   - add proc fs interface to set cip_n, cip_d, syt_offset, and video signal
81   - expose xmit and recv as separate devices (not exclusive)
82   - expose NTSC and PAL as separate devices (can be overridden)
83
84 */
85
86 #include <linux/kernel.h>
87 #include <linux/list.h>
88 #include <linux/slab.h>
89 #include <linux/interrupt.h>
90 #include <linux/wait.h>
91 #include <linux/errno.h>
92 #include <linux/module.h>
93 #include <linux/init.h>
94 #include <linux/pci.h>
95 #include <linux/fs.h>
96 #include <linux/poll.h>
97 #include <linux/mutex.h>
98 #include <linux/bitops.h>
99 #include <asm/byteorder.h>
100 #include <asm/atomic.h>
101 #include <asm/io.h>
102 #include <asm/uaccess.h>
103 #include <linux/delay.h>
104 #include <asm/pgtable.h>
105 #include <asm/page.h>
106 #include <linux/sched.h>
107 #include <linux/types.h>
108 #include <linux/vmalloc.h>
109 #include <linux/string.h>
110 #include <linux/compat.h>
111 #include <linux/cdev.h>
112
113 #include "dv1394.h"
114 #include "dv1394-private.h"
115 #include "highlevel.h"
116 #include "hosts.h"
117 #include "ieee1394.h"
118 #include "ieee1394_core.h"
119 #include "ieee1394_hotplug.h"
120 #include "ieee1394_types.h"
121 #include "nodemgr.h"
122 #include "ohci1394.h"
123
124 /* DEBUG LEVELS:
125    0 - no debugging messages
126    1 - some debugging messages, but none during DMA frame transmission
127    2 - lots of messages, including during DMA frame transmission
128        (will cause undeflows if your machine is too slow!)
129 */
130
131 #define DV1394_DEBUG_LEVEL 0
132
133 /* for debugging use ONLY: allow more than one open() of the device */
134 /* #define DV1394_ALLOW_MORE_THAN_ONE_OPEN 1 */
135
136 #if DV1394_DEBUG_LEVEL >= 2
137 #define irq_printk( args... ) printk( args )
138 #else
139 #define irq_printk( args... ) do {} while (0)
140 #endif
141
142 #if DV1394_DEBUG_LEVEL >= 1
143 #define debug_printk( args... ) printk( args)
144 #else
145 #define debug_printk( args... ) do {} while (0)
146 #endif
147
148 /* issue a dummy PCI read to force the preceding write
149    to be posted to the PCI bus immediately */
150
151 static inline void flush_pci_write(struct ti_ohci *ohci)
152 {
153         mb();
154         reg_read(ohci, OHCI1394_IsochronousCycleTimer);
155 }
156
157 static void it_tasklet_func(unsigned long data);
158 static void ir_tasklet_func(unsigned long data);
159
160 #ifdef CONFIG_COMPAT
161 static long dv1394_compat_ioctl(struct file *file, unsigned int cmd,
162                                unsigned long arg);
163 #endif
164
165 /* GLOBAL DATA */
166
167 /* list of all video_cards */
168 static LIST_HEAD(dv1394_cards);
169 static DEFINE_SPINLOCK(dv1394_cards_lock);
170
171 /* translate from a struct file* to the corresponding struct video_card* */
172
173 static inline struct video_card* file_to_video_card(struct file *file)
174 {
175         return (struct video_card*) file->private_data;
176 }
177
178 /*** FRAME METHODS *********************************************************/
179
180 static void frame_reset(struct frame *f)
181 {
182         f->state = FRAME_CLEAR;
183         f->done = 0;
184         f->n_packets = 0;
185         f->frame_begin_timestamp = NULL;
186         f->assigned_timestamp = 0;
187         f->cip_syt1 = NULL;
188         f->cip_syt2 = NULL;
189         f->mid_frame_timestamp = NULL;
190         f->frame_end_timestamp = NULL;
191         f->frame_end_branch = NULL;
192 }
193
194 static struct frame* frame_new(unsigned int frame_num, struct video_card *video)
195 {
196         struct frame *f = kmalloc(sizeof(*f), GFP_KERNEL);
197         if (!f)
198                 return NULL;
199
200         f->video = video;
201         f->frame_num = frame_num;
202
203         f->header_pool = pci_alloc_consistent(f->video->ohci->dev, PAGE_SIZE, &f->header_pool_dma);
204         if (!f->header_pool) {
205                 printk(KERN_ERR "dv1394: failed to allocate CIP header pool\n");
206                 kfree(f);
207                 return NULL;
208         }
209
210         debug_printk("dv1394: frame_new: allocated CIP header pool at virt 0x%08lx (contig) dma 0x%08lx size %ld\n",
211                      (unsigned long) f->header_pool, (unsigned long) f->header_pool_dma, PAGE_SIZE);
212
213         f->descriptor_pool_size = MAX_PACKETS * sizeof(struct DMA_descriptor_block);
214         /* make it an even # of pages */
215         f->descriptor_pool_size += PAGE_SIZE - (f->descriptor_pool_size%PAGE_SIZE);
216
217         f->descriptor_pool = pci_alloc_consistent(f->video->ohci->dev,
218                                                   f->descriptor_pool_size,
219                                                   &f->descriptor_pool_dma);
220         if (!f->descriptor_pool) {
221                 pci_free_consistent(f->video->ohci->dev, PAGE_SIZE, f->header_pool, f->header_pool_dma);
222                 kfree(f);
223                 return NULL;
224         }
225
226         debug_printk("dv1394: frame_new: allocated DMA program memory at virt 0x%08lx (contig) dma 0x%08lx size %ld\n",
227                      (unsigned long) f->descriptor_pool, (unsigned long) f->descriptor_pool_dma, f->descriptor_pool_size);
228
229         f->data = 0;
230         frame_reset(f);
231
232         return f;
233 }
234
235 static void frame_delete(struct frame *f)
236 {
237         pci_free_consistent(f->video->ohci->dev, PAGE_SIZE, f->header_pool, f->header_pool_dma);
238         pci_free_consistent(f->video->ohci->dev, f->descriptor_pool_size, f->descriptor_pool, f->descriptor_pool_dma);
239         kfree(f);
240 }
241
242
243
244
245 /*
246    frame_prepare() - build the DMA program for transmitting
247
248    Frame_prepare() must be called OUTSIDE the video->spinlock.
249    However, frame_prepare() must still be serialized, so
250    it should be called WITH the video->mtx taken.
251  */
252
253 static void frame_prepare(struct video_card *video, unsigned int this_frame)
254 {
255         struct frame *f = video->frames[this_frame];
256         int last_frame;
257
258         struct DMA_descriptor_block *block;
259         dma_addr_t block_dma;
260         struct CIP_header *cip;
261         dma_addr_t cip_dma;
262
263         unsigned int n_descriptors, full_packets, packets_per_frame, payload_size;
264
265         /* these flags denote packets that need special attention */
266         int empty_packet, first_packet, last_packet, mid_packet;
267
268         __le32 *branch_address, *last_branch_address = NULL;
269         unsigned long data_p;
270         int first_packet_empty = 0;
271         u32 cycleTimer, ct_sec, ct_cyc, ct_off;
272         unsigned long irq_flags;
273
274         irq_printk("frame_prepare( %d ) ---------------------\n", this_frame);
275
276         full_packets = 0;
277
278
279
280         if (video->pal_or_ntsc == DV1394_PAL)
281                 packets_per_frame = DV1394_PAL_PACKETS_PER_FRAME;
282         else
283                 packets_per_frame = DV1394_NTSC_PACKETS_PER_FRAME;
284
285         while ( full_packets < packets_per_frame ) {
286                 empty_packet = first_packet = last_packet = mid_packet = 0;
287
288                 data_p = f->data + full_packets * 480;
289
290                 /************************************************/
291                 /* allocate a descriptor block and a CIP header */
292                 /************************************************/
293
294                 /* note: these should NOT cross a page boundary (DMA restriction) */
295
296                 if (f->n_packets >= MAX_PACKETS) {
297                         printk(KERN_ERR "dv1394: FATAL ERROR: max packet count exceeded\n");
298                         return;
299                 }
300
301                 /* the block surely won't cross a page boundary,
302                    since an even number of descriptor_blocks fit on a page */
303                 block = &(f->descriptor_pool[f->n_packets]);
304
305                 /* DMA address of the block = offset of block relative
306                     to the kernel base address of the descriptor pool
307                     + DMA base address of the descriptor pool */
308                 block_dma = ((unsigned long) block - (unsigned long) f->descriptor_pool) + f->descriptor_pool_dma;
309
310
311                 /* the whole CIP pool fits on one page, so no worries about boundaries */
312                 if ( ((unsigned long) &(f->header_pool[f->n_packets]) - (unsigned long) f->header_pool)
313                     > PAGE_SIZE) {
314                         printk(KERN_ERR "dv1394: FATAL ERROR: no room to allocate CIP header\n");
315                         return;
316                 }
317
318                 cip = &(f->header_pool[f->n_packets]);
319
320                 /* DMA address of the CIP header = offset of cip
321                    relative to kernel base address of the header pool
322                    + DMA base address of the header pool */
323                 cip_dma = (unsigned long) cip % PAGE_SIZE + f->header_pool_dma;
324
325                 /* is this an empty packet? */
326
327                 if (video->cip_accum > (video->cip_d - video->cip_n)) {
328                         empty_packet = 1;
329                         payload_size = 8;
330                         video->cip_accum -= (video->cip_d - video->cip_n);
331                 } else {
332                         payload_size = 488;
333                         video->cip_accum += video->cip_n;
334                 }
335
336                 /* there are three important packets each frame:
337
338                    the first packet in the frame - we ask the card to record the timestamp when
339                                                    this packet is actually sent, so we can monitor
340                                                    how accurate our timestamps are. Also, the first
341                                                    packet serves as a semaphore to let us know that
342                                                    it's OK to free the *previous* frame's DMA buffer
343
344                    the last packet in the frame -  this packet is used to detect buffer underflows.
345                                                    if this is the last ready frame, the last DMA block
346                                                    will have a branch back to the beginning of the frame
347                                                    (so that the card will re-send the frame on underflow).
348                                                    if this branch gets taken, we know that at least one
349                                                    frame has been dropped. When the next frame is ready,
350                                                    the branch is pointed to its first packet, and the
351                                                    semaphore is disabled.
352
353                    a "mid" packet slightly before the end of the frame - this packet should trigger
354                                    an interrupt so we can go and assign a timestamp to the first packet
355                                    in the next frame. We don't use the very last packet in the frame
356                                    for this purpose, because that would leave very little time to set
357                                    the timestamp before DMA starts on the next frame.
358                 */
359
360                 if (f->n_packets == 0) {
361                         first_packet = 1;
362                 } else if ( full_packets == (packets_per_frame-1) ) {
363                         last_packet = 1;
364                 } else if (f->n_packets == packets_per_frame) {
365                         mid_packet = 1;
366                 }
367
368
369                 /********************/
370                 /* setup CIP header */
371                 /********************/
372
373                 /* the timestamp will be written later from the
374                    mid-frame interrupt handler. For now we just
375                    store the address of the CIP header(s) that
376                    need a timestamp. */
377
378                 /* first packet in the frame needs a timestamp */
379                 if (first_packet) {
380                         f->cip_syt1 = cip;
381                         if (empty_packet)
382                                 first_packet_empty = 1;
383
384                 } else if (first_packet_empty && (f->n_packets == 1) ) {
385                         /* if the first packet was empty, the second
386                            packet's CIP header also needs a timestamp */
387                         f->cip_syt2 = cip;
388                 }
389
390                 fill_cip_header(cip,
391                                 /* the node ID number of the OHCI card */
392                                 reg_read(video->ohci, OHCI1394_NodeID) & 0x3F,
393                                 video->continuity_counter,
394                                 video->pal_or_ntsc,
395                                 0xFFFF /* the timestamp is filled in later */);
396
397                 /* advance counter, only for full packets */
398                 if ( ! empty_packet )
399                         video->continuity_counter++;
400
401                 /******************************/
402                 /* setup DMA descriptor block */
403                 /******************************/
404
405                 /* first descriptor - OUTPUT_MORE_IMMEDIATE, for the controller's IT header */
406                 fill_output_more_immediate( &(block->u.out.omi), 1, video->channel, 0, payload_size);
407
408                 if (empty_packet) {
409                         /* second descriptor - OUTPUT_LAST for CIP header */
410                         fill_output_last( &(block->u.out.u.empty.ol),
411
412                                           /* want completion status on all interesting packets */
413                                           (first_packet || mid_packet || last_packet) ? 1 : 0,
414
415                                           /* want interrupts on all interesting packets */
416                                           (first_packet || mid_packet || last_packet) ? 1 : 0,
417
418                                           sizeof(struct CIP_header), /* data size */
419                                           cip_dma);
420
421                         if (first_packet)
422                                 f->frame_begin_timestamp = &(block->u.out.u.empty.ol.q[3]);
423                         else if (mid_packet)
424                                 f->mid_frame_timestamp = &(block->u.out.u.empty.ol.q[3]);
425                         else if (last_packet) {
426                                 f->frame_end_timestamp = &(block->u.out.u.empty.ol.q[3]);
427                                 f->frame_end_branch = &(block->u.out.u.empty.ol.q[2]);
428                         }
429
430                         branch_address = &(block->u.out.u.empty.ol.q[2]);
431                         n_descriptors = 3;
432                         if (first_packet)
433                                 f->first_n_descriptors = n_descriptors;
434
435                 } else { /* full packet */
436
437                         /* second descriptor - OUTPUT_MORE for CIP header */
438                         fill_output_more( &(block->u.out.u.full.om),
439                                           sizeof(struct CIP_header), /* data size */
440                                           cip_dma);
441
442
443                         /* third (and possibly fourth) descriptor - for DV data */
444                         /* the 480-byte payload can cross a page boundary; if so,
445                            we need to split it into two DMA descriptors */
446
447                         /* does the 480-byte data payload cross a page boundary? */
448                         if ( (PAGE_SIZE- ((unsigned long)data_p % PAGE_SIZE) ) < 480 ) {
449
450                                 /* page boundary crossed */
451
452                                 fill_output_more( &(block->u.out.u.full.u.cross.om),
453                                                   /* data size - how much of data_p fits on the first page */
454                                                   PAGE_SIZE - (data_p % PAGE_SIZE),
455
456                                                   /* DMA address of data_p */
457                                                   dma_region_offset_to_bus(&video->dv_buf,
458                                                                            data_p - (unsigned long) video->dv_buf.kvirt));
459
460                                 fill_output_last( &(block->u.out.u.full.u.cross.ol),
461
462                                                   /* want completion status on all interesting packets */
463                                                   (first_packet || mid_packet || last_packet) ? 1 : 0,
464
465                                                   /* want interrupt on all interesting packets */
466                                                   (first_packet || mid_packet || last_packet) ? 1 : 0,
467
468                                                   /* data size - remaining portion of data_p */
469                                                   480 - (PAGE_SIZE - (data_p % PAGE_SIZE)),
470
471                                                   /* DMA address of data_p + PAGE_SIZE - (data_p % PAGE_SIZE) */
472                                                   dma_region_offset_to_bus(&video->dv_buf,
473                                                                            data_p + PAGE_SIZE - (data_p % PAGE_SIZE) - (unsigned long) video->dv_buf.kvirt));
474
475                                 if (first_packet)
476                                         f->frame_begin_timestamp = &(block->u.out.u.full.u.cross.ol.q[3]);
477                                 else if (mid_packet)
478                                         f->mid_frame_timestamp = &(block->u.out.u.full.u.cross.ol.q[3]);
479                                 else if (last_packet) {
480                                         f->frame_end_timestamp = &(block->u.out.u.full.u.cross.ol.q[3]);
481                                         f->frame_end_branch = &(block->u.out.u.full.u.cross.ol.q[2]);
482                                 }
483
484                                 branch_address = &(block->u.out.u.full.u.cross.ol.q[2]);
485
486                                 n_descriptors = 5;
487                                 if (first_packet)
488                                         f->first_n_descriptors = n_descriptors;
489
490                                 full_packets++;
491
492                         } else {
493                                 /* fits on one page */
494
495                                 fill_output_last( &(block->u.out.u.full.u.nocross.ol),
496
497                                                   /* want completion status on all interesting packets */
498                                                   (first_packet || mid_packet || last_packet) ? 1 : 0,
499
500                                                   /* want interrupt on all interesting packets */
501                                                   (first_packet || mid_packet || last_packet) ? 1 : 0,
502
503                                                   480, /* data size (480 bytes of DV data) */
504
505
506                                                   /* DMA address of data_p */
507                                                   dma_region_offset_to_bus(&video->dv_buf,
508                                                                            data_p - (unsigned long) video->dv_buf.kvirt));
509
510                                 if (first_packet)
511                                         f->frame_begin_timestamp = &(block->u.out.u.full.u.nocross.ol.q[3]);
512                                 else if (mid_packet)
513                                         f->mid_frame_timestamp = &(block->u.out.u.full.u.nocross.ol.q[3]);
514                                 else if (last_packet) {
515                                         f->frame_end_timestamp = &(block->u.out.u.full.u.nocross.ol.q[3]);
516                                         f->frame_end_branch = &(block->u.out.u.full.u.nocross.ol.q[2]);
517                                 }
518
519                                 branch_address = &(block->u.out.u.full.u.nocross.ol.q[2]);
520
521                                 n_descriptors = 4;
522                                 if (first_packet)
523                                         f->first_n_descriptors = n_descriptors;
524
525                                 full_packets++;
526                         }
527                 }
528
529                 /* link this descriptor block into the DMA program by filling in
530                    the branch address of the previous block */
531
532                 /* note: we are not linked into the active DMA chain yet */
533
534                 if (last_branch_address) {
535                         *(last_branch_address) = cpu_to_le32(block_dma | n_descriptors);
536                 }
537
538                 last_branch_address = branch_address;
539
540
541                 f->n_packets++;
542
543         }
544
545         /* when we first assemble a new frame, set the final branch
546            to loop back up to the top */
547         *(f->frame_end_branch) = cpu_to_le32(f->descriptor_pool_dma | f->first_n_descriptors);
548
549         /* make the latest version of this frame visible to the PCI card */
550         dma_region_sync_for_device(&video->dv_buf, f->data - (unsigned long) video->dv_buf.kvirt, video->frame_size);
551
552         /* lock against DMA interrupt */
553         spin_lock_irqsave(&video->spinlock, irq_flags);
554
555         f->state = FRAME_READY;
556
557         video->n_clear_frames--;
558
559         last_frame = video->first_clear_frame - 1;
560         if (last_frame == -1)
561                 last_frame = video->n_frames-1;
562
563         video->first_clear_frame = (video->first_clear_frame + 1) % video->n_frames;
564
565         irq_printk("   frame %d prepared, active_frame = %d, n_clear_frames = %d, first_clear_frame = %d\n last=%d\n",
566                    this_frame, video->active_frame, video->n_clear_frames, video->first_clear_frame, last_frame);
567
568         irq_printk("   begin_ts %08lx mid_ts %08lx end_ts %08lx end_br %08lx\n",
569                    (unsigned long) f->frame_begin_timestamp,
570                    (unsigned long) f->mid_frame_timestamp,
571                    (unsigned long) f->frame_end_timestamp,
572                    (unsigned long) f->frame_end_branch);
573
574         if (video->active_frame != -1) {
575
576                 /* if DMA is already active, we are almost done */
577                 /* just link us onto the active DMA chain */
578                 if (video->frames[last_frame]->frame_end_branch) {
579                         u32 temp;
580
581                         /* point the previous frame's tail to this frame's head */
582                         *(video->frames[last_frame]->frame_end_branch) = cpu_to_le32(f->descriptor_pool_dma | f->first_n_descriptors);
583
584                         /* this write MUST precede the next one, or we could silently drop frames */
585                         wmb();
586
587                         /* disable the want_status semaphore on the last packet */
588                         temp = le32_to_cpu(*(video->frames[last_frame]->frame_end_branch - 2));
589                         temp &= 0xF7CFFFFF;
590                         *(video->frames[last_frame]->frame_end_branch - 2) = cpu_to_le32(temp);
591
592                         /* flush these writes to memory ASAP */
593                         flush_pci_write(video->ohci);
594
595                         /* NOTE:
596                            ideally the writes should be "atomic": if
597                            the OHCI card reads the want_status flag in
598                            between them, we'll falsely report a
599                            dropped frame. Hopefully this window is too
600                            small to really matter, and the consequence
601                            is rather harmless. */
602
603
604                         irq_printk("     new frame %d linked onto DMA chain\n", this_frame);
605
606                 } else {
607                         printk(KERN_ERR "dv1394: last frame not ready???\n");
608                 }
609
610         } else {
611
612                 u32 transmit_sec, transmit_cyc;
613                 u32 ts_cyc, ts_off;
614
615                 /* DMA is stopped, so this is the very first frame */
616                 video->active_frame = this_frame;
617
618                 /* set CommandPtr to address and size of first descriptor block */
619                 reg_write(video->ohci, video->ohci_IsoXmitCommandPtr,
620                           video->frames[video->active_frame]->descriptor_pool_dma |
621                           f->first_n_descriptors);
622
623                 /* assign a timestamp based on the current cycle time...
624                    We'll tell the card to begin DMA 100 cycles from now,
625                    and assign a timestamp 103 cycles from now */
626
627                 cycleTimer = reg_read(video->ohci, OHCI1394_IsochronousCycleTimer);
628
629                 ct_sec = cycleTimer >> 25;
630                 ct_cyc = (cycleTimer >> 12) & 0x1FFF;
631                 ct_off = cycleTimer & 0xFFF;
632
633                 transmit_sec = ct_sec;
634                 transmit_cyc = ct_cyc + 100;
635
636                 transmit_sec += transmit_cyc/8000;
637                 transmit_cyc %= 8000;
638
639                 ts_off = ct_off;
640                 ts_cyc = transmit_cyc + 3;
641                 ts_cyc %= 8000;
642
643                 f->assigned_timestamp = (ts_cyc&0xF) << 12;
644
645                 /* now actually write the timestamp into the appropriate CIP headers */
646                 if (f->cip_syt1) {
647                         f->cip_syt1->b[6] = f->assigned_timestamp >> 8;
648                         f->cip_syt1->b[7] = f->assigned_timestamp & 0xFF;
649                 }
650                 if (f->cip_syt2) {
651                         f->cip_syt2->b[6] = f->assigned_timestamp >> 8;
652                         f->cip_syt2->b[7] = f->assigned_timestamp & 0xFF;
653                 }
654
655                 /* --- start DMA --- */
656
657                 /* clear all bits in ContextControl register */
658
659                 reg_write(video->ohci, video->ohci_IsoXmitContextControlClear, 0xFFFFFFFF);
660                 wmb();
661
662                 /* the OHCI card has the ability to start ISO transmission on a
663                    particular cycle (start-on-cycle). This way we can ensure that
664                    the first DV frame will have an accurate timestamp.
665
666                    However, start-on-cycle only appears to work if the OHCI card
667                    is cycle master! Since the consequences of messing up the first
668                    timestamp are minimal*, just disable start-on-cycle for now.
669
670                    * my DV deck drops the first few frames before it "locks in;"
671                      so the first frame having an incorrect timestamp is inconsequential.
672                 */
673
674 #if 0
675                 reg_write(video->ohci, video->ohci_IsoXmitContextControlSet,
676                           (1 << 31) /* enable start-on-cycle */
677                           | ( (transmit_sec & 0x3) << 29)
678                           | (transmit_cyc << 16));
679                 wmb();
680 #endif
681
682                 video->dma_running = 1;
683
684                 /* set the 'run' bit */
685                 reg_write(video->ohci, video->ohci_IsoXmitContextControlSet, 0x8000);
686                 flush_pci_write(video->ohci);
687
688                 /* --- DMA should be running now --- */
689
690                 debug_printk("    Cycle = %4u ContextControl = %08x CmdPtr = %08x\n",
691                              (reg_read(video->ohci, OHCI1394_IsochronousCycleTimer) >> 12) & 0x1FFF,
692                              reg_read(video->ohci, video->ohci_IsoXmitContextControlSet),
693                              reg_read(video->ohci, video->ohci_IsoXmitCommandPtr));
694
695                 debug_printk("    DMA start - current cycle %4u, transmit cycle %4u (%2u), assigning ts cycle %2u\n",
696                              ct_cyc, transmit_cyc, transmit_cyc & 0xF, ts_cyc & 0xF);
697
698 #if DV1394_DEBUG_LEVEL >= 2
699                 {
700                         /* check if DMA is really running */
701                         int i = 0;
702                         while (i < 20) {
703                                 mb();
704                                 mdelay(1);
705                                 if (reg_read(video->ohci, video->ohci_IsoXmitContextControlSet) & (1 << 10)) {
706                                         printk("DMA ACTIVE after %d msec\n", i);
707                                         break;
708                                 }
709                                 i++;
710                         }
711
712                         printk("set = %08x, cmdPtr = %08x\n",
713                                reg_read(video->ohci, video->ohci_IsoXmitContextControlSet),
714                                reg_read(video->ohci, video->ohci_IsoXmitCommandPtr)
715                                );
716
717                         if ( ! (reg_read(video->ohci, video->ohci_IsoXmitContextControlSet) &  (1 << 10)) ) {
718                                 printk("DMA did NOT go active after 20ms, event = %x\n",
719                                        reg_read(video->ohci, video->ohci_IsoXmitContextControlSet) & 0x1F);
720                         } else
721                                 printk("DMA is RUNNING!\n");
722                 }
723 #endif
724
725         }
726
727
728         spin_unlock_irqrestore(&video->spinlock, irq_flags);
729 }
730
731
732
733 /*** RECEIVE FUNCTIONS *****************************************************/
734
735 /*
736         frame method put_packet
737
738         map and copy the packet data to its location in the frame
739         based upon DIF section and sequence
740 */
741
742 static void inline
743 frame_put_packet (struct frame *f, struct packet *p)
744 {
745         int section_type = p->data[0] >> 5;           /* section type is in bits 5 - 7 */
746         int dif_sequence = p->data[1] >> 4;           /* dif sequence number is in bits 4 - 7 */
747         int dif_block = p->data[2];
748
749         /* sanity check */
750         if (dif_sequence > 11 || dif_block > 149) return;
751
752         switch (section_type) {
753         case 0:           /* 1 Header block */
754                 memcpy( (void *) f->data + dif_sequence * 150 * 80, p->data, 480);
755                 break;
756
757         case 1:           /* 2 Subcode blocks */
758                 memcpy( (void *) f->data + dif_sequence * 150 * 80 + (1 + dif_block) * 80, p->data, 480);
759                 break;
760
761         case 2:           /* 3 VAUX blocks */
762                 memcpy( (void *) f->data + dif_sequence * 150 * 80 + (3 + dif_block) * 80, p->data, 480);
763                 break;
764
765         case 3:           /* 9 Audio blocks interleaved with video */
766                 memcpy( (void *) f->data + dif_sequence * 150 * 80 + (6 + dif_block * 16) * 80, p->data, 480);
767                 break;
768
769         case 4:           /* 135 Video blocks interleaved with audio */
770                 memcpy( (void *) f->data + dif_sequence * 150 * 80 + (7 + (dif_block / 15) + dif_block) * 80, p->data, 480);
771                 break;
772
773         default:           /* we can not handle any other data */
774                 break;
775         }
776 }
777
778
779 static void start_dma_receive(struct video_card *video)
780 {
781         if (video->first_run == 1) {
782                 video->first_run = 0;
783
784                 /* start DMA once all of the frames are READY */
785                 video->n_clear_frames = 0;
786                 video->first_clear_frame = -1;
787                 video->current_packet = 0;
788                 video->active_frame = 0;
789
790                 /* reset iso recv control register */
791                 reg_write(video->ohci, video->ohci_IsoRcvContextControlClear, 0xFFFFFFFF);
792                 wmb();
793
794                 /* clear bufferFill, set isochHeader and speed (0=100) */
795                 reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, 0x40000000);
796
797                 /* match on all tags, listen on channel */
798                 reg_write(video->ohci, video->ohci_IsoRcvContextMatch, 0xf0000000 | video->channel);
799
800                 /* address and first descriptor block + Z=1 */
801                 reg_write(video->ohci, video->ohci_IsoRcvCommandPtr,
802                           video->frames[0]->descriptor_pool_dma | 1); /* Z=1 */
803                 wmb();
804
805                 video->dma_running = 1;
806
807                 /* run */
808                 reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, 0x8000);
809                 flush_pci_write(video->ohci);
810
811                 debug_printk("dv1394: DMA started\n");
812
813 #if DV1394_DEBUG_LEVEL >= 2
814                 {
815                         int i;
816
817                         for (i = 0; i < 1000; ++i) {
818                                 mdelay(1);
819                                 if (reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) & (1 << 10)) {
820                                         printk("DMA ACTIVE after %d msec\n", i);
821                                         break;
822                                 }
823                         }
824                         if ( reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) &  (1 << 11) ) {
825                                 printk("DEAD, event = %x\n",
826                                            reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) & 0x1F);
827                         } else
828                                 printk("RUNNING!\n");
829                 }
830 #endif
831         } else if ( reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) &  (1 << 11) ) {
832                 debug_printk("DEAD, event = %x\n",
833                              reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) & 0x1F);
834
835                 /* wake */
836                 reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, (1 << 12));
837         }
838 }
839
840
841 /*
842    receive_packets() - build the DMA program for receiving
843 */
844
845 static void receive_packets(struct video_card *video)
846 {
847         struct DMA_descriptor_block *block = NULL;
848         dma_addr_t block_dma = 0;
849         struct packet *data = NULL;
850         dma_addr_t data_dma = 0;
851         __le32 *last_branch_address = NULL;
852         unsigned long irq_flags;
853         int want_interrupt = 0;
854         struct frame *f = NULL;
855         int i, j;
856
857         spin_lock_irqsave(&video->spinlock, irq_flags);
858
859         for (j = 0; j < video->n_frames; j++) {
860
861                 /* connect frames */
862                 if (j > 0 && f != NULL && f->frame_end_branch != NULL)
863                         *(f->frame_end_branch) = cpu_to_le32(video->frames[j]->descriptor_pool_dma | 1); /* set Z=1 */
864
865                 f = video->frames[j];
866
867                 for (i = 0; i < MAX_PACKETS; i++) {
868                         /* locate a descriptor block and packet from the buffer */
869                         block = &(f->descriptor_pool[i]);
870                         block_dma = ((unsigned long) block - (unsigned long) f->descriptor_pool) + f->descriptor_pool_dma;
871
872                         data = ((struct packet*)video->packet_buf.kvirt) + f->frame_num * MAX_PACKETS + i;
873                         data_dma = dma_region_offset_to_bus( &video->packet_buf,
874                                                              ((unsigned long) data - (unsigned long) video->packet_buf.kvirt) );
875
876                         /* setup DMA descriptor block */
877                         want_interrupt = ((i % (MAX_PACKETS/2)) == 0 || i == (MAX_PACKETS-1));
878                         fill_input_last( &(block->u.in.il), want_interrupt, 512, data_dma);
879
880                         /* link descriptors */
881                         last_branch_address = f->frame_end_branch;
882
883                         if (last_branch_address != NULL)
884                                 *(last_branch_address) = cpu_to_le32(block_dma | 1); /* set Z=1 */
885
886                         f->frame_end_branch = &(block->u.in.il.q[2]);
887                 }
888
889         } /* next j */
890
891         spin_unlock_irqrestore(&video->spinlock, irq_flags);
892
893 }
894
895
896
897 /*** MANAGEMENT FUNCTIONS **************************************************/
898
899 static int do_dv1394_init(struct video_card *video, struct dv1394_init *init)
900 {
901         unsigned long flags, new_buf_size;
902         int i;
903         u64 chan_mask;
904         int retval = -EINVAL;
905
906         debug_printk("dv1394: initialising %d\n", video->id);
907         if (init->api_version != DV1394_API_VERSION)
908                 return -EINVAL;
909
910         /* first sanitize all the parameters */
911         if ( (init->n_frames < 2) || (init->n_frames > DV1394_MAX_FRAMES) )
912                 return -EINVAL;
913
914         if ( (init->format != DV1394_NTSC) && (init->format != DV1394_PAL) )
915                 return -EINVAL;
916
917         if ( (init->syt_offset == 0) || (init->syt_offset > 50) )
918                 /* default SYT offset is 3 cycles */
919                 init->syt_offset = 3;
920
921         if (init->channel > 63)
922                 init->channel = 63;
923
924         chan_mask = (u64)1 << init->channel;
925
926         /* calculate what size DMA buffer is needed */
927         if (init->format == DV1394_NTSC)
928                 new_buf_size = DV1394_NTSC_FRAME_SIZE * init->n_frames;
929         else
930                 new_buf_size = DV1394_PAL_FRAME_SIZE * init->n_frames;
931
932         /* round up to PAGE_SIZE */
933         if (new_buf_size % PAGE_SIZE) new_buf_size += PAGE_SIZE - (new_buf_size % PAGE_SIZE);
934
935         /* don't allow the user to allocate the DMA buffer more than once */
936         if (video->dv_buf.kvirt && video->dv_buf_size != new_buf_size) {
937                 printk("dv1394: re-sizing the DMA buffer is not allowed\n");
938                 return -EINVAL;
939         }
940
941         /* shutdown the card if it's currently active */
942         /* (the card should not be reset if the parameters are screwy) */
943
944         do_dv1394_shutdown(video, 0);
945
946         /* try to claim the ISO channel */
947         spin_lock_irqsave(&video->ohci->IR_channel_lock, flags);
948         if (video->ohci->ISO_channel_usage & chan_mask) {
949                 spin_unlock_irqrestore(&video->ohci->IR_channel_lock, flags);
950                 retval = -EBUSY;
951                 goto err;
952         }
953         video->ohci->ISO_channel_usage |= chan_mask;
954         spin_unlock_irqrestore(&video->ohci->IR_channel_lock, flags);
955
956         video->channel = init->channel;
957
958         /* initialize misc. fields of video */
959         video->n_frames = init->n_frames;
960         video->pal_or_ntsc = init->format;
961
962         video->cip_accum = 0;
963         video->continuity_counter = 0;
964
965         video->active_frame = -1;
966         video->first_clear_frame = 0;
967         video->n_clear_frames = video->n_frames;
968         video->dropped_frames = 0;
969
970         video->write_off = 0;
971
972         video->first_run = 1;
973         video->current_packet = -1;
974         video->first_frame = 0;
975
976         if (video->pal_or_ntsc == DV1394_NTSC) {
977                 video->cip_n = init->cip_n != 0 ? init->cip_n : CIP_N_NTSC;
978                 video->cip_d = init->cip_d != 0 ? init->cip_d : CIP_D_NTSC;
979                 video->frame_size = DV1394_NTSC_FRAME_SIZE;
980         } else {
981                 video->cip_n = init->cip_n != 0 ? init->cip_n : CIP_N_PAL;
982                 video->cip_d = init->cip_d != 0 ? init->cip_d : CIP_D_PAL;
983                 video->frame_size = DV1394_PAL_FRAME_SIZE;
984         }
985
986         video->syt_offset = init->syt_offset;
987
988         /* find and claim DMA contexts on the OHCI card */
989
990         if (video->ohci_it_ctx == -1) {
991                 ohci1394_init_iso_tasklet(&video->it_tasklet, OHCI_ISO_TRANSMIT,
992                                           it_tasklet_func, (unsigned long) video);
993
994                 if (ohci1394_register_iso_tasklet(video->ohci, &video->it_tasklet) < 0) {
995                         printk(KERN_ERR "dv1394: could not find an available IT DMA context\n");
996                         retval = -EBUSY;
997                         goto err;
998                 }
999
1000                 video->ohci_it_ctx = video->it_tasklet.context;
1001                 debug_printk("dv1394: claimed IT DMA context %d\n", video->ohci_it_ctx);
1002         }
1003
1004         if (video->ohci_ir_ctx == -1) {
1005                 ohci1394_init_iso_tasklet(&video->ir_tasklet, OHCI_ISO_RECEIVE,
1006                                           ir_tasklet_func, (unsigned long) video);
1007
1008                 if (ohci1394_register_iso_tasklet(video->ohci, &video->ir_tasklet) < 0) {
1009                         printk(KERN_ERR "dv1394: could not find an available IR DMA context\n");
1010                         retval = -EBUSY;
1011                         goto err;
1012                 }
1013                 video->ohci_ir_ctx = video->ir_tasklet.context;
1014                 debug_printk("dv1394: claimed IR DMA context %d\n", video->ohci_ir_ctx);
1015         }
1016
1017         /* allocate struct frames */
1018         for (i = 0; i < init->n_frames; i++) {
1019                 video->frames[i] = frame_new(i, video);
1020
1021                 if (!video->frames[i]) {
1022                         printk(KERN_ERR "dv1394: Cannot allocate frame structs\n");
1023                         retval = -ENOMEM;
1024                         goto err;
1025                 }
1026         }
1027
1028         if (!video->dv_buf.kvirt) {
1029                 /* allocate the ringbuffer */
1030                 retval = dma_region_alloc(&video->dv_buf, new_buf_size, video->ohci->dev, PCI_DMA_TODEVICE);
1031                 if (retval)
1032                         goto err;
1033
1034                 video->dv_buf_size = new_buf_size;
1035
1036                 debug_printk("dv1394: Allocated %d frame buffers, total %u pages (%u DMA pages), %lu bytes\n", 
1037                              video->n_frames, video->dv_buf.n_pages,
1038                              video->dv_buf.n_dma_pages, video->dv_buf_size);
1039         }
1040
1041         /* set up the frame->data pointers */
1042         for (i = 0; i < video->n_frames; i++)
1043                 video->frames[i]->data = (unsigned long) video->dv_buf.kvirt + i * video->frame_size;
1044
1045         if (!video->packet_buf.kvirt) {
1046                 /* allocate packet buffer */
1047                 video->packet_buf_size = sizeof(struct packet) * video->n_frames * MAX_PACKETS;
1048                 if (video->packet_buf_size % PAGE_SIZE)
1049                         video->packet_buf_size += PAGE_SIZE - (video->packet_buf_size % PAGE_SIZE);
1050
1051                 retval = dma_region_alloc(&video->packet_buf, video->packet_buf_size,
1052                                           video->ohci->dev, PCI_DMA_FROMDEVICE);
1053                 if (retval)
1054                         goto err;
1055
1056                 debug_printk("dv1394: Allocated %d packets in buffer, total %u pages (%u DMA pages), %lu bytes\n",
1057                                  video->n_frames*MAX_PACKETS, video->packet_buf.n_pages,
1058                                  video->packet_buf.n_dma_pages, video->packet_buf_size);
1059         }
1060
1061         /* set up register offsets for IT context */
1062         /* IT DMA context registers are spaced 16 bytes apart */
1063         video->ohci_IsoXmitContextControlSet = OHCI1394_IsoXmitContextControlSet+16*video->ohci_it_ctx;
1064         video->ohci_IsoXmitContextControlClear = OHCI1394_IsoXmitContextControlClear+16*video->ohci_it_ctx;
1065         video->ohci_IsoXmitCommandPtr = OHCI1394_IsoXmitCommandPtr+16*video->ohci_it_ctx;
1066
1067         /* enable interrupts for IT context */
1068         reg_write(video->ohci, OHCI1394_IsoXmitIntMaskSet, (1 << video->ohci_it_ctx));
1069         debug_printk("dv1394: interrupts enabled for IT context %d\n", video->ohci_it_ctx);
1070
1071         /* set up register offsets for IR context */
1072         /* IR DMA context registers are spaced 32 bytes apart */
1073         video->ohci_IsoRcvContextControlSet = OHCI1394_IsoRcvContextControlSet+32*video->ohci_ir_ctx;
1074         video->ohci_IsoRcvContextControlClear = OHCI1394_IsoRcvContextControlClear+32*video->ohci_ir_ctx;
1075         video->ohci_IsoRcvCommandPtr = OHCI1394_IsoRcvCommandPtr+32*video->ohci_ir_ctx;
1076         video->ohci_IsoRcvContextMatch = OHCI1394_IsoRcvContextMatch+32*video->ohci_ir_ctx;
1077
1078         /* enable interrupts for IR context */
1079         reg_write(video->ohci, OHCI1394_IsoRecvIntMaskSet, (1 << video->ohci_ir_ctx) );
1080         debug_printk("dv1394: interrupts enabled for IR context %d\n", video->ohci_ir_ctx);
1081
1082         return 0;
1083
1084 err:
1085         do_dv1394_shutdown(video, 1);
1086         return retval;
1087 }
1088
1089 /* if the user doesn't bother to call ioctl(INIT) before starting
1090    mmap() or read()/write(), just give him some default values */
1091
1092 static int do_dv1394_init_default(struct video_card *video)
1093 {
1094         struct dv1394_init init;
1095
1096         init.api_version = DV1394_API_VERSION;
1097         init.n_frames = DV1394_MAX_FRAMES / 4;
1098         init.channel = video->channel;
1099         init.format = video->pal_or_ntsc;
1100         init.cip_n = video->cip_n;
1101         init.cip_d = video->cip_d;
1102         init.syt_offset = video->syt_offset;
1103
1104         return do_dv1394_init(video, &init);
1105 }
1106
1107 /* do NOT call from interrupt context */
1108 static void stop_dma(struct video_card *video)
1109 {
1110         unsigned long flags;
1111         int i;
1112
1113         /* no interrupts */
1114         spin_lock_irqsave(&video->spinlock, flags);
1115
1116         video->dma_running = 0;
1117
1118         if ( (video->ohci_it_ctx == -1) && (video->ohci_ir_ctx == -1) )
1119                 goto out;
1120
1121         /* stop DMA if in progress */
1122         if ( (video->active_frame != -1) ||
1123             (reg_read(video->ohci, video->ohci_IsoXmitContextControlClear) & (1 << 10)) ||
1124             (reg_read(video->ohci, video->ohci_IsoRcvContextControlClear) &  (1 << 10)) ) {
1125
1126                 /* clear the .run bits */
1127                 reg_write(video->ohci, video->ohci_IsoXmitContextControlClear, (1 << 15));
1128                 reg_write(video->ohci, video->ohci_IsoRcvContextControlClear, (1 << 15));
1129                 flush_pci_write(video->ohci);
1130
1131                 video->active_frame = -1;
1132                 video->first_run = 1;
1133
1134                 /* wait until DMA really stops */
1135                 i = 0;
1136                 while (i < 1000) {
1137
1138                         /* wait 0.1 millisecond */
1139                         udelay(100);
1140
1141                         if ( (reg_read(video->ohci, video->ohci_IsoXmitContextControlClear) & (1 << 10)) ||
1142                             (reg_read(video->ohci, video->ohci_IsoRcvContextControlClear)  & (1 << 10)) ) {
1143                                 /* still active */
1144                                 debug_printk("dv1394: stop_dma: DMA not stopped yet\n" );
1145                                 mb();
1146                         } else {
1147                                 debug_printk("dv1394: stop_dma: DMA stopped safely after %d ms\n", i/10);
1148                                 break;
1149                         }
1150
1151                         i++;
1152                 }
1153
1154                 if (i == 1000) {
1155                         printk(KERN_ERR "dv1394: stop_dma: DMA still going after %d ms!\n", i/10);
1156                 }
1157         }
1158         else
1159                 debug_printk("dv1394: stop_dma: already stopped.\n");
1160
1161 out:
1162         spin_unlock_irqrestore(&video->spinlock, flags);
1163 }
1164
1165
1166
1167 static void do_dv1394_shutdown(struct video_card *video, int free_dv_buf)
1168 {
1169         int i;
1170
1171         debug_printk("dv1394: shutdown...\n");
1172
1173         /* stop DMA if in progress */
1174         stop_dma(video);
1175
1176         /* release the DMA contexts */
1177         if (video->ohci_it_ctx != -1) {
1178                 video->ohci_IsoXmitContextControlSet = 0;
1179                 video->ohci_IsoXmitContextControlClear = 0;
1180                 video->ohci_IsoXmitCommandPtr = 0;
1181
1182                 /* disable interrupts for IT context */
1183                 reg_write(video->ohci, OHCI1394_IsoXmitIntMaskClear, (1 << video->ohci_it_ctx));
1184
1185                 /* remove tasklet */
1186                 ohci1394_unregister_iso_tasklet(video->ohci, &video->it_tasklet);
1187                 debug_printk("dv1394: IT context %d released\n", video->ohci_it_ctx);
1188                 video->ohci_it_ctx = -1;
1189         }
1190
1191         if (video->ohci_ir_ctx != -1) {
1192                 video->ohci_IsoRcvContextControlSet = 0;
1193                 video->ohci_IsoRcvContextControlClear = 0;
1194                 video->ohci_IsoRcvCommandPtr = 0;
1195                 video->ohci_IsoRcvContextMatch = 0;
1196
1197                 /* disable interrupts for IR context */
1198                 reg_write(video->ohci, OHCI1394_IsoRecvIntMaskClear, (1 << video->ohci_ir_ctx));
1199
1200                 /* remove tasklet */
1201                 ohci1394_unregister_iso_tasklet(video->ohci, &video->ir_tasklet);
1202                 debug_printk("dv1394: IR context %d released\n", video->ohci_ir_ctx);
1203                 video->ohci_ir_ctx = -1;
1204         }
1205
1206         /* release the ISO channel */
1207         if (video->channel != -1) {
1208                 u64 chan_mask;
1209                 unsigned long flags;
1210
1211                 chan_mask = (u64)1 << video->channel;
1212
1213                 spin_lock_irqsave(&video->ohci->IR_channel_lock, flags);
1214                 video->ohci->ISO_channel_usage &= ~(chan_mask);
1215                 spin_unlock_irqrestore(&video->ohci->IR_channel_lock, flags);
1216
1217                 video->channel = -1;
1218         }
1219
1220         /* free the frame structs */
1221         for (i = 0; i < DV1394_MAX_FRAMES; i++) {
1222                 if (video->frames[i])
1223                         frame_delete(video->frames[i]);
1224                 video->frames[i] = NULL;
1225         }
1226
1227         video->n_frames = 0;
1228
1229         /* we can't free the DMA buffer unless it is guaranteed that
1230            no more user-space mappings exist */
1231
1232         if (free_dv_buf) {
1233                 dma_region_free(&video->dv_buf);
1234                 video->dv_buf_size = 0;
1235         }
1236
1237         /* free packet buffer */
1238         dma_region_free(&video->packet_buf);
1239         video->packet_buf_size = 0;
1240
1241         debug_printk("dv1394: shutdown OK\n");
1242 }
1243
1244 /*
1245        **********************************
1246        *** MMAP() THEORY OF OPERATION ***
1247        **********************************
1248
1249         The ringbuffer cannot be re-allocated or freed while
1250         a user program maintains a mapping of it. (note that a mapping
1251         can persist even after the device fd is closed!)
1252
1253         So, only let the user process allocate the DMA buffer once.
1254         To resize or deallocate it, you must close the device file
1255         and open it again.
1256
1257         Previously Dan M. hacked out a scheme that allowed the DMA
1258         buffer to change by forcefully unmapping it from the user's
1259         address space. It was prone to error because it's very hard to
1260         track all the places the buffer could have been mapped (we
1261         would have had to walk the vma list of every process in the
1262         system to be sure we found all the mappings!). Instead, we
1263         force the user to choose one buffer size and stick with
1264         it. This small sacrifice is worth the huge reduction in
1265         error-prone code in dv1394.
1266 */
1267
1268 static int dv1394_mmap(struct file *file, struct vm_area_struct *vma)
1269 {
1270         struct video_card *video = file_to_video_card(file);
1271         int retval = -EINVAL;
1272
1273         /*
1274          * We cannot use the blocking variant mutex_lock here because .mmap
1275          * is called with mmap_sem held, while .ioctl, .read, .write acquire
1276          * video->mtx and subsequently call copy_to/from_user which will
1277          * grab mmap_sem in case of a page fault.
1278          */
1279         if (!mutex_trylock(&video->mtx))
1280                 return -EAGAIN;
1281
1282         if ( ! video_card_initialized(video) ) {
1283                 retval = do_dv1394_init_default(video);
1284                 if (retval)
1285                         goto out;
1286         }
1287
1288         retval = dma_region_mmap(&video->dv_buf, file, vma);
1289 out:
1290         mutex_unlock(&video->mtx);
1291         return retval;
1292 }
1293
1294 /*** DEVICE FILE INTERFACE *************************************************/
1295
1296 /* no need to serialize, multiple threads OK */
1297 static unsigned int dv1394_poll(struct file *file, struct poll_table_struct *wait)
1298 {
1299         struct video_card *video = file_to_video_card(file);
1300         unsigned int mask = 0;
1301         unsigned long flags;
1302
1303         poll_wait(file, &video->waitq, wait);
1304
1305         spin_lock_irqsave(&video->spinlock, flags);
1306         if ( video->n_frames == 0 ) {
1307
1308         } else if ( video->active_frame == -1 ) {
1309                 /* nothing going on */
1310                 mask |= POLLOUT;
1311         } else {
1312                 /* any clear/ready buffers? */
1313                 if (video->n_clear_frames >0)
1314                         mask |= POLLOUT | POLLIN;
1315         }
1316         spin_unlock_irqrestore(&video->spinlock, flags);
1317
1318         return mask;
1319 }
1320
1321 static int dv1394_fasync(int fd, struct file *file, int on)
1322 {
1323         /* I just copied this code verbatim from Alan Cox's mouse driver example
1324            (Documentation/DocBook/) */
1325
1326         struct video_card *video = file_to_video_card(file);
1327
1328         int retval = fasync_helper(fd, file, on, &video->fasync);
1329
1330         if (retval < 0)
1331                 return retval;
1332         return 0;
1333 }
1334
1335 static ssize_t dv1394_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1336 {
1337         struct video_card *video = file_to_video_card(file);
1338         DECLARE_WAITQUEUE(wait, current);
1339         ssize_t ret;
1340         size_t cnt;
1341         unsigned long flags;
1342         int target_frame;
1343
1344         /* serialize this to prevent multi-threaded mayhem */
1345         if (file->f_flags & O_NONBLOCK) {
1346                 if (!mutex_trylock(&video->mtx))
1347                         return -EAGAIN;
1348         } else {
1349                 if (mutex_lock_interruptible(&video->mtx))
1350                         return -ERESTARTSYS;
1351         }
1352
1353         if ( !video_card_initialized(video) ) {
1354                 ret = do_dv1394_init_default(video);
1355                 if (ret) {
1356                         mutex_unlock(&video->mtx);
1357                         return ret;
1358                 }
1359         }
1360
1361         ret = 0;
1362         add_wait_queue(&video->waitq, &wait);
1363
1364         while (count > 0) {
1365
1366                 /* must set TASK_INTERRUPTIBLE *before* checking for free
1367                    buffers; otherwise we could miss a wakeup if the interrupt
1368                    fires between the check and the schedule() */
1369
1370                 set_current_state(TASK_INTERRUPTIBLE);
1371
1372                 spin_lock_irqsave(&video->spinlock, flags);
1373
1374                 target_frame = video->first_clear_frame;
1375
1376                 spin_unlock_irqrestore(&video->spinlock, flags);
1377
1378                 if (video->frames[target_frame]->state == FRAME_CLEAR) {
1379
1380                         /* how much room is left in the target frame buffer */
1381                         cnt = video->frame_size - (video->write_off - target_frame * video->frame_size);
1382
1383                 } else {
1384                         /* buffer is already used */
1385                         cnt = 0;
1386                 }
1387
1388                 if (cnt > count)
1389                         cnt = count;
1390
1391                 if (cnt <= 0) {
1392                         /* no room left, gotta wait */
1393                         if (file->f_flags & O_NONBLOCK) {
1394                                 if (!ret)
1395                                         ret = -EAGAIN;
1396                                 break;
1397                         }
1398                         if (signal_pending(current)) {
1399                                 if (!ret)
1400                                         ret = -ERESTARTSYS;
1401                                 break;
1402                         }
1403
1404                         schedule();
1405
1406                         continue; /* start over from 'while(count > 0)...' */
1407                 }
1408
1409                 if (copy_from_user(video->dv_buf.kvirt + video->write_off, buffer, cnt)) {
1410                         if (!ret)
1411                                 ret = -EFAULT;
1412                         break;
1413                 }
1414
1415                 video->write_off = (video->write_off + cnt) % (video->n_frames * video->frame_size);
1416
1417                 count -= cnt;
1418                 buffer += cnt;
1419                 ret += cnt;
1420
1421                 if (video->write_off == video->frame_size * ((target_frame + 1) % video->n_frames))
1422                                 frame_prepare(video, target_frame);
1423         }
1424
1425         remove_wait_queue(&video->waitq, &wait);
1426         set_current_state(TASK_RUNNING);
1427         mutex_unlock(&video->mtx);
1428         return ret;
1429 }
1430
1431
1432 static ssize_t dv1394_read(struct file *file,  char __user *buffer, size_t count, loff_t *ppos)
1433 {
1434         struct video_card *video = file_to_video_card(file);
1435         DECLARE_WAITQUEUE(wait, current);
1436         ssize_t ret;
1437         size_t cnt;
1438         unsigned long flags;
1439         int target_frame;
1440
1441         /* serialize this to prevent multi-threaded mayhem */
1442         if (file->f_flags & O_NONBLOCK) {
1443                 if (!mutex_trylock(&video->mtx))
1444                         return -EAGAIN;
1445         } else {
1446                 if (mutex_lock_interruptible(&video->mtx))
1447                         return -ERESTARTSYS;
1448         }
1449
1450         if ( !video_card_initialized(video) ) {
1451                 ret = do_dv1394_init_default(video);
1452                 if (ret) {
1453                         mutex_unlock(&video->mtx);
1454                         return ret;
1455                 }
1456                 video->continuity_counter = -1;
1457
1458                 receive_packets(video);
1459
1460                 start_dma_receive(video);
1461         }
1462
1463         ret = 0;
1464         add_wait_queue(&video->waitq, &wait);
1465
1466         while (count > 0) {
1467
1468                 /* must set TASK_INTERRUPTIBLE *before* checking for free
1469                    buffers; otherwise we could miss a wakeup if the interrupt
1470                    fires between the check and the schedule() */
1471
1472                 set_current_state(TASK_INTERRUPTIBLE);
1473
1474                 spin_lock_irqsave(&video->spinlock, flags);
1475
1476                 target_frame = video->first_clear_frame;
1477
1478                 spin_unlock_irqrestore(&video->spinlock, flags);
1479
1480                 if (target_frame >= 0 &&
1481                         video->n_clear_frames > 0 &&
1482                         video->frames[target_frame]->state == FRAME_CLEAR) {
1483
1484                         /* how much room is left in the target frame buffer */
1485                         cnt = video->frame_size - (video->write_off - target_frame * video->frame_size);
1486
1487                 } else {
1488                         /* buffer is already used */
1489                         cnt = 0;
1490                 }
1491
1492                 if (cnt > count)
1493                         cnt = count;
1494
1495                 if (cnt <= 0) {
1496                         /* no room left, gotta wait */
1497                         if (file->f_flags & O_NONBLOCK) {
1498                                 if (!ret)
1499                                         ret = -EAGAIN;
1500                                 break;
1501                         }
1502                         if (signal_pending(current)) {
1503                                 if (!ret)
1504                                         ret = -ERESTARTSYS;
1505                                 break;
1506                         }
1507
1508                         schedule();
1509
1510                         continue; /* start over from 'while(count > 0)...' */
1511                 }
1512
1513                 if (copy_to_user(buffer, video->dv_buf.kvirt + video->write_off, cnt)) {
1514                                 if (!ret)
1515                                         ret = -EFAULT;
1516                                 break;
1517                 }
1518
1519                 video->write_off = (video->write_off + cnt) % (video->n_frames * video->frame_size);
1520
1521                 count -= cnt;
1522                 buffer += cnt;
1523                 ret += cnt;
1524
1525                 if (video->write_off == video->frame_size * ((target_frame + 1) % video->n_frames)) {
1526                         spin_lock_irqsave(&video->spinlock, flags);
1527                         video->n_clear_frames--;
1528                         video->first_clear_frame = (video->first_clear_frame + 1) % video->n_frames;
1529                         spin_unlock_irqrestore(&video->spinlock, flags);
1530                 }
1531         }
1532
1533         remove_wait_queue(&video->waitq, &wait);
1534         set_current_state(TASK_RUNNING);
1535         mutex_unlock(&video->mtx);
1536         return ret;
1537 }
1538
1539
1540 /*** DEVICE IOCTL INTERFACE ************************************************/
1541
1542 static long dv1394_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1543 {
1544         struct video_card *video = file_to_video_card(file);
1545         unsigned long flags;
1546         int ret = -EINVAL;
1547         void __user *argp = (void __user *)arg;
1548
1549         DECLARE_WAITQUEUE(wait, current);
1550
1551         /* serialize this to prevent multi-threaded mayhem */
1552         if (file->f_flags & O_NONBLOCK) {
1553                 if (!mutex_trylock(&video->mtx))
1554                         return -EAGAIN;
1555         } else {
1556                 if (mutex_lock_interruptible(&video->mtx))
1557                         return -ERESTARTSYS;
1558         }
1559
1560         switch(cmd)
1561         {
1562         case DV1394_IOC_SUBMIT_FRAMES: {
1563                 unsigned int n_submit;
1564
1565                 if ( !video_card_initialized(video) ) {
1566                         ret = do_dv1394_init_default(video);
1567                         if (ret)
1568                                 goto out;
1569                 }
1570
1571                 n_submit = (unsigned int) arg;
1572
1573                 if (n_submit > video->n_frames) {
1574                         ret = -EINVAL;
1575                         goto out;
1576                 }
1577
1578                 while (n_submit > 0) {
1579
1580                         add_wait_queue(&video->waitq, &wait);
1581                         set_current_state(TASK_INTERRUPTIBLE);
1582
1583                         spin_lock_irqsave(&video->spinlock, flags);
1584
1585                         /* wait until video->first_clear_frame is really CLEAR */
1586                         while (video->frames[video->first_clear_frame]->state != FRAME_CLEAR) {
1587
1588                                 spin_unlock_irqrestore(&video->spinlock, flags);
1589
1590                                 if (signal_pending(current)) {
1591                                         remove_wait_queue(&video->waitq, &wait);
1592                                         set_current_state(TASK_RUNNING);
1593                                         ret = -EINTR;
1594                                         goto out;
1595                                 }
1596
1597                                 schedule();
1598                                 set_current_state(TASK_INTERRUPTIBLE);
1599
1600                                 spin_lock_irqsave(&video->spinlock, flags);
1601                         }
1602                         spin_unlock_irqrestore(&video->spinlock, flags);
1603
1604                         remove_wait_queue(&video->waitq, &wait);
1605                         set_current_state(TASK_RUNNING);
1606
1607                         frame_prepare(video, video->first_clear_frame);
1608
1609                         n_submit--;
1610                 }
1611
1612                 ret = 0;
1613                 break;
1614         }
1615
1616         case DV1394_IOC_WAIT_FRAMES: {
1617                 unsigned int n_wait;
1618
1619                 if ( !video_card_initialized(video) ) {
1620                         ret = -EINVAL;
1621                         goto out;
1622                 }
1623
1624                 n_wait = (unsigned int) arg;
1625
1626                 /* since we re-run the last frame on underflow, we will
1627                    never actually have n_frames clear frames; at most only
1628                    n_frames - 1 */
1629
1630                 if (n_wait > (video->n_frames-1) ) {
1631                         ret = -EINVAL;
1632                         goto out;
1633                 }
1634
1635                 add_wait_queue(&video->waitq, &wait);
1636                 set_current_state(TASK_INTERRUPTIBLE);
1637
1638                 spin_lock_irqsave(&video->spinlock, flags);
1639
1640                 while (video->n_clear_frames < n_wait) {
1641
1642                         spin_unlock_irqrestore(&video->spinlock, flags);
1643
1644                         if (signal_pending(current)) {
1645                                 remove_wait_queue(&video->waitq, &wait);
1646                                 set_current_state(TASK_RUNNING);
1647                                 ret = -EINTR;
1648                                 goto out;
1649                         }
1650
1651                         schedule();
1652                         set_current_state(TASK_INTERRUPTIBLE);
1653
1654                         spin_lock_irqsave(&video->spinlock, flags);
1655                 }
1656
1657                 spin_unlock_irqrestore(&video->spinlock, flags);
1658
1659                 remove_wait_queue(&video->waitq, &wait);
1660                 set_current_state(TASK_RUNNING);
1661                 ret = 0;
1662                 break;
1663         }
1664
1665         case DV1394_IOC_RECEIVE_FRAMES: {
1666                 unsigned int n_recv;
1667
1668                 if ( !video_card_initialized(video) ) {
1669                         ret = -EINVAL;
1670                         goto out;
1671                 }
1672
1673                 n_recv = (unsigned int) arg;
1674
1675                 /* at least one frame must be active */
1676                 if (n_recv > (video->n_frames-1) ) {
1677                         ret = -EINVAL;
1678                         goto out;
1679                 }
1680
1681                 spin_lock_irqsave(&video->spinlock, flags);
1682
1683                 /* release the clear frames */
1684                 video->n_clear_frames -= n_recv;
1685
1686                 /* advance the clear frame cursor */
1687                 video->first_clear_frame = (video->first_clear_frame + n_recv) % video->n_frames;
1688
1689                 /* reset dropped_frames */
1690                 video->dropped_frames = 0;
1691
1692                 spin_unlock_irqrestore(&video->spinlock, flags);
1693
1694                 ret = 0;
1695                 break;
1696         }
1697
1698         case DV1394_IOC_START_RECEIVE: {
1699                 if ( !video_card_initialized(video) ) {
1700                         ret = do_dv1394_init_default(video);
1701                         if (ret)
1702                                 goto out;
1703                 }
1704
1705                 video->continuity_counter = -1;
1706
1707                 receive_packets(video);
1708
1709                 start_dma_receive(video);
1710
1711                 ret = 0;
1712                 break;
1713         }
1714
1715         case DV1394_IOC_INIT: {
1716                 struct dv1394_init init;
1717                 if (!argp) {
1718                         ret = do_dv1394_init_default(video);
1719                 } else {
1720                         if (copy_from_user(&init, argp, sizeof(init))) {
1721                                 ret = -EFAULT;
1722                                 goto out;
1723                         }
1724                         ret = do_dv1394_init(video, &init);
1725                 }
1726                 break;
1727         }
1728
1729         case DV1394_IOC_SHUTDOWN:
1730                 do_dv1394_shutdown(video, 0);
1731                 ret = 0;
1732                 break;
1733
1734
1735         case DV1394_IOC_GET_STATUS: {
1736                 struct dv1394_status status;
1737
1738                 if ( !video_card_initialized(video) ) {
1739                         ret = -EINVAL;
1740                         goto out;
1741                 }
1742
1743                 status.init.api_version = DV1394_API_VERSION;
1744                 status.init.channel = video->channel;
1745                 status.init.n_frames = video->n_frames;
1746                 status.init.format = video->pal_or_ntsc;
1747                 status.init.cip_n = video->cip_n;
1748                 status.init.cip_d = video->cip_d;
1749                 status.init.syt_offset = video->syt_offset;
1750
1751                 status.first_clear_frame = video->first_clear_frame;
1752
1753                 /* the rest of the fields need to be locked against the interrupt */
1754                 spin_lock_irqsave(&video->spinlock, flags);
1755
1756                 status.active_frame = video->active_frame;
1757                 status.n_clear_frames = video->n_clear_frames;
1758
1759                 status.dropped_frames = video->dropped_frames;
1760
1761                 /* reset dropped_frames */
1762                 video->dropped_frames = 0;
1763
1764                 spin_unlock_irqrestore(&video->spinlock, flags);
1765
1766                 if (copy_to_user(argp, &status, sizeof(status))) {
1767                         ret = -EFAULT;
1768                         goto out;
1769                 }
1770
1771                 ret = 0;
1772                 break;
1773         }
1774
1775         default:
1776                 break;
1777         }
1778
1779  out:
1780         mutex_unlock(&video->mtx);
1781         return ret;
1782 }
1783
1784 /*** DEVICE FILE INTERFACE CONTINUED ***************************************/
1785
1786 static int dv1394_open(struct inode *inode, struct file *file)
1787 {
1788         struct video_card *video = NULL;
1789
1790         if (file->private_data) {
1791                 video = (struct video_card*) file->private_data;
1792
1793         } else {
1794                 /* look up the card by ID */
1795                 unsigned long flags;
1796
1797                 spin_lock_irqsave(&dv1394_cards_lock, flags);
1798                 if (!list_empty(&dv1394_cards)) {
1799                         struct video_card *p;
1800                         list_for_each_entry(p, &dv1394_cards, list) {
1801                                 if ((p->id) == ieee1394_file_to_instance(file)) {
1802                                         video = p;
1803                                         break;
1804                                 }
1805                         }
1806                 }
1807                 spin_unlock_irqrestore(&dv1394_cards_lock, flags);
1808
1809                 if (!video) {
1810                         debug_printk("dv1394: OHCI card %d not found", ieee1394_file_to_instance(file));
1811                         return -ENODEV;
1812                 }
1813
1814                 file->private_data = (void*) video;
1815         }
1816
1817 #ifndef DV1394_ALLOW_MORE_THAN_ONE_OPEN
1818
1819         if ( test_and_set_bit(0, &video->open) ) {
1820                 /* video is already open by someone else */
1821                 return -EBUSY;
1822         }
1823
1824 #endif
1825
1826         printk(KERN_INFO "%s: NOTE, the dv1394 interface is unsupported "
1827                "and will not be available in the new firewire driver stack. "
1828                "Try libraw1394 based programs instead.\n", current->comm);
1829
1830         return 0;
1831 }
1832
1833
1834 static int dv1394_release(struct inode *inode, struct file *file)
1835 {
1836         struct video_card *video = file_to_video_card(file);
1837
1838         /* OK to free the DMA buffer, no more mappings can exist */
1839         do_dv1394_shutdown(video, 1);
1840
1841         /* give someone else a turn */
1842         clear_bit(0, &video->open);
1843
1844         return 0;
1845 }
1846
1847
1848 /*** DEVICE DRIVER HANDLERS ************************************************/
1849
1850 static void it_tasklet_func(unsigned long data)
1851 {
1852         int wake = 0;
1853         struct video_card *video = (struct video_card*) data;
1854
1855         spin_lock(&video->spinlock);
1856
1857         if (!video->dma_running)
1858                 goto out;
1859
1860         irq_printk("ContextControl = %08x, CommandPtr = %08x\n",
1861                reg_read(video->ohci, video->ohci_IsoXmitContextControlSet),
1862                reg_read(video->ohci, video->ohci_IsoXmitCommandPtr)
1863                );
1864
1865
1866         if ( (video->ohci_it_ctx != -1) &&
1867             (reg_read(video->ohci, video->ohci_IsoXmitContextControlSet) & (1 << 10)) ) {
1868
1869                 struct frame *f;
1870                 unsigned int frame, i;
1871
1872
1873                 if (video->active_frame == -1)
1874                         frame = 0;
1875                 else
1876                         frame = video->active_frame;
1877
1878                 /* check all the DMA-able frames */
1879                 for (i = 0; i < video->n_frames; i++, frame = (frame+1) % video->n_frames) {
1880
1881                         irq_printk("IRQ checking frame %d...", frame);
1882                         f = video->frames[frame];
1883                         if (f->state != FRAME_READY) {
1884                                 irq_printk("clear, skipping\n");
1885                                 /* we don't own this frame */
1886                                 continue;
1887                         }
1888
1889                         irq_printk("DMA\n");
1890
1891                         /* check the frame begin semaphore to see if we can free the previous frame */
1892                         if ( *(f->frame_begin_timestamp) ) {
1893                                 int prev_frame;
1894                                 struct frame *prev_f;
1895
1896
1897
1898                                 /* don't reset, need this later *(f->frame_begin_timestamp) = 0; */
1899                                 irq_printk("  BEGIN\n");
1900
1901                                 prev_frame = frame - 1;
1902                                 if (prev_frame == -1)
1903                                         prev_frame += video->n_frames;
1904                                 prev_f = video->frames[prev_frame];
1905
1906                                 /* make sure we can actually garbage collect
1907                                    this frame */
1908                                 if ( (prev_f->state == FRAME_READY) &&
1909                                     prev_f->done && (!f->done) )
1910                                 {
1911                                         frame_reset(prev_f);
1912                                         video->n_clear_frames++;
1913                                         wake = 1;
1914                                         video->active_frame = frame;
1915
1916                                         irq_printk("  BEGIN - freeing previous frame %d, new active frame is %d\n", prev_frame, frame);
1917                                 } else {
1918                                         irq_printk("  BEGIN - can't free yet\n");
1919                                 }
1920
1921                                 f->done = 1;
1922                         }
1923
1924
1925                         /* see if we need to set the timestamp for the next frame */
1926                         if ( *(f->mid_frame_timestamp) ) {
1927                                 struct frame *next_frame;
1928                                 u32 begin_ts, ts_cyc, ts_off;
1929
1930                                 *(f->mid_frame_timestamp) = 0;
1931
1932                                 begin_ts = le32_to_cpu(*(f->frame_begin_timestamp));
1933
1934                                 irq_printk("  MIDDLE - first packet was sent at cycle %4u (%2u), assigned timestamp was (%2u) %4u\n",
1935                                            begin_ts & 0x1FFF, begin_ts & 0xF,
1936                                            f->assigned_timestamp >> 12, f->assigned_timestamp & 0xFFF);
1937
1938                                 /* prepare next frame and assign timestamp */
1939                                 next_frame = video->frames[ (frame+1) % video->n_frames ];
1940
1941                                 if (next_frame->state == FRAME_READY) {
1942                                         irq_printk("  MIDDLE - next frame is ready, good\n");
1943                                 } else {
1944                                         debug_printk("dv1394: Underflow! At least one frame has been dropped.\n");
1945                                         next_frame = f;
1946                                 }
1947
1948                                 /* set the timestamp to the timestamp of the last frame sent,
1949                                    plus the length of the last frame sent, plus the syt latency */
1950                                 ts_cyc = begin_ts & 0xF;
1951                                 /* advance one frame, plus syt latency (typically 2-3) */
1952                                 ts_cyc += f->n_packets + video->syt_offset ;
1953
1954                                 ts_off = 0;
1955
1956                                 ts_cyc += ts_off/3072;
1957                                 ts_off %= 3072;
1958
1959                                 next_frame->assigned_timestamp = ((ts_cyc&0xF) << 12) + ts_off;
1960                                 if (next_frame->cip_syt1) {
1961                                         next_frame->cip_syt1->b[6] = next_frame->assigned_timestamp >> 8;
1962                                         next_frame->cip_syt1->b[7] = next_frame->assigned_timestamp & 0xFF;
1963                                 }
1964                                 if (next_frame->cip_syt2) {
1965                                         next_frame->cip_syt2->b[6] = next_frame->assigned_timestamp >> 8;
1966                                         next_frame->cip_syt2->b[7] = next_frame->assigned_timestamp & 0xFF;
1967                                 }
1968
1969                         }
1970
1971                         /* see if the frame looped */
1972                         if ( *(f->frame_end_timestamp) ) {
1973
1974                                 *(f->frame_end_timestamp) = 0;
1975
1976                                 debug_printk("  END - the frame looped at least once\n");
1977
1978                                 video->dropped_frames++;
1979                         }
1980
1981                 } /* for (each frame) */
1982         }
1983
1984         if (wake) {
1985                 kill_fasync(&video->fasync, SIGIO, POLL_OUT);
1986
1987                 /* wake readers/writers/ioctl'ers */
1988                 wake_up_interruptible(&video->waitq);
1989         }
1990
1991 out:
1992         spin_unlock(&video->spinlock);
1993 }
1994
1995 static void ir_tasklet_func(unsigned long data)
1996 {
1997         int wake = 0;
1998         struct video_card *video = (struct video_card*) data;
1999
2000         spin_lock(&video->spinlock);
2001
2002         if (!video->dma_running)
2003                 goto out;
2004
2005         if ( (video->ohci_ir_ctx != -1) &&
2006             (reg_read(video->ohci, video->ohci_IsoRcvContextControlSet) & (1 << 10)) ) {
2007
2008                 int sof=0; /* start-of-frame flag */
2009                 struct frame *f;
2010                 u16 packet_length, packet_time;
2011                 int i, dbc=0;
2012                 struct DMA_descriptor_block *block = NULL;
2013                 u16 xferstatus;
2014
2015                 int next_i, prev_i;
2016                 struct DMA_descriptor_block *next = NULL;
2017                 dma_addr_t next_dma = 0;
2018                 struct DMA_descriptor_block *prev = NULL;
2019
2020                 /* loop over all descriptors in all frames */
2021                 for (i = 0; i < video->n_frames*MAX_PACKETS; i++) {
2022                         struct packet *p = dma_region_i(&video->packet_buf, struct packet, video->current_packet);
2023
2024                         /* make sure we are seeing the latest changes to p */
2025                         dma_region_sync_for_cpu(&video->packet_buf,
2026                                                 (unsigned long) p - (unsigned long) video->packet_buf.kvirt,
2027                                                 sizeof(struct packet));
2028
2029                         packet_length = le16_to_cpu(p->data_length);
2030                         packet_time   = le16_to_cpu(p->timestamp);
2031
2032                         irq_printk("received packet %02d, timestamp=%04x, length=%04x, sof=%02x%02x\n", video->current_packet,
2033                                    packet_time, packet_length,
2034                                    p->data[0], p->data[1]);
2035
2036                         /* get the descriptor based on packet_buffer cursor */
2037                         f = video->frames[video->current_packet / MAX_PACKETS];
2038                         block = &(f->descriptor_pool[video->current_packet % MAX_PACKETS]);
2039                         xferstatus = le32_to_cpu(block->u.in.il.q[3]) >> 16;
2040                         xferstatus &= 0x1F;
2041                         irq_printk("ir_tasklet_func: xferStatus/resCount [%d] = 0x%08x\n", i, le32_to_cpu(block->u.in.il.q[3]) );
2042
2043                         /* get the current frame */
2044                         f = video->frames[video->active_frame];
2045
2046                         /* exclude empty packet */
2047                         if (packet_length > 8 && xferstatus == 0x11) {
2048                                 /* check for start of frame */
2049                                 /* DRD> Changed to check section type ([0]>>5==0)
2050                                    and dif sequence ([1]>>4==0) */
2051                                 sof = ( (p->data[0] >> 5) == 0 && (p->data[1] >> 4) == 0);
2052
2053                                 dbc = (int) (p->cip_h1 >> 24);
2054                                 if ( video->continuity_counter != -1 && dbc > ((video->continuity_counter + 1) % 256) )
2055                                 {
2056                                         printk(KERN_WARNING "dv1394: discontinuity detected, dropping all frames\n" );
2057                                         video->dropped_frames += video->n_clear_frames + 1;
2058                                         video->first_frame = 0;
2059                                         video->n_clear_frames = 0;
2060                                         video->first_clear_frame = -1;
2061                                 }
2062                                 video->continuity_counter = dbc;
2063
2064                                 if (!video->first_frame) {
2065                                         if (sof) {
2066                                                 video->first_frame = 1;
2067                                         }
2068
2069                                 } else if (sof) {
2070                                         /* close current frame */
2071                                         frame_reset(f);  /* f->state = STATE_CLEAR */
2072                                         video->n_clear_frames++;
2073                                         if (video->n_clear_frames > video->n_frames) {
2074                                                 video->dropped_frames++;
2075                                                 printk(KERN_WARNING "dv1394: dropped a frame during reception\n" );
2076                                                 video->n_clear_frames = video->n_frames-1;
2077                                                 video->first_clear_frame = (video->first_clear_frame + 1) % video->n_frames;
2078                                         }
2079                                         if (video->first_clear_frame == -1)
2080                                                 video->first_clear_frame = video->active_frame;
2081
2082                                         /* get the next frame */
2083                                         video->active_frame = (video->active_frame + 1) % video->n_frames;
2084                                         f = video->frames[video->active_frame];
2085                                         irq_printk("   frame received, active_frame = %d, n_clear_frames = %d, first_clear_frame = %d\n",
2086                                                    video->active_frame, video->n_clear_frames, video->first_clear_frame);
2087                                 }
2088                                 if (video->first_frame) {
2089                                         if (sof) {
2090                                                 /* open next frame */
2091                                                 f->state = FRAME_READY;
2092                                         }
2093
2094                                         /* copy to buffer */
2095                                         if (f->n_packets > (video->frame_size / 480)) {
2096                                                 printk(KERN_ERR "frame buffer overflow during receive\n");
2097                                         }
2098
2099                                         frame_put_packet(f, p);
2100
2101                                 } /* first_frame */
2102                         }
2103
2104                         /* stop, end of ready packets */
2105                         else if (xferstatus == 0) {
2106                                 break;
2107                         }
2108
2109                         /* reset xferStatus & resCount */
2110                         block->u.in.il.q[3] = cpu_to_le32(512);
2111
2112                         /* terminate dma chain at this (next) packet */
2113                         next_i = video->current_packet;
2114                         f = video->frames[next_i / MAX_PACKETS];
2115                         next = &(f->descriptor_pool[next_i % MAX_PACKETS]);
2116                         next_dma = ((unsigned long) block - (unsigned long) f->descriptor_pool) + f->descriptor_pool_dma;
2117                         next->u.in.il.q[0] |= cpu_to_le32(3 << 20); /* enable interrupt */
2118                         next->u.in.il.q[2] = cpu_to_le32(0); /* disable branch */
2119
2120                         /* link previous to next */
2121                         prev_i = (next_i == 0) ? (MAX_PACKETS * video->n_frames - 1) : (next_i - 1);
2122                         f = video->frames[prev_i / MAX_PACKETS];
2123                         prev = &(f->descriptor_pool[prev_i % MAX_PACKETS]);
2124                         if (prev_i % (MAX_PACKETS/2)) {
2125                                 prev->u.in.il.q[0] &= ~cpu_to_le32(3 << 20); /* no interrupt */
2126                         } else {
2127                                 prev->u.in.il.q[0] |= cpu_to_le32(3 << 20); /* enable interrupt */
2128                         }
2129                         prev->u.in.il.q[2] = cpu_to_le32(next_dma | 1); /* set Z=1 */
2130                         wmb();
2131
2132                         /* wake up DMA in case it fell asleep */
2133                         reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, (1 << 12));
2134
2135                         /* advance packet_buffer cursor */
2136                         video->current_packet = (video->current_packet + 1) % (MAX_PACKETS * video->n_frames);
2137
2138                 } /* for all packets */
2139
2140                 wake = 1; /* why the hell not? */
2141
2142         } /* receive interrupt */
2143
2144         if (wake) {
2145                 kill_fasync(&video->fasync, SIGIO, POLL_IN);
2146
2147                 /* wake readers/writers/ioctl'ers */
2148                 wake_up_interruptible(&video->waitq);
2149         }
2150
2151 out:
2152         spin_unlock(&video->spinlock);
2153 }
2154
2155 static struct cdev dv1394_cdev;
2156 static const struct file_operations dv1394_fops=
2157 {
2158         .owner =        THIS_MODULE,
2159         .poll =         dv1394_poll,
2160         .unlocked_ioctl = dv1394_ioctl,
2161 #ifdef CONFIG_COMPAT
2162         .compat_ioctl = dv1394_compat_ioctl,
2163 #endif
2164         .mmap =         dv1394_mmap,
2165         .open =         dv1394_open,
2166         .write =        dv1394_write,
2167         .read =         dv1394_read,
2168         .release =      dv1394_release,
2169         .fasync =       dv1394_fasync,
2170 };
2171
2172
2173 /*** HOTPLUG STUFF **********************************************************/
2174 /*
2175  * Export information about protocols/devices supported by this driver.
2176  */
2177 #ifdef MODULE
2178 static struct ieee1394_device_id dv1394_id_table[] = {
2179         {
2180                 .match_flags    = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
2181                 .specifier_id   = AVC_UNIT_SPEC_ID_ENTRY & 0xffffff,
2182                 .version        = AVC_SW_VERSION_ENTRY & 0xffffff
2183         },
2184         { }
2185 };
2186
2187 MODULE_DEVICE_TABLE(ieee1394, dv1394_id_table);
2188 #endif /* MODULE */
2189
2190 static struct hpsb_protocol_driver dv1394_driver = {
2191         .name = "dv1394",
2192 };
2193
2194
2195 /*** IEEE1394 HPSB CALLBACKS ***********************************************/
2196
2197 static int dv1394_init(struct ti_ohci *ohci, enum pal_or_ntsc format, enum modes mode)
2198 {
2199         struct video_card *video;
2200         unsigned long flags;
2201         int i;
2202
2203         video = kzalloc(sizeof(*video), GFP_KERNEL);
2204         if (!video) {
2205                 printk(KERN_ERR "dv1394: cannot allocate video_card\n");
2206                 return -1;
2207         }
2208
2209         video->ohci = ohci;
2210         /* lower 2 bits of id indicate which of four "plugs"
2211            per host */
2212         video->id = ohci->host->id << 2;
2213         if (format == DV1394_NTSC)
2214                 video->id |= mode;
2215         else
2216                 video->id |= 2 + mode;
2217
2218         video->ohci_it_ctx = -1;
2219         video->ohci_ir_ctx = -1;
2220
2221         video->ohci_IsoXmitContextControlSet = 0;
2222         video->ohci_IsoXmitContextControlClear = 0;
2223         video->ohci_IsoXmitCommandPtr = 0;
2224
2225         video->ohci_IsoRcvContextControlSet = 0;
2226         video->ohci_IsoRcvContextControlClear = 0;
2227         video->ohci_IsoRcvCommandPtr = 0;
2228         video->ohci_IsoRcvContextMatch = 0;
2229
2230         video->n_frames = 0; /* flag that video is not initialized */
2231         video->channel = 63; /* default to broadcast channel */
2232         video->active_frame = -1;
2233
2234         /* initialize the following */
2235         video->pal_or_ntsc = format;
2236         video->cip_n = 0; /* 0 = use builtin default */
2237         video->cip_d = 0;
2238         video->syt_offset = 0;
2239         video->mode = mode;
2240
2241         for (i = 0; i < DV1394_MAX_FRAMES; i++)
2242                 video->frames[i] = NULL;
2243
2244         dma_region_init(&video->dv_buf);
2245         video->dv_buf_size = 0;
2246         dma_region_init(&video->packet_buf);
2247         video->packet_buf_size = 0;
2248
2249         clear_bit(0, &video->open);
2250         spin_lock_init(&video->spinlock);
2251         video->dma_running = 0;
2252         mutex_init(&video->mtx);
2253         init_waitqueue_head(&video->waitq);
2254         video->fasync = NULL;
2255
2256         spin_lock_irqsave(&dv1394_cards_lock, flags);
2257         INIT_LIST_HEAD(&video->list);
2258         list_add_tail(&video->list, &dv1394_cards);
2259         spin_unlock_irqrestore(&dv1394_cards_lock, flags);
2260
2261         debug_printk("dv1394: dv1394_init() OK on ID %d\n", video->id);
2262         return 0;
2263 }
2264
2265 static void dv1394_remove_host(struct hpsb_host *host)
2266 {
2267         struct video_card *video, *tmp_video;
2268         unsigned long flags;
2269         int found_ohci_card = 0;
2270
2271         do {
2272                 video = NULL;
2273                 spin_lock_irqsave(&dv1394_cards_lock, flags);
2274                 list_for_each_entry(tmp_video, &dv1394_cards, list) {
2275                         if ((tmp_video->id >> 2) == host->id) {
2276                                 list_del(&tmp_video->list);
2277                                 video = tmp_video;
2278                                 found_ohci_card = 1;
2279                                 break;
2280                         }
2281                 }
2282                 spin_unlock_irqrestore(&dv1394_cards_lock, flags);
2283
2284                 if (video) {
2285                         do_dv1394_shutdown(video, 1);
2286                         kfree(video);
2287                 }
2288         } while (video);
2289
2290         if (found_ohci_card)
2291                 device_destroy(hpsb_protocol_class, MKDEV(IEEE1394_MAJOR,
2292                            IEEE1394_MINOR_BLOCK_DV1394 * 16 + (host->id << 2)));
2293 }
2294
2295 static void dv1394_add_host(struct hpsb_host *host)
2296 {
2297         struct ti_ohci *ohci;
2298         int id = host->id;
2299
2300         /* We only work with the OHCI-1394 driver */
2301         if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME))
2302                 return;
2303
2304         ohci = (struct ti_ohci *)host->hostdata;
2305
2306         device_create(hpsb_protocol_class, NULL,
2307                       MKDEV(IEEE1394_MAJOR,
2308                             IEEE1394_MINOR_BLOCK_DV1394 * 16 + (id<<2)),
2309                       NULL, "dv1394-%d", id);
2310
2311         dv1394_init(ohci, DV1394_NTSC, MODE_RECEIVE);
2312         dv1394_init(ohci, DV1394_NTSC, MODE_TRANSMIT);
2313         dv1394_init(ohci, DV1394_PAL, MODE_RECEIVE);
2314         dv1394_init(ohci, DV1394_PAL, MODE_TRANSMIT);
2315 }
2316
2317
2318 /* Bus reset handler. In the event of a bus reset, we may need to
2319    re-start the DMA contexts - otherwise the user program would
2320    end up waiting forever.
2321 */
2322
2323 static void dv1394_host_reset(struct hpsb_host *host)
2324 {
2325         struct ti_ohci *ohci;
2326         struct video_card *video = NULL, *tmp_vid;
2327         unsigned long flags;
2328
2329         /* We only work with the OHCI-1394 driver */
2330         if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME))
2331                 return;
2332
2333         ohci = (struct ti_ohci *)host->hostdata;
2334
2335
2336         /* find the corresponding video_cards */
2337         spin_lock_irqsave(&dv1394_cards_lock, flags);
2338         list_for_each_entry(tmp_vid, &dv1394_cards, list) {
2339                 if ((tmp_vid->id >> 2) == host->id) {
2340                         video = tmp_vid;
2341                         break;
2342                 }
2343         }
2344         spin_unlock_irqrestore(&dv1394_cards_lock, flags);
2345
2346         if (!video)
2347                 return;
2348
2349
2350         spin_lock_irqsave(&video->spinlock, flags);
2351
2352         if (!video->dma_running)
2353                 goto out;
2354
2355         /* check IT context */
2356         if (video->ohci_it_ctx != -1) {
2357                 u32 ctx;
2358
2359                 ctx = reg_read(video->ohci, video->ohci_IsoXmitContextControlSet);
2360
2361                 /* if (RUN but not ACTIVE) */
2362                 if ( (ctx & (1<<15)) &&
2363                     !(ctx & (1<<10)) ) {
2364
2365                         debug_printk("dv1394: IT context stopped due to bus reset; waking it up\n");
2366
2367                         /* to be safe, assume a frame has been dropped. User-space programs
2368                            should handle this condition like an underflow. */
2369                         video->dropped_frames++;
2370
2371                         /* for some reason you must clear, then re-set the RUN bit to restart DMA */
2372
2373                         /* clear RUN */
2374                         reg_write(video->ohci, video->ohci_IsoXmitContextControlClear, (1 << 15));
2375                         flush_pci_write(video->ohci);
2376
2377                         /* set RUN */
2378                         reg_write(video->ohci, video->ohci_IsoXmitContextControlSet, (1 << 15));
2379                         flush_pci_write(video->ohci);
2380
2381                         /* set the WAKE bit (just in case; this isn't strictly necessary) */
2382                         reg_write(video->ohci, video->ohci_IsoXmitContextControlSet, (1 << 12));
2383                         flush_pci_write(video->ohci);
2384
2385                         irq_printk("dv1394: AFTER IT restart ctx 0x%08x ptr 0x%08x\n",
2386                                    reg_read(video->ohci, video->ohci_IsoXmitContextControlSet),
2387                                    reg_read(video->ohci, video->ohci_IsoXmitCommandPtr));
2388                 }
2389         }
2390
2391         /* check IR context */
2392         if (video->ohci_ir_ctx != -1) {
2393                 u32 ctx;
2394
2395                 ctx = reg_read(video->ohci, video->ohci_IsoRcvContextControlSet);
2396
2397                 /* if (RUN but not ACTIVE) */
2398                 if ( (ctx & (1<<15)) &&
2399                     !(ctx & (1<<10)) ) {
2400
2401                         debug_printk("dv1394: IR context stopped due to bus reset; waking it up\n");
2402
2403                         /* to be safe, assume a frame has been dropped. User-space programs
2404                            should handle this condition like an overflow. */
2405                         video->dropped_frames++;
2406
2407                         /* for some reason you must clear, then re-set the RUN bit to restart DMA */
2408                         /* XXX this doesn't work for me, I can't get IR DMA to restart :[ */
2409
2410                         /* clear RUN */
2411                         reg_write(video->ohci, video->ohci_IsoRcvContextControlClear, (1 << 15));
2412                         flush_pci_write(video->ohci);
2413
2414                         /* set RUN */
2415                         reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, (1 << 15));
2416                         flush_pci_write(video->ohci);
2417
2418                         /* set the WAKE bit (just in case; this isn't strictly necessary) */
2419                         reg_write(video->ohci, video->ohci_IsoRcvContextControlSet, (1 << 12));
2420                         flush_pci_write(video->ohci);
2421
2422                         irq_printk("dv1394: AFTER IR restart ctx 0x%08x ptr 0x%08x\n",
2423                                    reg_read(video->ohci, video->ohci_IsoRcvContextControlSet),
2424                                    reg_read(video->ohci, video->ohci_IsoRcvCommandPtr));
2425                 }
2426         }
2427
2428 out:
2429         spin_unlock_irqrestore(&video->spinlock, flags);
2430
2431         /* wake readers/writers/ioctl'ers */
2432         wake_up_interruptible(&video->waitq);
2433 }
2434
2435 static struct hpsb_highlevel dv1394_highlevel = {
2436         .name =         "dv1394",
2437         .add_host =     dv1394_add_host,
2438         .remove_host =  dv1394_remove_host,
2439         .host_reset =   dv1394_host_reset,
2440 };
2441
2442 #ifdef CONFIG_COMPAT
2443
2444 #define DV1394_IOC32_INIT       _IOW('#', 0x06, struct dv1394_init32)
2445 #define DV1394_IOC32_GET_STATUS _IOR('#', 0x0c, struct dv1394_status32)
2446
2447 struct dv1394_init32 {
2448         u32 api_version;
2449         u32 channel;
2450         u32 n_frames;
2451         u32 format;
2452         u32 cip_n;
2453         u32 cip_d;
2454         u32 syt_offset;
2455 };
2456
2457 struct dv1394_status32 {
2458         struct dv1394_init32 init;
2459         s32 active_frame;
2460         u32 first_clear_frame;
2461         u32 n_clear_frames;
2462         u32 dropped_frames;
2463 };
2464
2465 /* RED-PEN: this should use compat_alloc_userspace instead */
2466
2467 static int handle_dv1394_init(struct file *file, unsigned int cmd, unsigned long arg)
2468 {
2469         struct dv1394_init32 dv32;
2470         struct dv1394_init dv;
2471         mm_segment_t old_fs;
2472         int ret;
2473
2474         if (file->f_op->unlocked_ioctl != dv1394_ioctl)
2475                 return -EFAULT;
2476
2477         if (copy_from_user(&dv32, (void __user *)arg, sizeof(dv32)))
2478                 return -EFAULT;
2479
2480         dv.api_version = dv32.api_version;
2481         dv.channel = dv32.channel;
2482         dv.n_frames = dv32.n_frames;
2483         dv.format = dv32.format;
2484         dv.cip_n = (unsigned long)dv32.cip_n;
2485         dv.cip_d = (unsigned long)dv32.cip_d;
2486         dv.syt_offset = dv32.syt_offset;
2487
2488         old_fs = get_fs();
2489         set_fs(KERNEL_DS);
2490         ret = dv1394_ioctl(file, DV1394_IOC_INIT, (unsigned long)&dv);
2491         set_fs(old_fs);
2492
2493         return ret;
2494 }
2495
2496 static int handle_dv1394_get_status(struct file *file, unsigned int cmd, unsigned long arg)
2497 {
2498         struct dv1394_status32 dv32;
2499         struct dv1394_status dv;
2500         mm_segment_t old_fs;
2501         int ret;
2502
2503         if (file->f_op->unlocked_ioctl != dv1394_ioctl)
2504                 return -EFAULT;
2505
2506         old_fs = get_fs();
2507         set_fs(KERNEL_DS);
2508         ret = dv1394_ioctl(file, DV1394_IOC_GET_STATUS, (unsigned long)&dv);
2509         set_fs(old_fs);
2510
2511         if (!ret) {
2512                 dv32.init.api_version = dv.init.api_version;
2513                 dv32.init.channel = dv.init.channel;
2514                 dv32.init.n_frames = dv.init.n_frames;
2515                 dv32.init.format = dv.init.format;
2516                 dv32.init.cip_n = (u32)dv.init.cip_n;
2517                 dv32.init.cip_d = (u32)dv.init.cip_d;
2518                 dv32.init.syt_offset = dv.init.syt_offset;
2519                 dv32.active_frame = dv.active_frame;
2520                 dv32.first_clear_frame = dv.first_clear_frame;
2521                 dv32.n_clear_frames = dv.n_clear_frames;
2522                 dv32.dropped_frames = dv.dropped_frames;
2523
2524                 if (copy_to_user((struct dv1394_status32 __user *)arg, &dv32, sizeof(dv32)))
2525                         ret = -EFAULT;
2526         }
2527
2528         return ret;
2529 }
2530
2531
2532
2533 static long dv1394_compat_ioctl(struct file *file, unsigned int cmd,
2534                                unsigned long arg)
2535 {
2536         switch (cmd) {
2537         case DV1394_IOC_SHUTDOWN:
2538         case DV1394_IOC_SUBMIT_FRAMES:
2539         case DV1394_IOC_WAIT_FRAMES:
2540         case DV1394_IOC_RECEIVE_FRAMES:
2541         case DV1394_IOC_START_RECEIVE:
2542                 return dv1394_ioctl(file, cmd, arg);
2543
2544         case DV1394_IOC32_INIT:
2545                 return handle_dv1394_init(file, cmd, arg);
2546         case DV1394_IOC32_GET_STATUS:
2547                 return handle_dv1394_get_status(file, cmd, arg);
2548         default:
2549                 return -ENOIOCTLCMD;
2550         }
2551 }
2552
2553 #endif /* CONFIG_COMPAT */
2554
2555
2556 /*** KERNEL MODULE HANDLERS ************************************************/
2557
2558 MODULE_AUTHOR("Dan Maas <dmaas@dcine.com>, Dan Dennedy <dan@dennedy.org>");
2559 MODULE_DESCRIPTION("driver for DV input/output on OHCI board");
2560 MODULE_SUPPORTED_DEVICE("dv1394");
2561 MODULE_LICENSE("GPL");
2562
2563 static void __exit dv1394_exit_module(void)
2564 {
2565         hpsb_unregister_protocol(&dv1394_driver);
2566         hpsb_unregister_highlevel(&dv1394_highlevel);
2567         cdev_del(&dv1394_cdev);
2568 }
2569
2570 static int __init dv1394_init_module(void)
2571 {
2572         int ret;
2573
2574         cdev_init(&dv1394_cdev, &dv1394_fops);
2575         dv1394_cdev.owner = THIS_MODULE;
2576         ret = cdev_add(&dv1394_cdev, IEEE1394_DV1394_DEV, 16);
2577         if (ret) {
2578                 printk(KERN_ERR "dv1394: unable to register character device\n");
2579                 return ret;
2580         }
2581
2582         hpsb_register_highlevel(&dv1394_highlevel);
2583
2584         ret = hpsb_register_protocol(&dv1394_driver);
2585         if (ret) {
2586                 printk(KERN_ERR "dv1394: failed to register protocol\n");
2587                 hpsb_unregister_highlevel(&dv1394_highlevel);
2588                 cdev_del(&dv1394_cdev);
2589                 return ret;
2590         }
2591
2592         return 0;
2593 }
2594
2595 module_init(dv1394_init_module);
2596 module_exit(dv1394_exit_module);