Merge branch 'i2c-next' of git://aeryn.fluff.org.uk/bjdooks/linux
[linux-2.6.git] / drivers / i2c / busses / i2c-omap.c
1 /*
2  * TI OMAP I2C master mode driver
3  *
4  * Copyright (C) 2003 MontaVista Software, Inc.
5  * Copyright (C) 2005 Nokia Corporation
6  * Copyright (C) 2004 - 2007 Texas Instruments.
7  *
8  * Originally written by MontaVista Software, Inc.
9  * Additional contributions by:
10  *      Tony Lindgren <tony@atomide.com>
11  *      Imre Deak <imre.deak@nokia.com>
12  *      Juha Yrjölä <juha.yrjola@solidboot.com>
13  *      Syed Khasim <x0khasim@ti.com>
14  *      Nishant Menon <nm@ti.com>
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License as published by
18  * the Free Software Foundation; either version 2 of the License, or
19  * (at your option) any later version.
20  *
21  * This program is distributed in the hope that it will be useful,
22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24  * GNU General Public License for more details.
25  *
26  * You should have received a copy of the GNU General Public License
27  * along with this program; if not, write to the Free Software
28  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29  */
30
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
39 #include <linux/io.h>
40
41 /* I2C controller revisions */
42 #define OMAP_I2C_REV_2                  0x20
43
44 /* I2C controller revisions present on specific hardware */
45 #define OMAP_I2C_REV_ON_2430            0x36
46 #define OMAP_I2C_REV_ON_3430            0x3C
47
48 /* timeout waiting for the controller to respond */
49 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
50
51 #define OMAP_I2C_REV_REG                0x00
52 #define OMAP_I2C_IE_REG                 0x04
53 #define OMAP_I2C_STAT_REG               0x08
54 #define OMAP_I2C_IV_REG                 0x0c
55 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56 #define OMAP_I2C_WE_REG                 0x0c
57 #define OMAP_I2C_SYSS_REG               0x10
58 #define OMAP_I2C_BUF_REG                0x14
59 #define OMAP_I2C_CNT_REG                0x18
60 #define OMAP_I2C_DATA_REG               0x1c
61 #define OMAP_I2C_SYSC_REG               0x20
62 #define OMAP_I2C_CON_REG                0x24
63 #define OMAP_I2C_OA_REG                 0x28
64 #define OMAP_I2C_SA_REG                 0x2c
65 #define OMAP_I2C_PSC_REG                0x30
66 #define OMAP_I2C_SCLL_REG               0x34
67 #define OMAP_I2C_SCLH_REG               0x38
68 #define OMAP_I2C_SYSTEST_REG            0x3c
69 #define OMAP_I2C_BUFSTAT_REG            0x40
70
71 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
72 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer drain int enable */
73 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer drain int enable */
74 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
75 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
76 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
77 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
78 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
79
80 /* I2C Status Register (OMAP_I2C_STAT): */
81 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
82 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
83 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
84 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
85 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
86 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
87 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
88 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
89 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
90 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
91 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
92 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
93
94 /* I2C WE wakeup enable register */
95 #define OMAP_I2C_WE_XDR_WE      (1 << 14)       /* TX drain wakup */
96 #define OMAP_I2C_WE_RDR_WE      (1 << 13)       /* RX drain wakeup */
97 #define OMAP_I2C_WE_AAS_WE      (1 << 9)        /* Address as slave wakeup*/
98 #define OMAP_I2C_WE_BF_WE       (1 << 8)        /* Bus free wakeup */
99 #define OMAP_I2C_WE_STC_WE      (1 << 6)        /* Start condition wakeup */
100 #define OMAP_I2C_WE_GC_WE       (1 << 5)        /* General call wakeup */
101 #define OMAP_I2C_WE_DRDY_WE     (1 << 3)        /* TX/RX data ready wakeup */
102 #define OMAP_I2C_WE_ARDY_WE     (1 << 2)        /* Reg access ready wakeup */
103 #define OMAP_I2C_WE_NACK_WE     (1 << 1)        /* No acknowledgment wakeup */
104 #define OMAP_I2C_WE_AL_WE       (1 << 0)        /* Arbitration lost wakeup */
105
106 #define OMAP_I2C_WE_ALL         (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
107                                 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
108                                 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
109                                 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
110                                 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
111
112 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
113 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
114 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
115 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
116 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
117
118 /* I2C Configuration Register (OMAP_I2C_CON): */
119 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
120 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
121 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
122 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
123 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
124 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
125 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
126 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
127 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
128 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
129
130 /* I2C SCL time value when Master */
131 #define OMAP_I2C_SCLL_HSSCLL    8
132 #define OMAP_I2C_SCLH_HSSCLH    8
133
134 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
135 #ifdef DEBUG
136 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
137 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
138 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
139 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
140 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
141 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
142 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
143 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
144 #endif
145
146 /* OCP_SYSSTATUS bit definitions */
147 #define SYSS_RESETDONE_MASK             (1 << 0)
148
149 /* OCP_SYSCONFIG bit definitions */
150 #define SYSC_CLOCKACTIVITY_MASK         (0x3 << 8)
151 #define SYSC_SIDLEMODE_MASK             (0x3 << 3)
152 #define SYSC_ENAWAKEUP_MASK             (1 << 2)
153 #define SYSC_SOFTRESET_MASK             (1 << 1)
154 #define SYSC_AUTOIDLE_MASK              (1 << 0)
155
156 #define SYSC_IDLEMODE_SMART             0x2
157 #define SYSC_CLOCKACTIVITY_FCLK         0x2
158
159
160 struct omap_i2c_dev {
161         struct device           *dev;
162         void __iomem            *base;          /* virtual */
163         int                     irq;
164         struct clk              *iclk;          /* Interface clock */
165         struct clk              *fclk;          /* Functional clock */
166         struct completion       cmd_complete;
167         struct resource         *ioarea;
168         u32                     speed;          /* Speed of bus in Khz */
169         u16                     cmd_err;
170         u8                      *buf;
171         size_t                  buf_len;
172         struct i2c_adapter      adapter;
173         u8                      fifo_size;      /* use as flag and value
174                                                  * fifo_size==0 implies no fifo
175                                                  * if set, should be trsh+1
176                                                  */
177         u8                      rev;
178         unsigned                b_hw:1;         /* bad h/w fixes */
179         unsigned                idle:1;
180         u16                     iestate;        /* Saved interrupt register */
181 };
182
183 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
184                                       int reg, u16 val)
185 {
186         __raw_writew(val, i2c_dev->base + reg);
187 }
188
189 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
190 {
191         return __raw_readw(i2c_dev->base + reg);
192 }
193
194 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
195 {
196         if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
197                 dev->iclk = clk_get(dev->dev, "i2c_ick");
198                 if (IS_ERR(dev->iclk)) {
199                         dev->iclk = NULL;
200                         return -ENODEV;
201                 }
202         }
203
204         dev->fclk = clk_get(dev->dev, "i2c_fck");
205         if (IS_ERR(dev->fclk)) {
206                 if (dev->iclk != NULL) {
207                         clk_put(dev->iclk);
208                         dev->iclk = NULL;
209                 }
210                 dev->fclk = NULL;
211                 return -ENODEV;
212         }
213
214         return 0;
215 }
216
217 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
218 {
219         clk_put(dev->fclk);
220         dev->fclk = NULL;
221         if (dev->iclk != NULL) {
222                 clk_put(dev->iclk);
223                 dev->iclk = NULL;
224         }
225 }
226
227 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
228 {
229         WARN_ON(!dev->idle);
230
231         if (dev->iclk != NULL)
232                 clk_enable(dev->iclk);
233         clk_enable(dev->fclk);
234         dev->idle = 0;
235         if (dev->iestate)
236                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
237 }
238
239 static void omap_i2c_idle(struct omap_i2c_dev *dev)
240 {
241         u16 iv;
242
243         WARN_ON(dev->idle);
244
245         dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
246         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
247         if (dev->rev < OMAP_I2C_REV_2) {
248                 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
249         } else {
250                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
251
252                 /* Flush posted write before the dev->idle store occurs */
253                 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
254         }
255         dev->idle = 1;
256         clk_disable(dev->fclk);
257         if (dev->iclk != NULL)
258                 clk_disable(dev->iclk);
259 }
260
261 static int omap_i2c_init(struct omap_i2c_dev *dev)
262 {
263         u16 psc = 0, scll = 0, sclh = 0;
264         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
265         unsigned long fclk_rate = 12000000;
266         unsigned long timeout;
267         unsigned long internal_clk = 0;
268
269         if (dev->rev >= OMAP_I2C_REV_2) {
270                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
271                 /* For some reason we need to set the EN bit before the
272                  * reset done bit gets set. */
273                 timeout = jiffies + OMAP_I2C_TIMEOUT;
274                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
275                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
276                          SYSS_RESETDONE_MASK)) {
277                         if (time_after(jiffies, timeout)) {
278                                 dev_warn(dev->dev, "timeout waiting "
279                                                 "for controller reset\n");
280                                 return -ETIMEDOUT;
281                         }
282                         msleep(1);
283                 }
284
285                 /* SYSC register is cleared by the reset; rewrite it */
286                 if (dev->rev == OMAP_I2C_REV_ON_2430) {
287
288                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
289                                            SYSC_AUTOIDLE_MASK);
290
291                 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
292                         u32 v;
293
294                         v = SYSC_AUTOIDLE_MASK;
295                         v |= SYSC_ENAWAKEUP_MASK;
296                         v |= (SYSC_IDLEMODE_SMART <<
297                               __ffs(SYSC_SIDLEMODE_MASK));
298                         v |= (SYSC_CLOCKACTIVITY_FCLK <<
299                               __ffs(SYSC_CLOCKACTIVITY_MASK));
300
301                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, v);
302                         /*
303                          * Enabling all wakup sources to stop I2C freezing on
304                          * WFI instruction.
305                          * REVISIT: Some wkup sources might not be needed.
306                          */
307                         omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
308                                                         OMAP_I2C_WE_ALL);
309
310                 }
311         }
312         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
313
314         if (cpu_class_is_omap1()) {
315                 struct clk *armxor_ck;
316
317                 armxor_ck = clk_get(NULL, "armxor_ck");
318                 if (IS_ERR(armxor_ck))
319                         dev_warn(dev->dev, "Could not get armxor_ck\n");
320                 else {
321                         fclk_rate = clk_get_rate(armxor_ck);
322                         clk_put(armxor_ck);
323                 }
324                 /* TRM for 5912 says the I2C clock must be prescaled to be
325                  * between 7 - 12 MHz. The XOR input clock is typically
326                  * 12, 13 or 19.2 MHz. So we should have code that produces:
327                  *
328                  * XOR MHz      Divider         Prescaler
329                  * 12           1               0
330                  * 13           2               1
331                  * 19.2         2               1
332                  */
333                 if (fclk_rate > 12000000)
334                         psc = fclk_rate / 12000000;
335         }
336
337         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
338
339                 /* HSI2C controller internal clk rate should be 19.2 Mhz */
340                 internal_clk = 19200;
341                 fclk_rate = clk_get_rate(dev->fclk) / 1000;
342
343                 /* Compute prescaler divisor */
344                 psc = fclk_rate / internal_clk;
345                 psc = psc - 1;
346
347                 /* If configured for High Speed */
348                 if (dev->speed > 400) {
349                         /* For first phase of HS mode */
350                         fsscll = internal_clk / (400 * 2) - 6;
351                         fssclh = internal_clk / (400 * 2) - 6;
352
353                         /* For second phase of HS mode */
354                         hsscll = fclk_rate / (dev->speed * 2) - 6;
355                         hssclh = fclk_rate / (dev->speed * 2) - 6;
356                 } else {
357                         /* To handle F/S modes */
358                         fsscll = internal_clk / (dev->speed * 2) - 6;
359                         fssclh = internal_clk / (dev->speed * 2) - 6;
360                 }
361                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
362                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
363         } else {
364                 /* Program desired operating rate */
365                 fclk_rate /= (psc + 1) * 1000;
366                 if (psc > 2)
367                         psc = 2;
368                 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
369                 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
370         }
371
372         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
373         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
374
375         /* SCL low and high time values */
376         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
377         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
378
379         if (dev->fifo_size)
380                 /* Note: setup required fifo size - 1 */
381                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
382                                         (dev->fifo_size - 1) << 8 | /* RTRSH */
383                                         OMAP_I2C_BUF_RXFIF_CLR |
384                                         (dev->fifo_size - 1) | /* XTRSH */
385                                         OMAP_I2C_BUF_TXFIF_CLR);
386
387         /* Take the I2C module out of reset: */
388         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
389
390         /* Enable interrupts */
391         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
392                         (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
393                         OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
394                         OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
395                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
396         return 0;
397 }
398
399 /*
400  * Waiting on Bus Busy
401  */
402 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
403 {
404         unsigned long timeout;
405
406         timeout = jiffies + OMAP_I2C_TIMEOUT;
407         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
408                 if (time_after(jiffies, timeout)) {
409                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
410                         return -ETIMEDOUT;
411                 }
412                 msleep(1);
413         }
414
415         return 0;
416 }
417
418 /*
419  * Low level master read/write transaction.
420  */
421 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
422                              struct i2c_msg *msg, int stop)
423 {
424         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
425         int r;
426         u16 w;
427
428         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
429                 msg->addr, msg->len, msg->flags, stop);
430
431         if (msg->len == 0)
432                 return -EINVAL;
433
434         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
435
436         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
437         dev->buf = msg->buf;
438         dev->buf_len = msg->len;
439
440         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
441
442         /* Clear the FIFO Buffers */
443         w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
444         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
445         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
446
447         init_completion(&dev->cmd_complete);
448         dev->cmd_err = 0;
449
450         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
451
452         /* High speed configuration */
453         if (dev->speed > 400)
454                 w |= OMAP_I2C_CON_OPMODE_HS;
455
456         if (msg->flags & I2C_M_TEN)
457                 w |= OMAP_I2C_CON_XA;
458         if (!(msg->flags & I2C_M_RD))
459                 w |= OMAP_I2C_CON_TRX;
460
461         if (!dev->b_hw && stop)
462                 w |= OMAP_I2C_CON_STP;
463
464         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
465
466         /*
467          * Don't write stt and stp together on some hardware.
468          */
469         if (dev->b_hw && stop) {
470                 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
471                 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
472                 while (con & OMAP_I2C_CON_STT) {
473                         con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
474
475                         /* Let the user know if i2c is in a bad state */
476                         if (time_after(jiffies, delay)) {
477                                 dev_err(dev->dev, "controller timed out "
478                                 "waiting for start condition to finish\n");
479                                 return -ETIMEDOUT;
480                         }
481                         cpu_relax();
482                 }
483
484                 w |= OMAP_I2C_CON_STP;
485                 w &= ~OMAP_I2C_CON_STT;
486                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
487         }
488
489         /*
490          * REVISIT: We should abort the transfer on signals, but the bus goes
491          * into arbitration and we're currently unable to recover from it.
492          */
493         r = wait_for_completion_timeout(&dev->cmd_complete,
494                                         OMAP_I2C_TIMEOUT);
495         dev->buf_len = 0;
496         if (r < 0)
497                 return r;
498         if (r == 0) {
499                 dev_err(dev->dev, "controller timed out\n");
500                 omap_i2c_init(dev);
501                 return -ETIMEDOUT;
502         }
503
504         if (likely(!dev->cmd_err))
505                 return 0;
506
507         /* We have an error */
508         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
509                             OMAP_I2C_STAT_XUDF)) {
510                 omap_i2c_init(dev);
511                 return -EIO;
512         }
513
514         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
515                 if (msg->flags & I2C_M_IGNORE_NAK)
516                         return 0;
517                 if (stop) {
518                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
519                         w |= OMAP_I2C_CON_STP;
520                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
521                 }
522                 return -EREMOTEIO;
523         }
524         return -EIO;
525 }
526
527
528 /*
529  * Prepare controller for a transaction and call omap_i2c_xfer_msg
530  * to do the work during IRQ processing.
531  */
532 static int
533 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
534 {
535         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
536         int i;
537         int r;
538
539         omap_i2c_unidle(dev);
540
541         r = omap_i2c_wait_for_bb(dev);
542         if (r < 0)
543                 goto out;
544
545         for (i = 0; i < num; i++) {
546                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
547                 if (r != 0)
548                         break;
549         }
550
551         if (r == 0)
552                 r = num;
553 out:
554         omap_i2c_idle(dev);
555         return r;
556 }
557
558 static u32
559 omap_i2c_func(struct i2c_adapter *adap)
560 {
561         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
562 }
563
564 static inline void
565 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
566 {
567         dev->cmd_err |= err;
568         complete(&dev->cmd_complete);
569 }
570
571 static inline void
572 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
573 {
574         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
575 }
576
577 /* rev1 devices are apparently only on some 15xx */
578 #ifdef CONFIG_ARCH_OMAP15XX
579
580 static irqreturn_t
581 omap_i2c_rev1_isr(int this_irq, void *dev_id)
582 {
583         struct omap_i2c_dev *dev = dev_id;
584         u16 iv, w;
585
586         if (dev->idle)
587                 return IRQ_NONE;
588
589         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
590         switch (iv) {
591         case 0x00:      /* None */
592                 break;
593         case 0x01:      /* Arbitration lost */
594                 dev_err(dev->dev, "Arbitration lost\n");
595                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
596                 break;
597         case 0x02:      /* No acknowledgement */
598                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
599                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
600                 break;
601         case 0x03:      /* Register access ready */
602                 omap_i2c_complete_cmd(dev, 0);
603                 break;
604         case 0x04:      /* Receive data ready */
605                 if (dev->buf_len) {
606                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
607                         *dev->buf++ = w;
608                         dev->buf_len--;
609                         if (dev->buf_len) {
610                                 *dev->buf++ = w >> 8;
611                                 dev->buf_len--;
612                         }
613                 } else
614                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
615                 break;
616         case 0x05:      /* Transmit data ready */
617                 if (dev->buf_len) {
618                         w = *dev->buf++;
619                         dev->buf_len--;
620                         if (dev->buf_len) {
621                                 w |= *dev->buf++ << 8;
622                                 dev->buf_len--;
623                         }
624                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
625                 } else
626                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
627                 break;
628         default:
629                 return IRQ_NONE;
630         }
631
632         return IRQ_HANDLED;
633 }
634 #else
635 #define omap_i2c_rev1_isr               NULL
636 #endif
637
638 static irqreturn_t
639 omap_i2c_isr(int this_irq, void *dev_id)
640 {
641         struct omap_i2c_dev *dev = dev_id;
642         u16 bits;
643         u16 stat, w;
644         int err, count = 0;
645
646         if (dev->idle)
647                 return IRQ_NONE;
648
649         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
650         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
651                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
652                 if (count++ == 100) {
653                         dev_warn(dev->dev, "Too much work in one IRQ\n");
654                         break;
655                 }
656
657                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
658
659                 err = 0;
660                 if (stat & OMAP_I2C_STAT_NACK) {
661                         err |= OMAP_I2C_STAT_NACK;
662                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
663                                            OMAP_I2C_CON_STP);
664                 }
665                 if (stat & OMAP_I2C_STAT_AL) {
666                         dev_err(dev->dev, "Arbitration lost\n");
667                         err |= OMAP_I2C_STAT_AL;
668                 }
669                 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
670                                         OMAP_I2C_STAT_AL))
671                         omap_i2c_complete_cmd(dev, err);
672                 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
673                         u8 num_bytes = 1;
674                         if (dev->fifo_size) {
675                                 if (stat & OMAP_I2C_STAT_RRDY)
676                                         num_bytes = dev->fifo_size;
677                                 else
678                                         num_bytes = omap_i2c_read_reg(dev,
679                                                         OMAP_I2C_BUFSTAT_REG);
680                         }
681                         while (num_bytes) {
682                                 num_bytes--;
683                                 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
684                                 if (dev->buf_len) {
685                                         *dev->buf++ = w;
686                                         dev->buf_len--;
687                                         /* Data reg from 2430 is 8 bit wide */
688                                         if (!cpu_is_omap2430() &&
689                                                         !cpu_is_omap34xx()) {
690                                                 if (dev->buf_len) {
691                                                         *dev->buf++ = w >> 8;
692                                                         dev->buf_len--;
693                                                 }
694                                         }
695                                 } else {
696                                         if (stat & OMAP_I2C_STAT_RRDY)
697                                                 dev_err(dev->dev,
698                                                         "RRDY IRQ while no data"
699                                                                 " requested\n");
700                                         if (stat & OMAP_I2C_STAT_RDR)
701                                                 dev_err(dev->dev,
702                                                         "RDR IRQ while no data"
703                                                                 " requested\n");
704                                         break;
705                                 }
706                         }
707                         omap_i2c_ack_stat(dev,
708                                 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
709                         continue;
710                 }
711                 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
712                         u8 num_bytes = 1;
713                         if (dev->fifo_size) {
714                                 if (stat & OMAP_I2C_STAT_XRDY)
715                                         num_bytes = dev->fifo_size;
716                                 else
717                                         num_bytes = omap_i2c_read_reg(dev,
718                                                         OMAP_I2C_BUFSTAT_REG);
719                         }
720                         while (num_bytes) {
721                                 num_bytes--;
722                                 w = 0;
723                                 if (dev->buf_len) {
724                                         w = *dev->buf++;
725                                         dev->buf_len--;
726                                         /* Data reg from  2430 is 8 bit wide */
727                                         if (!cpu_is_omap2430() &&
728                                                         !cpu_is_omap34xx()) {
729                                                 if (dev->buf_len) {
730                                                         w |= *dev->buf++ << 8;
731                                                         dev->buf_len--;
732                                                 }
733                                         }
734                                 } else {
735                                         if (stat & OMAP_I2C_STAT_XRDY)
736                                                 dev_err(dev->dev,
737                                                         "XRDY IRQ while no "
738                                                         "data to send\n");
739                                         if (stat & OMAP_I2C_STAT_XDR)
740                                                 dev_err(dev->dev,
741                                                         "XDR IRQ while no "
742                                                         "data to send\n");
743                                         break;
744                                 }
745                                 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
746                         }
747                         omap_i2c_ack_stat(dev,
748                                 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
749                         continue;
750                 }
751                 if (stat & OMAP_I2C_STAT_ROVR) {
752                         dev_err(dev->dev, "Receive overrun\n");
753                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
754                 }
755                 if (stat & OMAP_I2C_STAT_XUDF) {
756                         dev_err(dev->dev, "Transmit underflow\n");
757                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
758                 }
759         }
760
761         return count ? IRQ_HANDLED : IRQ_NONE;
762 }
763
764 static const struct i2c_algorithm omap_i2c_algo = {
765         .master_xfer    = omap_i2c_xfer,
766         .functionality  = omap_i2c_func,
767 };
768
769 static int __init
770 omap_i2c_probe(struct platform_device *pdev)
771 {
772         struct omap_i2c_dev     *dev;
773         struct i2c_adapter      *adap;
774         struct resource         *mem, *irq, *ioarea;
775         irq_handler_t isr;
776         int r;
777         u32 speed = 0;
778
779         /* NOTE: driver uses the static register mapping */
780         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
781         if (!mem) {
782                 dev_err(&pdev->dev, "no mem resource?\n");
783                 return -ENODEV;
784         }
785         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
786         if (!irq) {
787                 dev_err(&pdev->dev, "no irq resource?\n");
788                 return -ENODEV;
789         }
790
791         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
792                         pdev->name);
793         if (!ioarea) {
794                 dev_err(&pdev->dev, "I2C region already claimed\n");
795                 return -EBUSY;
796         }
797
798         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
799         if (!dev) {
800                 r = -ENOMEM;
801                 goto err_release_region;
802         }
803
804         if (pdev->dev.platform_data != NULL)
805                 speed = *(u32 *)pdev->dev.platform_data;
806         else
807                 speed = 100;    /* Defualt speed */
808
809         dev->speed = speed;
810         dev->idle = 1;
811         dev->dev = &pdev->dev;
812         dev->irq = irq->start;
813         dev->base = ioremap(mem->start, mem->end - mem->start + 1);
814         if (!dev->base) {
815                 r = -ENOMEM;
816                 goto err_free_mem;
817         }
818
819         platform_set_drvdata(pdev, dev);
820
821         if ((r = omap_i2c_get_clocks(dev)) != 0)
822                 goto err_iounmap;
823
824         omap_i2c_unidle(dev);
825
826         dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
827
828         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
829                 u16 s;
830
831                 /* Set up the fifo size - Get total size */
832                 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
833                 dev->fifo_size = 0x8 << s;
834
835                 /*
836                  * Set up notification threshold as half the total available
837                  * size. This is to ensure that we can handle the status on int
838                  * call back latencies.
839                  */
840                 dev->fifo_size = (dev->fifo_size / 2);
841                 dev->b_hw = 1; /* Enable hardware fixes */
842         }
843
844         /* reset ASAP, clearing any IRQs */
845         omap_i2c_init(dev);
846
847         isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
848         r = request_irq(dev->irq, isr, 0, pdev->name, dev);
849
850         if (r) {
851                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
852                 goto err_unuse_clocks;
853         }
854
855         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
856                  pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
857
858         omap_i2c_idle(dev);
859
860         adap = &dev->adapter;
861         i2c_set_adapdata(adap, dev);
862         adap->owner = THIS_MODULE;
863         adap->class = I2C_CLASS_HWMON;
864         strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
865         adap->algo = &omap_i2c_algo;
866         adap->dev.parent = &pdev->dev;
867
868         /* i2c device drivers may be active on return from add_adapter() */
869         adap->nr = pdev->id;
870         r = i2c_add_numbered_adapter(adap);
871         if (r) {
872                 dev_err(dev->dev, "failure adding adapter\n");
873                 goto err_free_irq;
874         }
875
876         return 0;
877
878 err_free_irq:
879         free_irq(dev->irq, dev);
880 err_unuse_clocks:
881         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
882         omap_i2c_idle(dev);
883         omap_i2c_put_clocks(dev);
884 err_iounmap:
885         iounmap(dev->base);
886 err_free_mem:
887         platform_set_drvdata(pdev, NULL);
888         kfree(dev);
889 err_release_region:
890         release_mem_region(mem->start, (mem->end - mem->start) + 1);
891
892         return r;
893 }
894
895 static int
896 omap_i2c_remove(struct platform_device *pdev)
897 {
898         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
899         struct resource         *mem;
900
901         platform_set_drvdata(pdev, NULL);
902
903         free_irq(dev->irq, dev);
904         i2c_del_adapter(&dev->adapter);
905         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
906         omap_i2c_put_clocks(dev);
907         iounmap(dev->base);
908         kfree(dev);
909         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
910         release_mem_region(mem->start, (mem->end - mem->start) + 1);
911         return 0;
912 }
913
914 static struct platform_driver omap_i2c_driver = {
915         .probe          = omap_i2c_probe,
916         .remove         = omap_i2c_remove,
917         .driver         = {
918                 .name   = "i2c_omap",
919                 .owner  = THIS_MODULE,
920         },
921 };
922
923 /* I2C may be needed to bring up other drivers */
924 static int __init
925 omap_i2c_init_driver(void)
926 {
927         return platform_driver_register(&omap_i2c_driver);
928 }
929 subsys_initcall(omap_i2c_init_driver);
930
931 static void __exit omap_i2c_exit_driver(void)
932 {
933         platform_driver_unregister(&omap_i2c_driver);
934 }
935 module_exit(omap_i2c_exit_driver);
936
937 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
938 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
939 MODULE_LICENSE("GPL");
940 MODULE_ALIAS("platform:i2c_omap");