drm/radeon/kms/pm/r600: select the mid clock mode for single head low profile
[linux-2.6.git] / drivers / gpu / drm / radeon / r600.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
32 #include "drmP.h"
33 #include "radeon_drm.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "radeon_mode.h"
37 #include "r600d.h"
38 #include "atom.h"
39 #include "avivod.h"
40
41 #define PFP_UCODE_SIZE 576
42 #define PM4_UCODE_SIZE 1792
43 #define RLC_UCODE_SIZE 768
44 #define R700_PFP_UCODE_SIZE 848
45 #define R700_PM4_UCODE_SIZE 1360
46 #define R700_RLC_UCODE_SIZE 1024
47 #define EVERGREEN_PFP_UCODE_SIZE 1120
48 #define EVERGREEN_PM4_UCODE_SIZE 1376
49 #define EVERGREEN_RLC_UCODE_SIZE 768
50
51 /* Firmware Names */
52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
53 MODULE_FIRMWARE("radeon/R600_me.bin");
54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
55 MODULE_FIRMWARE("radeon/RV610_me.bin");
56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
57 MODULE_FIRMWARE("radeon/RV630_me.bin");
58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
59 MODULE_FIRMWARE("radeon/RV620_me.bin");
60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
61 MODULE_FIRMWARE("radeon/RV635_me.bin");
62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
63 MODULE_FIRMWARE("radeon/RV670_me.bin");
64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
65 MODULE_FIRMWARE("radeon/RS780_me.bin");
66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
67 MODULE_FIRMWARE("radeon/RV770_me.bin");
68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
69 MODULE_FIRMWARE("radeon/RV730_me.bin");
70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
71 MODULE_FIRMWARE("radeon/RV710_me.bin");
72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
86
87 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
88
89 /* r600,rv610,rv630,rv620,rv635,rv670 */
90 int r600_mc_wait_for_idle(struct radeon_device *rdev);
91 void r600_gpu_init(struct radeon_device *rdev);
92 void r600_fini(struct radeon_device *rdev);
93 void r600_irq_disable(struct radeon_device *rdev);
94
95 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
96 {
97         int i;
98
99         rdev->pm.dynpm_can_upclock = true;
100         rdev->pm.dynpm_can_downclock = true;
101
102         /* power state array is low to high, default is first */
103         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
104                 int min_power_state_index = 0;
105
106                 if (rdev->pm.num_power_states > 2)
107                         min_power_state_index = 1;
108
109                 switch (rdev->pm.dynpm_planned_action) {
110                 case DYNPM_ACTION_MINIMUM:
111                         rdev->pm.requested_power_state_index = min_power_state_index;
112                         rdev->pm.requested_clock_mode_index = 0;
113                         rdev->pm.dynpm_can_downclock = false;
114                         break;
115                 case DYNPM_ACTION_DOWNCLOCK:
116                         if (rdev->pm.current_power_state_index == min_power_state_index) {
117                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
118                                 rdev->pm.dynpm_can_downclock = false;
119                         } else {
120                                 if (rdev->pm.active_crtc_count > 1) {
121                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
122                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
123                                                         continue;
124                                                 else if (i >= rdev->pm.current_power_state_index) {
125                                                         rdev->pm.requested_power_state_index =
126                                                                 rdev->pm.current_power_state_index;
127                                                         break;
128                                                 } else {
129                                                         rdev->pm.requested_power_state_index = i;
130                                                         break;
131                                                 }
132                                         }
133                                 } else
134                                         rdev->pm.requested_power_state_index =
135                                                 rdev->pm.current_power_state_index - 1;
136                         }
137                         rdev->pm.requested_clock_mode_index = 0;
138                         /* don't use the power state if crtcs are active and no display flag is set */
139                         if ((rdev->pm.active_crtc_count > 0) &&
140                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
141                              clock_info[rdev->pm.requested_clock_mode_index].flags &
142                              RADEON_PM_MODE_NO_DISPLAY)) {
143                                 rdev->pm.requested_power_state_index++;
144                         }
145                         break;
146                 case DYNPM_ACTION_UPCLOCK:
147                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
148                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
149                                 rdev->pm.dynpm_can_upclock = false;
150                         } else {
151                                 if (rdev->pm.active_crtc_count > 1) {
152                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
153                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
154                                                         continue;
155                                                 else if (i <= rdev->pm.current_power_state_index) {
156                                                         rdev->pm.requested_power_state_index =
157                                                                 rdev->pm.current_power_state_index;
158                                                         break;
159                                                 } else {
160                                                         rdev->pm.requested_power_state_index = i;
161                                                         break;
162                                                 }
163                                         }
164                                 } else
165                                         rdev->pm.requested_power_state_index =
166                                                 rdev->pm.current_power_state_index + 1;
167                         }
168                         rdev->pm.requested_clock_mode_index = 0;
169                         break;
170                 case DYNPM_ACTION_DEFAULT:
171                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
172                         rdev->pm.requested_clock_mode_index = 0;
173                         rdev->pm.dynpm_can_upclock = false;
174                         break;
175                 case DYNPM_ACTION_NONE:
176                 default:
177                         DRM_ERROR("Requested mode for not defined action\n");
178                         return;
179                 }
180         } else {
181                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
182                 /* for now just select the first power state and switch between clock modes */
183                 /* power state array is low to high, default is first (0) */
184                 if (rdev->pm.active_crtc_count > 1) {
185                         rdev->pm.requested_power_state_index = -1;
186                         /* start at 1 as we don't want the default mode */
187                         for (i = 1; i < rdev->pm.num_power_states; i++) {
188                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
189                                         continue;
190                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
191                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
192                                         rdev->pm.requested_power_state_index = i;
193                                         break;
194                                 }
195                         }
196                         /* if nothing selected, grab the default state. */
197                         if (rdev->pm.requested_power_state_index == -1)
198                                 rdev->pm.requested_power_state_index = 0;
199                 } else
200                         rdev->pm.requested_power_state_index = 1;
201
202                 switch (rdev->pm.dynpm_planned_action) {
203                 case DYNPM_ACTION_MINIMUM:
204                         rdev->pm.requested_clock_mode_index = 0;
205                         rdev->pm.dynpm_can_downclock = false;
206                         break;
207                 case DYNPM_ACTION_DOWNCLOCK:
208                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
209                                 if (rdev->pm.current_clock_mode_index == 0) {
210                                         rdev->pm.requested_clock_mode_index = 0;
211                                         rdev->pm.dynpm_can_downclock = false;
212                                 } else
213                                         rdev->pm.requested_clock_mode_index =
214                                                 rdev->pm.current_clock_mode_index - 1;
215                         } else {
216                                 rdev->pm.requested_clock_mode_index = 0;
217                                 rdev->pm.dynpm_can_downclock = false;
218                         }
219                         /* don't use the power state if crtcs are active and no display flag is set */
220                         if ((rdev->pm.active_crtc_count > 0) &&
221                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
222                              clock_info[rdev->pm.requested_clock_mode_index].flags &
223                              RADEON_PM_MODE_NO_DISPLAY)) {
224                                 rdev->pm.requested_clock_mode_index++;
225                         }
226                         break;
227                 case DYNPM_ACTION_UPCLOCK:
228                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
229                                 if (rdev->pm.current_clock_mode_index ==
230                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
231                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
232                                         rdev->pm.dynpm_can_upclock = false;
233                                 } else
234                                         rdev->pm.requested_clock_mode_index =
235                                                 rdev->pm.current_clock_mode_index + 1;
236                         } else {
237                                 rdev->pm.requested_clock_mode_index =
238                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
239                                 rdev->pm.dynpm_can_upclock = false;
240                         }
241                         break;
242                 case DYNPM_ACTION_DEFAULT:
243                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
244                         rdev->pm.requested_clock_mode_index = 0;
245                         rdev->pm.dynpm_can_upclock = false;
246                         break;
247                 case DYNPM_ACTION_NONE:
248                 default:
249                         DRM_ERROR("Requested mode for not defined action\n");
250                         return;
251                 }
252         }
253
254         DRM_DEBUG("Requested: e: %d m: %d p: %d\n",
255                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
256                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
257                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
258                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
259                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
260                   pcie_lanes);
261 }
262
263 static int r600_pm_get_type_index(struct radeon_device *rdev,
264                                   enum radeon_pm_state_type ps_type,
265                                   int instance)
266 {
267         int i;
268         int found_instance = -1;
269
270         for (i = 0; i < rdev->pm.num_power_states; i++) {
271                 if (rdev->pm.power_state[i].type == ps_type) {
272                         found_instance++;
273                         if (found_instance == instance)
274                                 return i;
275                 }
276         }
277         /* return default if no match */
278         return rdev->pm.default_power_state_index;
279 }
280
281 void rs780_pm_init_profile(struct radeon_device *rdev)
282 {
283         if (rdev->pm.num_power_states == 2) {
284                 /* default */
285                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
286                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
287                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
288                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
289                 /* low sh */
290                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
291                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
292                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
293                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
294                 /* high sh */
295                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
296                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
297                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
298                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
299                 /* low mh */
300                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
301                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
302                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
303                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
304                 /* high mh */
305                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
306                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
307                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
308                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
309         } else if (rdev->pm.num_power_states == 3) {
310                 /* default */
311                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
312                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
313                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
314                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
315                 /* low sh */
316                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
317                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
318                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
319                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
320                 /* high sh */
321                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
322                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
323                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
324                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
325                 /* low mh */
326                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
327                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
328                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
329                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
330                 /* high mh */
331                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
332                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
333                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
334                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
335         } else {
336                 /* default */
337                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
338                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
339                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
340                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
341                 /* low sh */
342                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
343                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
344                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
345                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
346                 /* high sh */
347                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
348                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
349                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
350                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
351                 /* low mh */
352                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
353                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
354                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
355                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
356                 /* high mh */
357                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
358                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
359                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
360                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
361         }
362 }
363
364 void r600_pm_init_profile(struct radeon_device *rdev)
365 {
366         if (rdev->family == CHIP_R600) {
367                 /* XXX */
368                 /* default */
369                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
370                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
371                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
372                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
373                 /* low sh */
374                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
375                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
376                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
377                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
378                 /* high sh */
379                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
380                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
381                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
382                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
383                 /* low mh */
384                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
385                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
386                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
387                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
388                 /* high mh */
389                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
390                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
391                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
392                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
393         } else {
394                 if (rdev->pm.num_power_states < 4) {
395                         /* default */
396                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
397                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
398                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
399                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
400                         /* low sh */
401                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
402                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
403                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
404                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 1;
405                         /* high sh */
406                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
407                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
408                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
409                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
410                         /* low mh */
411                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
412                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
413                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
414                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 1;
415                         /* high mh */
416                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
417                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
418                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
419                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
420                 } else {
421                         /* default */
422                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
423                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
424                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
425                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
426                         /* low sh */
427                         if (rdev->flags & RADEON_IS_MOBILITY) {
428                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
429                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
430                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
431                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
432                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
433                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 1;
434                         } else {
435                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
436                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
437                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
438                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
439                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
440                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 1;
441                         }
442                         /* high sh */
443                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
444                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
445                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
446                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
447                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
448                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
449                         /* low mh */
450                         if (rdev->flags & RADEON_IS_MOBILITY) {
451                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
452                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
453                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
454                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
455                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
456                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 2;
457                         } else {
458                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
459                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
460                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
461                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
462                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
463                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 1;
464                         }
465                         /* high mh */
466                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
467                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
468                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
469                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
470                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
471                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
472                 }
473         }
474 }
475
476 void r600_pm_misc(struct radeon_device *rdev)
477 {
478
479 }
480
481 bool r600_gui_idle(struct radeon_device *rdev)
482 {
483         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
484                 return false;
485         else
486                 return true;
487 }
488
489 /* hpd for digital panel detect/disconnect */
490 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
491 {
492         bool connected = false;
493
494         if (ASIC_IS_DCE3(rdev)) {
495                 switch (hpd) {
496                 case RADEON_HPD_1:
497                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
498                                 connected = true;
499                         break;
500                 case RADEON_HPD_2:
501                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
502                                 connected = true;
503                         break;
504                 case RADEON_HPD_3:
505                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
506                                 connected = true;
507                         break;
508                 case RADEON_HPD_4:
509                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
510                                 connected = true;
511                         break;
512                         /* DCE 3.2 */
513                 case RADEON_HPD_5:
514                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
515                                 connected = true;
516                         break;
517                 case RADEON_HPD_6:
518                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
519                                 connected = true;
520                         break;
521                 default:
522                         break;
523                 }
524         } else {
525                 switch (hpd) {
526                 case RADEON_HPD_1:
527                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
528                                 connected = true;
529                         break;
530                 case RADEON_HPD_2:
531                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
532                                 connected = true;
533                         break;
534                 case RADEON_HPD_3:
535                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
536                                 connected = true;
537                         break;
538                 default:
539                         break;
540                 }
541         }
542         return connected;
543 }
544
545 void r600_hpd_set_polarity(struct radeon_device *rdev,
546                            enum radeon_hpd_id hpd)
547 {
548         u32 tmp;
549         bool connected = r600_hpd_sense(rdev, hpd);
550
551         if (ASIC_IS_DCE3(rdev)) {
552                 switch (hpd) {
553                 case RADEON_HPD_1:
554                         tmp = RREG32(DC_HPD1_INT_CONTROL);
555                         if (connected)
556                                 tmp &= ~DC_HPDx_INT_POLARITY;
557                         else
558                                 tmp |= DC_HPDx_INT_POLARITY;
559                         WREG32(DC_HPD1_INT_CONTROL, tmp);
560                         break;
561                 case RADEON_HPD_2:
562                         tmp = RREG32(DC_HPD2_INT_CONTROL);
563                         if (connected)
564                                 tmp &= ~DC_HPDx_INT_POLARITY;
565                         else
566                                 tmp |= DC_HPDx_INT_POLARITY;
567                         WREG32(DC_HPD2_INT_CONTROL, tmp);
568                         break;
569                 case RADEON_HPD_3:
570                         tmp = RREG32(DC_HPD3_INT_CONTROL);
571                         if (connected)
572                                 tmp &= ~DC_HPDx_INT_POLARITY;
573                         else
574                                 tmp |= DC_HPDx_INT_POLARITY;
575                         WREG32(DC_HPD3_INT_CONTROL, tmp);
576                         break;
577                 case RADEON_HPD_4:
578                         tmp = RREG32(DC_HPD4_INT_CONTROL);
579                         if (connected)
580                                 tmp &= ~DC_HPDx_INT_POLARITY;
581                         else
582                                 tmp |= DC_HPDx_INT_POLARITY;
583                         WREG32(DC_HPD4_INT_CONTROL, tmp);
584                         break;
585                 case RADEON_HPD_5:
586                         tmp = RREG32(DC_HPD5_INT_CONTROL);
587                         if (connected)
588                                 tmp &= ~DC_HPDx_INT_POLARITY;
589                         else
590                                 tmp |= DC_HPDx_INT_POLARITY;
591                         WREG32(DC_HPD5_INT_CONTROL, tmp);
592                         break;
593                         /* DCE 3.2 */
594                 case RADEON_HPD_6:
595                         tmp = RREG32(DC_HPD6_INT_CONTROL);
596                         if (connected)
597                                 tmp &= ~DC_HPDx_INT_POLARITY;
598                         else
599                                 tmp |= DC_HPDx_INT_POLARITY;
600                         WREG32(DC_HPD6_INT_CONTROL, tmp);
601                         break;
602                 default:
603                         break;
604                 }
605         } else {
606                 switch (hpd) {
607                 case RADEON_HPD_1:
608                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
609                         if (connected)
610                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
611                         else
612                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
613                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
614                         break;
615                 case RADEON_HPD_2:
616                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
617                         if (connected)
618                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
619                         else
620                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
621                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
622                         break;
623                 case RADEON_HPD_3:
624                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
625                         if (connected)
626                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
627                         else
628                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
629                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
630                         break;
631                 default:
632                         break;
633                 }
634         }
635 }
636
637 void r600_hpd_init(struct radeon_device *rdev)
638 {
639         struct drm_device *dev = rdev->ddev;
640         struct drm_connector *connector;
641
642         if (ASIC_IS_DCE3(rdev)) {
643                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
644                 if (ASIC_IS_DCE32(rdev))
645                         tmp |= DC_HPDx_EN;
646
647                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
648                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
649                         switch (radeon_connector->hpd.hpd) {
650                         case RADEON_HPD_1:
651                                 WREG32(DC_HPD1_CONTROL, tmp);
652                                 rdev->irq.hpd[0] = true;
653                                 break;
654                         case RADEON_HPD_2:
655                                 WREG32(DC_HPD2_CONTROL, tmp);
656                                 rdev->irq.hpd[1] = true;
657                                 break;
658                         case RADEON_HPD_3:
659                                 WREG32(DC_HPD3_CONTROL, tmp);
660                                 rdev->irq.hpd[2] = true;
661                                 break;
662                         case RADEON_HPD_4:
663                                 WREG32(DC_HPD4_CONTROL, tmp);
664                                 rdev->irq.hpd[3] = true;
665                                 break;
666                                 /* DCE 3.2 */
667                         case RADEON_HPD_5:
668                                 WREG32(DC_HPD5_CONTROL, tmp);
669                                 rdev->irq.hpd[4] = true;
670                                 break;
671                         case RADEON_HPD_6:
672                                 WREG32(DC_HPD6_CONTROL, tmp);
673                                 rdev->irq.hpd[5] = true;
674                                 break;
675                         default:
676                                 break;
677                         }
678                 }
679         } else {
680                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
681                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
682                         switch (radeon_connector->hpd.hpd) {
683                         case RADEON_HPD_1:
684                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
685                                 rdev->irq.hpd[0] = true;
686                                 break;
687                         case RADEON_HPD_2:
688                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
689                                 rdev->irq.hpd[1] = true;
690                                 break;
691                         case RADEON_HPD_3:
692                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
693                                 rdev->irq.hpd[2] = true;
694                                 break;
695                         default:
696                                 break;
697                         }
698                 }
699         }
700         if (rdev->irq.installed)
701                 r600_irq_set(rdev);
702 }
703
704 void r600_hpd_fini(struct radeon_device *rdev)
705 {
706         struct drm_device *dev = rdev->ddev;
707         struct drm_connector *connector;
708
709         if (ASIC_IS_DCE3(rdev)) {
710                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
711                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
712                         switch (radeon_connector->hpd.hpd) {
713                         case RADEON_HPD_1:
714                                 WREG32(DC_HPD1_CONTROL, 0);
715                                 rdev->irq.hpd[0] = false;
716                                 break;
717                         case RADEON_HPD_2:
718                                 WREG32(DC_HPD2_CONTROL, 0);
719                                 rdev->irq.hpd[1] = false;
720                                 break;
721                         case RADEON_HPD_3:
722                                 WREG32(DC_HPD3_CONTROL, 0);
723                                 rdev->irq.hpd[2] = false;
724                                 break;
725                         case RADEON_HPD_4:
726                                 WREG32(DC_HPD4_CONTROL, 0);
727                                 rdev->irq.hpd[3] = false;
728                                 break;
729                                 /* DCE 3.2 */
730                         case RADEON_HPD_5:
731                                 WREG32(DC_HPD5_CONTROL, 0);
732                                 rdev->irq.hpd[4] = false;
733                                 break;
734                         case RADEON_HPD_6:
735                                 WREG32(DC_HPD6_CONTROL, 0);
736                                 rdev->irq.hpd[5] = false;
737                                 break;
738                         default:
739                                 break;
740                         }
741                 }
742         } else {
743                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
744                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
745                         switch (radeon_connector->hpd.hpd) {
746                         case RADEON_HPD_1:
747                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
748                                 rdev->irq.hpd[0] = false;
749                                 break;
750                         case RADEON_HPD_2:
751                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
752                                 rdev->irq.hpd[1] = false;
753                                 break;
754                         case RADEON_HPD_3:
755                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
756                                 rdev->irq.hpd[2] = false;
757                                 break;
758                         default:
759                                 break;
760                         }
761                 }
762         }
763 }
764
765 /*
766  * R600 PCIE GART
767  */
768 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
769 {
770         unsigned i;
771         u32 tmp;
772
773         /* flush hdp cache so updates hit vram */
774         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
775
776         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
777         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
778         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
779         for (i = 0; i < rdev->usec_timeout; i++) {
780                 /* read MC_STATUS */
781                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
782                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
783                 if (tmp == 2) {
784                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
785                         return;
786                 }
787                 if (tmp) {
788                         return;
789                 }
790                 udelay(1);
791         }
792 }
793
794 int r600_pcie_gart_init(struct radeon_device *rdev)
795 {
796         int r;
797
798         if (rdev->gart.table.vram.robj) {
799                 WARN(1, "R600 PCIE GART already initialized.\n");
800                 return 0;
801         }
802         /* Initialize common gart structure */
803         r = radeon_gart_init(rdev);
804         if (r)
805                 return r;
806         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
807         return radeon_gart_table_vram_alloc(rdev);
808 }
809
810 int r600_pcie_gart_enable(struct radeon_device *rdev)
811 {
812         u32 tmp;
813         int r, i;
814
815         if (rdev->gart.table.vram.robj == NULL) {
816                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
817                 return -EINVAL;
818         }
819         r = radeon_gart_table_vram_pin(rdev);
820         if (r)
821                 return r;
822         radeon_gart_restore(rdev);
823
824         /* Setup L2 cache */
825         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
826                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
827                                 EFFECTIVE_L2_QUEUE_SIZE(7));
828         WREG32(VM_L2_CNTL2, 0);
829         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
830         /* Setup TLB control */
831         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
832                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
833                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
834                 ENABLE_WAIT_L2_QUERY;
835         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
836         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
837         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
838         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
839         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
840         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
841         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
842         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
843         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
844         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
845         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
846         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
847         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
848         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
849         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
850         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
851         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
852         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
853                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
854         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
855                         (u32)(rdev->dummy_page.addr >> 12));
856         for (i = 1; i < 7; i++)
857                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
858
859         r600_pcie_gart_tlb_flush(rdev);
860         rdev->gart.ready = true;
861         return 0;
862 }
863
864 void r600_pcie_gart_disable(struct radeon_device *rdev)
865 {
866         u32 tmp;
867         int i, r;
868
869         /* Disable all tables */
870         for (i = 0; i < 7; i++)
871                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
872
873         /* Disable L2 cache */
874         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
875                                 EFFECTIVE_L2_QUEUE_SIZE(7));
876         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
877         /* Setup L1 TLB control */
878         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
879                 ENABLE_WAIT_L2_QUERY;
880         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
881         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
882         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
883         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
884         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
885         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
886         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
887         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
888         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
889         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
890         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
891         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
892         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
893         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
894         if (rdev->gart.table.vram.robj) {
895                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
896                 if (likely(r == 0)) {
897                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
898                         radeon_bo_unpin(rdev->gart.table.vram.robj);
899                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
900                 }
901         }
902 }
903
904 void r600_pcie_gart_fini(struct radeon_device *rdev)
905 {
906         radeon_gart_fini(rdev);
907         r600_pcie_gart_disable(rdev);
908         radeon_gart_table_vram_free(rdev);
909 }
910
911 void r600_agp_enable(struct radeon_device *rdev)
912 {
913         u32 tmp;
914         int i;
915
916         /* Setup L2 cache */
917         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
918                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
919                                 EFFECTIVE_L2_QUEUE_SIZE(7));
920         WREG32(VM_L2_CNTL2, 0);
921         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
922         /* Setup TLB control */
923         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
924                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
925                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
926                 ENABLE_WAIT_L2_QUERY;
927         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
928         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
929         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
930         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
931         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
932         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
933         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
934         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
935         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
936         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
937         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
938         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
939         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
940         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
941         for (i = 0; i < 7; i++)
942                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
943 }
944
945 int r600_mc_wait_for_idle(struct radeon_device *rdev)
946 {
947         unsigned i;
948         u32 tmp;
949
950         for (i = 0; i < rdev->usec_timeout; i++) {
951                 /* read MC_STATUS */
952                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
953                 if (!tmp)
954                         return 0;
955                 udelay(1);
956         }
957         return -1;
958 }
959
960 static void r600_mc_program(struct radeon_device *rdev)
961 {
962         struct rv515_mc_save save;
963         u32 tmp;
964         int i, j;
965
966         /* Initialize HDP */
967         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
968                 WREG32((0x2c14 + j), 0x00000000);
969                 WREG32((0x2c18 + j), 0x00000000);
970                 WREG32((0x2c1c + j), 0x00000000);
971                 WREG32((0x2c20 + j), 0x00000000);
972                 WREG32((0x2c24 + j), 0x00000000);
973         }
974         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
975
976         rv515_mc_stop(rdev, &save);
977         if (r600_mc_wait_for_idle(rdev)) {
978                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
979         }
980         /* Lockout access through VGA aperture (doesn't exist before R600) */
981         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
982         /* Update configuration */
983         if (rdev->flags & RADEON_IS_AGP) {
984                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
985                         /* VRAM before AGP */
986                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
987                                 rdev->mc.vram_start >> 12);
988                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
989                                 rdev->mc.gtt_end >> 12);
990                 } else {
991                         /* VRAM after AGP */
992                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
993                                 rdev->mc.gtt_start >> 12);
994                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
995                                 rdev->mc.vram_end >> 12);
996                 }
997         } else {
998                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
999                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1000         }
1001         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1002         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1003         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1004         WREG32(MC_VM_FB_LOCATION, tmp);
1005         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1006         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1007         WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
1008         if (rdev->flags & RADEON_IS_AGP) {
1009                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1010                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1011                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1012         } else {
1013                 WREG32(MC_VM_AGP_BASE, 0);
1014                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1015                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1016         }
1017         if (r600_mc_wait_for_idle(rdev)) {
1018                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1019         }
1020         rv515_mc_resume(rdev, &save);
1021         /* we need to own VRAM, so turn off the VGA renderer here
1022          * to stop it overwriting our objects */
1023         rv515_vga_render_disable(rdev);
1024 }
1025
1026 /**
1027  * r600_vram_gtt_location - try to find VRAM & GTT location
1028  * @rdev: radeon device structure holding all necessary informations
1029  * @mc: memory controller structure holding memory informations
1030  *
1031  * Function will place try to place VRAM at same place as in CPU (PCI)
1032  * address space as some GPU seems to have issue when we reprogram at
1033  * different address space.
1034  *
1035  * If there is not enough space to fit the unvisible VRAM after the
1036  * aperture then we limit the VRAM size to the aperture.
1037  *
1038  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1039  * them to be in one from GPU point of view so that we can program GPU to
1040  * catch access outside them (weird GPU policy see ??).
1041  *
1042  * This function will never fails, worst case are limiting VRAM or GTT.
1043  *
1044  * Note: GTT start, end, size should be initialized before calling this
1045  * function on AGP platform.
1046  */
1047 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1048 {
1049         u64 size_bf, size_af;
1050
1051         if (mc->mc_vram_size > 0xE0000000) {
1052                 /* leave room for at least 512M GTT */
1053                 dev_warn(rdev->dev, "limiting VRAM\n");
1054                 mc->real_vram_size = 0xE0000000;
1055                 mc->mc_vram_size = 0xE0000000;
1056         }
1057         if (rdev->flags & RADEON_IS_AGP) {
1058                 size_bf = mc->gtt_start;
1059                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1060                 if (size_bf > size_af) {
1061                         if (mc->mc_vram_size > size_bf) {
1062                                 dev_warn(rdev->dev, "limiting VRAM\n");
1063                                 mc->real_vram_size = size_bf;
1064                                 mc->mc_vram_size = size_bf;
1065                         }
1066                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1067                 } else {
1068                         if (mc->mc_vram_size > size_af) {
1069                                 dev_warn(rdev->dev, "limiting VRAM\n");
1070                                 mc->real_vram_size = size_af;
1071                                 mc->mc_vram_size = size_af;
1072                         }
1073                         mc->vram_start = mc->gtt_end;
1074                 }
1075                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1076                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1077                                 mc->mc_vram_size >> 20, mc->vram_start,
1078                                 mc->vram_end, mc->real_vram_size >> 20);
1079         } else {
1080                 u64 base = 0;
1081                 if (rdev->flags & RADEON_IS_IGP)
1082                         base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
1083                 radeon_vram_location(rdev, &rdev->mc, base);
1084                 radeon_gtt_location(rdev, mc);
1085         }
1086 }
1087
1088 int r600_mc_init(struct radeon_device *rdev)
1089 {
1090         u32 tmp;
1091         int chansize, numchan;
1092
1093         /* Get VRAM informations */
1094         rdev->mc.vram_is_ddr = true;
1095         tmp = RREG32(RAMCFG);
1096         if (tmp & CHANSIZE_OVERRIDE) {
1097                 chansize = 16;
1098         } else if (tmp & CHANSIZE_MASK) {
1099                 chansize = 64;
1100         } else {
1101                 chansize = 32;
1102         }
1103         tmp = RREG32(CHMAP);
1104         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1105         case 0:
1106         default:
1107                 numchan = 1;
1108                 break;
1109         case 1:
1110                 numchan = 2;
1111                 break;
1112         case 2:
1113                 numchan = 4;
1114                 break;
1115         case 3:
1116                 numchan = 8;
1117                 break;
1118         }
1119         rdev->mc.vram_width = numchan * chansize;
1120         /* Could aper size report 0 ? */
1121         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1122         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1123         /* Setup GPU memory space */
1124         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1125         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1126         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1127         r600_vram_gtt_location(rdev, &rdev->mc);
1128
1129         if (rdev->flags & RADEON_IS_IGP)
1130                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1131         radeon_update_bandwidth_info(rdev);
1132         return 0;
1133 }
1134
1135 /* We doesn't check that the GPU really needs a reset we simply do the
1136  * reset, it's up to the caller to determine if the GPU needs one. We
1137  * might add an helper function to check that.
1138  */
1139 int r600_gpu_soft_reset(struct radeon_device *rdev)
1140 {
1141         struct rv515_mc_save save;
1142         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1143                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1144                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1145                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1146                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1147                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1148                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1149                                 S_008010_GUI_ACTIVE(1);
1150         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1151                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1152                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1153                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1154                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1155                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1156                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1157                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1158         u32 tmp;
1159
1160         dev_info(rdev->dev, "GPU softreset \n");
1161         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1162                 RREG32(R_008010_GRBM_STATUS));
1163         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1164                 RREG32(R_008014_GRBM_STATUS2));
1165         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1166                 RREG32(R_000E50_SRBM_STATUS));
1167         rv515_mc_stop(rdev, &save);
1168         if (r600_mc_wait_for_idle(rdev)) {
1169                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1170         }
1171         /* Disable CP parsing/prefetching */
1172         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1173         /* Check if any of the rendering block is busy and reset it */
1174         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1175             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1176                 tmp = S_008020_SOFT_RESET_CR(1) |
1177                         S_008020_SOFT_RESET_DB(1) |
1178                         S_008020_SOFT_RESET_CB(1) |
1179                         S_008020_SOFT_RESET_PA(1) |
1180                         S_008020_SOFT_RESET_SC(1) |
1181                         S_008020_SOFT_RESET_SMX(1) |
1182                         S_008020_SOFT_RESET_SPI(1) |
1183                         S_008020_SOFT_RESET_SX(1) |
1184                         S_008020_SOFT_RESET_SH(1) |
1185                         S_008020_SOFT_RESET_TC(1) |
1186                         S_008020_SOFT_RESET_TA(1) |
1187                         S_008020_SOFT_RESET_VC(1) |
1188                         S_008020_SOFT_RESET_VGT(1);
1189                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1190                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1191                 RREG32(R_008020_GRBM_SOFT_RESET);
1192                 mdelay(15);
1193                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1194         }
1195         /* Reset CP (we always reset CP) */
1196         tmp = S_008020_SOFT_RESET_CP(1);
1197         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1198         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1199         RREG32(R_008020_GRBM_SOFT_RESET);
1200         mdelay(15);
1201         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1202         /* Wait a little for things to settle down */
1203         mdelay(1);
1204         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1205                 RREG32(R_008010_GRBM_STATUS));
1206         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1207                 RREG32(R_008014_GRBM_STATUS2));
1208         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1209                 RREG32(R_000E50_SRBM_STATUS));
1210         rv515_mc_resume(rdev, &save);
1211         return 0;
1212 }
1213
1214 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1215 {
1216         u32 srbm_status;
1217         u32 grbm_status;
1218         u32 grbm_status2;
1219         int r;
1220
1221         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1222         grbm_status = RREG32(R_008010_GRBM_STATUS);
1223         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1224         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1225                 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1226                 return false;
1227         }
1228         /* force CP activities */
1229         r = radeon_ring_lock(rdev, 2);
1230         if (!r) {
1231                 /* PACKET2 NOP */
1232                 radeon_ring_write(rdev, 0x80000000);
1233                 radeon_ring_write(rdev, 0x80000000);
1234                 radeon_ring_unlock_commit(rdev);
1235         }
1236         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1237         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1238 }
1239
1240 int r600_asic_reset(struct radeon_device *rdev)
1241 {
1242         return r600_gpu_soft_reset(rdev);
1243 }
1244
1245 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1246                                              u32 num_backends,
1247                                              u32 backend_disable_mask)
1248 {
1249         u32 backend_map = 0;
1250         u32 enabled_backends_mask;
1251         u32 enabled_backends_count;
1252         u32 cur_pipe;
1253         u32 swizzle_pipe[R6XX_MAX_PIPES];
1254         u32 cur_backend;
1255         u32 i;
1256
1257         if (num_tile_pipes > R6XX_MAX_PIPES)
1258                 num_tile_pipes = R6XX_MAX_PIPES;
1259         if (num_tile_pipes < 1)
1260                 num_tile_pipes = 1;
1261         if (num_backends > R6XX_MAX_BACKENDS)
1262                 num_backends = R6XX_MAX_BACKENDS;
1263         if (num_backends < 1)
1264                 num_backends = 1;
1265
1266         enabled_backends_mask = 0;
1267         enabled_backends_count = 0;
1268         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1269                 if (((backend_disable_mask >> i) & 1) == 0) {
1270                         enabled_backends_mask |= (1 << i);
1271                         ++enabled_backends_count;
1272                 }
1273                 if (enabled_backends_count == num_backends)
1274                         break;
1275         }
1276
1277         if (enabled_backends_count == 0) {
1278                 enabled_backends_mask = 1;
1279                 enabled_backends_count = 1;
1280         }
1281
1282         if (enabled_backends_count != num_backends)
1283                 num_backends = enabled_backends_count;
1284
1285         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1286         switch (num_tile_pipes) {
1287         case 1:
1288                 swizzle_pipe[0] = 0;
1289                 break;
1290         case 2:
1291                 swizzle_pipe[0] = 0;
1292                 swizzle_pipe[1] = 1;
1293                 break;
1294         case 3:
1295                 swizzle_pipe[0] = 0;
1296                 swizzle_pipe[1] = 1;
1297                 swizzle_pipe[2] = 2;
1298                 break;
1299         case 4:
1300                 swizzle_pipe[0] = 0;
1301                 swizzle_pipe[1] = 1;
1302                 swizzle_pipe[2] = 2;
1303                 swizzle_pipe[3] = 3;
1304                 break;
1305         case 5:
1306                 swizzle_pipe[0] = 0;
1307                 swizzle_pipe[1] = 1;
1308                 swizzle_pipe[2] = 2;
1309                 swizzle_pipe[3] = 3;
1310                 swizzle_pipe[4] = 4;
1311                 break;
1312         case 6:
1313                 swizzle_pipe[0] = 0;
1314                 swizzle_pipe[1] = 2;
1315                 swizzle_pipe[2] = 4;
1316                 swizzle_pipe[3] = 5;
1317                 swizzle_pipe[4] = 1;
1318                 swizzle_pipe[5] = 3;
1319                 break;
1320         case 7:
1321                 swizzle_pipe[0] = 0;
1322                 swizzle_pipe[1] = 2;
1323                 swizzle_pipe[2] = 4;
1324                 swizzle_pipe[3] = 6;
1325                 swizzle_pipe[4] = 1;
1326                 swizzle_pipe[5] = 3;
1327                 swizzle_pipe[6] = 5;
1328                 break;
1329         case 8:
1330                 swizzle_pipe[0] = 0;
1331                 swizzle_pipe[1] = 2;
1332                 swizzle_pipe[2] = 4;
1333                 swizzle_pipe[3] = 6;
1334                 swizzle_pipe[4] = 1;
1335                 swizzle_pipe[5] = 3;
1336                 swizzle_pipe[6] = 5;
1337                 swizzle_pipe[7] = 7;
1338                 break;
1339         }
1340
1341         cur_backend = 0;
1342         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1343                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1344                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1345
1346                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1347
1348                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1349         }
1350
1351         return backend_map;
1352 }
1353
1354 int r600_count_pipe_bits(uint32_t val)
1355 {
1356         int i, ret = 0;
1357
1358         for (i = 0; i < 32; i++) {
1359                 ret += val & 1;
1360                 val >>= 1;
1361         }
1362         return ret;
1363 }
1364
1365 void r600_gpu_init(struct radeon_device *rdev)
1366 {
1367         u32 tiling_config;
1368         u32 ramcfg;
1369         u32 backend_map;
1370         u32 cc_rb_backend_disable;
1371         u32 cc_gc_shader_pipe_config;
1372         u32 tmp;
1373         int i, j;
1374         u32 sq_config;
1375         u32 sq_gpr_resource_mgmt_1 = 0;
1376         u32 sq_gpr_resource_mgmt_2 = 0;
1377         u32 sq_thread_resource_mgmt = 0;
1378         u32 sq_stack_resource_mgmt_1 = 0;
1379         u32 sq_stack_resource_mgmt_2 = 0;
1380
1381         /* FIXME: implement */
1382         switch (rdev->family) {
1383         case CHIP_R600:
1384                 rdev->config.r600.max_pipes = 4;
1385                 rdev->config.r600.max_tile_pipes = 8;
1386                 rdev->config.r600.max_simds = 4;
1387                 rdev->config.r600.max_backends = 4;
1388                 rdev->config.r600.max_gprs = 256;
1389                 rdev->config.r600.max_threads = 192;
1390                 rdev->config.r600.max_stack_entries = 256;
1391                 rdev->config.r600.max_hw_contexts = 8;
1392                 rdev->config.r600.max_gs_threads = 16;
1393                 rdev->config.r600.sx_max_export_size = 128;
1394                 rdev->config.r600.sx_max_export_pos_size = 16;
1395                 rdev->config.r600.sx_max_export_smx_size = 128;
1396                 rdev->config.r600.sq_num_cf_insts = 2;
1397                 break;
1398         case CHIP_RV630:
1399         case CHIP_RV635:
1400                 rdev->config.r600.max_pipes = 2;
1401                 rdev->config.r600.max_tile_pipes = 2;
1402                 rdev->config.r600.max_simds = 3;
1403                 rdev->config.r600.max_backends = 1;
1404                 rdev->config.r600.max_gprs = 128;
1405                 rdev->config.r600.max_threads = 192;
1406                 rdev->config.r600.max_stack_entries = 128;
1407                 rdev->config.r600.max_hw_contexts = 8;
1408                 rdev->config.r600.max_gs_threads = 4;
1409                 rdev->config.r600.sx_max_export_size = 128;
1410                 rdev->config.r600.sx_max_export_pos_size = 16;
1411                 rdev->config.r600.sx_max_export_smx_size = 128;
1412                 rdev->config.r600.sq_num_cf_insts = 2;
1413                 break;
1414         case CHIP_RV610:
1415         case CHIP_RV620:
1416         case CHIP_RS780:
1417         case CHIP_RS880:
1418                 rdev->config.r600.max_pipes = 1;
1419                 rdev->config.r600.max_tile_pipes = 1;
1420                 rdev->config.r600.max_simds = 2;
1421                 rdev->config.r600.max_backends = 1;
1422                 rdev->config.r600.max_gprs = 128;
1423                 rdev->config.r600.max_threads = 192;
1424                 rdev->config.r600.max_stack_entries = 128;
1425                 rdev->config.r600.max_hw_contexts = 4;
1426                 rdev->config.r600.max_gs_threads = 4;
1427                 rdev->config.r600.sx_max_export_size = 128;
1428                 rdev->config.r600.sx_max_export_pos_size = 16;
1429                 rdev->config.r600.sx_max_export_smx_size = 128;
1430                 rdev->config.r600.sq_num_cf_insts = 1;
1431                 break;
1432         case CHIP_RV670:
1433                 rdev->config.r600.max_pipes = 4;
1434                 rdev->config.r600.max_tile_pipes = 4;
1435                 rdev->config.r600.max_simds = 4;
1436                 rdev->config.r600.max_backends = 4;
1437                 rdev->config.r600.max_gprs = 192;
1438                 rdev->config.r600.max_threads = 192;
1439                 rdev->config.r600.max_stack_entries = 256;
1440                 rdev->config.r600.max_hw_contexts = 8;
1441                 rdev->config.r600.max_gs_threads = 16;
1442                 rdev->config.r600.sx_max_export_size = 128;
1443                 rdev->config.r600.sx_max_export_pos_size = 16;
1444                 rdev->config.r600.sx_max_export_smx_size = 128;
1445                 rdev->config.r600.sq_num_cf_insts = 2;
1446                 break;
1447         default:
1448                 break;
1449         }
1450
1451         /* Initialize HDP */
1452         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1453                 WREG32((0x2c14 + j), 0x00000000);
1454                 WREG32((0x2c18 + j), 0x00000000);
1455                 WREG32((0x2c1c + j), 0x00000000);
1456                 WREG32((0x2c20 + j), 0x00000000);
1457                 WREG32((0x2c24 + j), 0x00000000);
1458         }
1459
1460         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1461
1462         /* Setup tiling */
1463         tiling_config = 0;
1464         ramcfg = RREG32(RAMCFG);
1465         switch (rdev->config.r600.max_tile_pipes) {
1466         case 1:
1467                 tiling_config |= PIPE_TILING(0);
1468                 break;
1469         case 2:
1470                 tiling_config |= PIPE_TILING(1);
1471                 break;
1472         case 4:
1473                 tiling_config |= PIPE_TILING(2);
1474                 break;
1475         case 8:
1476                 tiling_config |= PIPE_TILING(3);
1477                 break;
1478         default:
1479                 break;
1480         }
1481         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1482         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1483         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1484         tiling_config |= GROUP_SIZE(0);
1485         rdev->config.r600.tiling_group_size = 256;
1486         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1487         if (tmp > 3) {
1488                 tiling_config |= ROW_TILING(3);
1489                 tiling_config |= SAMPLE_SPLIT(3);
1490         } else {
1491                 tiling_config |= ROW_TILING(tmp);
1492                 tiling_config |= SAMPLE_SPLIT(tmp);
1493         }
1494         tiling_config |= BANK_SWAPS(1);
1495
1496         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1497         cc_rb_backend_disable |=
1498                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1499
1500         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1501         cc_gc_shader_pipe_config |=
1502                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1503         cc_gc_shader_pipe_config |=
1504                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1505
1506         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1507                                                         (R6XX_MAX_BACKENDS -
1508                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1509                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1510                                                         (cc_rb_backend_disable >> 16));
1511
1512         tiling_config |= BACKEND_MAP(backend_map);
1513         WREG32(GB_TILING_CONFIG, tiling_config);
1514         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1515         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1516
1517         /* Setup pipes */
1518         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1519         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1520         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1521
1522         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1523         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1524         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1525
1526         /* Setup some CP states */
1527         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1528         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1529
1530         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1531                              SYNC_WALKER | SYNC_ALIGNER));
1532         /* Setup various GPU states */
1533         if (rdev->family == CHIP_RV670)
1534                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1535
1536         tmp = RREG32(SX_DEBUG_1);
1537         tmp |= SMX_EVENT_RELEASE;
1538         if ((rdev->family > CHIP_R600))
1539                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1540         WREG32(SX_DEBUG_1, tmp);
1541
1542         if (((rdev->family) == CHIP_R600) ||
1543             ((rdev->family) == CHIP_RV630) ||
1544             ((rdev->family) == CHIP_RV610) ||
1545             ((rdev->family) == CHIP_RV620) ||
1546             ((rdev->family) == CHIP_RS780) ||
1547             ((rdev->family) == CHIP_RS880)) {
1548                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1549         } else {
1550                 WREG32(DB_DEBUG, 0);
1551         }
1552         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1553                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1554
1555         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1556         WREG32(VGT_NUM_INSTANCES, 0);
1557
1558         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1559         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1560
1561         tmp = RREG32(SQ_MS_FIFO_SIZES);
1562         if (((rdev->family) == CHIP_RV610) ||
1563             ((rdev->family) == CHIP_RV620) ||
1564             ((rdev->family) == CHIP_RS780) ||
1565             ((rdev->family) == CHIP_RS880)) {
1566                 tmp = (CACHE_FIFO_SIZE(0xa) |
1567                        FETCH_FIFO_HIWATER(0xa) |
1568                        DONE_FIFO_HIWATER(0xe0) |
1569                        ALU_UPDATE_FIFO_HIWATER(0x8));
1570         } else if (((rdev->family) == CHIP_R600) ||
1571                    ((rdev->family) == CHIP_RV630)) {
1572                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1573                 tmp |= DONE_FIFO_HIWATER(0x4);
1574         }
1575         WREG32(SQ_MS_FIFO_SIZES, tmp);
1576
1577         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1578          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1579          */
1580         sq_config = RREG32(SQ_CONFIG);
1581         sq_config &= ~(PS_PRIO(3) |
1582                        VS_PRIO(3) |
1583                        GS_PRIO(3) |
1584                        ES_PRIO(3));
1585         sq_config |= (DX9_CONSTS |
1586                       VC_ENABLE |
1587                       PS_PRIO(0) |
1588                       VS_PRIO(1) |
1589                       GS_PRIO(2) |
1590                       ES_PRIO(3));
1591
1592         if ((rdev->family) == CHIP_R600) {
1593                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1594                                           NUM_VS_GPRS(124) |
1595                                           NUM_CLAUSE_TEMP_GPRS(4));
1596                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1597                                           NUM_ES_GPRS(0));
1598                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1599                                            NUM_VS_THREADS(48) |
1600                                            NUM_GS_THREADS(4) |
1601                                            NUM_ES_THREADS(4));
1602                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1603                                             NUM_VS_STACK_ENTRIES(128));
1604                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1605                                             NUM_ES_STACK_ENTRIES(0));
1606         } else if (((rdev->family) == CHIP_RV610) ||
1607                    ((rdev->family) == CHIP_RV620) ||
1608                    ((rdev->family) == CHIP_RS780) ||
1609                    ((rdev->family) == CHIP_RS880)) {
1610                 /* no vertex cache */
1611                 sq_config &= ~VC_ENABLE;
1612
1613                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1614                                           NUM_VS_GPRS(44) |
1615                                           NUM_CLAUSE_TEMP_GPRS(2));
1616                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1617                                           NUM_ES_GPRS(17));
1618                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1619                                            NUM_VS_THREADS(78) |
1620                                            NUM_GS_THREADS(4) |
1621                                            NUM_ES_THREADS(31));
1622                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1623                                             NUM_VS_STACK_ENTRIES(40));
1624                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1625                                             NUM_ES_STACK_ENTRIES(16));
1626         } else if (((rdev->family) == CHIP_RV630) ||
1627                    ((rdev->family) == CHIP_RV635)) {
1628                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1629                                           NUM_VS_GPRS(44) |
1630                                           NUM_CLAUSE_TEMP_GPRS(2));
1631                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1632                                           NUM_ES_GPRS(18));
1633                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1634                                            NUM_VS_THREADS(78) |
1635                                            NUM_GS_THREADS(4) |
1636                                            NUM_ES_THREADS(31));
1637                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1638                                             NUM_VS_STACK_ENTRIES(40));
1639                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1640                                             NUM_ES_STACK_ENTRIES(16));
1641         } else if ((rdev->family) == CHIP_RV670) {
1642                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1643                                           NUM_VS_GPRS(44) |
1644                                           NUM_CLAUSE_TEMP_GPRS(2));
1645                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1646                                           NUM_ES_GPRS(17));
1647                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1648                                            NUM_VS_THREADS(78) |
1649                                            NUM_GS_THREADS(4) |
1650                                            NUM_ES_THREADS(31));
1651                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1652                                             NUM_VS_STACK_ENTRIES(64));
1653                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1654                                             NUM_ES_STACK_ENTRIES(64));
1655         }
1656
1657         WREG32(SQ_CONFIG, sq_config);
1658         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1659         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1660         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1661         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1662         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1663
1664         if (((rdev->family) == CHIP_RV610) ||
1665             ((rdev->family) == CHIP_RV620) ||
1666             ((rdev->family) == CHIP_RS780) ||
1667             ((rdev->family) == CHIP_RS880)) {
1668                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1669         } else {
1670                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1671         }
1672
1673         /* More default values. 2D/3D driver should adjust as needed */
1674         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1675                                          S1_X(0x4) | S1_Y(0xc)));
1676         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1677                                          S1_X(0x2) | S1_Y(0x2) |
1678                                          S2_X(0xa) | S2_Y(0x6) |
1679                                          S3_X(0x6) | S3_Y(0xa)));
1680         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1681                                              S1_X(0x4) | S1_Y(0xc) |
1682                                              S2_X(0x1) | S2_Y(0x6) |
1683                                              S3_X(0xa) | S3_Y(0xe)));
1684         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1685                                              S5_X(0x0) | S5_Y(0x0) |
1686                                              S6_X(0xb) | S6_Y(0x4) |
1687                                              S7_X(0x7) | S7_Y(0x8)));
1688
1689         WREG32(VGT_STRMOUT_EN, 0);
1690         tmp = rdev->config.r600.max_pipes * 16;
1691         switch (rdev->family) {
1692         case CHIP_RV610:
1693         case CHIP_RV620:
1694         case CHIP_RS780:
1695         case CHIP_RS880:
1696                 tmp += 32;
1697                 break;
1698         case CHIP_RV670:
1699                 tmp += 128;
1700                 break;
1701         default:
1702                 break;
1703         }
1704         if (tmp > 256) {
1705                 tmp = 256;
1706         }
1707         WREG32(VGT_ES_PER_GS, 128);
1708         WREG32(VGT_GS_PER_ES, tmp);
1709         WREG32(VGT_GS_PER_VS, 2);
1710         WREG32(VGT_GS_VERTEX_REUSE, 16);
1711
1712         /* more default values. 2D/3D driver should adjust as needed */
1713         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1714         WREG32(VGT_STRMOUT_EN, 0);
1715         WREG32(SX_MISC, 0);
1716         WREG32(PA_SC_MODE_CNTL, 0);
1717         WREG32(PA_SC_AA_CONFIG, 0);
1718         WREG32(PA_SC_LINE_STIPPLE, 0);
1719         WREG32(SPI_INPUT_Z, 0);
1720         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1721         WREG32(CB_COLOR7_FRAG, 0);
1722
1723         /* Clear render buffer base addresses */
1724         WREG32(CB_COLOR0_BASE, 0);
1725         WREG32(CB_COLOR1_BASE, 0);
1726         WREG32(CB_COLOR2_BASE, 0);
1727         WREG32(CB_COLOR3_BASE, 0);
1728         WREG32(CB_COLOR4_BASE, 0);
1729         WREG32(CB_COLOR5_BASE, 0);
1730         WREG32(CB_COLOR6_BASE, 0);
1731         WREG32(CB_COLOR7_BASE, 0);
1732         WREG32(CB_COLOR7_FRAG, 0);
1733
1734         switch (rdev->family) {
1735         case CHIP_RV610:
1736         case CHIP_RV620:
1737         case CHIP_RS780:
1738         case CHIP_RS880:
1739                 tmp = TC_L2_SIZE(8);
1740                 break;
1741         case CHIP_RV630:
1742         case CHIP_RV635:
1743                 tmp = TC_L2_SIZE(4);
1744                 break;
1745         case CHIP_R600:
1746                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1747                 break;
1748         default:
1749                 tmp = TC_L2_SIZE(0);
1750                 break;
1751         }
1752         WREG32(TC_CNTL, tmp);
1753
1754         tmp = RREG32(HDP_HOST_PATH_CNTL);
1755         WREG32(HDP_HOST_PATH_CNTL, tmp);
1756
1757         tmp = RREG32(ARB_POP);
1758         tmp |= ENABLE_TC128;
1759         WREG32(ARB_POP, tmp);
1760
1761         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1762         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1763                                NUM_CLIP_SEQ(3)));
1764         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1765 }
1766
1767
1768 /*
1769  * Indirect registers accessor
1770  */
1771 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1772 {
1773         u32 r;
1774
1775         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1776         (void)RREG32(PCIE_PORT_INDEX);
1777         r = RREG32(PCIE_PORT_DATA);
1778         return r;
1779 }
1780
1781 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1782 {
1783         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1784         (void)RREG32(PCIE_PORT_INDEX);
1785         WREG32(PCIE_PORT_DATA, (v));
1786         (void)RREG32(PCIE_PORT_DATA);
1787 }
1788
1789 /*
1790  * CP & Ring
1791  */
1792 void r600_cp_stop(struct radeon_device *rdev)
1793 {
1794         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1795 }
1796
1797 int r600_init_microcode(struct radeon_device *rdev)
1798 {
1799         struct platform_device *pdev;
1800         const char *chip_name;
1801         const char *rlc_chip_name;
1802         size_t pfp_req_size, me_req_size, rlc_req_size;
1803         char fw_name[30];
1804         int err;
1805
1806         DRM_DEBUG("\n");
1807
1808         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1809         err = IS_ERR(pdev);
1810         if (err) {
1811                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1812                 return -EINVAL;
1813         }
1814
1815         switch (rdev->family) {
1816         case CHIP_R600:
1817                 chip_name = "R600";
1818                 rlc_chip_name = "R600";
1819                 break;
1820         case CHIP_RV610:
1821                 chip_name = "RV610";
1822                 rlc_chip_name = "R600";
1823                 break;
1824         case CHIP_RV630:
1825                 chip_name = "RV630";
1826                 rlc_chip_name = "R600";
1827                 break;
1828         case CHIP_RV620:
1829                 chip_name = "RV620";
1830                 rlc_chip_name = "R600";
1831                 break;
1832         case CHIP_RV635:
1833                 chip_name = "RV635";
1834                 rlc_chip_name = "R600";
1835                 break;
1836         case CHIP_RV670:
1837                 chip_name = "RV670";
1838                 rlc_chip_name = "R600";
1839                 break;
1840         case CHIP_RS780:
1841         case CHIP_RS880:
1842                 chip_name = "RS780";
1843                 rlc_chip_name = "R600";
1844                 break;
1845         case CHIP_RV770:
1846                 chip_name = "RV770";
1847                 rlc_chip_name = "R700";
1848                 break;
1849         case CHIP_RV730:
1850         case CHIP_RV740:
1851                 chip_name = "RV730";
1852                 rlc_chip_name = "R700";
1853                 break;
1854         case CHIP_RV710:
1855                 chip_name = "RV710";
1856                 rlc_chip_name = "R700";
1857                 break;
1858         case CHIP_CEDAR:
1859                 chip_name = "CEDAR";
1860                 rlc_chip_name = "CEDAR";
1861                 break;
1862         case CHIP_REDWOOD:
1863                 chip_name = "REDWOOD";
1864                 rlc_chip_name = "REDWOOD";
1865                 break;
1866         case CHIP_JUNIPER:
1867                 chip_name = "JUNIPER";
1868                 rlc_chip_name = "JUNIPER";
1869                 break;
1870         case CHIP_CYPRESS:
1871         case CHIP_HEMLOCK:
1872                 chip_name = "CYPRESS";
1873                 rlc_chip_name = "CYPRESS";
1874                 break;
1875         default: BUG();
1876         }
1877
1878         if (rdev->family >= CHIP_CEDAR) {
1879                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1880                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
1881                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
1882         } else if (rdev->family >= CHIP_RV770) {
1883                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1884                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1885                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1886         } else {
1887                 pfp_req_size = PFP_UCODE_SIZE * 4;
1888                 me_req_size = PM4_UCODE_SIZE * 12;
1889                 rlc_req_size = RLC_UCODE_SIZE * 4;
1890         }
1891
1892         DRM_INFO("Loading %s Microcode\n", chip_name);
1893
1894         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1895         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1896         if (err)
1897                 goto out;
1898         if (rdev->pfp_fw->size != pfp_req_size) {
1899                 printk(KERN_ERR
1900                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1901                        rdev->pfp_fw->size, fw_name);
1902                 err = -EINVAL;
1903                 goto out;
1904         }
1905
1906         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1907         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1908         if (err)
1909                 goto out;
1910         if (rdev->me_fw->size != me_req_size) {
1911                 printk(KERN_ERR
1912                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1913                        rdev->me_fw->size, fw_name);
1914                 err = -EINVAL;
1915         }
1916
1917         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1918         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1919         if (err)
1920                 goto out;
1921         if (rdev->rlc_fw->size != rlc_req_size) {
1922                 printk(KERN_ERR
1923                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1924                        rdev->rlc_fw->size, fw_name);
1925                 err = -EINVAL;
1926         }
1927
1928 out:
1929         platform_device_unregister(pdev);
1930
1931         if (err) {
1932                 if (err != -EINVAL)
1933                         printk(KERN_ERR
1934                                "r600_cp: Failed to load firmware \"%s\"\n",
1935                                fw_name);
1936                 release_firmware(rdev->pfp_fw);
1937                 rdev->pfp_fw = NULL;
1938                 release_firmware(rdev->me_fw);
1939                 rdev->me_fw = NULL;
1940                 release_firmware(rdev->rlc_fw);
1941                 rdev->rlc_fw = NULL;
1942         }
1943         return err;
1944 }
1945
1946 static int r600_cp_load_microcode(struct radeon_device *rdev)
1947 {
1948         const __be32 *fw_data;
1949         int i;
1950
1951         if (!rdev->me_fw || !rdev->pfp_fw)
1952                 return -EINVAL;
1953
1954         r600_cp_stop(rdev);
1955
1956         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1957
1958         /* Reset cp */
1959         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1960         RREG32(GRBM_SOFT_RESET);
1961         mdelay(15);
1962         WREG32(GRBM_SOFT_RESET, 0);
1963
1964         WREG32(CP_ME_RAM_WADDR, 0);
1965
1966         fw_data = (const __be32 *)rdev->me_fw->data;
1967         WREG32(CP_ME_RAM_WADDR, 0);
1968         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1969                 WREG32(CP_ME_RAM_DATA,
1970                        be32_to_cpup(fw_data++));
1971
1972         fw_data = (const __be32 *)rdev->pfp_fw->data;
1973         WREG32(CP_PFP_UCODE_ADDR, 0);
1974         for (i = 0; i < PFP_UCODE_SIZE; i++)
1975                 WREG32(CP_PFP_UCODE_DATA,
1976                        be32_to_cpup(fw_data++));
1977
1978         WREG32(CP_PFP_UCODE_ADDR, 0);
1979         WREG32(CP_ME_RAM_WADDR, 0);
1980         WREG32(CP_ME_RAM_RADDR, 0);
1981         return 0;
1982 }
1983
1984 int r600_cp_start(struct radeon_device *rdev)
1985 {
1986         int r;
1987         uint32_t cp_me;
1988
1989         r = radeon_ring_lock(rdev, 7);
1990         if (r) {
1991                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1992                 return r;
1993         }
1994         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1995         radeon_ring_write(rdev, 0x1);
1996         if (rdev->family >= CHIP_CEDAR) {
1997                 radeon_ring_write(rdev, 0x0);
1998                 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1999         } else if (rdev->family >= CHIP_RV770) {
2000                 radeon_ring_write(rdev, 0x0);
2001                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2002         } else {
2003                 radeon_ring_write(rdev, 0x3);
2004                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2005         }
2006         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2007         radeon_ring_write(rdev, 0);
2008         radeon_ring_write(rdev, 0);
2009         radeon_ring_unlock_commit(rdev);
2010
2011         cp_me = 0xff;
2012         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2013         return 0;
2014 }
2015
2016 int r600_cp_resume(struct radeon_device *rdev)
2017 {
2018         u32 tmp;
2019         u32 rb_bufsz;
2020         int r;
2021
2022         /* Reset cp */
2023         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2024         RREG32(GRBM_SOFT_RESET);
2025         mdelay(15);
2026         WREG32(GRBM_SOFT_RESET, 0);
2027
2028         /* Set ring buffer size */
2029         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2030         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2031 #ifdef __BIG_ENDIAN
2032         tmp |= BUF_SWAP_32BIT;
2033 #endif
2034         WREG32(CP_RB_CNTL, tmp);
2035         WREG32(CP_SEM_WAIT_TIMER, 0x4);
2036
2037         /* Set the write pointer delay */
2038         WREG32(CP_RB_WPTR_DELAY, 0);
2039
2040         /* Initialize the ring buffer's read and write pointers */
2041         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2042         WREG32(CP_RB_RPTR_WR, 0);
2043         WREG32(CP_RB_WPTR, 0);
2044         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
2045         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
2046         mdelay(1);
2047         WREG32(CP_RB_CNTL, tmp);
2048
2049         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2050         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2051
2052         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2053         rdev->cp.wptr = RREG32(CP_RB_WPTR);
2054
2055         r600_cp_start(rdev);
2056         rdev->cp.ready = true;
2057         r = radeon_ring_test(rdev);
2058         if (r) {
2059                 rdev->cp.ready = false;
2060                 return r;
2061         }
2062         return 0;
2063 }
2064
2065 void r600_cp_commit(struct radeon_device *rdev)
2066 {
2067         WREG32(CP_RB_WPTR, rdev->cp.wptr);
2068         (void)RREG32(CP_RB_WPTR);
2069 }
2070
2071 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2072 {
2073         u32 rb_bufsz;
2074
2075         /* Align ring size */
2076         rb_bufsz = drm_order(ring_size / 8);
2077         ring_size = (1 << (rb_bufsz + 1)) * 4;
2078         rdev->cp.ring_size = ring_size;
2079         rdev->cp.align_mask = 16 - 1;
2080 }
2081
2082 void r600_cp_fini(struct radeon_device *rdev)
2083 {
2084         r600_cp_stop(rdev);
2085         radeon_ring_fini(rdev);
2086 }
2087
2088
2089 /*
2090  * GPU scratch registers helpers function.
2091  */
2092 void r600_scratch_init(struct radeon_device *rdev)
2093 {
2094         int i;
2095
2096         rdev->scratch.num_reg = 7;
2097         for (i = 0; i < rdev->scratch.num_reg; i++) {
2098                 rdev->scratch.free[i] = true;
2099                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
2100         }
2101 }
2102
2103 int r600_ring_test(struct radeon_device *rdev)
2104 {
2105         uint32_t scratch;
2106         uint32_t tmp = 0;
2107         unsigned i;
2108         int r;
2109
2110         r = radeon_scratch_get(rdev, &scratch);
2111         if (r) {
2112                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2113                 return r;
2114         }
2115         WREG32(scratch, 0xCAFEDEAD);
2116         r = radeon_ring_lock(rdev, 3);
2117         if (r) {
2118                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2119                 radeon_scratch_free(rdev, scratch);
2120                 return r;
2121         }
2122         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2123         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2124         radeon_ring_write(rdev, 0xDEADBEEF);
2125         radeon_ring_unlock_commit(rdev);
2126         for (i = 0; i < rdev->usec_timeout; i++) {
2127                 tmp = RREG32(scratch);
2128                 if (tmp == 0xDEADBEEF)
2129                         break;
2130                 DRM_UDELAY(1);
2131         }
2132         if (i < rdev->usec_timeout) {
2133                 DRM_INFO("ring test succeeded in %d usecs\n", i);
2134         } else {
2135                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2136                           scratch, tmp);
2137                 r = -EINVAL;
2138         }
2139         radeon_scratch_free(rdev, scratch);
2140         return r;
2141 }
2142
2143 void r600_wb_disable(struct radeon_device *rdev)
2144 {
2145         int r;
2146
2147         WREG32(SCRATCH_UMSK, 0);
2148         if (rdev->wb.wb_obj) {
2149                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2150                 if (unlikely(r != 0))
2151                         return;
2152                 radeon_bo_kunmap(rdev->wb.wb_obj);
2153                 radeon_bo_unpin(rdev->wb.wb_obj);
2154                 radeon_bo_unreserve(rdev->wb.wb_obj);
2155         }
2156 }
2157
2158 void r600_wb_fini(struct radeon_device *rdev)
2159 {
2160         r600_wb_disable(rdev);
2161         if (rdev->wb.wb_obj) {
2162                 radeon_bo_unref(&rdev->wb.wb_obj);
2163                 rdev->wb.wb = NULL;
2164                 rdev->wb.wb_obj = NULL;
2165         }
2166 }
2167
2168 int r600_wb_enable(struct radeon_device *rdev)
2169 {
2170         int r;
2171
2172         if (rdev->wb.wb_obj == NULL) {
2173                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
2174                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
2175                 if (r) {
2176                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
2177                         return r;
2178                 }
2179                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2180                 if (unlikely(r != 0)) {
2181                         r600_wb_fini(rdev);
2182                         return r;
2183                 }
2184                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
2185                                 &rdev->wb.gpu_addr);
2186                 if (r) {
2187                         radeon_bo_unreserve(rdev->wb.wb_obj);
2188                         dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
2189                         r600_wb_fini(rdev);
2190                         return r;
2191                 }
2192                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
2193                 radeon_bo_unreserve(rdev->wb.wb_obj);
2194                 if (r) {
2195                         dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
2196                         r600_wb_fini(rdev);
2197                         return r;
2198                 }
2199         }
2200         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
2201         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
2202         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
2203         WREG32(SCRATCH_UMSK, 0xff);
2204         return 0;
2205 }
2206
2207 void r600_fence_ring_emit(struct radeon_device *rdev,
2208                           struct radeon_fence *fence)
2209 {
2210         /* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
2211
2212         radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2213         radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
2214         /* wait for 3D idle clean */
2215         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2216         radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2217         radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2218         /* Emit fence sequence & fire IRQ */
2219         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2220         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2221         radeon_ring_write(rdev, fence->seq);
2222         /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2223         radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2224         radeon_ring_write(rdev, RB_INT_STAT);
2225 }
2226
2227 int r600_copy_blit(struct radeon_device *rdev,
2228                    uint64_t src_offset, uint64_t dst_offset,
2229                    unsigned num_pages, struct radeon_fence *fence)
2230 {
2231         int r;
2232
2233         mutex_lock(&rdev->r600_blit.mutex);
2234         rdev->r600_blit.vb_ib = NULL;
2235         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2236         if (r) {
2237                 if (rdev->r600_blit.vb_ib)
2238                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2239                 mutex_unlock(&rdev->r600_blit.mutex);
2240                 return r;
2241         }
2242         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2243         r600_blit_done_copy(rdev, fence);
2244         mutex_unlock(&rdev->r600_blit.mutex);
2245         return 0;
2246 }
2247
2248 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2249                          uint32_t tiling_flags, uint32_t pitch,
2250                          uint32_t offset, uint32_t obj_size)
2251 {
2252         /* FIXME: implement */
2253         return 0;
2254 }
2255
2256 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2257 {
2258         /* FIXME: implement */
2259 }
2260
2261
2262 bool r600_card_posted(struct radeon_device *rdev)
2263 {
2264         uint32_t reg;
2265
2266         /* first check CRTCs */
2267         reg = RREG32(D1CRTC_CONTROL) |
2268                 RREG32(D2CRTC_CONTROL);
2269         if (reg & CRTC_EN)
2270                 return true;
2271
2272         /* then check MEM_SIZE, in case the crtcs are off */
2273         if (RREG32(CONFIG_MEMSIZE))
2274                 return true;
2275
2276         return false;
2277 }
2278
2279 int r600_startup(struct radeon_device *rdev)
2280 {
2281         int r;
2282
2283         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2284                 r = r600_init_microcode(rdev);
2285                 if (r) {
2286                         DRM_ERROR("Failed to load firmware!\n");
2287                         return r;
2288                 }
2289         }
2290
2291         r600_mc_program(rdev);
2292         if (rdev->flags & RADEON_IS_AGP) {
2293                 r600_agp_enable(rdev);
2294         } else {
2295                 r = r600_pcie_gart_enable(rdev);
2296                 if (r)
2297                         return r;
2298         }
2299         r600_gpu_init(rdev);
2300         r = r600_blit_init(rdev);
2301         if (r) {
2302                 r600_blit_fini(rdev);
2303                 rdev->asic->copy = NULL;
2304                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2305         }
2306         /* pin copy shader into vram */
2307         if (rdev->r600_blit.shader_obj) {
2308                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2309                 if (unlikely(r != 0))
2310                         return r;
2311                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
2312                                 &rdev->r600_blit.shader_gpu_addr);
2313                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2314                 if (r) {
2315                         dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
2316                         return r;
2317                 }
2318         }
2319         /* Enable IRQ */
2320         r = r600_irq_init(rdev);
2321         if (r) {
2322                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2323                 radeon_irq_kms_fini(rdev);
2324                 return r;
2325         }
2326         r600_irq_set(rdev);
2327
2328         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2329         if (r)
2330                 return r;
2331         r = r600_cp_load_microcode(rdev);
2332         if (r)
2333                 return r;
2334         r = r600_cp_resume(rdev);
2335         if (r)
2336                 return r;
2337         /* write back buffer are not vital so don't worry about failure */
2338         r600_wb_enable(rdev);
2339         return 0;
2340 }
2341
2342 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2343 {
2344         uint32_t temp;
2345
2346         temp = RREG32(CONFIG_CNTL);
2347         if (state == false) {
2348                 temp &= ~(1<<0);
2349                 temp |= (1<<1);
2350         } else {
2351                 temp &= ~(1<<1);
2352         }
2353         WREG32(CONFIG_CNTL, temp);
2354 }
2355
2356 int r600_resume(struct radeon_device *rdev)
2357 {
2358         int r;
2359
2360         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2361          * posting will perform necessary task to bring back GPU into good
2362          * shape.
2363          */
2364         /* post card */
2365         atom_asic_init(rdev->mode_info.atom_context);
2366         /* Initialize clocks */
2367         r = radeon_clocks_init(rdev);
2368         if (r) {
2369                 return r;
2370         }
2371
2372         r = r600_startup(rdev);
2373         if (r) {
2374                 DRM_ERROR("r600 startup failed on resume\n");
2375                 return r;
2376         }
2377
2378         r = r600_ib_test(rdev);
2379         if (r) {
2380                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2381                 return r;
2382         }
2383
2384         r = r600_audio_init(rdev);
2385         if (r) {
2386                 DRM_ERROR("radeon: audio resume failed\n");
2387                 return r;
2388         }
2389
2390         return r;
2391 }
2392
2393 int r600_suspend(struct radeon_device *rdev)
2394 {
2395         int r;
2396
2397         r600_audio_fini(rdev);
2398         /* FIXME: we should wait for ring to be empty */
2399         r600_cp_stop(rdev);
2400         rdev->cp.ready = false;
2401         r600_irq_suspend(rdev);
2402         r600_wb_disable(rdev);
2403         r600_pcie_gart_disable(rdev);
2404         /* unpin shaders bo */
2405         if (rdev->r600_blit.shader_obj) {
2406                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2407                 if (!r) {
2408                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2409                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2410                 }
2411         }
2412         return 0;
2413 }
2414
2415 /* Plan is to move initialization in that function and use
2416  * helper function so that radeon_device_init pretty much
2417  * do nothing more than calling asic specific function. This
2418  * should also allow to remove a bunch of callback function
2419  * like vram_info.
2420  */
2421 int r600_init(struct radeon_device *rdev)
2422 {
2423         int r;
2424
2425         r = radeon_dummy_page_init(rdev);
2426         if (r)
2427                 return r;
2428         if (r600_debugfs_mc_info_init(rdev)) {
2429                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2430         }
2431         /* This don't do much */
2432         r = radeon_gem_init(rdev);
2433         if (r)
2434                 return r;
2435         /* Read BIOS */
2436         if (!radeon_get_bios(rdev)) {
2437                 if (ASIC_IS_AVIVO(rdev))
2438                         return -EINVAL;
2439         }
2440         /* Must be an ATOMBIOS */
2441         if (!rdev->is_atom_bios) {
2442                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2443                 return -EINVAL;
2444         }
2445         r = radeon_atombios_init(rdev);
2446         if (r)
2447                 return r;
2448         /* Post card if necessary */
2449         if (!r600_card_posted(rdev)) {
2450                 if (!rdev->bios) {
2451                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2452                         return -EINVAL;
2453                 }
2454                 DRM_INFO("GPU not posted. posting now...\n");
2455                 atom_asic_init(rdev->mode_info.atom_context);
2456         }
2457         /* Initialize scratch registers */
2458         r600_scratch_init(rdev);
2459         /* Initialize surface registers */
2460         radeon_surface_init(rdev);
2461         /* Initialize clocks */
2462         radeon_get_clock_info(rdev->ddev);
2463         r = radeon_clocks_init(rdev);
2464         if (r)
2465                 return r;
2466         /* Fence driver */
2467         r = radeon_fence_driver_init(rdev);
2468         if (r)
2469                 return r;
2470         if (rdev->flags & RADEON_IS_AGP) {
2471                 r = radeon_agp_init(rdev);
2472                 if (r)
2473                         radeon_agp_disable(rdev);
2474         }
2475         r = r600_mc_init(rdev);
2476         if (r)
2477                 return r;
2478         /* Memory manager */
2479         r = radeon_bo_init(rdev);
2480         if (r)
2481                 return r;
2482
2483         r = radeon_irq_kms_init(rdev);
2484         if (r)
2485                 return r;
2486
2487         rdev->cp.ring_obj = NULL;
2488         r600_ring_init(rdev, 1024 * 1024);
2489
2490         rdev->ih.ring_obj = NULL;
2491         r600_ih_ring_init(rdev, 64 * 1024);
2492
2493         r = r600_pcie_gart_init(rdev);
2494         if (r)
2495                 return r;
2496
2497         rdev->accel_working = true;
2498         r = r600_startup(rdev);
2499         if (r) {
2500                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2501                 r600_cp_fini(rdev);
2502                 r600_wb_fini(rdev);
2503                 r600_irq_fini(rdev);
2504                 radeon_irq_kms_fini(rdev);
2505                 r600_pcie_gart_fini(rdev);
2506                 rdev->accel_working = false;
2507         }
2508         if (rdev->accel_working) {
2509                 r = radeon_ib_pool_init(rdev);
2510                 if (r) {
2511                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2512                         rdev->accel_working = false;
2513                 } else {
2514                         r = r600_ib_test(rdev);
2515                         if (r) {
2516                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2517                                 rdev->accel_working = false;
2518                         }
2519                 }
2520         }
2521
2522         r = r600_audio_init(rdev);
2523         if (r)
2524                 return r; /* TODO error handling */
2525         return 0;
2526 }
2527
2528 void r600_fini(struct radeon_device *rdev)
2529 {
2530         r600_audio_fini(rdev);
2531         r600_blit_fini(rdev);
2532         r600_cp_fini(rdev);
2533         r600_wb_fini(rdev);
2534         r600_irq_fini(rdev);
2535         radeon_irq_kms_fini(rdev);
2536         r600_pcie_gart_fini(rdev);
2537         radeon_agp_fini(rdev);
2538         radeon_gem_fini(rdev);
2539         radeon_fence_driver_fini(rdev);
2540         radeon_clocks_fini(rdev);
2541         radeon_bo_fini(rdev);
2542         radeon_atombios_fini(rdev);
2543         kfree(rdev->bios);
2544         rdev->bios = NULL;
2545         radeon_dummy_page_fini(rdev);
2546 }
2547
2548
2549 /*
2550  * CS stuff
2551  */
2552 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2553 {
2554         /* FIXME: implement */
2555         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2556         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2557         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2558         radeon_ring_write(rdev, ib->length_dw);
2559 }
2560
2561 int r600_ib_test(struct radeon_device *rdev)
2562 {
2563         struct radeon_ib *ib;
2564         uint32_t scratch;
2565         uint32_t tmp = 0;
2566         unsigned i;
2567         int r;
2568
2569         r = radeon_scratch_get(rdev, &scratch);
2570         if (r) {
2571                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2572                 return r;
2573         }
2574         WREG32(scratch, 0xCAFEDEAD);
2575         r = radeon_ib_get(rdev, &ib);
2576         if (r) {
2577                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2578                 return r;
2579         }
2580         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2581         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2582         ib->ptr[2] = 0xDEADBEEF;
2583         ib->ptr[3] = PACKET2(0);
2584         ib->ptr[4] = PACKET2(0);
2585         ib->ptr[5] = PACKET2(0);
2586         ib->ptr[6] = PACKET2(0);
2587         ib->ptr[7] = PACKET2(0);
2588         ib->ptr[8] = PACKET2(0);
2589         ib->ptr[9] = PACKET2(0);
2590         ib->ptr[10] = PACKET2(0);
2591         ib->ptr[11] = PACKET2(0);
2592         ib->ptr[12] = PACKET2(0);
2593         ib->ptr[13] = PACKET2(0);
2594         ib->ptr[14] = PACKET2(0);
2595         ib->ptr[15] = PACKET2(0);
2596         ib->length_dw = 16;
2597         r = radeon_ib_schedule(rdev, ib);
2598         if (r) {
2599                 radeon_scratch_free(rdev, scratch);
2600                 radeon_ib_free(rdev, &ib);
2601                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2602                 return r;
2603         }
2604         r = radeon_fence_wait(ib->fence, false);
2605         if (r) {
2606                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2607                 return r;
2608         }
2609         for (i = 0; i < rdev->usec_timeout; i++) {
2610                 tmp = RREG32(scratch);
2611                 if (tmp == 0xDEADBEEF)
2612                         break;
2613                 DRM_UDELAY(1);
2614         }
2615         if (i < rdev->usec_timeout) {
2616                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2617         } else {
2618                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2619                           scratch, tmp);
2620                 r = -EINVAL;
2621         }
2622         radeon_scratch_free(rdev, scratch);
2623         radeon_ib_free(rdev, &ib);
2624         return r;
2625 }
2626
2627 /*
2628  * Interrupts
2629  *
2630  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2631  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2632  * writing to the ring and the GPU consuming, the GPU writes to the ring
2633  * and host consumes.  As the host irq handler processes interrupts, it
2634  * increments the rptr.  When the rptr catches up with the wptr, all the
2635  * current interrupts have been processed.
2636  */
2637
2638 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2639 {
2640         u32 rb_bufsz;
2641
2642         /* Align ring size */
2643         rb_bufsz = drm_order(ring_size / 4);
2644         ring_size = (1 << rb_bufsz) * 4;
2645         rdev->ih.ring_size = ring_size;
2646         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2647         rdev->ih.rptr = 0;
2648 }
2649
2650 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2651 {
2652         int r;
2653
2654         /* Allocate ring buffer */
2655         if (rdev->ih.ring_obj == NULL) {
2656                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2657                                      true,
2658                                      RADEON_GEM_DOMAIN_GTT,
2659                                      &rdev->ih.ring_obj);
2660                 if (r) {
2661                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2662                         return r;
2663                 }
2664                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2665                 if (unlikely(r != 0))
2666                         return r;
2667                 r = radeon_bo_pin(rdev->ih.ring_obj,
2668                                   RADEON_GEM_DOMAIN_GTT,
2669                                   &rdev->ih.gpu_addr);
2670                 if (r) {
2671                         radeon_bo_unreserve(rdev->ih.ring_obj);
2672                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2673                         return r;
2674                 }
2675                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2676                                    (void **)&rdev->ih.ring);
2677                 radeon_bo_unreserve(rdev->ih.ring_obj);
2678                 if (r) {
2679                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2680                         return r;
2681                 }
2682         }
2683         return 0;
2684 }
2685
2686 static void r600_ih_ring_fini(struct radeon_device *rdev)
2687 {
2688         int r;
2689         if (rdev->ih.ring_obj) {
2690                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2691                 if (likely(r == 0)) {
2692                         radeon_bo_kunmap(rdev->ih.ring_obj);
2693                         radeon_bo_unpin(rdev->ih.ring_obj);
2694                         radeon_bo_unreserve(rdev->ih.ring_obj);
2695                 }
2696                 radeon_bo_unref(&rdev->ih.ring_obj);
2697                 rdev->ih.ring = NULL;
2698                 rdev->ih.ring_obj = NULL;
2699         }
2700 }
2701
2702 void r600_rlc_stop(struct radeon_device *rdev)
2703 {
2704
2705         if ((rdev->family >= CHIP_RV770) &&
2706             (rdev->family <= CHIP_RV740)) {
2707                 /* r7xx asics need to soft reset RLC before halting */
2708                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2709                 RREG32(SRBM_SOFT_RESET);
2710                 udelay(15000);
2711                 WREG32(SRBM_SOFT_RESET, 0);
2712                 RREG32(SRBM_SOFT_RESET);
2713         }
2714
2715         WREG32(RLC_CNTL, 0);
2716 }
2717
2718 static void r600_rlc_start(struct radeon_device *rdev)
2719 {
2720         WREG32(RLC_CNTL, RLC_ENABLE);
2721 }
2722
2723 static int r600_rlc_init(struct radeon_device *rdev)
2724 {
2725         u32 i;
2726         const __be32 *fw_data;
2727
2728         if (!rdev->rlc_fw)
2729                 return -EINVAL;
2730
2731         r600_rlc_stop(rdev);
2732
2733         WREG32(RLC_HB_BASE, 0);
2734         WREG32(RLC_HB_CNTL, 0);
2735         WREG32(RLC_HB_RPTR, 0);
2736         WREG32(RLC_HB_WPTR, 0);
2737         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2738         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2739         WREG32(RLC_MC_CNTL, 0);
2740         WREG32(RLC_UCODE_CNTL, 0);
2741
2742         fw_data = (const __be32 *)rdev->rlc_fw->data;
2743         if (rdev->family >= CHIP_CEDAR) {
2744                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2745                         WREG32(RLC_UCODE_ADDR, i);
2746                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2747                 }
2748         } else if (rdev->family >= CHIP_RV770) {
2749                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2750                         WREG32(RLC_UCODE_ADDR, i);
2751                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2752                 }
2753         } else {
2754                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2755                         WREG32(RLC_UCODE_ADDR, i);
2756                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2757                 }
2758         }
2759         WREG32(RLC_UCODE_ADDR, 0);
2760
2761         r600_rlc_start(rdev);
2762
2763         return 0;
2764 }
2765
2766 static void r600_enable_interrupts(struct radeon_device *rdev)
2767 {
2768         u32 ih_cntl = RREG32(IH_CNTL);
2769         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2770
2771         ih_cntl |= ENABLE_INTR;
2772         ih_rb_cntl |= IH_RB_ENABLE;
2773         WREG32(IH_CNTL, ih_cntl);
2774         WREG32(IH_RB_CNTL, ih_rb_cntl);
2775         rdev->ih.enabled = true;
2776 }
2777
2778 void r600_disable_interrupts(struct radeon_device *rdev)
2779 {
2780         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2781         u32 ih_cntl = RREG32(IH_CNTL);
2782
2783         ih_rb_cntl &= ~IH_RB_ENABLE;
2784         ih_cntl &= ~ENABLE_INTR;
2785         WREG32(IH_RB_CNTL, ih_rb_cntl);
2786         WREG32(IH_CNTL, ih_cntl);
2787         /* set rptr, wptr to 0 */
2788         WREG32(IH_RB_RPTR, 0);
2789         WREG32(IH_RB_WPTR, 0);
2790         rdev->ih.enabled = false;
2791         rdev->ih.wptr = 0;
2792         rdev->ih.rptr = 0;
2793 }
2794
2795 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2796 {
2797         u32 tmp;
2798
2799         WREG32(CP_INT_CNTL, 0);
2800         WREG32(GRBM_INT_CNTL, 0);
2801         WREG32(DxMODE_INT_MASK, 0);
2802         if (ASIC_IS_DCE3(rdev)) {
2803                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2804                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2805                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2806                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2807                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2808                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2809                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2810                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2811                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2812                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2813                 if (ASIC_IS_DCE32(rdev)) {
2814                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2815                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2816                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2817                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2818                 }
2819         } else {
2820                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2821                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2822                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2823                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2824                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2825                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2826                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2827                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2828         }
2829 }
2830
2831 int r600_irq_init(struct radeon_device *rdev)
2832 {
2833         int ret = 0;
2834         int rb_bufsz;
2835         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2836
2837         /* allocate ring */
2838         ret = r600_ih_ring_alloc(rdev);
2839         if (ret)
2840                 return ret;
2841
2842         /* disable irqs */
2843         r600_disable_interrupts(rdev);
2844
2845         /* init rlc */
2846         ret = r600_rlc_init(rdev);
2847         if (ret) {
2848                 r600_ih_ring_fini(rdev);
2849                 return ret;
2850         }
2851
2852         /* setup interrupt control */
2853         /* set dummy read address to ring address */
2854         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2855         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2856         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2857          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2858          */
2859         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2860         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2861         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2862         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2863
2864         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2865         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2866
2867         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2868                       IH_WPTR_OVERFLOW_CLEAR |
2869                       (rb_bufsz << 1));
2870         /* WPTR writeback, not yet */
2871         /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2872         WREG32(IH_RB_WPTR_ADDR_LO, 0);
2873         WREG32(IH_RB_WPTR_ADDR_HI, 0);
2874
2875         WREG32(IH_RB_CNTL, ih_rb_cntl);
2876
2877         /* set rptr, wptr to 0 */
2878         WREG32(IH_RB_RPTR, 0);
2879         WREG32(IH_RB_WPTR, 0);
2880
2881         /* Default settings for IH_CNTL (disabled at first) */
2882         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2883         /* RPTR_REARM only works if msi's are enabled */
2884         if (rdev->msi_enabled)
2885                 ih_cntl |= RPTR_REARM;
2886
2887 #ifdef __BIG_ENDIAN
2888         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2889 #endif
2890         WREG32(IH_CNTL, ih_cntl);
2891
2892         /* force the active interrupt state to all disabled */
2893         if (rdev->family >= CHIP_CEDAR)
2894                 evergreen_disable_interrupt_state(rdev);
2895         else
2896                 r600_disable_interrupt_state(rdev);
2897
2898         /* enable irqs */
2899         r600_enable_interrupts(rdev);
2900
2901         return ret;
2902 }
2903
2904 void r600_irq_suspend(struct radeon_device *rdev)
2905 {
2906         r600_irq_disable(rdev);
2907         r600_rlc_stop(rdev);
2908 }
2909
2910 void r600_irq_fini(struct radeon_device *rdev)
2911 {
2912         r600_irq_suspend(rdev);
2913         r600_ih_ring_fini(rdev);
2914 }
2915
2916 int r600_irq_set(struct radeon_device *rdev)
2917 {
2918         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2919         u32 mode_int = 0;
2920         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2921         u32 grbm_int_cntl = 0;
2922         u32 hdmi1, hdmi2;
2923
2924         if (!rdev->irq.installed) {
2925                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2926                 return -EINVAL;
2927         }
2928         /* don't enable anything if the ih is disabled */
2929         if (!rdev->ih.enabled) {
2930                 r600_disable_interrupts(rdev);
2931                 /* force the active interrupt state to all disabled */
2932                 r600_disable_interrupt_state(rdev);
2933                 return 0;
2934         }
2935
2936         hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
2937         if (ASIC_IS_DCE3(rdev)) {
2938                 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
2939                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2940                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2941                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2942                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2943                 if (ASIC_IS_DCE32(rdev)) {
2944                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2945                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2946                 }
2947         } else {
2948                 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
2949                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2950                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2951                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2952         }
2953
2954         if (rdev->irq.sw_int) {
2955                 DRM_DEBUG("r600_irq_set: sw int\n");
2956                 cp_int_cntl |= RB_INT_ENABLE;
2957         }
2958         if (rdev->irq.crtc_vblank_int[0]) {
2959                 DRM_DEBUG("r600_irq_set: vblank 0\n");
2960                 mode_int |= D1MODE_VBLANK_INT_MASK;
2961         }
2962         if (rdev->irq.crtc_vblank_int[1]) {
2963                 DRM_DEBUG("r600_irq_set: vblank 1\n");
2964                 mode_int |= D2MODE_VBLANK_INT_MASK;
2965         }
2966         if (rdev->irq.hpd[0]) {
2967                 DRM_DEBUG("r600_irq_set: hpd 1\n");
2968                 hpd1 |= DC_HPDx_INT_EN;
2969         }
2970         if (rdev->irq.hpd[1]) {
2971                 DRM_DEBUG("r600_irq_set: hpd 2\n");
2972                 hpd2 |= DC_HPDx_INT_EN;
2973         }
2974         if (rdev->irq.hpd[2]) {
2975                 DRM_DEBUG("r600_irq_set: hpd 3\n");
2976                 hpd3 |= DC_HPDx_INT_EN;
2977         }
2978         if (rdev->irq.hpd[3]) {
2979                 DRM_DEBUG("r600_irq_set: hpd 4\n");
2980                 hpd4 |= DC_HPDx_INT_EN;
2981         }
2982         if (rdev->irq.hpd[4]) {
2983                 DRM_DEBUG("r600_irq_set: hpd 5\n");
2984                 hpd5 |= DC_HPDx_INT_EN;
2985         }
2986         if (rdev->irq.hpd[5]) {
2987                 DRM_DEBUG("r600_irq_set: hpd 6\n");
2988                 hpd6 |= DC_HPDx_INT_EN;
2989         }
2990         if (rdev->irq.hdmi[0]) {
2991                 DRM_DEBUG("r600_irq_set: hdmi 1\n");
2992                 hdmi1 |= R600_HDMI_INT_EN;
2993         }
2994         if (rdev->irq.hdmi[1]) {
2995                 DRM_DEBUG("r600_irq_set: hdmi 2\n");
2996                 hdmi2 |= R600_HDMI_INT_EN;
2997         }
2998         if (rdev->irq.gui_idle) {
2999                 DRM_DEBUG("gui idle\n");
3000                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3001         }
3002
3003         WREG32(CP_INT_CNTL, cp_int_cntl);
3004         WREG32(DxMODE_INT_MASK, mode_int);
3005         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3006         WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3007         if (ASIC_IS_DCE3(rdev)) {
3008                 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3009                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3010                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3011                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3012                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3013                 if (ASIC_IS_DCE32(rdev)) {
3014                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3015                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3016                 }
3017         } else {
3018                 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3019                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3020                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3021                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3022         }
3023
3024         return 0;
3025 }
3026
3027 static inline void r600_irq_ack(struct radeon_device *rdev,
3028                                 u32 *disp_int,
3029                                 u32 *disp_int_cont,
3030                                 u32 *disp_int_cont2)
3031 {
3032         u32 tmp;
3033
3034         if (ASIC_IS_DCE3(rdev)) {
3035                 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3036                 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3037                 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3038         } else {
3039                 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
3040                 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3041                 *disp_int_cont2 = 0;
3042         }
3043
3044         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
3045                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3046         if (*disp_int & LB_D1_VLINE_INTERRUPT)
3047                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3048         if (*disp_int & LB_D2_VBLANK_INTERRUPT)
3049                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3050         if (*disp_int & LB_D2_VLINE_INTERRUPT)
3051                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3052         if (*disp_int & DC_HPD1_INTERRUPT) {
3053                 if (ASIC_IS_DCE3(rdev)) {
3054                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3055                         tmp |= DC_HPDx_INT_ACK;
3056                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3057                 } else {
3058                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3059                         tmp |= DC_HPDx_INT_ACK;
3060                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3061                 }
3062         }
3063         if (*disp_int & DC_HPD2_INTERRUPT) {
3064                 if (ASIC_IS_DCE3(rdev)) {
3065                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3066                         tmp |= DC_HPDx_INT_ACK;
3067                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3068                 } else {
3069                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3070                         tmp |= DC_HPDx_INT_ACK;
3071                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3072                 }
3073         }
3074         if (*disp_int_cont & DC_HPD3_INTERRUPT) {
3075                 if (ASIC_IS_DCE3(rdev)) {
3076                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3077                         tmp |= DC_HPDx_INT_ACK;
3078                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3079                 } else {
3080                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3081                         tmp |= DC_HPDx_INT_ACK;
3082                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3083                 }
3084         }
3085         if (*disp_int_cont & DC_HPD4_INTERRUPT) {
3086                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3087                 tmp |= DC_HPDx_INT_ACK;
3088                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3089         }
3090         if (ASIC_IS_DCE32(rdev)) {
3091                 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
3092                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3093                         tmp |= DC_HPDx_INT_ACK;
3094                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3095                 }
3096                 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
3097                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3098                         tmp |= DC_HPDx_INT_ACK;
3099                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3100                 }
3101         }
3102         if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3103                 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3104         }
3105         if (ASIC_IS_DCE3(rdev)) {
3106                 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3107                         WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3108                 }
3109         } else {
3110                 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3111                         WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3112                 }
3113         }
3114 }
3115
3116 void r600_irq_disable(struct radeon_device *rdev)
3117 {
3118         u32 disp_int, disp_int_cont, disp_int_cont2;
3119
3120         r600_disable_interrupts(rdev);
3121         /* Wait and acknowledge irq */
3122         mdelay(1);
3123         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3124         r600_disable_interrupt_state(rdev);
3125 }
3126
3127 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3128 {
3129         u32 wptr, tmp;
3130
3131         /* XXX use writeback */
3132         wptr = RREG32(IH_RB_WPTR);
3133
3134         if (wptr & RB_OVERFLOW) {
3135                 /* When a ring buffer overflow happen start parsing interrupt
3136                  * from the last not overwritten vector (wptr + 16). Hopefully
3137                  * this should allow us to catchup.
3138                  */
3139                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3140                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3141                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3142                 tmp = RREG32(IH_RB_CNTL);
3143                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3144                 WREG32(IH_RB_CNTL, tmp);
3145         }
3146         return (wptr & rdev->ih.ptr_mask);
3147 }
3148
3149 /*        r600 IV Ring
3150  * Each IV ring entry is 128 bits:
3151  * [7:0]    - interrupt source id
3152  * [31:8]   - reserved
3153  * [59:32]  - interrupt source data
3154  * [127:60]  - reserved
3155  *
3156  * The basic interrupt vector entries
3157  * are decoded as follows:
3158  * src_id  src_data  description
3159  *      1         0  D1 Vblank
3160  *      1         1  D1 Vline
3161  *      5         0  D2 Vblank
3162  *      5         1  D2 Vline
3163  *     19         0  FP Hot plug detection A
3164  *     19         1  FP Hot plug detection B
3165  *     19         2  DAC A auto-detection
3166  *     19         3  DAC B auto-detection
3167  *     21         4  HDMI block A
3168  *     21         5  HDMI block B
3169  *    176         -  CP_INT RB
3170  *    177         -  CP_INT IB1
3171  *    178         -  CP_INT IB2
3172  *    181         -  EOP Interrupt
3173  *    233         -  GUI Idle
3174  *
3175  * Note, these are based on r600 and may need to be
3176  * adjusted or added to on newer asics
3177  */
3178
3179 int r600_irq_process(struct radeon_device *rdev)
3180 {
3181         u32 wptr = r600_get_ih_wptr(rdev);
3182         u32 rptr = rdev->ih.rptr;
3183         u32 src_id, src_data;
3184         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
3185         unsigned long flags;
3186         bool queue_hotplug = false;
3187
3188         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3189         if (!rdev->ih.enabled)
3190                 return IRQ_NONE;
3191
3192         spin_lock_irqsave(&rdev->ih.lock, flags);
3193
3194         if (rptr == wptr) {
3195                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3196                 return IRQ_NONE;
3197         }
3198         if (rdev->shutdown) {
3199                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3200                 return IRQ_NONE;
3201         }
3202
3203 restart_ih:
3204         /* display interrupts */
3205         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3206
3207         rdev->ih.wptr = wptr;
3208         while (rptr != wptr) {
3209                 /* wptr/rptr are in bytes! */
3210                 ring_index = rptr / 4;
3211                 src_id =  rdev->ih.ring[ring_index] & 0xff;
3212                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3213
3214                 switch (src_id) {
3215                 case 1: /* D1 vblank/vline */
3216                         switch (src_data) {
3217                         case 0: /* D1 vblank */
3218                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3219                                         drm_handle_vblank(rdev->ddev, 0);
3220                                         rdev->pm.vblank_sync = true;
3221                                         wake_up(&rdev->irq.vblank_queue);
3222                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3223                                         DRM_DEBUG("IH: D1 vblank\n");
3224                                 }
3225                                 break;
3226                         case 1: /* D1 vline */
3227                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3228                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
3229                                         DRM_DEBUG("IH: D1 vline\n");
3230                                 }
3231                                 break;
3232                         default:
3233                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3234                                 break;
3235                         }
3236                         break;
3237                 case 5: /* D2 vblank/vline */
3238                         switch (src_data) {
3239                         case 0: /* D2 vblank */
3240                                 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3241                                         drm_handle_vblank(rdev->ddev, 1);
3242                                         rdev->pm.vblank_sync = true;
3243                                         wake_up(&rdev->irq.vblank_queue);
3244                                         disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3245                                         DRM_DEBUG("IH: D2 vblank\n");
3246                                 }
3247                                 break;
3248                         case 1: /* D1 vline */
3249                                 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3250                                         disp_int &= ~LB_D2_VLINE_INTERRUPT;
3251                                         DRM_DEBUG("IH: D2 vline\n");
3252                                 }
3253                                 break;
3254                         default:
3255                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3256                                 break;
3257                         }
3258                         break;
3259                 case 19: /* HPD/DAC hotplug */
3260                         switch (src_data) {
3261                         case 0:
3262                                 if (disp_int & DC_HPD1_INTERRUPT) {
3263                                         disp_int &= ~DC_HPD1_INTERRUPT;
3264                                         queue_hotplug = true;
3265                                         DRM_DEBUG("IH: HPD1\n");
3266                                 }
3267                                 break;
3268                         case 1:
3269                                 if (disp_int & DC_HPD2_INTERRUPT) {
3270                                         disp_int &= ~DC_HPD2_INTERRUPT;
3271                                         queue_hotplug = true;
3272                                         DRM_DEBUG("IH: HPD2\n");
3273                                 }
3274                                 break;
3275                         case 4:
3276                                 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3277                                         disp_int_cont &= ~DC_HPD3_INTERRUPT;
3278                                         queue_hotplug = true;
3279                                         DRM_DEBUG("IH: HPD3\n");
3280                                 }
3281                                 break;
3282                         case 5:
3283                                 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3284                                         disp_int_cont &= ~DC_HPD4_INTERRUPT;
3285                                         queue_hotplug = true;
3286                                         DRM_DEBUG("IH: HPD4\n");
3287                                 }
3288                                 break;
3289                         case 10:
3290                                 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
3291                                         disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3292                                         queue_hotplug = true;
3293                                         DRM_DEBUG("IH: HPD5\n");
3294                                 }
3295                                 break;
3296                         case 12:
3297                                 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
3298                                         disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3299                                         queue_hotplug = true;
3300                                         DRM_DEBUG("IH: HPD6\n");
3301                                 }
3302                                 break;
3303                         default:
3304                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3305                                 break;
3306                         }
3307                         break;
3308                 case 21: /* HDMI */
3309                         DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3310                         r600_audio_schedule_polling(rdev);
3311                         break;
3312                 case 176: /* CP_INT in ring buffer */
3313                 case 177: /* CP_INT in IB1 */
3314                 case 178: /* CP_INT in IB2 */
3315                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3316                         radeon_fence_process(rdev);
3317                         break;
3318                 case 181: /* CP EOP event */
3319                         DRM_DEBUG("IH: CP EOP\n");
3320                         break;
3321                 case 233: /* GUI IDLE */
3322                         DRM_DEBUG("IH: CP EOP\n");
3323                         rdev->pm.gui_idle = true;
3324                         wake_up(&rdev->irq.idle_queue);
3325                         break;
3326                 default:
3327                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3328                         break;
3329                 }
3330
3331                 /* wptr/rptr are in bytes! */
3332                 rptr += 16;
3333                 rptr &= rdev->ih.ptr_mask;
3334         }
3335         /* make sure wptr hasn't changed while processing */
3336         wptr = r600_get_ih_wptr(rdev);
3337         if (wptr != rdev->ih.wptr)
3338                 goto restart_ih;
3339         if (queue_hotplug)
3340                 queue_work(rdev->wq, &rdev->hotplug_work);
3341         rdev->ih.rptr = rptr;
3342         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3343         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3344         return IRQ_HANDLED;
3345 }
3346
3347 /*
3348  * Debugfs info
3349  */
3350 #if defined(CONFIG_DEBUG_FS)
3351
3352 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3353 {
3354         struct drm_info_node *node = (struct drm_info_node *) m->private;
3355         struct drm_device *dev = node->minor->dev;
3356         struct radeon_device *rdev = dev->dev_private;
3357         unsigned count, i, j;
3358
3359         radeon_ring_free_size(rdev);
3360         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3361         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3362         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3363         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3364         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3365         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3366         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3367         seq_printf(m, "%u dwords in ring\n", count);
3368         i = rdev->cp.rptr;
3369         for (j = 0; j <= count; j++) {
3370                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3371                 i = (i + 1) & rdev->cp.ptr_mask;
3372         }
3373         return 0;
3374 }
3375
3376 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3377 {
3378         struct drm_info_node *node = (struct drm_info_node *) m->private;
3379         struct drm_device *dev = node->minor->dev;
3380         struct radeon_device *rdev = dev->dev_private;
3381
3382         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3383         DREG32_SYS(m, rdev, VM_L2_STATUS);
3384         return 0;
3385 }
3386
3387 static struct drm_info_list r600_mc_info_list[] = {
3388         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3389         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3390 };
3391 #endif
3392
3393 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3394 {
3395 #if defined(CONFIG_DEBUG_FS)
3396         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3397 #else
3398         return 0;
3399 #endif
3400 }
3401
3402 /**
3403  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3404  * rdev: radeon device structure
3405  * bo: buffer object struct which userspace is waiting for idle
3406  *
3407  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3408  * through ring buffer, this leads to corruption in rendering, see
3409  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3410  * directly perform HDP flush by writing register through MMIO.
3411  */
3412 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3413 {
3414         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3415 }