Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[linux-2.6.git] / drivers / gpu / drm / radeon / r100.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "r100d.h"
37 #include "rs100d.h"
38 #include "rv200d.h"
39 #include "rv250d.h"
40 #include "atom.h"
41
42 #include <linux/firmware.h>
43 #include <linux/platform_device.h>
44 #include <linux/module.h>
45
46 #include "r100_reg_safe.h"
47 #include "rn50_reg_safe.h"
48
49 /* Firmware Names */
50 #define FIRMWARE_R100           "radeon/R100_cp.bin"
51 #define FIRMWARE_R200           "radeon/R200_cp.bin"
52 #define FIRMWARE_R300           "radeon/R300_cp.bin"
53 #define FIRMWARE_R420           "radeon/R420_cp.bin"
54 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
55 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
56 #define FIRMWARE_R520           "radeon/R520_cp.bin"
57
58 MODULE_FIRMWARE(FIRMWARE_R100);
59 MODULE_FIRMWARE(FIRMWARE_R200);
60 MODULE_FIRMWARE(FIRMWARE_R300);
61 MODULE_FIRMWARE(FIRMWARE_R420);
62 MODULE_FIRMWARE(FIRMWARE_RS690);
63 MODULE_FIRMWARE(FIRMWARE_RS600);
64 MODULE_FIRMWARE(FIRMWARE_R520);
65
66 #include "r100_track.h"
67
68 /* This files gather functions specifics to:
69  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
70  */
71
72 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
73                             struct radeon_cs_packet *pkt,
74                             unsigned idx,
75                             unsigned reg)
76 {
77         int r;
78         u32 tile_flags = 0;
79         u32 tmp;
80         struct radeon_cs_reloc *reloc;
81         u32 value;
82
83         r = r100_cs_packet_next_reloc(p, &reloc);
84         if (r) {
85                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
86                           idx, reg);
87                 r100_cs_dump_packet(p, pkt);
88                 return r;
89         }
90         value = radeon_get_ib_value(p, idx);
91         tmp = value & 0x003fffff;
92         tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
93
94         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
95                 tile_flags |= RADEON_DST_TILE_MACRO;
96         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
97                 if (reg == RADEON_SRC_PITCH_OFFSET) {
98                         DRM_ERROR("Cannot src blit from microtiled surface\n");
99                         r100_cs_dump_packet(p, pkt);
100                         return -EINVAL;
101                 }
102                 tile_flags |= RADEON_DST_TILE_MICRO;
103         }
104
105         tmp |= tile_flags;
106         p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
107         return 0;
108 }
109
110 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
111                              struct radeon_cs_packet *pkt,
112                              int idx)
113 {
114         unsigned c, i;
115         struct radeon_cs_reloc *reloc;
116         struct r100_cs_track *track;
117         int r = 0;
118         volatile uint32_t *ib;
119         u32 idx_value;
120
121         ib = p->ib->ptr;
122         track = (struct r100_cs_track *)p->track;
123         c = radeon_get_ib_value(p, idx++) & 0x1F;
124         if (c > 16) {
125             DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
126                       pkt->opcode);
127             r100_cs_dump_packet(p, pkt);
128             return -EINVAL;
129         }
130         track->num_arrays = c;
131         for (i = 0; i < (c - 1); i+=2, idx+=3) {
132                 r = r100_cs_packet_next_reloc(p, &reloc);
133                 if (r) {
134                         DRM_ERROR("No reloc for packet3 %d\n",
135                                   pkt->opcode);
136                         r100_cs_dump_packet(p, pkt);
137                         return r;
138                 }
139                 idx_value = radeon_get_ib_value(p, idx);
140                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
141
142                 track->arrays[i + 0].esize = idx_value >> 8;
143                 track->arrays[i + 0].robj = reloc->robj;
144                 track->arrays[i + 0].esize &= 0x7F;
145                 r = r100_cs_packet_next_reloc(p, &reloc);
146                 if (r) {
147                         DRM_ERROR("No reloc for packet3 %d\n",
148                                   pkt->opcode);
149                         r100_cs_dump_packet(p, pkt);
150                         return r;
151                 }
152                 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
153                 track->arrays[i + 1].robj = reloc->robj;
154                 track->arrays[i + 1].esize = idx_value >> 24;
155                 track->arrays[i + 1].esize &= 0x7F;
156         }
157         if (c & 1) {
158                 r = r100_cs_packet_next_reloc(p, &reloc);
159                 if (r) {
160                         DRM_ERROR("No reloc for packet3 %d\n",
161                                           pkt->opcode);
162                         r100_cs_dump_packet(p, pkt);
163                         return r;
164                 }
165                 idx_value = radeon_get_ib_value(p, idx);
166                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
167                 track->arrays[i + 0].robj = reloc->robj;
168                 track->arrays[i + 0].esize = idx_value >> 8;
169                 track->arrays[i + 0].esize &= 0x7F;
170         }
171         return r;
172 }
173
174 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
175 {
176         /* enable the pflip int */
177         radeon_irq_kms_pflip_irq_get(rdev, crtc);
178 }
179
180 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
181 {
182         /* disable the pflip int */
183         radeon_irq_kms_pflip_irq_put(rdev, crtc);
184 }
185
186 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
187 {
188         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
189         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
190         int i;
191
192         /* Lock the graphics update lock */
193         /* update the scanout addresses */
194         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
195
196         /* Wait for update_pending to go high. */
197         for (i = 0; i < rdev->usec_timeout; i++) {
198                 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
199                         break;
200                 udelay(1);
201         }
202         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
203
204         /* Unlock the lock, so double-buffering can take place inside vblank */
205         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
206         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
207
208         /* Return current update_pending status: */
209         return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
210 }
211
212 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
213 {
214         int i;
215         rdev->pm.dynpm_can_upclock = true;
216         rdev->pm.dynpm_can_downclock = true;
217
218         switch (rdev->pm.dynpm_planned_action) {
219         case DYNPM_ACTION_MINIMUM:
220                 rdev->pm.requested_power_state_index = 0;
221                 rdev->pm.dynpm_can_downclock = false;
222                 break;
223         case DYNPM_ACTION_DOWNCLOCK:
224                 if (rdev->pm.current_power_state_index == 0) {
225                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
226                         rdev->pm.dynpm_can_downclock = false;
227                 } else {
228                         if (rdev->pm.active_crtc_count > 1) {
229                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
230                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
231                                                 continue;
232                                         else if (i >= rdev->pm.current_power_state_index) {
233                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
234                                                 break;
235                                         } else {
236                                                 rdev->pm.requested_power_state_index = i;
237                                                 break;
238                                         }
239                                 }
240                         } else
241                                 rdev->pm.requested_power_state_index =
242                                         rdev->pm.current_power_state_index - 1;
243                 }
244                 /* don't use the power state if crtcs are active and no display flag is set */
245                 if ((rdev->pm.active_crtc_count > 0) &&
246                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
247                      RADEON_PM_MODE_NO_DISPLAY)) {
248                         rdev->pm.requested_power_state_index++;
249                 }
250                 break;
251         case DYNPM_ACTION_UPCLOCK:
252                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
253                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
254                         rdev->pm.dynpm_can_upclock = false;
255                 } else {
256                         if (rdev->pm.active_crtc_count > 1) {
257                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
258                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
259                                                 continue;
260                                         else if (i <= rdev->pm.current_power_state_index) {
261                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
262                                                 break;
263                                         } else {
264                                                 rdev->pm.requested_power_state_index = i;
265                                                 break;
266                                         }
267                                 }
268                         } else
269                                 rdev->pm.requested_power_state_index =
270                                         rdev->pm.current_power_state_index + 1;
271                 }
272                 break;
273         case DYNPM_ACTION_DEFAULT:
274                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
275                 rdev->pm.dynpm_can_upclock = false;
276                 break;
277         case DYNPM_ACTION_NONE:
278         default:
279                 DRM_ERROR("Requested mode for not defined action\n");
280                 return;
281         }
282         /* only one clock mode per power state */
283         rdev->pm.requested_clock_mode_index = 0;
284
285         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
286                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
287                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
288                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
289                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
290                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
291                   pcie_lanes);
292 }
293
294 void r100_pm_init_profile(struct radeon_device *rdev)
295 {
296         /* default */
297         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
298         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
299         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
300         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
301         /* low sh */
302         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
303         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
304         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
305         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
306         /* mid sh */
307         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
308         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
309         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
310         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
311         /* high sh */
312         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
313         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
314         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
315         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
316         /* low mh */
317         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
318         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
319         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
320         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
321         /* mid mh */
322         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
323         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
324         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
325         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
326         /* high mh */
327         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
328         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
329         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
330         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
331 }
332
333 void r100_pm_misc(struct radeon_device *rdev)
334 {
335         int requested_index = rdev->pm.requested_power_state_index;
336         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
337         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
338         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
339
340         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
341                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
342                         tmp = RREG32(voltage->gpio.reg);
343                         if (voltage->active_high)
344                                 tmp |= voltage->gpio.mask;
345                         else
346                                 tmp &= ~(voltage->gpio.mask);
347                         WREG32(voltage->gpio.reg, tmp);
348                         if (voltage->delay)
349                                 udelay(voltage->delay);
350                 } else {
351                         tmp = RREG32(voltage->gpio.reg);
352                         if (voltage->active_high)
353                                 tmp &= ~voltage->gpio.mask;
354                         else
355                                 tmp |= voltage->gpio.mask;
356                         WREG32(voltage->gpio.reg, tmp);
357                         if (voltage->delay)
358                                 udelay(voltage->delay);
359                 }
360         }
361
362         sclk_cntl = RREG32_PLL(SCLK_CNTL);
363         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
364         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
365         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
366         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
367         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
368                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
369                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
370                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
371                 else
372                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
373                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
374                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
375                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
376                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
377         } else
378                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
379
380         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
381                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
382                 if (voltage->delay) {
383                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
384                         switch (voltage->delay) {
385                         case 33:
386                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
387                                 break;
388                         case 66:
389                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
390                                 break;
391                         case 99:
392                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
393                                 break;
394                         case 132:
395                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
396                                 break;
397                         }
398                 } else
399                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
400         } else
401                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
402
403         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
404                 sclk_cntl &= ~FORCE_HDP;
405         else
406                 sclk_cntl |= FORCE_HDP;
407
408         WREG32_PLL(SCLK_CNTL, sclk_cntl);
409         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
410         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
411
412         /* set pcie lanes */
413         if ((rdev->flags & RADEON_IS_PCIE) &&
414             !(rdev->flags & RADEON_IS_IGP) &&
415             rdev->asic->set_pcie_lanes &&
416             (ps->pcie_lanes !=
417              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
418                 radeon_set_pcie_lanes(rdev,
419                                       ps->pcie_lanes);
420                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
421         }
422 }
423
424 void r100_pm_prepare(struct radeon_device *rdev)
425 {
426         struct drm_device *ddev = rdev->ddev;
427         struct drm_crtc *crtc;
428         struct radeon_crtc *radeon_crtc;
429         u32 tmp;
430
431         /* disable any active CRTCs */
432         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
433                 radeon_crtc = to_radeon_crtc(crtc);
434                 if (radeon_crtc->enabled) {
435                         if (radeon_crtc->crtc_id) {
436                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
437                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
438                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
439                         } else {
440                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
441                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
442                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
443                         }
444                 }
445         }
446 }
447
448 void r100_pm_finish(struct radeon_device *rdev)
449 {
450         struct drm_device *ddev = rdev->ddev;
451         struct drm_crtc *crtc;
452         struct radeon_crtc *radeon_crtc;
453         u32 tmp;
454
455         /* enable any active CRTCs */
456         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
457                 radeon_crtc = to_radeon_crtc(crtc);
458                 if (radeon_crtc->enabled) {
459                         if (radeon_crtc->crtc_id) {
460                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
461                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
462                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
463                         } else {
464                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
465                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
466                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
467                         }
468                 }
469         }
470 }
471
472 bool r100_gui_idle(struct radeon_device *rdev)
473 {
474         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
475                 return false;
476         else
477                 return true;
478 }
479
480 /* hpd for digital panel detect/disconnect */
481 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
482 {
483         bool connected = false;
484
485         switch (hpd) {
486         case RADEON_HPD_1:
487                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
488                         connected = true;
489                 break;
490         case RADEON_HPD_2:
491                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
492                         connected = true;
493                 break;
494         default:
495                 break;
496         }
497         return connected;
498 }
499
500 void r100_hpd_set_polarity(struct radeon_device *rdev,
501                            enum radeon_hpd_id hpd)
502 {
503         u32 tmp;
504         bool connected = r100_hpd_sense(rdev, hpd);
505
506         switch (hpd) {
507         case RADEON_HPD_1:
508                 tmp = RREG32(RADEON_FP_GEN_CNTL);
509                 if (connected)
510                         tmp &= ~RADEON_FP_DETECT_INT_POL;
511                 else
512                         tmp |= RADEON_FP_DETECT_INT_POL;
513                 WREG32(RADEON_FP_GEN_CNTL, tmp);
514                 break;
515         case RADEON_HPD_2:
516                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
517                 if (connected)
518                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
519                 else
520                         tmp |= RADEON_FP2_DETECT_INT_POL;
521                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
522                 break;
523         default:
524                 break;
525         }
526 }
527
528 void r100_hpd_init(struct radeon_device *rdev)
529 {
530         struct drm_device *dev = rdev->ddev;
531         struct drm_connector *connector;
532
533         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
534                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
535                 switch (radeon_connector->hpd.hpd) {
536                 case RADEON_HPD_1:
537                         rdev->irq.hpd[0] = true;
538                         break;
539                 case RADEON_HPD_2:
540                         rdev->irq.hpd[1] = true;
541                         break;
542                 default:
543                         break;
544                 }
545                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
546         }
547         if (rdev->irq.installed)
548                 r100_irq_set(rdev);
549 }
550
551 void r100_hpd_fini(struct radeon_device *rdev)
552 {
553         struct drm_device *dev = rdev->ddev;
554         struct drm_connector *connector;
555
556         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
557                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
558                 switch (radeon_connector->hpd.hpd) {
559                 case RADEON_HPD_1:
560                         rdev->irq.hpd[0] = false;
561                         break;
562                 case RADEON_HPD_2:
563                         rdev->irq.hpd[1] = false;
564                         break;
565                 default:
566                         break;
567                 }
568         }
569 }
570
571 /*
572  * PCI GART
573  */
574 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
575 {
576         /* TODO: can we do somethings here ? */
577         /* It seems hw only cache one entry so we should discard this
578          * entry otherwise if first GPU GART read hit this entry it
579          * could end up in wrong address. */
580 }
581
582 int r100_pci_gart_init(struct radeon_device *rdev)
583 {
584         int r;
585
586         if (rdev->gart.ptr) {
587                 WARN(1, "R100 PCI GART already initialized\n");
588                 return 0;
589         }
590         /* Initialize common gart structure */
591         r = radeon_gart_init(rdev);
592         if (r)
593                 return r;
594         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
595         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
596         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
597         return radeon_gart_table_ram_alloc(rdev);
598 }
599
600 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
601 void r100_enable_bm(struct radeon_device *rdev)
602 {
603         uint32_t tmp;
604         /* Enable bus mastering */
605         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
606         WREG32(RADEON_BUS_CNTL, tmp);
607 }
608
609 int r100_pci_gart_enable(struct radeon_device *rdev)
610 {
611         uint32_t tmp;
612
613         radeon_gart_restore(rdev);
614         /* discard memory request outside of configured range */
615         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
616         WREG32(RADEON_AIC_CNTL, tmp);
617         /* set address range for PCI address translate */
618         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
619         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
620         /* set PCI GART page-table base address */
621         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
622         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
623         WREG32(RADEON_AIC_CNTL, tmp);
624         r100_pci_gart_tlb_flush(rdev);
625         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
626                  (unsigned)(rdev->mc.gtt_size >> 20),
627                  (unsigned long long)rdev->gart.table_addr);
628         rdev->gart.ready = true;
629         return 0;
630 }
631
632 void r100_pci_gart_disable(struct radeon_device *rdev)
633 {
634         uint32_t tmp;
635
636         /* discard memory request outside of configured range */
637         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
638         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
639         WREG32(RADEON_AIC_LO_ADDR, 0);
640         WREG32(RADEON_AIC_HI_ADDR, 0);
641 }
642
643 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
644 {
645         u32 *gtt = rdev->gart.ptr;
646
647         if (i < 0 || i > rdev->gart.num_gpu_pages) {
648                 return -EINVAL;
649         }
650         gtt[i] = cpu_to_le32(lower_32_bits(addr));
651         return 0;
652 }
653
654 void r100_pci_gart_fini(struct radeon_device *rdev)
655 {
656         radeon_gart_fini(rdev);
657         r100_pci_gart_disable(rdev);
658         radeon_gart_table_ram_free(rdev);
659 }
660
661 int r100_irq_set(struct radeon_device *rdev)
662 {
663         uint32_t tmp = 0;
664
665         if (!rdev->irq.installed) {
666                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
667                 WREG32(R_000040_GEN_INT_CNTL, 0);
668                 return -EINVAL;
669         }
670         if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
671                 tmp |= RADEON_SW_INT_ENABLE;
672         }
673         if (rdev->irq.gui_idle) {
674                 tmp |= RADEON_GUI_IDLE_MASK;
675         }
676         if (rdev->irq.crtc_vblank_int[0] ||
677             rdev->irq.pflip[0]) {
678                 tmp |= RADEON_CRTC_VBLANK_MASK;
679         }
680         if (rdev->irq.crtc_vblank_int[1] ||
681             rdev->irq.pflip[1]) {
682                 tmp |= RADEON_CRTC2_VBLANK_MASK;
683         }
684         if (rdev->irq.hpd[0]) {
685                 tmp |= RADEON_FP_DETECT_MASK;
686         }
687         if (rdev->irq.hpd[1]) {
688                 tmp |= RADEON_FP2_DETECT_MASK;
689         }
690         WREG32(RADEON_GEN_INT_CNTL, tmp);
691         return 0;
692 }
693
694 void r100_irq_disable(struct radeon_device *rdev)
695 {
696         u32 tmp;
697
698         WREG32(R_000040_GEN_INT_CNTL, 0);
699         /* Wait and acknowledge irq */
700         mdelay(1);
701         tmp = RREG32(R_000044_GEN_INT_STATUS);
702         WREG32(R_000044_GEN_INT_STATUS, tmp);
703 }
704
705 static uint32_t r100_irq_ack(struct radeon_device *rdev)
706 {
707         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
708         uint32_t irq_mask = RADEON_SW_INT_TEST |
709                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
710                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
711
712         /* the interrupt works, but the status bit is permanently asserted */
713         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
714                 if (!rdev->irq.gui_idle_acked)
715                         irq_mask |= RADEON_GUI_IDLE_STAT;
716         }
717
718         if (irqs) {
719                 WREG32(RADEON_GEN_INT_STATUS, irqs);
720         }
721         return irqs & irq_mask;
722 }
723
724 int r100_irq_process(struct radeon_device *rdev)
725 {
726         uint32_t status, msi_rearm;
727         bool queue_hotplug = false;
728
729         /* reset gui idle ack.  the status bit is broken */
730         rdev->irq.gui_idle_acked = false;
731
732         status = r100_irq_ack(rdev);
733         if (!status) {
734                 return IRQ_NONE;
735         }
736         if (rdev->shutdown) {
737                 return IRQ_NONE;
738         }
739         while (status) {
740                 /* SW interrupt */
741                 if (status & RADEON_SW_INT_TEST) {
742                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
743                 }
744                 /* gui idle interrupt */
745                 if (status & RADEON_GUI_IDLE_STAT) {
746                         rdev->irq.gui_idle_acked = true;
747                         rdev->pm.gui_idle = true;
748                         wake_up(&rdev->irq.idle_queue);
749                 }
750                 /* Vertical blank interrupts */
751                 if (status & RADEON_CRTC_VBLANK_STAT) {
752                         if (rdev->irq.crtc_vblank_int[0]) {
753                                 drm_handle_vblank(rdev->ddev, 0);
754                                 rdev->pm.vblank_sync = true;
755                                 wake_up(&rdev->irq.vblank_queue);
756                         }
757                         if (rdev->irq.pflip[0])
758                                 radeon_crtc_handle_flip(rdev, 0);
759                 }
760                 if (status & RADEON_CRTC2_VBLANK_STAT) {
761                         if (rdev->irq.crtc_vblank_int[1]) {
762                                 drm_handle_vblank(rdev->ddev, 1);
763                                 rdev->pm.vblank_sync = true;
764                                 wake_up(&rdev->irq.vblank_queue);
765                         }
766                         if (rdev->irq.pflip[1])
767                                 radeon_crtc_handle_flip(rdev, 1);
768                 }
769                 if (status & RADEON_FP_DETECT_STAT) {
770                         queue_hotplug = true;
771                         DRM_DEBUG("HPD1\n");
772                 }
773                 if (status & RADEON_FP2_DETECT_STAT) {
774                         queue_hotplug = true;
775                         DRM_DEBUG("HPD2\n");
776                 }
777                 status = r100_irq_ack(rdev);
778         }
779         /* reset gui idle ack.  the status bit is broken */
780         rdev->irq.gui_idle_acked = false;
781         if (queue_hotplug)
782                 schedule_work(&rdev->hotplug_work);
783         if (rdev->msi_enabled) {
784                 switch (rdev->family) {
785                 case CHIP_RS400:
786                 case CHIP_RS480:
787                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
788                         WREG32(RADEON_AIC_CNTL, msi_rearm);
789                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
790                         break;
791                 default:
792                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
793                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
794                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
795                         break;
796                 }
797         }
798         return IRQ_HANDLED;
799 }
800
801 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
802 {
803         if (crtc == 0)
804                 return RREG32(RADEON_CRTC_CRNT_FRAME);
805         else
806                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
807 }
808
809 /* Who ever call radeon_fence_emit should call ring_lock and ask
810  * for enough space (today caller are ib schedule and buffer move) */
811 void r100_fence_ring_emit(struct radeon_device *rdev,
812                           struct radeon_fence *fence)
813 {
814         struct radeon_ring *ring = &rdev->ring[fence->ring];
815
816         /* We have to make sure that caches are flushed before
817          * CPU might read something from VRAM. */
818         radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
819         radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
820         radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
821         radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
822         /* Wait until IDLE & CLEAN */
823         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
824         radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
825         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
826         radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
827                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
828         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
829         radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
830         /* Emit fence sequence & fire IRQ */
831         radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
832         radeon_ring_write(ring, fence->seq);
833         radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
834         radeon_ring_write(ring, RADEON_SW_INT_FIRE);
835 }
836
837 void r100_semaphore_ring_emit(struct radeon_device *rdev,
838                               struct radeon_ring *ring,
839                               struct radeon_semaphore *semaphore,
840                               bool emit_wait)
841 {
842         /* Unused on older asics, since we don't have semaphores or multiple rings */
843         BUG();
844 }
845
846 int r100_copy_blit(struct radeon_device *rdev,
847                    uint64_t src_offset,
848                    uint64_t dst_offset,
849                    unsigned num_gpu_pages,
850                    struct radeon_fence *fence)
851 {
852         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
853         uint32_t cur_pages;
854         uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
855         uint32_t pitch;
856         uint32_t stride_pixels;
857         unsigned ndw;
858         int num_loops;
859         int r = 0;
860
861         /* radeon limited to 16k stride */
862         stride_bytes &= 0x3fff;
863         /* radeon pitch is /64 */
864         pitch = stride_bytes / 64;
865         stride_pixels = stride_bytes / 4;
866         num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
867
868         /* Ask for enough room for blit + flush + fence */
869         ndw = 64 + (10 * num_loops);
870         r = radeon_ring_lock(rdev, ring, ndw);
871         if (r) {
872                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
873                 return -EINVAL;
874         }
875         while (num_gpu_pages > 0) {
876                 cur_pages = num_gpu_pages;
877                 if (cur_pages > 8191) {
878                         cur_pages = 8191;
879                 }
880                 num_gpu_pages -= cur_pages;
881
882                 /* pages are in Y direction - height
883                    page width in X direction - width */
884                 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
885                 radeon_ring_write(ring,
886                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
887                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
888                                   RADEON_GMC_SRC_CLIPPING |
889                                   RADEON_GMC_DST_CLIPPING |
890                                   RADEON_GMC_BRUSH_NONE |
891                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
892                                   RADEON_GMC_SRC_DATATYPE_COLOR |
893                                   RADEON_ROP3_S |
894                                   RADEON_DP_SRC_SOURCE_MEMORY |
895                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
896                                   RADEON_GMC_WR_MSK_DIS);
897                 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
898                 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
899                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
900                 radeon_ring_write(ring, 0);
901                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
902                 radeon_ring_write(ring, num_gpu_pages);
903                 radeon_ring_write(ring, num_gpu_pages);
904                 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
905         }
906         radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
907         radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
908         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
909         radeon_ring_write(ring,
910                           RADEON_WAIT_2D_IDLECLEAN |
911                           RADEON_WAIT_HOST_IDLECLEAN |
912                           RADEON_WAIT_DMA_GUI_IDLE);
913         if (fence) {
914                 r = radeon_fence_emit(rdev, fence);
915         }
916         radeon_ring_unlock_commit(rdev, ring);
917         return r;
918 }
919
920 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
921 {
922         unsigned i;
923         u32 tmp;
924
925         for (i = 0; i < rdev->usec_timeout; i++) {
926                 tmp = RREG32(R_000E40_RBBM_STATUS);
927                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
928                         return 0;
929                 }
930                 udelay(1);
931         }
932         return -1;
933 }
934
935 void r100_ring_start(struct radeon_device *rdev)
936 {
937         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
938         int r;
939
940         r = radeon_ring_lock(rdev, ring, 2);
941         if (r) {
942                 return;
943         }
944         radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
945         radeon_ring_write(ring,
946                           RADEON_ISYNC_ANY2D_IDLE3D |
947                           RADEON_ISYNC_ANY3D_IDLE2D |
948                           RADEON_ISYNC_WAIT_IDLEGUI |
949                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
950         radeon_ring_unlock_commit(rdev, ring);
951 }
952
953
954 /* Load the microcode for the CP */
955 static int r100_cp_init_microcode(struct radeon_device *rdev)
956 {
957         struct platform_device *pdev;
958         const char *fw_name = NULL;
959         int err;
960
961         DRM_DEBUG_KMS("\n");
962
963         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
964         err = IS_ERR(pdev);
965         if (err) {
966                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
967                 return -EINVAL;
968         }
969         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
970             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
971             (rdev->family == CHIP_RS200)) {
972                 DRM_INFO("Loading R100 Microcode\n");
973                 fw_name = FIRMWARE_R100;
974         } else if ((rdev->family == CHIP_R200) ||
975                    (rdev->family == CHIP_RV250) ||
976                    (rdev->family == CHIP_RV280) ||
977                    (rdev->family == CHIP_RS300)) {
978                 DRM_INFO("Loading R200 Microcode\n");
979                 fw_name = FIRMWARE_R200;
980         } else if ((rdev->family == CHIP_R300) ||
981                    (rdev->family == CHIP_R350) ||
982                    (rdev->family == CHIP_RV350) ||
983                    (rdev->family == CHIP_RV380) ||
984                    (rdev->family == CHIP_RS400) ||
985                    (rdev->family == CHIP_RS480)) {
986                 DRM_INFO("Loading R300 Microcode\n");
987                 fw_name = FIRMWARE_R300;
988         } else if ((rdev->family == CHIP_R420) ||
989                    (rdev->family == CHIP_R423) ||
990                    (rdev->family == CHIP_RV410)) {
991                 DRM_INFO("Loading R400 Microcode\n");
992                 fw_name = FIRMWARE_R420;
993         } else if ((rdev->family == CHIP_RS690) ||
994                    (rdev->family == CHIP_RS740)) {
995                 DRM_INFO("Loading RS690/RS740 Microcode\n");
996                 fw_name = FIRMWARE_RS690;
997         } else if (rdev->family == CHIP_RS600) {
998                 DRM_INFO("Loading RS600 Microcode\n");
999                 fw_name = FIRMWARE_RS600;
1000         } else if ((rdev->family == CHIP_RV515) ||
1001                    (rdev->family == CHIP_R520) ||
1002                    (rdev->family == CHIP_RV530) ||
1003                    (rdev->family == CHIP_R580) ||
1004                    (rdev->family == CHIP_RV560) ||
1005                    (rdev->family == CHIP_RV570)) {
1006                 DRM_INFO("Loading R500 Microcode\n");
1007                 fw_name = FIRMWARE_R520;
1008         }
1009
1010         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1011         platform_device_unregister(pdev);
1012         if (err) {
1013                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1014                        fw_name);
1015         } else if (rdev->me_fw->size % 8) {
1016                 printk(KERN_ERR
1017                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1018                        rdev->me_fw->size, fw_name);
1019                 err = -EINVAL;
1020                 release_firmware(rdev->me_fw);
1021                 rdev->me_fw = NULL;
1022         }
1023         return err;
1024 }
1025
1026 static void r100_cp_load_microcode(struct radeon_device *rdev)
1027 {
1028         const __be32 *fw_data;
1029         int i, size;
1030
1031         if (r100_gui_wait_for_idle(rdev)) {
1032                 printk(KERN_WARNING "Failed to wait GUI idle while "
1033                        "programming pipes. Bad things might happen.\n");
1034         }
1035
1036         if (rdev->me_fw) {
1037                 size = rdev->me_fw->size / 4;
1038                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1039                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1040                 for (i = 0; i < size; i += 2) {
1041                         WREG32(RADEON_CP_ME_RAM_DATAH,
1042                                be32_to_cpup(&fw_data[i]));
1043                         WREG32(RADEON_CP_ME_RAM_DATAL,
1044                                be32_to_cpup(&fw_data[i + 1]));
1045                 }
1046         }
1047 }
1048
1049 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1050 {
1051         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1052         unsigned rb_bufsz;
1053         unsigned rb_blksz;
1054         unsigned max_fetch;
1055         unsigned pre_write_timer;
1056         unsigned pre_write_limit;
1057         unsigned indirect2_start;
1058         unsigned indirect1_start;
1059         uint32_t tmp;
1060         int r;
1061
1062         if (r100_debugfs_cp_init(rdev)) {
1063                 DRM_ERROR("Failed to register debugfs file for CP !\n");
1064         }
1065         if (!rdev->me_fw) {
1066                 r = r100_cp_init_microcode(rdev);
1067                 if (r) {
1068                         DRM_ERROR("Failed to load firmware!\n");
1069                         return r;
1070                 }
1071         }
1072
1073         /* Align ring size */
1074         rb_bufsz = drm_order(ring_size / 8);
1075         ring_size = (1 << (rb_bufsz + 1)) * 4;
1076         r100_cp_load_microcode(rdev);
1077         r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1078                              RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
1079                              0, 0x7fffff, RADEON_CP_PACKET2);
1080         if (r) {
1081                 return r;
1082         }
1083         /* Each time the cp read 1024 bytes (16 dword/quadword) update
1084          * the rptr copy in system ram */
1085         rb_blksz = 9;
1086         /* cp will read 128bytes at a time (4 dwords) */
1087         max_fetch = 1;
1088         ring->align_mask = 16 - 1;
1089         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1090         pre_write_timer = 64;
1091         /* Force CP_RB_WPTR write if written more than one time before the
1092          * delay expire
1093          */
1094         pre_write_limit = 0;
1095         /* Setup the cp cache like this (cache size is 96 dwords) :
1096          *      RING            0  to 15
1097          *      INDIRECT1       16 to 79
1098          *      INDIRECT2       80 to 95
1099          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1100          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1101          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1102          * Idea being that most of the gpu cmd will be through indirect1 buffer
1103          * so it gets the bigger cache.
1104          */
1105         indirect2_start = 80;
1106         indirect1_start = 16;
1107         /* cp setup */
1108         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1109         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1110                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1111                REG_SET(RADEON_MAX_FETCH, max_fetch));
1112 #ifdef __BIG_ENDIAN
1113         tmp |= RADEON_BUF_SWAP_32BIT;
1114 #endif
1115         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1116
1117         /* Set ring address */
1118         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1119         WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1120         /* Force read & write ptr to 0 */
1121         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1122         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1123         ring->wptr = 0;
1124         WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1125
1126         /* set the wb address whether it's enabled or not */
1127         WREG32(R_00070C_CP_RB_RPTR_ADDR,
1128                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1129         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1130
1131         if (rdev->wb.enabled)
1132                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1133         else {
1134                 tmp |= RADEON_RB_NO_UPDATE;
1135                 WREG32(R_000770_SCRATCH_UMSK, 0);
1136         }
1137
1138         WREG32(RADEON_CP_RB_CNTL, tmp);
1139         udelay(10);
1140         ring->rptr = RREG32(RADEON_CP_RB_RPTR);
1141         /* Set cp mode to bus mastering & enable cp*/
1142         WREG32(RADEON_CP_CSQ_MODE,
1143                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1144                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1145         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1146         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1147         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1148         radeon_ring_start(rdev);
1149         r = radeon_ring_test(rdev, ring);
1150         if (r) {
1151                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1152                 return r;
1153         }
1154         ring->ready = true;
1155         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1156         return 0;
1157 }
1158
1159 void r100_cp_fini(struct radeon_device *rdev)
1160 {
1161         if (r100_cp_wait_for_idle(rdev)) {
1162                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1163         }
1164         /* Disable ring */
1165         r100_cp_disable(rdev);
1166         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1167         DRM_INFO("radeon: cp finalized\n");
1168 }
1169
1170 void r100_cp_disable(struct radeon_device *rdev)
1171 {
1172         /* Disable ring */
1173         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1174         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1175         WREG32(RADEON_CP_CSQ_MODE, 0);
1176         WREG32(RADEON_CP_CSQ_CNTL, 0);
1177         WREG32(R_000770_SCRATCH_UMSK, 0);
1178         if (r100_gui_wait_for_idle(rdev)) {
1179                 printk(KERN_WARNING "Failed to wait GUI idle while "
1180                        "programming pipes. Bad things might happen.\n");
1181         }
1182 }
1183
1184 /*
1185  * CS functions
1186  */
1187 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1188                           struct radeon_cs_packet *pkt,
1189                           const unsigned *auth, unsigned n,
1190                           radeon_packet0_check_t check)
1191 {
1192         unsigned reg;
1193         unsigned i, j, m;
1194         unsigned idx;
1195         int r;
1196
1197         idx = pkt->idx + 1;
1198         reg = pkt->reg;
1199         /* Check that register fall into register range
1200          * determined by the number of entry (n) in the
1201          * safe register bitmap.
1202          */
1203         if (pkt->one_reg_wr) {
1204                 if ((reg >> 7) > n) {
1205                         return -EINVAL;
1206                 }
1207         } else {
1208                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1209                         return -EINVAL;
1210                 }
1211         }
1212         for (i = 0; i <= pkt->count; i++, idx++) {
1213                 j = (reg >> 7);
1214                 m = 1 << ((reg >> 2) & 31);
1215                 if (auth[j] & m) {
1216                         r = check(p, pkt, idx, reg);
1217                         if (r) {
1218                                 return r;
1219                         }
1220                 }
1221                 if (pkt->one_reg_wr) {
1222                         if (!(auth[j] & m)) {
1223                                 break;
1224                         }
1225                 } else {
1226                         reg += 4;
1227                 }
1228         }
1229         return 0;
1230 }
1231
1232 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1233                          struct radeon_cs_packet *pkt)
1234 {
1235         volatile uint32_t *ib;
1236         unsigned i;
1237         unsigned idx;
1238
1239         ib = p->ib->ptr;
1240         idx = pkt->idx;
1241         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1242                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1243         }
1244 }
1245
1246 /**
1247  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1248  * @parser:     parser structure holding parsing context.
1249  * @pkt:        where to store packet informations
1250  *
1251  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1252  * if packet is bigger than remaining ib size. or if packets is unknown.
1253  **/
1254 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1255                          struct radeon_cs_packet *pkt,
1256                          unsigned idx)
1257 {
1258         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1259         uint32_t header;
1260
1261         if (idx >= ib_chunk->length_dw) {
1262                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1263                           idx, ib_chunk->length_dw);
1264                 return -EINVAL;
1265         }
1266         header = radeon_get_ib_value(p, idx);
1267         pkt->idx = idx;
1268         pkt->type = CP_PACKET_GET_TYPE(header);
1269         pkt->count = CP_PACKET_GET_COUNT(header);
1270         switch (pkt->type) {
1271         case PACKET_TYPE0:
1272                 pkt->reg = CP_PACKET0_GET_REG(header);
1273                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1274                 break;
1275         case PACKET_TYPE3:
1276                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1277                 break;
1278         case PACKET_TYPE2:
1279                 pkt->count = -1;
1280                 break;
1281         default:
1282                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1283                 return -EINVAL;
1284         }
1285         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1286                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1287                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1288                 return -EINVAL;
1289         }
1290         return 0;
1291 }
1292
1293 /**
1294  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1295  * @parser:             parser structure holding parsing context.
1296  *
1297  * Userspace sends a special sequence for VLINE waits.
1298  * PACKET0 - VLINE_START_END + value
1299  * PACKET0 - WAIT_UNTIL +_value
1300  * RELOC (P3) - crtc_id in reloc.
1301  *
1302  * This function parses this and relocates the VLINE START END
1303  * and WAIT UNTIL packets to the correct crtc.
1304  * It also detects a switched off crtc and nulls out the
1305  * wait in that case.
1306  */
1307 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1308 {
1309         struct drm_mode_object *obj;
1310         struct drm_crtc *crtc;
1311         struct radeon_crtc *radeon_crtc;
1312         struct radeon_cs_packet p3reloc, waitreloc;
1313         int crtc_id;
1314         int r;
1315         uint32_t header, h_idx, reg;
1316         volatile uint32_t *ib;
1317
1318         ib = p->ib->ptr;
1319
1320         /* parse the wait until */
1321         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1322         if (r)
1323                 return r;
1324
1325         /* check its a wait until and only 1 count */
1326         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1327             waitreloc.count != 0) {
1328                 DRM_ERROR("vline wait had illegal wait until segment\n");
1329                 return -EINVAL;
1330         }
1331
1332         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1333                 DRM_ERROR("vline wait had illegal wait until\n");
1334                 return -EINVAL;
1335         }
1336
1337         /* jump over the NOP */
1338         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1339         if (r)
1340                 return r;
1341
1342         h_idx = p->idx - 2;
1343         p->idx += waitreloc.count + 2;
1344         p->idx += p3reloc.count + 2;
1345
1346         header = radeon_get_ib_value(p, h_idx);
1347         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1348         reg = CP_PACKET0_GET_REG(header);
1349         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1350         if (!obj) {
1351                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1352                 return -EINVAL;
1353         }
1354         crtc = obj_to_crtc(obj);
1355         radeon_crtc = to_radeon_crtc(crtc);
1356         crtc_id = radeon_crtc->crtc_id;
1357
1358         if (!crtc->enabled) {
1359                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1360                 ib[h_idx + 2] = PACKET2(0);
1361                 ib[h_idx + 3] = PACKET2(0);
1362         } else if (crtc_id == 1) {
1363                 switch (reg) {
1364                 case AVIVO_D1MODE_VLINE_START_END:
1365                         header &= ~R300_CP_PACKET0_REG_MASK;
1366                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1367                         break;
1368                 case RADEON_CRTC_GUI_TRIG_VLINE:
1369                         header &= ~R300_CP_PACKET0_REG_MASK;
1370                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1371                         break;
1372                 default:
1373                         DRM_ERROR("unknown crtc reloc\n");
1374                         return -EINVAL;
1375                 }
1376                 ib[h_idx] = header;
1377                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1378         }
1379
1380         return 0;
1381 }
1382
1383 /**
1384  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1385  * @parser:             parser structure holding parsing context.
1386  * @data:               pointer to relocation data
1387  * @offset_start:       starting offset
1388  * @offset_mask:        offset mask (to align start offset on)
1389  * @reloc:              reloc informations
1390  *
1391  * Check next packet is relocation packet3, do bo validation and compute
1392  * GPU offset using the provided start.
1393  **/
1394 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1395                               struct radeon_cs_reloc **cs_reloc)
1396 {
1397         struct radeon_cs_chunk *relocs_chunk;
1398         struct radeon_cs_packet p3reloc;
1399         unsigned idx;
1400         int r;
1401
1402         if (p->chunk_relocs_idx == -1) {
1403                 DRM_ERROR("No relocation chunk !\n");
1404                 return -EINVAL;
1405         }
1406         *cs_reloc = NULL;
1407         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1408         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1409         if (r) {
1410                 return r;
1411         }
1412         p->idx += p3reloc.count + 2;
1413         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1414                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1415                           p3reloc.idx);
1416                 r100_cs_dump_packet(p, &p3reloc);
1417                 return -EINVAL;
1418         }
1419         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1420         if (idx >= relocs_chunk->length_dw) {
1421                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1422                           idx, relocs_chunk->length_dw);
1423                 r100_cs_dump_packet(p, &p3reloc);
1424                 return -EINVAL;
1425         }
1426         /* FIXME: we assume reloc size is 4 dwords */
1427         *cs_reloc = p->relocs_ptr[(idx / 4)];
1428         return 0;
1429 }
1430
1431 static int r100_get_vtx_size(uint32_t vtx_fmt)
1432 {
1433         int vtx_size;
1434         vtx_size = 2;
1435         /* ordered according to bits in spec */
1436         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1437                 vtx_size++;
1438         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1439                 vtx_size += 3;
1440         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1441                 vtx_size++;
1442         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1443                 vtx_size++;
1444         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1445                 vtx_size += 3;
1446         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1447                 vtx_size++;
1448         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1449                 vtx_size++;
1450         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1451                 vtx_size += 2;
1452         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1453                 vtx_size += 2;
1454         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1455                 vtx_size++;
1456         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1457                 vtx_size += 2;
1458         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1459                 vtx_size++;
1460         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1461                 vtx_size += 2;
1462         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1463                 vtx_size++;
1464         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1465                 vtx_size++;
1466         /* blend weight */
1467         if (vtx_fmt & (0x7 << 15))
1468                 vtx_size += (vtx_fmt >> 15) & 0x7;
1469         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1470                 vtx_size += 3;
1471         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1472                 vtx_size += 2;
1473         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1474                 vtx_size++;
1475         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1476                 vtx_size++;
1477         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1478                 vtx_size++;
1479         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1480                 vtx_size++;
1481         return vtx_size;
1482 }
1483
1484 static int r100_packet0_check(struct radeon_cs_parser *p,
1485                               struct radeon_cs_packet *pkt,
1486                               unsigned idx, unsigned reg)
1487 {
1488         struct radeon_cs_reloc *reloc;
1489         struct r100_cs_track *track;
1490         volatile uint32_t *ib;
1491         uint32_t tmp;
1492         int r;
1493         int i, face;
1494         u32 tile_flags = 0;
1495         u32 idx_value;
1496
1497         ib = p->ib->ptr;
1498         track = (struct r100_cs_track *)p->track;
1499
1500         idx_value = radeon_get_ib_value(p, idx);
1501
1502         switch (reg) {
1503         case RADEON_CRTC_GUI_TRIG_VLINE:
1504                 r = r100_cs_packet_parse_vline(p);
1505                 if (r) {
1506                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1507                                   idx, reg);
1508                         r100_cs_dump_packet(p, pkt);
1509                         return r;
1510                 }
1511                 break;
1512                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1513                  * range access */
1514         case RADEON_DST_PITCH_OFFSET:
1515         case RADEON_SRC_PITCH_OFFSET:
1516                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1517                 if (r)
1518                         return r;
1519                 break;
1520         case RADEON_RB3D_DEPTHOFFSET:
1521                 r = r100_cs_packet_next_reloc(p, &reloc);
1522                 if (r) {
1523                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1524                                   idx, reg);
1525                         r100_cs_dump_packet(p, pkt);
1526                         return r;
1527                 }
1528                 track->zb.robj = reloc->robj;
1529                 track->zb.offset = idx_value;
1530                 track->zb_dirty = true;
1531                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1532                 break;
1533         case RADEON_RB3D_COLOROFFSET:
1534                 r = r100_cs_packet_next_reloc(p, &reloc);
1535                 if (r) {
1536                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1537                                   idx, reg);
1538                         r100_cs_dump_packet(p, pkt);
1539                         return r;
1540                 }
1541                 track->cb[0].robj = reloc->robj;
1542                 track->cb[0].offset = idx_value;
1543                 track->cb_dirty = true;
1544                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1545                 break;
1546         case RADEON_PP_TXOFFSET_0:
1547         case RADEON_PP_TXOFFSET_1:
1548         case RADEON_PP_TXOFFSET_2:
1549                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1550                 r = r100_cs_packet_next_reloc(p, &reloc);
1551                 if (r) {
1552                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1553                                   idx, reg);
1554                         r100_cs_dump_packet(p, pkt);
1555                         return r;
1556                 }
1557                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1558                 track->textures[i].robj = reloc->robj;
1559                 track->tex_dirty = true;
1560                 break;
1561         case RADEON_PP_CUBIC_OFFSET_T0_0:
1562         case RADEON_PP_CUBIC_OFFSET_T0_1:
1563         case RADEON_PP_CUBIC_OFFSET_T0_2:
1564         case RADEON_PP_CUBIC_OFFSET_T0_3:
1565         case RADEON_PP_CUBIC_OFFSET_T0_4:
1566                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1567                 r = r100_cs_packet_next_reloc(p, &reloc);
1568                 if (r) {
1569                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1570                                   idx, reg);
1571                         r100_cs_dump_packet(p, pkt);
1572                         return r;
1573                 }
1574                 track->textures[0].cube_info[i].offset = idx_value;
1575                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1576                 track->textures[0].cube_info[i].robj = reloc->robj;
1577                 track->tex_dirty = true;
1578                 break;
1579         case RADEON_PP_CUBIC_OFFSET_T1_0:
1580         case RADEON_PP_CUBIC_OFFSET_T1_1:
1581         case RADEON_PP_CUBIC_OFFSET_T1_2:
1582         case RADEON_PP_CUBIC_OFFSET_T1_3:
1583         case RADEON_PP_CUBIC_OFFSET_T1_4:
1584                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1585                 r = r100_cs_packet_next_reloc(p, &reloc);
1586                 if (r) {
1587                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1588                                   idx, reg);
1589                         r100_cs_dump_packet(p, pkt);
1590                         return r;
1591                 }
1592                 track->textures[1].cube_info[i].offset = idx_value;
1593                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1594                 track->textures[1].cube_info[i].robj = reloc->robj;
1595                 track->tex_dirty = true;
1596                 break;
1597         case RADEON_PP_CUBIC_OFFSET_T2_0:
1598         case RADEON_PP_CUBIC_OFFSET_T2_1:
1599         case RADEON_PP_CUBIC_OFFSET_T2_2:
1600         case RADEON_PP_CUBIC_OFFSET_T2_3:
1601         case RADEON_PP_CUBIC_OFFSET_T2_4:
1602                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1603                 r = r100_cs_packet_next_reloc(p, &reloc);
1604                 if (r) {
1605                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1606                                   idx, reg);
1607                         r100_cs_dump_packet(p, pkt);
1608                         return r;
1609                 }
1610                 track->textures[2].cube_info[i].offset = idx_value;
1611                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1612                 track->textures[2].cube_info[i].robj = reloc->robj;
1613                 track->tex_dirty = true;
1614                 break;
1615         case RADEON_RE_WIDTH_HEIGHT:
1616                 track->maxy = ((idx_value >> 16) & 0x7FF);
1617                 track->cb_dirty = true;
1618                 track->zb_dirty = true;
1619                 break;
1620         case RADEON_RB3D_COLORPITCH:
1621                 r = r100_cs_packet_next_reloc(p, &reloc);
1622                 if (r) {
1623                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1624                                   idx, reg);
1625                         r100_cs_dump_packet(p, pkt);
1626                         return r;
1627                 }
1628
1629                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1630                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1631                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1632                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1633
1634                 tmp = idx_value & ~(0x7 << 16);
1635                 tmp |= tile_flags;
1636                 ib[idx] = tmp;
1637
1638                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1639                 track->cb_dirty = true;
1640                 break;
1641         case RADEON_RB3D_DEPTHPITCH:
1642                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1643                 track->zb_dirty = true;
1644                 break;
1645         case RADEON_RB3D_CNTL:
1646                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1647                 case 7:
1648                 case 8:
1649                 case 9:
1650                 case 11:
1651                 case 12:
1652                         track->cb[0].cpp = 1;
1653                         break;
1654                 case 3:
1655                 case 4:
1656                 case 15:
1657                         track->cb[0].cpp = 2;
1658                         break;
1659                 case 6:
1660                         track->cb[0].cpp = 4;
1661                         break;
1662                 default:
1663                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1664                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1665                         return -EINVAL;
1666                 }
1667                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1668                 track->cb_dirty = true;
1669                 track->zb_dirty = true;
1670                 break;
1671         case RADEON_RB3D_ZSTENCILCNTL:
1672                 switch (idx_value & 0xf) {
1673                 case 0:
1674                         track->zb.cpp = 2;
1675                         break;
1676                 case 2:
1677                 case 3:
1678                 case 4:
1679                 case 5:
1680                 case 9:
1681                 case 11:
1682                         track->zb.cpp = 4;
1683                         break;
1684                 default:
1685                         break;
1686                 }
1687                 track->zb_dirty = true;
1688                 break;
1689         case RADEON_RB3D_ZPASS_ADDR:
1690                 r = r100_cs_packet_next_reloc(p, &reloc);
1691                 if (r) {
1692                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1693                                   idx, reg);
1694                         r100_cs_dump_packet(p, pkt);
1695                         return r;
1696                 }
1697                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1698                 break;
1699         case RADEON_PP_CNTL:
1700                 {
1701                         uint32_t temp = idx_value >> 4;
1702                         for (i = 0; i < track->num_texture; i++)
1703                                 track->textures[i].enabled = !!(temp & (1 << i));
1704                         track->tex_dirty = true;
1705                 }
1706                 break;
1707         case RADEON_SE_VF_CNTL:
1708                 track->vap_vf_cntl = idx_value;
1709                 break;
1710         case RADEON_SE_VTX_FMT:
1711                 track->vtx_size = r100_get_vtx_size(idx_value);
1712                 break;
1713         case RADEON_PP_TEX_SIZE_0:
1714         case RADEON_PP_TEX_SIZE_1:
1715         case RADEON_PP_TEX_SIZE_2:
1716                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1717                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1718                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1719                 track->tex_dirty = true;
1720                 break;
1721         case RADEON_PP_TEX_PITCH_0:
1722         case RADEON_PP_TEX_PITCH_1:
1723         case RADEON_PP_TEX_PITCH_2:
1724                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1725                 track->textures[i].pitch = idx_value + 32;
1726                 track->tex_dirty = true;
1727                 break;
1728         case RADEON_PP_TXFILTER_0:
1729         case RADEON_PP_TXFILTER_1:
1730         case RADEON_PP_TXFILTER_2:
1731                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1732                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1733                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1734                 tmp = (idx_value >> 23) & 0x7;
1735                 if (tmp == 2 || tmp == 6)
1736                         track->textures[i].roundup_w = false;
1737                 tmp = (idx_value >> 27) & 0x7;
1738                 if (tmp == 2 || tmp == 6)
1739                         track->textures[i].roundup_h = false;
1740                 track->tex_dirty = true;
1741                 break;
1742         case RADEON_PP_TXFORMAT_0:
1743         case RADEON_PP_TXFORMAT_1:
1744         case RADEON_PP_TXFORMAT_2:
1745                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1746                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1747                         track->textures[i].use_pitch = 1;
1748                 } else {
1749                         track->textures[i].use_pitch = 0;
1750                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1751                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1752                 }
1753                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1754                         track->textures[i].tex_coord_type = 2;
1755                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1756                 case RADEON_TXFORMAT_I8:
1757                 case RADEON_TXFORMAT_RGB332:
1758                 case RADEON_TXFORMAT_Y8:
1759                         track->textures[i].cpp = 1;
1760                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1761                         break;
1762                 case RADEON_TXFORMAT_AI88:
1763                 case RADEON_TXFORMAT_ARGB1555:
1764                 case RADEON_TXFORMAT_RGB565:
1765                 case RADEON_TXFORMAT_ARGB4444:
1766                 case RADEON_TXFORMAT_VYUY422:
1767                 case RADEON_TXFORMAT_YVYU422:
1768                 case RADEON_TXFORMAT_SHADOW16:
1769                 case RADEON_TXFORMAT_LDUDV655:
1770                 case RADEON_TXFORMAT_DUDV88:
1771                         track->textures[i].cpp = 2;
1772                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1773                         break;
1774                 case RADEON_TXFORMAT_ARGB8888:
1775                 case RADEON_TXFORMAT_RGBA8888:
1776                 case RADEON_TXFORMAT_SHADOW32:
1777                 case RADEON_TXFORMAT_LDUDUV8888:
1778                         track->textures[i].cpp = 4;
1779                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1780                         break;
1781                 case RADEON_TXFORMAT_DXT1:
1782                         track->textures[i].cpp = 1;
1783                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1784                         break;
1785                 case RADEON_TXFORMAT_DXT23:
1786                 case RADEON_TXFORMAT_DXT45:
1787                         track->textures[i].cpp = 1;
1788                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1789                         break;
1790                 }
1791                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1792                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1793                 track->tex_dirty = true;
1794                 break;
1795         case RADEON_PP_CUBIC_FACES_0:
1796         case RADEON_PP_CUBIC_FACES_1:
1797         case RADEON_PP_CUBIC_FACES_2:
1798                 tmp = idx_value;
1799                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1800                 for (face = 0; face < 4; face++) {
1801                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1802                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1803                 }
1804                 track->tex_dirty = true;
1805                 break;
1806         default:
1807                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1808                        reg, idx);
1809                 return -EINVAL;
1810         }
1811         return 0;
1812 }
1813
1814 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1815                                          struct radeon_cs_packet *pkt,
1816                                          struct radeon_bo *robj)
1817 {
1818         unsigned idx;
1819         u32 value;
1820         idx = pkt->idx + 1;
1821         value = radeon_get_ib_value(p, idx + 2);
1822         if ((value + 1) > radeon_bo_size(robj)) {
1823                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1824                           "(need %u have %lu) !\n",
1825                           value + 1,
1826                           radeon_bo_size(robj));
1827                 return -EINVAL;
1828         }
1829         return 0;
1830 }
1831
1832 static int r100_packet3_check(struct radeon_cs_parser *p,
1833                               struct radeon_cs_packet *pkt)
1834 {
1835         struct radeon_cs_reloc *reloc;
1836         struct r100_cs_track *track;
1837         unsigned idx;
1838         volatile uint32_t *ib;
1839         int r;
1840
1841         ib = p->ib->ptr;
1842         idx = pkt->idx + 1;
1843         track = (struct r100_cs_track *)p->track;
1844         switch (pkt->opcode) {
1845         case PACKET3_3D_LOAD_VBPNTR:
1846                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1847                 if (r)
1848                         return r;
1849                 break;
1850         case PACKET3_INDX_BUFFER:
1851                 r = r100_cs_packet_next_reloc(p, &reloc);
1852                 if (r) {
1853                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1854                         r100_cs_dump_packet(p, pkt);
1855                         return r;
1856                 }
1857                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1858                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1859                 if (r) {
1860                         return r;
1861                 }
1862                 break;
1863         case 0x23:
1864                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1865                 r = r100_cs_packet_next_reloc(p, &reloc);
1866                 if (r) {
1867                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1868                         r100_cs_dump_packet(p, pkt);
1869                         return r;
1870                 }
1871                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1872                 track->num_arrays = 1;
1873                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1874
1875                 track->arrays[0].robj = reloc->robj;
1876                 track->arrays[0].esize = track->vtx_size;
1877
1878                 track->max_indx = radeon_get_ib_value(p, idx+1);
1879
1880                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1881                 track->immd_dwords = pkt->count - 1;
1882                 r = r100_cs_track_check(p->rdev, track);
1883                 if (r)
1884                         return r;
1885                 break;
1886         case PACKET3_3D_DRAW_IMMD:
1887                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1888                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1889                         return -EINVAL;
1890                 }
1891                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1892                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1893                 track->immd_dwords = pkt->count - 1;
1894                 r = r100_cs_track_check(p->rdev, track);
1895                 if (r)
1896                         return r;
1897                 break;
1898                 /* triggers drawing using in-packet vertex data */
1899         case PACKET3_3D_DRAW_IMMD_2:
1900                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1901                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1902                         return -EINVAL;
1903                 }
1904                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1905                 track->immd_dwords = pkt->count;
1906                 r = r100_cs_track_check(p->rdev, track);
1907                 if (r)
1908                         return r;
1909                 break;
1910                 /* triggers drawing using in-packet vertex data */
1911         case PACKET3_3D_DRAW_VBUF_2:
1912                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1913                 r = r100_cs_track_check(p->rdev, track);
1914                 if (r)
1915                         return r;
1916                 break;
1917                 /* triggers drawing of vertex buffers setup elsewhere */
1918         case PACKET3_3D_DRAW_INDX_2:
1919                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1920                 r = r100_cs_track_check(p->rdev, track);
1921                 if (r)
1922                         return r;
1923                 break;
1924                 /* triggers drawing using indices to vertex buffer */
1925         case PACKET3_3D_DRAW_VBUF:
1926                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1927                 r = r100_cs_track_check(p->rdev, track);
1928                 if (r)
1929                         return r;
1930                 break;
1931                 /* triggers drawing of vertex buffers setup elsewhere */
1932         case PACKET3_3D_DRAW_INDX:
1933                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1934                 r = r100_cs_track_check(p->rdev, track);
1935                 if (r)
1936                         return r;
1937                 break;
1938                 /* triggers drawing using indices to vertex buffer */
1939         case PACKET3_3D_CLEAR_HIZ:
1940         case PACKET3_3D_CLEAR_ZMASK:
1941                 if (p->rdev->hyperz_filp != p->filp)
1942                         return -EINVAL;
1943                 break;
1944         case PACKET3_NOP:
1945                 break;
1946         default:
1947                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1948                 return -EINVAL;
1949         }
1950         return 0;
1951 }
1952
1953 int r100_cs_parse(struct radeon_cs_parser *p)
1954 {
1955         struct radeon_cs_packet pkt;
1956         struct r100_cs_track *track;
1957         int r;
1958
1959         track = kzalloc(sizeof(*track), GFP_KERNEL);
1960         r100_cs_track_clear(p->rdev, track);
1961         p->track = track;
1962         do {
1963                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1964                 if (r) {
1965                         return r;
1966                 }
1967                 p->idx += pkt.count + 2;
1968                 switch (pkt.type) {
1969                         case PACKET_TYPE0:
1970                                 if (p->rdev->family >= CHIP_R200)
1971                                         r = r100_cs_parse_packet0(p, &pkt,
1972                                                                   p->rdev->config.r100.reg_safe_bm,
1973                                                                   p->rdev->config.r100.reg_safe_bm_size,
1974                                                                   &r200_packet0_check);
1975                                 else
1976                                         r = r100_cs_parse_packet0(p, &pkt,
1977                                                                   p->rdev->config.r100.reg_safe_bm,
1978                                                                   p->rdev->config.r100.reg_safe_bm_size,
1979                                                                   &r100_packet0_check);
1980                                 break;
1981                         case PACKET_TYPE2:
1982                                 break;
1983                         case PACKET_TYPE3:
1984                                 r = r100_packet3_check(p, &pkt);
1985                                 break;
1986                         default:
1987                                 DRM_ERROR("Unknown packet type %d !\n",
1988                                           pkt.type);
1989                                 return -EINVAL;
1990                 }
1991                 if (r) {
1992                         return r;
1993                 }
1994         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1995         return 0;
1996 }
1997
1998
1999 /*
2000  * Global GPU functions
2001  */
2002 void r100_errata(struct radeon_device *rdev)
2003 {
2004         rdev->pll_errata = 0;
2005
2006         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2007                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2008         }
2009
2010         if (rdev->family == CHIP_RV100 ||
2011             rdev->family == CHIP_RS100 ||
2012             rdev->family == CHIP_RS200) {
2013                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2014         }
2015 }
2016
2017 /* Wait for vertical sync on primary CRTC */
2018 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2019 {
2020         uint32_t crtc_gen_cntl, tmp;
2021         int i;
2022
2023         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2024         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2025             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2026                 return;
2027         }
2028         /* Clear the CRTC_VBLANK_SAVE bit */
2029         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2030         for (i = 0; i < rdev->usec_timeout; i++) {
2031                 tmp = RREG32(RADEON_CRTC_STATUS);
2032                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2033                         return;
2034                 }
2035                 DRM_UDELAY(1);
2036         }
2037 }
2038
2039 /* Wait for vertical sync on secondary CRTC */
2040 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2041 {
2042         uint32_t crtc2_gen_cntl, tmp;
2043         int i;
2044
2045         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2046         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2047             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2048                 return;
2049
2050         /* Clear the CRTC_VBLANK_SAVE bit */
2051         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2052         for (i = 0; i < rdev->usec_timeout; i++) {
2053                 tmp = RREG32(RADEON_CRTC2_STATUS);
2054                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2055                         return;
2056                 }
2057                 DRM_UDELAY(1);
2058         }
2059 }
2060
2061 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2062 {
2063         unsigned i;
2064         uint32_t tmp;
2065
2066         for (i = 0; i < rdev->usec_timeout; i++) {
2067                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2068                 if (tmp >= n) {
2069                         return 0;
2070                 }
2071                 DRM_UDELAY(1);
2072         }
2073         return -1;
2074 }
2075
2076 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2077 {
2078         unsigned i;
2079         uint32_t tmp;
2080
2081         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2082                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2083                        " Bad things might happen.\n");
2084         }
2085         for (i = 0; i < rdev->usec_timeout; i++) {
2086                 tmp = RREG32(RADEON_RBBM_STATUS);
2087                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2088                         return 0;
2089                 }
2090                 DRM_UDELAY(1);
2091         }
2092         return -1;
2093 }
2094
2095 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2096 {
2097         unsigned i;
2098         uint32_t tmp;
2099
2100         for (i = 0; i < rdev->usec_timeout; i++) {
2101                 /* read MC_STATUS */
2102                 tmp = RREG32(RADEON_MC_STATUS);
2103                 if (tmp & RADEON_MC_IDLE) {
2104                         return 0;
2105                 }
2106                 DRM_UDELAY(1);
2107         }
2108         return -1;
2109 }
2110
2111 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_ring *ring)
2112 {
2113         lockup->last_cp_rptr = ring->rptr;
2114         lockup->last_jiffies = jiffies;
2115 }
2116
2117 /**
2118  * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2119  * @rdev:       radeon device structure
2120  * @lockup:     r100_gpu_lockup structure holding CP lockup tracking informations
2121  * @cp:         radeon_cp structure holding CP information
2122  *
2123  * We don't need to initialize the lockup tracking information as we will either
2124  * have CP rptr to a different value of jiffies wrap around which will force
2125  * initialization of the lockup tracking informations.
2126  *
2127  * A possible false positivie is if we get call after while and last_cp_rptr ==
2128  * the current CP rptr, even if it's unlikely it might happen. To avoid this
2129  * if the elapsed time since last call is bigger than 2 second than we return
2130  * false and update the tracking information. Due to this the caller must call
2131  * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2132  * the fencing code should be cautious about that.
2133  *
2134  * Caller should write to the ring to force CP to do something so we don't get
2135  * false positive when CP is just gived nothing to do.
2136  *
2137  **/
2138 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_ring *ring)
2139 {
2140         unsigned long cjiffies, elapsed;
2141
2142         cjiffies = jiffies;
2143         if (!time_after(cjiffies, lockup->last_jiffies)) {
2144                 /* likely a wrap around */
2145                 lockup->last_cp_rptr = ring->rptr;
2146                 lockup->last_jiffies = jiffies;
2147                 return false;
2148         }
2149         if (ring->rptr != lockup->last_cp_rptr) {
2150                 /* CP is still working no lockup */
2151                 lockup->last_cp_rptr = ring->rptr;
2152                 lockup->last_jiffies = jiffies;
2153                 return false;
2154         }
2155         elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2156         if (elapsed >= 10000) {
2157                 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2158                 return true;
2159         }
2160         /* give a chance to the GPU ... */
2161         return false;
2162 }
2163
2164 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2165 {
2166         u32 rbbm_status;
2167         int r;
2168
2169         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2170         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2171                 r100_gpu_lockup_update(&rdev->config.r100.lockup, ring);
2172                 return false;
2173         }
2174         /* force CP activities */
2175         r = radeon_ring_lock(rdev, ring, 2);
2176         if (!r) {
2177                 /* PACKET2 NOP */
2178                 radeon_ring_write(ring, 0x80000000);
2179                 radeon_ring_write(ring, 0x80000000);
2180                 radeon_ring_unlock_commit(rdev, ring);
2181         }
2182         ring->rptr = RREG32(ring->rptr_reg);
2183         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, ring);
2184 }
2185
2186 void r100_bm_disable(struct radeon_device *rdev)
2187 {
2188         u32 tmp;
2189
2190         /* disable bus mastering */
2191         tmp = RREG32(R_000030_BUS_CNTL);
2192         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2193         mdelay(1);
2194         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2195         mdelay(1);
2196         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2197         tmp = RREG32(RADEON_BUS_CNTL);
2198         mdelay(1);
2199         pci_clear_master(rdev->pdev);
2200         mdelay(1);
2201 }
2202
2203 int r100_asic_reset(struct radeon_device *rdev)
2204 {
2205         struct r100_mc_save save;
2206         u32 status, tmp;
2207         int ret = 0;
2208
2209         status = RREG32(R_000E40_RBBM_STATUS);
2210         if (!G_000E40_GUI_ACTIVE(status)) {
2211                 return 0;
2212         }
2213         r100_mc_stop(rdev, &save);
2214         status = RREG32(R_000E40_RBBM_STATUS);
2215         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2216         /* stop CP */
2217         WREG32(RADEON_CP_CSQ_CNTL, 0);
2218         tmp = RREG32(RADEON_CP_RB_CNTL);
2219         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2220         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2221         WREG32(RADEON_CP_RB_WPTR, 0);
2222         WREG32(RADEON_CP_RB_CNTL, tmp);
2223         /* save PCI state */
2224         pci_save_state(rdev->pdev);
2225         /* disable bus mastering */
2226         r100_bm_disable(rdev);
2227         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2228                                         S_0000F0_SOFT_RESET_RE(1) |
2229                                         S_0000F0_SOFT_RESET_PP(1) |
2230                                         S_0000F0_SOFT_RESET_RB(1));
2231         RREG32(R_0000F0_RBBM_SOFT_RESET);
2232         mdelay(500);
2233         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2234         mdelay(1);
2235         status = RREG32(R_000E40_RBBM_STATUS);
2236         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2237         /* reset CP */
2238         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2239         RREG32(R_0000F0_RBBM_SOFT_RESET);
2240         mdelay(500);
2241         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2242         mdelay(1);
2243         status = RREG32(R_000E40_RBBM_STATUS);
2244         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2245         /* restore PCI & busmastering */
2246         pci_restore_state(rdev->pdev);
2247         r100_enable_bm(rdev);
2248         /* Check if GPU is idle */
2249         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2250                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2251                 dev_err(rdev->dev, "failed to reset GPU\n");
2252                 rdev->gpu_lockup = true;
2253                 ret = -1;
2254         } else
2255                 dev_info(rdev->dev, "GPU reset succeed\n");
2256         r100_mc_resume(rdev, &save);
2257         return ret;
2258 }
2259
2260 void r100_set_common_regs(struct radeon_device *rdev)
2261 {
2262         struct drm_device *dev = rdev->ddev;
2263         bool force_dac2 = false;
2264         u32 tmp;
2265
2266         /* set these so they don't interfere with anything */
2267         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2268         WREG32(RADEON_SUBPIC_CNTL, 0);
2269         WREG32(RADEON_VIPH_CONTROL, 0);
2270         WREG32(RADEON_I2C_CNTL_1, 0);
2271         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2272         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2273         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2274
2275         /* always set up dac2 on rn50 and some rv100 as lots
2276          * of servers seem to wire it up to a VGA port but
2277          * don't report it in the bios connector
2278          * table.
2279          */
2280         switch (dev->pdev->device) {
2281                 /* RN50 */
2282         case 0x515e:
2283         case 0x5969:
2284                 force_dac2 = true;
2285                 break;
2286                 /* RV100*/
2287         case 0x5159:
2288         case 0x515a:
2289                 /* DELL triple head servers */
2290                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2291                     ((dev->pdev->subsystem_device == 0x016c) ||
2292                      (dev->pdev->subsystem_device == 0x016d) ||
2293                      (dev->pdev->subsystem_device == 0x016e) ||
2294                      (dev->pdev->subsystem_device == 0x016f) ||
2295                      (dev->pdev->subsystem_device == 0x0170) ||
2296                      (dev->pdev->subsystem_device == 0x017d) ||
2297                      (dev->pdev->subsystem_device == 0x017e) ||
2298                      (dev->pdev->subsystem_device == 0x0183) ||
2299                      (dev->pdev->subsystem_device == 0x018a) ||
2300                      (dev->pdev->subsystem_device == 0x019a)))
2301                         force_dac2 = true;
2302                 break;
2303         }
2304
2305         if (force_dac2) {
2306                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2307                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2308                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2309
2310                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2311                    enable it, even it's detected.
2312                 */
2313
2314                 /* force it to crtc0 */
2315                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2316                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2317                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2318
2319                 /* set up the TV DAC */
2320                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2321                                  RADEON_TV_DAC_STD_MASK |
2322                                  RADEON_TV_DAC_RDACPD |
2323                                  RADEON_TV_DAC_GDACPD |
2324                                  RADEON_TV_DAC_BDACPD |
2325                                  RADEON_TV_DAC_BGADJ_MASK |
2326                                  RADEON_TV_DAC_DACADJ_MASK);
2327                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2328                                 RADEON_TV_DAC_NHOLD |
2329                                 RADEON_TV_DAC_STD_PS2 |
2330                                 (0x58 << 16));
2331
2332                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2333                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2334                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2335         }
2336
2337         /* switch PM block to ACPI mode */
2338         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2339         tmp &= ~RADEON_PM_MODE_SEL;
2340         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2341
2342 }
2343
2344 /*
2345  * VRAM info
2346  */
2347 static void r100_vram_get_type(struct radeon_device *rdev)
2348 {
2349         uint32_t tmp;
2350
2351         rdev->mc.vram_is_ddr = false;
2352         if (rdev->flags & RADEON_IS_IGP)
2353                 rdev->mc.vram_is_ddr = true;
2354         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2355                 rdev->mc.vram_is_ddr = true;
2356         if ((rdev->family == CHIP_RV100) ||
2357             (rdev->family == CHIP_RS100) ||
2358             (rdev->family == CHIP_RS200)) {
2359                 tmp = RREG32(RADEON_MEM_CNTL);
2360                 if (tmp & RV100_HALF_MODE) {
2361                         rdev->mc.vram_width = 32;
2362                 } else {
2363                         rdev->mc.vram_width = 64;
2364                 }
2365                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2366                         rdev->mc.vram_width /= 4;
2367                         rdev->mc.vram_is_ddr = true;
2368                 }
2369         } else if (rdev->family <= CHIP_RV280) {
2370                 tmp = RREG32(RADEON_MEM_CNTL);
2371                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2372                         rdev->mc.vram_width = 128;
2373                 } else {
2374                         rdev->mc.vram_width = 64;
2375                 }
2376         } else {
2377                 /* newer IGPs */
2378                 rdev->mc.vram_width = 128;
2379         }
2380 }
2381
2382 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2383 {
2384         u32 aper_size;
2385         u8 byte;
2386
2387         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2388
2389         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2390          * that is has the 2nd generation multifunction PCI interface
2391          */
2392         if (rdev->family == CHIP_RV280 ||
2393             rdev->family >= CHIP_RV350) {
2394                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2395                        ~RADEON_HDP_APER_CNTL);
2396                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2397                 return aper_size * 2;
2398         }
2399
2400         /* Older cards have all sorts of funny issues to deal with. First
2401          * check if it's a multifunction card by reading the PCI config
2402          * header type... Limit those to one aperture size
2403          */
2404         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2405         if (byte & 0x80) {
2406                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2407                 DRM_INFO("Limiting VRAM to one aperture\n");
2408                 return aper_size;
2409         }
2410
2411         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2412          * have set it up. We don't write this as it's broken on some ASICs but
2413          * we expect the BIOS to have done the right thing (might be too optimistic...)
2414          */
2415         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2416                 return aper_size * 2;
2417         return aper_size;
2418 }
2419
2420 void r100_vram_init_sizes(struct radeon_device *rdev)
2421 {
2422         u64 config_aper_size;
2423
2424         /* work out accessible VRAM */
2425         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2426         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2427         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2428         /* FIXME we don't use the second aperture yet when we could use it */
2429         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2430                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2431         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2432         if (rdev->flags & RADEON_IS_IGP) {
2433                 uint32_t tom;
2434                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2435                 tom = RREG32(RADEON_NB_TOM);
2436                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2437                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2438                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2439         } else {
2440                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2441                 /* Some production boards of m6 will report 0
2442                  * if it's 8 MB
2443                  */
2444                 if (rdev->mc.real_vram_size == 0) {
2445                         rdev->mc.real_vram_size = 8192 * 1024;
2446                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2447                 }
2448                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 
2449                  * Novell bug 204882 + along with lots of ubuntu ones
2450                  */
2451                 if (rdev->mc.aper_size > config_aper_size)
2452                         config_aper_size = rdev->mc.aper_size;
2453
2454                 if (config_aper_size > rdev->mc.real_vram_size)
2455                         rdev->mc.mc_vram_size = config_aper_size;
2456                 else
2457                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2458         }
2459 }
2460
2461 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2462 {
2463         uint32_t temp;
2464
2465         temp = RREG32(RADEON_CONFIG_CNTL);
2466         if (state == false) {
2467                 temp &= ~RADEON_CFG_VGA_RAM_EN;
2468                 temp |= RADEON_CFG_VGA_IO_DIS;
2469         } else {
2470                 temp &= ~RADEON_CFG_VGA_IO_DIS;
2471         }
2472         WREG32(RADEON_CONFIG_CNTL, temp);
2473 }
2474
2475 void r100_mc_init(struct radeon_device *rdev)
2476 {
2477         u64 base;
2478
2479         r100_vram_get_type(rdev);
2480         r100_vram_init_sizes(rdev);
2481         base = rdev->mc.aper_base;
2482         if (rdev->flags & RADEON_IS_IGP)
2483                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2484         radeon_vram_location(rdev, &rdev->mc, base);
2485         rdev->mc.gtt_base_align = 0;
2486         if (!(rdev->flags & RADEON_IS_AGP))
2487                 radeon_gtt_location(rdev, &rdev->mc);
2488         radeon_update_bandwidth_info(rdev);
2489 }
2490
2491
2492 /*
2493  * Indirect registers accessor
2494  */
2495 void r100_pll_errata_after_index(struct radeon_device *rdev)
2496 {
2497         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2498                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2499                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2500         }
2501 }
2502
2503 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2504 {
2505         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2506          * or the chip could hang on a subsequent access
2507          */
2508         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2509                 udelay(5000);
2510         }
2511
2512         /* This function is required to workaround a hardware bug in some (all?)
2513          * revisions of the R300.  This workaround should be called after every
2514          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2515          * may not be correct.
2516          */
2517         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2518                 uint32_t save, tmp;
2519
2520                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2521                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2522                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2523                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2524                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2525         }
2526 }
2527
2528 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2529 {
2530         uint32_t data;
2531
2532         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2533         r100_pll_errata_after_index(rdev);
2534         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2535         r100_pll_errata_after_data(rdev);
2536         return data;
2537 }
2538
2539 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2540 {
2541         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2542         r100_pll_errata_after_index(rdev);
2543         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2544         r100_pll_errata_after_data(rdev);
2545 }
2546
2547 void r100_set_safe_registers(struct radeon_device *rdev)
2548 {
2549         if (ASIC_IS_RN50(rdev)) {
2550                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2551                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2552         } else if (rdev->family < CHIP_R200) {
2553                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2554                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2555         } else {
2556                 r200_set_safe_registers(rdev);
2557         }
2558 }
2559
2560 /*
2561  * Debugfs info
2562  */
2563 #if defined(CONFIG_DEBUG_FS)
2564 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2565 {
2566         struct drm_info_node *node = (struct drm_info_node *) m->private;
2567         struct drm_device *dev = node->minor->dev;
2568         struct radeon_device *rdev = dev->dev_private;
2569         uint32_t reg, value;
2570         unsigned i;
2571
2572         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2573         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2574         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2575         for (i = 0; i < 64; i++) {
2576                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2577                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2578                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2579                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2580                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2581         }
2582         return 0;
2583 }
2584
2585 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2586 {
2587         struct drm_info_node *node = (struct drm_info_node *) m->private;
2588         struct drm_device *dev = node->minor->dev;
2589         struct radeon_device *rdev = dev->dev_private;
2590         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2591         uint32_t rdp, wdp;
2592         unsigned count, i, j;
2593
2594         radeon_ring_free_size(rdev, ring);
2595         rdp = RREG32(RADEON_CP_RB_RPTR);
2596         wdp = RREG32(RADEON_CP_RB_WPTR);
2597         count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2598         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2599         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2600         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2601         seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2602         seq_printf(m, "%u dwords in ring\n", count);
2603         for (j = 0; j <= count; j++) {
2604                 i = (rdp + j) & ring->ptr_mask;
2605                 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2606         }
2607         return 0;
2608 }
2609
2610
2611 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2612 {
2613         struct drm_info_node *node = (struct drm_info_node *) m->private;
2614         struct drm_device *dev = node->minor->dev;
2615         struct radeon_device *rdev = dev->dev_private;
2616         uint32_t csq_stat, csq2_stat, tmp;
2617         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2618         unsigned i;
2619
2620         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2621         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2622         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2623         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2624         r_rptr = (csq_stat >> 0) & 0x3ff;
2625         r_wptr = (csq_stat >> 10) & 0x3ff;
2626         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2627         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2628         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2629         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2630         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2631         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2632         seq_printf(m, "Ring rptr %u\n", r_rptr);
2633         seq_printf(m, "Ring wptr %u\n", r_wptr);
2634         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2635         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2636         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2637         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2638         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2639          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2640         seq_printf(m, "Ring fifo:\n");
2641         for (i = 0; i < 256; i++) {
2642                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2643                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2644                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2645         }
2646         seq_printf(m, "Indirect1 fifo:\n");
2647         for (i = 256; i <= 512; i++) {
2648                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2649                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2650                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2651         }
2652         seq_printf(m, "Indirect2 fifo:\n");
2653         for (i = 640; i < ib1_wptr; i++) {
2654                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2655                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2656                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2657         }
2658         return 0;
2659 }
2660
2661 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2662 {
2663         struct drm_info_node *node = (struct drm_info_node *) m->private;
2664         struct drm_device *dev = node->minor->dev;
2665         struct radeon_device *rdev = dev->dev_private;
2666         uint32_t tmp;
2667
2668         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2669         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2670         tmp = RREG32(RADEON_MC_FB_LOCATION);
2671         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2672         tmp = RREG32(RADEON_BUS_CNTL);
2673         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2674         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2675         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2676         tmp = RREG32(RADEON_AGP_BASE);
2677         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2678         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2679         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2680         tmp = RREG32(0x01D0);
2681         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2682         tmp = RREG32(RADEON_AIC_LO_ADDR);
2683         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2684         tmp = RREG32(RADEON_AIC_HI_ADDR);
2685         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2686         tmp = RREG32(0x01E4);
2687         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2688         return 0;
2689 }
2690
2691 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2692         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2693 };
2694
2695 static struct drm_info_list r100_debugfs_cp_list[] = {
2696         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2697         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2698 };
2699
2700 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2701         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2702 };
2703 #endif
2704
2705 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2706 {
2707 #if defined(CONFIG_DEBUG_FS)
2708         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2709 #else
2710         return 0;
2711 #endif
2712 }
2713
2714 int r100_debugfs_cp_init(struct radeon_device *rdev)
2715 {
2716 #if defined(CONFIG_DEBUG_FS)
2717         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2718 #else
2719         return 0;
2720 #endif
2721 }
2722
2723 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2724 {
2725 #if defined(CONFIG_DEBUG_FS)
2726         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2727 #else
2728         return 0;
2729 #endif
2730 }
2731
2732 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2733                          uint32_t tiling_flags, uint32_t pitch,
2734                          uint32_t offset, uint32_t obj_size)
2735 {
2736         int surf_index = reg * 16;
2737         int flags = 0;
2738
2739         if (rdev->family <= CHIP_RS200) {
2740                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2741                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2742                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2743                 if (tiling_flags & RADEON_TILING_MACRO)
2744                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2745         } else if (rdev->family <= CHIP_RV280) {
2746                 if (tiling_flags & (RADEON_TILING_MACRO))
2747                         flags |= R200_SURF_TILE_COLOR_MACRO;
2748                 if (tiling_flags & RADEON_TILING_MICRO)
2749                         flags |= R200_SURF_TILE_COLOR_MICRO;
2750         } else {
2751                 if (tiling_flags & RADEON_TILING_MACRO)
2752                         flags |= R300_SURF_TILE_MACRO;
2753                 if (tiling_flags & RADEON_TILING_MICRO)
2754                         flags |= R300_SURF_TILE_MICRO;
2755         }
2756
2757         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2758                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2759         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2760                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2761
2762         /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2763         if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2764                 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2765                         if (ASIC_IS_RN50(rdev))
2766                                 pitch /= 16;
2767         }
2768
2769         /* r100/r200 divide by 16 */
2770         if (rdev->family < CHIP_R300)
2771                 flags |= pitch / 16;
2772         else
2773                 flags |= pitch / 8;
2774
2775
2776         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2777         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2778         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2779         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2780         return 0;
2781 }
2782
2783 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2784 {
2785         int surf_index = reg * 16;
2786         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2787 }
2788
2789 void r100_bandwidth_update(struct radeon_device *rdev)
2790 {
2791         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2792         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2793         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2794         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2795         fixed20_12 memtcas_ff[8] = {
2796                 dfixed_init(1),
2797                 dfixed_init(2),
2798                 dfixed_init(3),
2799                 dfixed_init(0),
2800                 dfixed_init_half(1),
2801                 dfixed_init_half(2),
2802                 dfixed_init(0),
2803         };
2804         fixed20_12 memtcas_rs480_ff[8] = {
2805                 dfixed_init(0),
2806                 dfixed_init(1),
2807                 dfixed_init(2),
2808                 dfixed_init(3),
2809                 dfixed_init(0),
2810                 dfixed_init_half(1),
2811                 dfixed_init_half(2),
2812                 dfixed_init_half(3),
2813         };
2814         fixed20_12 memtcas2_ff[8] = {
2815                 dfixed_init(0),
2816                 dfixed_init(1),
2817                 dfixed_init(2),
2818                 dfixed_init(3),
2819                 dfixed_init(4),
2820                 dfixed_init(5),
2821                 dfixed_init(6),
2822                 dfixed_init(7),
2823         };
2824         fixed20_12 memtrbs[8] = {
2825                 dfixed_init(1),
2826                 dfixed_init_half(1),
2827                 dfixed_init(2),
2828                 dfixed_init_half(2),
2829                 dfixed_init(3),
2830                 dfixed_init_half(3),
2831                 dfixed_init(4),
2832                 dfixed_init_half(4)
2833         };
2834         fixed20_12 memtrbs_r4xx[8] = {
2835                 dfixed_init(4),
2836                 dfixed_init(5),
2837                 dfixed_init(6),
2838                 dfixed_init(7),
2839                 dfixed_init(8),
2840                 dfixed_init(9),
2841                 dfixed_init(10),
2842                 dfixed_init(11)
2843         };
2844         fixed20_12 min_mem_eff;
2845         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2846         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2847         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2848                 disp_drain_rate2, read_return_rate;
2849         fixed20_12 time_disp1_drop_priority;
2850         int c;
2851         int cur_size = 16;       /* in octawords */
2852         int critical_point = 0, critical_point2;
2853 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2854         int stop_req, max_stop_req;
2855         struct drm_display_mode *mode1 = NULL;
2856         struct drm_display_mode *mode2 = NULL;
2857         uint32_t pixel_bytes1 = 0;
2858         uint32_t pixel_bytes2 = 0;
2859
2860         radeon_update_display_priority(rdev);
2861
2862         if (rdev->mode_info.crtcs[0]->base.enabled) {
2863                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2864                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2865         }
2866         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2867                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2868                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2869                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2870                 }
2871         }
2872
2873         min_mem_eff.full = dfixed_const_8(0);
2874         /* get modes */
2875         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2876                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2877                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2878                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2879                 /* check crtc enables */
2880                 if (mode2)
2881                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2882                 if (mode1)
2883                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2884                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2885         }
2886
2887         /*
2888          * determine is there is enough bw for current mode
2889          */
2890         sclk_ff = rdev->pm.sclk;
2891         mclk_ff = rdev->pm.mclk;
2892
2893         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2894         temp_ff.full = dfixed_const(temp);
2895         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2896
2897         pix_clk.full = 0;
2898         pix_clk2.full = 0;
2899         peak_disp_bw.full = 0;
2900         if (mode1) {
2901                 temp_ff.full = dfixed_const(1000);
2902                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2903                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2904                 temp_ff.full = dfixed_const(pixel_bytes1);
2905                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2906         }
2907         if (mode2) {
2908                 temp_ff.full = dfixed_const(1000);
2909                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2910                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2911                 temp_ff.full = dfixed_const(pixel_bytes2);
2912                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2913         }
2914
2915         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2916         if (peak_disp_bw.full >= mem_bw.full) {
2917                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2918                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2919         }
2920
2921         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2922         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2923         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2924                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2925                 mem_trp  = ((temp & 0x3)) + 1;
2926                 mem_tras = ((temp & 0x70) >> 4) + 1;
2927         } else if (rdev->family == CHIP_R300 ||
2928                    rdev->family == CHIP_R350) { /* r300, r350 */
2929                 mem_trcd = (temp & 0x7) + 1;
2930                 mem_trp = ((temp >> 8) & 0x7) + 1;
2931                 mem_tras = ((temp >> 11) & 0xf) + 4;
2932         } else if (rdev->family == CHIP_RV350 ||
2933                    rdev->family <= CHIP_RV380) {
2934                 /* rv3x0 */
2935                 mem_trcd = (temp & 0x7) + 3;
2936                 mem_trp = ((temp >> 8) & 0x7) + 3;
2937                 mem_tras = ((temp >> 11) & 0xf) + 6;
2938         } else if (rdev->family == CHIP_R420 ||
2939                    rdev->family == CHIP_R423 ||
2940                    rdev->family == CHIP_RV410) {
2941                 /* r4xx */
2942                 mem_trcd = (temp & 0xf) + 3;
2943                 if (mem_trcd > 15)
2944                         mem_trcd = 15;
2945                 mem_trp = ((temp >> 8) & 0xf) + 3;
2946                 if (mem_trp > 15)
2947                         mem_trp = 15;
2948                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2949                 if (mem_tras > 31)
2950                         mem_tras = 31;
2951         } else { /* RV200, R200 */
2952                 mem_trcd = (temp & 0x7) + 1;
2953                 mem_trp = ((temp >> 8) & 0x7) + 1;
2954                 mem_tras = ((temp >> 12) & 0xf) + 4;
2955         }
2956         /* convert to FF */
2957         trcd_ff.full = dfixed_const(mem_trcd);
2958         trp_ff.full = dfixed_const(mem_trp);
2959         tras_ff.full = dfixed_const(mem_tras);
2960
2961         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2962         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2963         data = (temp & (7 << 20)) >> 20;
2964         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2965                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2966                         tcas_ff = memtcas_rs480_ff[data];
2967                 else
2968                         tcas_ff = memtcas_ff[data];
2969         } else
2970                 tcas_ff = memtcas2_ff[data];
2971
2972         if (rdev->family == CHIP_RS400 ||
2973             rdev->family == CHIP_RS480) {
2974                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2975                 data = (temp >> 23) & 0x7;
2976                 if (data < 5)
2977                         tcas_ff.full += dfixed_const(data);
2978         }
2979
2980         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2981                 /* on the R300, Tcas is included in Trbs.
2982                  */
2983                 temp = RREG32(RADEON_MEM_CNTL);
2984                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2985                 if (data == 1) {
2986                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2987                                 temp = RREG32(R300_MC_IND_INDEX);
2988                                 temp &= ~R300_MC_IND_ADDR_MASK;
2989                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2990                                 WREG32(R300_MC_IND_INDEX, temp);
2991                                 temp = RREG32(R300_MC_IND_DATA);
2992                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2993                         } else {
2994                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2995                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2996                         }
2997                 } else {
2998                         temp = RREG32(R300_MC_READ_CNTL_AB);
2999                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3000                 }
3001                 if (rdev->family == CHIP_RV410 ||
3002                     rdev->family == CHIP_R420 ||
3003                     rdev->family == CHIP_R423)
3004                         trbs_ff = memtrbs_r4xx[data];
3005                 else
3006                         trbs_ff = memtrbs[data];
3007                 tcas_ff.full += trbs_ff.full;
3008         }
3009
3010         sclk_eff_ff.full = sclk_ff.full;
3011
3012         if (rdev->flags & RADEON_IS_AGP) {
3013                 fixed20_12 agpmode_ff;
3014                 agpmode_ff.full = dfixed_const(radeon_agpmode);
3015                 temp_ff.full = dfixed_const_666(16);
3016                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3017         }
3018         /* TODO PCIE lanes may affect this - agpmode == 16?? */
3019
3020         if (ASIC_IS_R300(rdev)) {
3021                 sclk_delay_ff.full = dfixed_const(250);
3022         } else {
3023                 if ((rdev->family == CHIP_RV100) ||
3024                     rdev->flags & RADEON_IS_IGP) {
3025                         if (rdev->mc.vram_is_ddr)
3026                                 sclk_delay_ff.full = dfixed_const(41);
3027                         else
3028                                 sclk_delay_ff.full = dfixed_const(33);
3029                 } else {
3030                         if (rdev->mc.vram_width == 128)
3031                                 sclk_delay_ff.full = dfixed_const(57);
3032                         else
3033                                 sclk_delay_ff.full = dfixed_const(41);
3034                 }
3035         }
3036
3037         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3038
3039         if (rdev->mc.vram_is_ddr) {
3040                 if (rdev->mc.vram_width == 32) {
3041                         k1.full = dfixed_const(40);
3042                         c  = 3;
3043                 } else {
3044                         k1.full = dfixed_const(20);
3045                         c  = 1;
3046                 }
3047         } else {
3048                 k1.full = dfixed_const(40);
3049                 c  = 3;
3050         }
3051
3052         temp_ff.full = dfixed_const(2);
3053         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3054         temp_ff.full = dfixed_const(c);
3055         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3056         temp_ff.full = dfixed_const(4);
3057         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3058         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3059         mc_latency_mclk.full += k1.full;
3060
3061         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3062         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3063
3064         /*
3065           HW cursor time assuming worst case of full size colour cursor.
3066         */
3067         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3068         temp_ff.full += trcd_ff.full;
3069         if (temp_ff.full < tras_ff.full)
3070                 temp_ff.full = tras_ff.full;
3071         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3072
3073         temp_ff.full = dfixed_const(cur_size);
3074         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3075         /*
3076           Find the total latency for the display data.
3077         */
3078         disp_latency_overhead.full = dfixed_const(8);
3079         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3080         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3081         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3082
3083         if (mc_latency_mclk.full > mc_latency_sclk.full)
3084                 disp_latency.full = mc_latency_mclk.full;
3085         else
3086                 disp_latency.full = mc_latency_sclk.full;
3087
3088         /* setup Max GRPH_STOP_REQ default value */
3089         if (ASIC_IS_RV100(rdev))
3090                 max_stop_req = 0x5c;
3091         else
3092                 max_stop_req = 0x7c;
3093
3094         if (mode1) {
3095                 /*  CRTC1
3096                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3097                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3098                 */
3099                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3100
3101                 if (stop_req > max_stop_req)
3102                         stop_req = max_stop_req;
3103
3104                 /*
3105                   Find the drain rate of the display buffer.
3106                 */
3107                 temp_ff.full = dfixed_const((16/pixel_bytes1));
3108                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3109
3110                 /*
3111                   Find the critical point of the display buffer.
3112                 */
3113                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3114                 crit_point_ff.full += dfixed_const_half(0);
3115
3116                 critical_point = dfixed_trunc(crit_point_ff);
3117
3118                 if (rdev->disp_priority == 2) {
3119                         critical_point = 0;
3120                 }
3121
3122                 /*
3123                   The critical point should never be above max_stop_req-4.  Setting
3124                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3125                 */
3126                 if (max_stop_req - critical_point < 4)
3127                         critical_point = 0;
3128
3129                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3130                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3131                         critical_point = 0x10;
3132                 }
3133
3134                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3135                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3136                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3137                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3138                 if ((rdev->family == CHIP_R350) &&
3139                     (stop_req > 0x15)) {
3140                         stop_req -= 0x10;
3141                 }
3142                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3143                 temp |= RADEON_GRPH_BUFFER_SIZE;
3144                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3145                           RADEON_GRPH_CRITICAL_AT_SOF |
3146                           RADEON_GRPH_STOP_CNTL);
3147                 /*
3148                   Write the result into the register.
3149                 */
3150                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3151                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3152
3153 #if 0
3154                 if ((rdev->family == CHIP_RS400) ||
3155                     (rdev->family == CHIP_RS480)) {
3156                         /* attempt to program RS400 disp regs correctly ??? */
3157                         temp = RREG32(RS400_DISP1_REG_CNTL);
3158                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3159                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3160                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3161                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3162                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3163                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3164                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3165                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3166                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3167                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3168                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3169                 }
3170 #endif
3171
3172                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3173                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3174                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3175         }
3176
3177         if (mode2) {
3178                 u32 grph2_cntl;
3179                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3180
3181                 if (stop_req > max_stop_req)
3182                         stop_req = max_stop_req;
3183
3184                 /*
3185                   Find the drain rate of the display buffer.
3186                 */
3187                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3188                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3189
3190                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3191                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3192                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3193                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3194                 if ((rdev->family == CHIP_R350) &&
3195                     (stop_req > 0x15)) {
3196                         stop_req -= 0x10;
3197                 }
3198                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3199                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3200                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3201                           RADEON_GRPH_CRITICAL_AT_SOF |
3202                           RADEON_GRPH_STOP_CNTL);
3203
3204                 if ((rdev->family == CHIP_RS100) ||
3205                     (rdev->family == CHIP_RS200))
3206                         critical_point2 = 0;
3207                 else {
3208                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3209                         temp_ff.full = dfixed_const(temp);
3210                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3211                         if (sclk_ff.full < temp_ff.full)
3212                                 temp_ff.full = sclk_ff.full;
3213
3214                         read_return_rate.full = temp_ff.full;
3215
3216                         if (mode1) {
3217                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3218                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3219                         } else {
3220                                 time_disp1_drop_priority.full = 0;
3221                         }
3222                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3223                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3224                         crit_point_ff.full += dfixed_const_half(0);
3225
3226                         critical_point2 = dfixed_trunc(crit_point_ff);
3227
3228                         if (rdev->disp_priority == 2) {
3229                                 critical_point2 = 0;
3230                         }
3231
3232                         if (max_stop_req - critical_point2 < 4)
3233                                 critical_point2 = 0;
3234
3235                 }
3236
3237                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3238                         /* some R300 cards have problem with this set to 0 */
3239                         critical_point2 = 0x10;
3240                 }
3241
3242                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3243                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3244
3245                 if ((rdev->family == CHIP_RS400) ||
3246                     (rdev->family == CHIP_RS480)) {
3247 #if 0
3248                         /* attempt to program RS400 disp2 regs correctly ??? */
3249                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3250                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3251                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3252                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3253                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3254                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3255                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3256                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3257                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3258                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3259                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3260                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3261 #endif
3262                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3263                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3264                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3265                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3266                 }
3267
3268                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3269                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3270         }
3271 }
3272
3273 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3274 {
3275         DRM_ERROR("pitch                      %d\n", t->pitch);
3276         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
3277         DRM_ERROR("width                      %d\n", t->width);
3278         DRM_ERROR("width_11                   %d\n", t->width_11);
3279         DRM_ERROR("height                     %d\n", t->height);
3280         DRM_ERROR("height_11                  %d\n", t->height_11);
3281         DRM_ERROR("num levels                 %d\n", t->num_levels);
3282         DRM_ERROR("depth                      %d\n", t->txdepth);
3283         DRM_ERROR("bpp                        %d\n", t->cpp);
3284         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
3285         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
3286         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3287         DRM_ERROR("compress format            %d\n", t->compress_format);
3288 }
3289
3290 static int r100_track_compress_size(int compress_format, int w, int h)
3291 {
3292         int block_width, block_height, block_bytes;
3293         int wblocks, hblocks;
3294         int min_wblocks;
3295         int sz;
3296
3297         block_width = 4;
3298         block_height = 4;
3299
3300         switch (compress_format) {
3301         case R100_TRACK_COMP_DXT1:
3302                 block_bytes = 8;
3303                 min_wblocks = 4;
3304                 break;
3305         default:
3306         case R100_TRACK_COMP_DXT35:
3307                 block_bytes = 16;
3308                 min_wblocks = 2;
3309                 break;
3310         }
3311
3312         hblocks = (h + block_height - 1) / block_height;
3313         wblocks = (w + block_width - 1) / block_width;
3314         if (wblocks < min_wblocks)
3315                 wblocks = min_wblocks;
3316         sz = wblocks * hblocks * block_bytes;
3317         return sz;
3318 }
3319
3320 static int r100_cs_track_cube(struct radeon_device *rdev,
3321                               struct r100_cs_track *track, unsigned idx)
3322 {
3323         unsigned face, w, h;
3324         struct radeon_bo *cube_robj;
3325         unsigned long size;
3326         unsigned compress_format = track->textures[idx].compress_format;
3327
3328         for (face = 0; face < 5; face++) {
3329                 cube_robj = track->textures[idx].cube_info[face].robj;
3330                 w = track->textures[idx].cube_info[face].width;
3331                 h = track->textures[idx].cube_info[face].height;
3332
3333                 if (compress_format) {
3334                         size = r100_track_compress_size(compress_format, w, h);
3335                 } else
3336                         size = w * h;
3337                 size *= track->textures[idx].cpp;
3338
3339                 size += track->textures[idx].cube_info[face].offset;
3340
3341                 if (size > radeon_bo_size(cube_robj)) {
3342                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3343                                   size, radeon_bo_size(cube_robj));
3344                         r100_cs_track_texture_print(&track->textures[idx]);
3345                         return -1;
3346                 }
3347         }
3348         return 0;
3349 }
3350
3351 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3352                                        struct r100_cs_track *track)
3353 {
3354         struct radeon_bo *robj;
3355         unsigned long size;
3356         unsigned u, i, w, h, d;
3357         int ret;
3358
3359         for (u = 0; u < track->num_texture; u++) {
3360                 if (!track->textures[u].enabled)
3361                         continue;
3362                 if (track->textures[u].lookup_disable)
3363                         continue;
3364                 robj = track->textures[u].robj;
3365                 if (robj == NULL) {
3366                         DRM_ERROR("No texture bound to unit %u\n", u);
3367                         return -EINVAL;
3368                 }
3369                 size = 0;
3370                 for (i = 0; i <= track->textures[u].num_levels; i++) {
3371                         if (track->textures[u].use_pitch) {
3372                                 if (rdev->family < CHIP_R300)
3373                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3374                                 else
3375                                         w = track->textures[u].pitch / (1 << i);
3376                         } else {
3377                                 w = track->textures[u].width;
3378                                 if (rdev->family >= CHIP_RV515)
3379                                         w |= track->textures[u].width_11;
3380                                 w = w / (1 << i);
3381                                 if (track->textures[u].roundup_w)
3382                                         w = roundup_pow_of_two(w);
3383                         }
3384                         h = track->textures[u].height;
3385                         if (rdev->family >= CHIP_RV515)
3386                                 h |= track->textures[u].height_11;
3387                         h = h / (1 << i);
3388                         if (track->textures[u].roundup_h)
3389                                 h = roundup_pow_of_two(h);
3390                         if (track->textures[u].tex_coord_type == 1) {
3391                                 d = (1 << track->textures[u].txdepth) / (1 << i);
3392                                 if (!d)
3393                                         d = 1;
3394                         } else {
3395                                 d = 1;
3396                         }
3397                         if (track->textures[u].compress_format) {
3398
3399                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3400                                 /* compressed textures are block based */
3401                         } else
3402                                 size += w * h * d;
3403                 }
3404                 size *= track->textures[u].cpp;
3405
3406                 switch (track->textures[u].tex_coord_type) {
3407                 case 0:
3408                 case 1:
3409                         break;
3410                 case 2:
3411                         if (track->separate_cube) {
3412                                 ret = r100_cs_track_cube(rdev, track, u);
3413                                 if (ret)
3414                                         return ret;
3415                         } else
3416                                 size *= 6;
3417                         break;
3418                 default:
3419                         DRM_ERROR("Invalid texture coordinate type %u for unit "
3420                                   "%u\n", track->textures[u].tex_coord_type, u);
3421                         return -EINVAL;
3422                 }
3423                 if (size > radeon_bo_size(robj)) {
3424                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3425                                   "%lu\n", u, size, radeon_bo_size(robj));
3426                         r100_cs_track_texture_print(&track->textures[u]);
3427                         return -EINVAL;
3428                 }
3429         }
3430         return 0;
3431 }
3432
3433 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3434 {
3435         unsigned i;
3436         unsigned long size;
3437         unsigned prim_walk;
3438         unsigned nverts;
3439         unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
3440
3441         if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
3442             !track->blend_read_enable)
3443                 num_cb = 0;
3444
3445         for (i = 0; i < num_cb; i++) {
3446                 if (track->cb[i].robj == NULL) {
3447                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3448                         return -EINVAL;
3449                 }
3450                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3451                 size += track->cb[i].offset;
3452                 if (size > radeon_bo_size(track->cb[i].robj)) {
3453                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
3454                                   "(need %lu have %lu) !\n", i, size,
3455                                   radeon_bo_size(track->cb[i].robj));
3456                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3457                                   i, track->cb[i].pitch, track->cb[i].cpp,
3458                                   track->cb[i].offset, track->maxy);
3459                         return -EINVAL;
3460                 }
3461         }
3462         track->cb_dirty = false;
3463
3464         if (track->zb_dirty && track->z_enabled) {
3465                 if (track->zb.robj == NULL) {
3466                         DRM_ERROR("[drm] No buffer for z buffer !\n");
3467                         return -EINVAL;
3468                 }
3469                 size = track->zb.pitch * track->zb.cpp * track->maxy;
3470                 size += track->zb.offset;
3471                 if (size > radeon_bo_size(track->zb.robj)) {
3472                         DRM_ERROR("[drm] Buffer too small for z buffer "
3473                                   "(need %lu have %lu) !\n", size,
3474                                   radeon_bo_size(track->zb.robj));
3475                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3476                                   track->zb.pitch, track->zb.cpp,
3477                                   track->zb.offset, track->maxy);
3478                         return -EINVAL;
3479                 }
3480         }
3481         track->zb_dirty = false;
3482
3483         if (track->aa_dirty && track->aaresolve) {
3484                 if (track->aa.robj == NULL) {
3485                         DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3486                         return -EINVAL;
3487                 }
3488                 /* I believe the format comes from colorbuffer0. */
3489                 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3490                 size += track->aa.offset;
3491                 if (size > radeon_bo_size(track->aa.robj)) {
3492                         DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3493                                   "(need %lu have %lu) !\n", i, size,
3494                                   radeon_bo_size(track->aa.robj));
3495                         DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3496                                   i, track->aa.pitch, track->cb[0].cpp,
3497                                   track->aa.offset, track->maxy);
3498                         return -EINVAL;
3499                 }
3500         }
3501         track->aa_dirty = false;
3502
3503         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3504         if (track->vap_vf_cntl & (1 << 14)) {
3505                 nverts = track->vap_alt_nverts;
3506         } else {
3507                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3508         }
3509         switch (prim_walk) {
3510         case 1:
3511                 for (i = 0; i < track->num_arrays; i++) {
3512                         size = track->arrays[i].esize * track->max_indx * 4;
3513                         if (track->arrays[i].robj == NULL) {
3514                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3515                                           "bound\n", prim_walk, i);
3516                                 return -EINVAL;
3517                         }
3518                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3519                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3520                                         "need %lu dwords have %lu dwords\n",
3521                                         prim_walk, i, size >> 2,
3522                                         radeon_bo_size(track->arrays[i].robj)
3523                                         >> 2);
3524                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3525                                 return -EINVAL;
3526                         }
3527                 }
3528                 break;
3529         case 2:
3530                 for (i = 0; i < track->num_arrays; i++) {
3531                         size = track->arrays[i].esize * (nverts - 1) * 4;
3532                         if (track->arrays[i].robj == NULL) {
3533                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3534                                           "bound\n", prim_walk, i);
3535                                 return -EINVAL;
3536                         }
3537                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3538                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3539                                         "need %lu dwords have %lu dwords\n",
3540                                         prim_walk, i, size >> 2,
3541                                         radeon_bo_size(track->arrays[i].robj)
3542                                         >> 2);
3543                                 return -EINVAL;
3544                         }
3545                 }
3546                 break;
3547         case 3:
3548                 size = track->vtx_size * nverts;
3549                 if (size != track->immd_dwords) {
3550                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3551                                   track->immd_dwords, size);
3552                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3553                                   nverts, track->vtx_size);
3554                         return -EINVAL;
3555                 }
3556                 break;
3557         default:
3558                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3559                           prim_walk);
3560                 return -EINVAL;
3561         }
3562
3563         if (track->tex_dirty) {
3564                 track->tex_dirty = false;
3565                 return r100_cs_track_texture_check(rdev, track);
3566         }
3567         return 0;
3568 }
3569
3570 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3571 {
3572         unsigned i, face;
3573
3574         track->cb_dirty = true;
3575         track->zb_dirty = true;
3576         track->tex_dirty = true;
3577         track->aa_dirty = true;
3578
3579         if (rdev->family < CHIP_R300) {
3580                 track->num_cb = 1;
3581                 if (rdev->family <= CHIP_RS200)
3582                         track->num_texture = 3;
3583                 else
3584                         track->num_texture = 6;
3585                 track->maxy = 2048;
3586                 track->separate_cube = 1;
3587         } else {
3588                 track->num_cb = 4;
3589                 track->num_texture = 16;
3590                 track->maxy = 4096;
3591                 track->separate_cube = 0;
3592                 track->aaresolve = false;
3593                 track->aa.robj = NULL;
3594         }
3595
3596         for (i = 0; i < track->num_cb; i++) {
3597                 track->cb[i].robj = NULL;
3598                 track->cb[i].pitch = 8192;
3599                 track->cb[i].cpp = 16;
3600                 track->cb[i].offset = 0;
3601         }
3602         track->z_enabled = true;
3603         track->zb.robj = NULL;
3604         track->zb.pitch = 8192;
3605         track->zb.cpp = 4;
3606         track->zb.offset = 0;
3607         track->vtx_size = 0x7F;
3608         track->immd_dwords = 0xFFFFFFFFUL;
3609         track->num_arrays = 11;
3610         track->max_indx = 0x00FFFFFFUL;
3611         for (i = 0; i < track->num_arrays; i++) {
3612                 track->arrays[i].robj = NULL;
3613                 track->arrays[i].esize = 0x7F;
3614         }
3615         for (i = 0; i < track->num_texture; i++) {
3616                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3617                 track->textures[i].pitch = 16536;
3618                 track->textures[i].width = 16536;
3619                 track->textures[i].height = 16536;
3620                 track->textures[i].width_11 = 1 << 11;
3621                 track->textures[i].height_11 = 1 << 11;
3622                 track->textures[i].num_levels = 12;
3623                 if (rdev->family <= CHIP_RS200) {
3624                         track->textures[i].tex_coord_type = 0;
3625                         track->textures[i].txdepth = 0;
3626                 } else {
3627                         track->textures[i].txdepth = 16;
3628                         track->textures[i].tex_coord_type = 1;
3629                 }
3630                 track->textures[i].cpp = 64;
3631                 track->textures[i].robj = NULL;
3632                 /* CS IB emission code makes sure texture unit are disabled */
3633                 track->textures[i].enabled = false;
3634                 track->textures[i].lookup_disable = false;
3635                 track->textures[i].roundup_w = true;
3636                 track->textures[i].roundup_h = true;
3637                 if (track->separate_cube)
3638                         for (face = 0; face < 5; face++) {
3639                                 track->textures[i].cube_info[face].robj = NULL;
3640                                 track->textures[i].cube_info[face].width = 16536;
3641                                 track->textures[i].cube_info[face].height = 16536;
3642                                 track->textures[i].cube_info[face].offset = 0;
3643                         }
3644         }
3645 }
3646
3647 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3648 {
3649         uint32_t scratch;
3650         uint32_t tmp = 0;
3651         unsigned i;
3652         int r;
3653
3654         r = radeon_scratch_get(rdev, &scratch);
3655         if (r) {
3656                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3657                 return r;
3658         }
3659         WREG32(scratch, 0xCAFEDEAD);
3660         r = radeon_ring_lock(rdev, ring, 2);
3661         if (r) {
3662                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3663                 radeon_scratch_free(rdev, scratch);
3664                 return r;
3665         }
3666         radeon_ring_write(ring, PACKET0(scratch, 0));
3667         radeon_ring_write(ring, 0xDEADBEEF);
3668         radeon_ring_unlock_commit(rdev, ring);
3669         for (i = 0; i < rdev->usec_timeout; i++) {
3670                 tmp = RREG32(scratch);
3671                 if (tmp == 0xDEADBEEF) {
3672                         break;
3673                 }
3674                 DRM_UDELAY(1);
3675         }
3676         if (i < rdev->usec_timeout) {
3677                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3678         } else {
3679                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3680                           scratch, tmp);
3681                 r = -EINVAL;
3682         }
3683         radeon_scratch_free(rdev, scratch);
3684         return r;
3685 }
3686
3687 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3688 {
3689         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3690
3691         radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3692         radeon_ring_write(ring, ib->gpu_addr);
3693         radeon_ring_write(ring, ib->length_dw);
3694 }
3695
3696 int r100_ib_test(struct radeon_device *rdev)
3697 {
3698         struct radeon_ib *ib;
3699         uint32_t scratch;
3700         uint32_t tmp = 0;
3701         unsigned i;
3702         int r;
3703
3704         r = radeon_scratch_get(rdev, &scratch);
3705         if (r) {
3706                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3707                 return r;
3708         }
3709         WREG32(scratch, 0xCAFEDEAD);
3710         r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256);
3711         if (r) {
3712                 return r;
3713         }
3714         ib->ptr[0] = PACKET0(scratch, 0);
3715         ib->ptr[1] = 0xDEADBEEF;
3716         ib->ptr[2] = PACKET2(0);
3717         ib->ptr[3] = PACKET2(0);
3718         ib->ptr[4] = PACKET2(0);
3719         ib->ptr[5] = PACKET2(0);
3720         ib->ptr[6] = PACKET2(0);
3721         ib->ptr[7] = PACKET2(0);
3722         ib->length_dw = 8;
3723         r = radeon_ib_schedule(rdev, ib);
3724         if (r) {
3725                 radeon_scratch_free(rdev, scratch);
3726                 radeon_ib_free(rdev, &ib);
3727                 return r;
3728         }
3729         r = radeon_fence_wait(ib->fence, false);
3730         if (r) {
3731                 return r;
3732         }
3733         for (i = 0; i < rdev->usec_timeout; i++) {
3734                 tmp = RREG32(scratch);
3735                 if (tmp == 0xDEADBEEF) {
3736                         break;
3737                 }
3738                 DRM_UDELAY(1);
3739         }
3740         if (i < rdev->usec_timeout) {
3741                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3742         } else {
3743                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3744                           scratch, tmp);
3745                 r = -EINVAL;
3746         }
3747         radeon_scratch_free(rdev, scratch);
3748         radeon_ib_free(rdev, &ib);
3749         return r;
3750 }
3751
3752 void r100_ib_fini(struct radeon_device *rdev)
3753 {
3754         radeon_ib_pool_suspend(rdev);
3755         radeon_ib_pool_fini(rdev);
3756 }
3757
3758 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3759 {
3760         /* Shutdown CP we shouldn't need to do that but better be safe than
3761          * sorry
3762          */
3763         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3764         WREG32(R_000740_CP_CSQ_CNTL, 0);
3765
3766         /* Save few CRTC registers */
3767         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3768         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3769         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3770         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3771         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3772                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3773                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3774         }
3775
3776         /* Disable VGA aperture access */
3777         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3778         /* Disable cursor, overlay, crtc */
3779         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3780         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3781                                         S_000054_CRTC_DISPLAY_DIS(1));
3782         WREG32(R_000050_CRTC_GEN_CNTL,
3783                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3784                         S_000050_CRTC_DISP_REQ_EN_B(1));
3785         WREG32(R_000420_OV0_SCALE_CNTL,
3786                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3787         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3788         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3789                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3790                                                 S_000360_CUR2_LOCK(1));
3791                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3792                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3793                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3794                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3795                 WREG32(R_000360_CUR2_OFFSET,
3796                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3797         }
3798 }
3799
3800 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3801 {
3802         /* Update base address for crtc */
3803         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3804         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3805                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3806         }
3807         /* Restore CRTC registers */
3808         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3809         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3810         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3811         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3812                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3813         }
3814 }
3815
3816 void r100_vga_render_disable(struct radeon_device *rdev)
3817 {
3818         u32 tmp;
3819
3820         tmp = RREG8(R_0003C2_GENMO_WT);
3821         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3822 }
3823
3824 static void r100_debugfs(struct radeon_device *rdev)
3825 {
3826         int r;
3827
3828         r = r100_debugfs_mc_info_init(rdev);
3829         if (r)
3830                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3831 }
3832
3833 static void r100_mc_program(struct radeon_device *rdev)
3834 {
3835         struct r100_mc_save save;
3836
3837         /* Stops all mc clients */
3838         r100_mc_stop(rdev, &save);
3839         if (rdev->flags & RADEON_IS_AGP) {
3840                 WREG32(R_00014C_MC_AGP_LOCATION,
3841                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3842                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3843                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3844                 if (rdev->family > CHIP_RV200)
3845                         WREG32(R_00015C_AGP_BASE_2,
3846                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3847         } else {
3848                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3849                 WREG32(R_000170_AGP_BASE, 0);
3850                 if (rdev->family > CHIP_RV200)
3851                         WREG32(R_00015C_AGP_BASE_2, 0);
3852         }
3853         /* Wait for mc idle */
3854         if (r100_mc_wait_for_idle(rdev))
3855                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3856         /* Program MC, should be a 32bits limited address space */
3857         WREG32(R_000148_MC_FB_LOCATION,
3858                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3859                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3860         r100_mc_resume(rdev, &save);
3861 }
3862
3863 void r100_clock_startup(struct radeon_device *rdev)
3864 {
3865         u32 tmp;
3866
3867         if (radeon_dynclks != -1 && radeon_dynclks)
3868                 radeon_legacy_set_clock_gating(rdev, 1);
3869         /* We need to force on some of the block */
3870         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3871         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3872         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3873                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3874         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3875 }
3876
3877 static int r100_startup(struct radeon_device *rdev)
3878 {
3879         int r;
3880
3881         /* set common regs */
3882         r100_set_common_regs(rdev);
3883         /* program mc */
3884         r100_mc_program(rdev);
3885         /* Resume clock */
3886         r100_clock_startup(rdev);
3887         /* Initialize GART (initialize after TTM so we can allocate
3888          * memory through TTM but finalize after TTM) */
3889         r100_enable_bm(rdev);
3890         if (rdev->flags & RADEON_IS_PCI) {
3891                 r = r100_pci_gart_enable(rdev);
3892                 if (r)
3893                         return r;
3894         }
3895
3896         /* allocate wb buffer */
3897         r = radeon_wb_init(rdev);
3898         if (r)
3899                 return r;
3900
3901         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3902         if (r) {
3903                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3904                 return r;
3905         }
3906
3907         /* Enable IRQ */
3908         r100_irq_set(rdev);
3909         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3910         /* 1M ring buffer */
3911         r = r100_cp_init(rdev, 1024 * 1024);
3912         if (r) {
3913                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3914                 return r;
3915         }
3916
3917         r = radeon_ib_pool_start(rdev);
3918         if (r)
3919                 return r;
3920
3921         r = r100_ib_test(rdev);
3922         if (r) {
3923                 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
3924                 rdev->accel_working = false;
3925                 return r;
3926         }
3927
3928         return 0;
3929 }
3930
3931 int r100_resume(struct radeon_device *rdev)
3932 {
3933         /* Make sur GART are not working */
3934         if (rdev->flags & RADEON_IS_PCI)
3935                 r100_pci_gart_disable(rdev);
3936         /* Resume clock before doing reset */
3937         r100_clock_startup(rdev);
3938         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3939         if (radeon_asic_reset(rdev)) {
3940                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3941                         RREG32(R_000E40_RBBM_STATUS),
3942                         RREG32(R_0007C0_CP_STAT));
3943         }
3944         /* post */
3945         radeon_combios_asic_init(rdev->ddev);
3946         /* Resume clock after posting */
3947         r100_clock_startup(rdev);
3948         /* Initialize surface registers */
3949         radeon_surface_init(rdev);
3950
3951         rdev->accel_working = true;
3952         return r100_startup(rdev);
3953 }
3954
3955 int r100_suspend(struct radeon_device *rdev)
3956 {
3957         radeon_ib_pool_suspend(rdev);
3958         r100_cp_disable(rdev);
3959         radeon_wb_disable(rdev);
3960         r100_irq_disable(rdev);
3961         if (rdev->flags & RADEON_IS_PCI)
3962                 r100_pci_gart_disable(rdev);
3963         return 0;
3964 }
3965
3966 void r100_fini(struct radeon_device *rdev)
3967 {
3968         r100_cp_fini(rdev);
3969         radeon_wb_fini(rdev);
3970         r100_ib_fini(rdev);
3971         radeon_gem_fini(rdev);
3972         if (rdev->flags & RADEON_IS_PCI)
3973                 r100_pci_gart_fini(rdev);
3974         radeon_agp_fini(rdev);
3975         radeon_irq_kms_fini(rdev);
3976         radeon_fence_driver_fini(rdev);
3977         radeon_bo_fini(rdev);
3978         radeon_atombios_fini(rdev);
3979         kfree(rdev->bios);
3980         rdev->bios = NULL;
3981 }
3982
3983 /*
3984  * Due to how kexec works, it can leave the hw fully initialised when it
3985  * boots the new kernel. However doing our init sequence with the CP and
3986  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3987  * do some quick sanity checks and restore sane values to avoid this
3988  * problem.
3989  */
3990 void r100_restore_sanity(struct radeon_device *rdev)
3991 {
3992         u32 tmp;
3993
3994         tmp = RREG32(RADEON_CP_CSQ_CNTL);
3995         if (tmp) {
3996                 WREG32(RADEON_CP_CSQ_CNTL, 0);
3997         }
3998         tmp = RREG32(RADEON_CP_RB_CNTL);
3999         if (tmp) {
4000                 WREG32(RADEON_CP_RB_CNTL, 0);
4001         }
4002         tmp = RREG32(RADEON_SCRATCH_UMSK);
4003         if (tmp) {
4004                 WREG32(RADEON_SCRATCH_UMSK, 0);
4005         }
4006 }
4007
4008 int r100_init(struct radeon_device *rdev)
4009 {
4010         int r;
4011
4012         /* Register debugfs file specific to this group of asics */
4013         r100_debugfs(rdev);
4014         /* Disable VGA */
4015         r100_vga_render_disable(rdev);
4016         /* Initialize scratch registers */
4017         radeon_scratch_init(rdev);
4018         /* Initialize surface registers */
4019         radeon_surface_init(rdev);
4020         /* sanity check some register to avoid hangs like after kexec */
4021         r100_restore_sanity(rdev);
4022         /* TODO: disable VGA need to use VGA request */
4023         /* BIOS*/
4024         if (!radeon_get_bios(rdev)) {
4025                 if (ASIC_IS_AVIVO(rdev))
4026                         return -EINVAL;
4027         }
4028         if (rdev->is_atom_bios) {
4029                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4030                 return -EINVAL;
4031         } else {
4032                 r = radeon_combios_init(rdev);
4033                 if (r)
4034                         return r;
4035         }
4036         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4037         if (radeon_asic_reset(rdev)) {
4038                 dev_warn(rdev->dev,
4039                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4040                         RREG32(R_000E40_RBBM_STATUS),
4041                         RREG32(R_0007C0_CP_STAT));
4042         }
4043         /* check if cards are posted or not */
4044         if (radeon_boot_test_post_card(rdev) == false)
4045                 return -EINVAL;
4046         /* Set asic errata */
4047         r100_errata(rdev);
4048         /* Initialize clocks */
4049         radeon_get_clock_info(rdev->ddev);
4050         /* initialize AGP */
4051         if (rdev->flags & RADEON_IS_AGP) {
4052                 r = radeon_agp_init(rdev);
4053                 if (r) {
4054                         radeon_agp_disable(rdev);
4055                 }
4056         }
4057         /* initialize VRAM */
4058         r100_mc_init(rdev);
4059         /* Fence driver */
4060         r = radeon_fence_driver_init(rdev);
4061         if (r)
4062                 return r;
4063         r = radeon_irq_kms_init(rdev);
4064         if (r)
4065                 return r;
4066         /* Memory manager */
4067         r = radeon_bo_init(rdev);
4068         if (r)
4069                 return r;
4070         if (rdev->flags & RADEON_IS_PCI) {
4071                 r = r100_pci_gart_init(rdev);
4072                 if (r)
4073                         return r;
4074         }
4075         r100_set_safe_registers(rdev);
4076
4077         r = radeon_ib_pool_init(rdev);
4078         rdev->accel_working = true;
4079         if (r) {
4080                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4081                 rdev->accel_working = false;
4082         }
4083
4084         r = r100_startup(rdev);
4085         if (r) {
4086                 /* Somethings want wront with the accel init stop accel */
4087                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4088                 r100_cp_fini(rdev);
4089                 radeon_wb_fini(rdev);
4090                 r100_ib_fini(rdev);
4091                 radeon_irq_kms_fini(rdev);
4092                 if (rdev->flags & RADEON_IS_PCI)
4093                         r100_pci_gart_fini(rdev);
4094                 rdev->accel_working = false;
4095         }
4096         return 0;
4097 }
4098
4099 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4100 {
4101         if (reg < rdev->rmmio_size)
4102                 return readl(((void __iomem *)rdev->rmmio) + reg);
4103         else {
4104                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4105                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4106         }
4107 }
4108
4109 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4110 {
4111         if (reg < rdev->rmmio_size)
4112                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4113         else {
4114                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4115                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4116         }
4117 }
4118
4119 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4120 {
4121         if (reg < rdev->rio_mem_size)
4122                 return ioread32(rdev->rio_mem + reg);
4123         else {
4124                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4125                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4126         }
4127 }
4128
4129 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4130 {
4131         if (reg < rdev->rio_mem_size)
4132                 iowrite32(v, rdev->rio_mem + reg);
4133         else {
4134                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4135                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4136         }
4137 }