3093b4d4a4ddb2329d407a09aa17bce413d5e77f
[linux-2.6.git] / drivers / gpu / drm / i915 / intel_sdvo.c
1 /*
2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright © 2006-2007 Intel Corporation
4  *   Jesse Barnes <jesse.barnes@intel.com>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23  * DEALINGS IN THE SOFTWARE.
24  *
25  * Authors:
26  *      Eric Anholt <eric@anholt.net>
27  */
28 #include <linux/i2c.h>
29 #include <linux/delay.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "drm_crtc.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "intel_sdvo_regs.h"
37
38 #undef SDVO_DEBUG
39
40 struct intel_sdvo_priv {
41         struct intel_i2c_chan *i2c_bus;
42         int slaveaddr;
43
44         /* Register for the SDVO device: SDVOB or SDVOC */
45         int output_device;
46
47         /* Active outputs controlled by this SDVO output */
48         uint16_t controlled_output;
49
50         /*
51          * Capabilities of the SDVO device returned by
52          * i830_sdvo_get_capabilities()
53          */
54         struct intel_sdvo_caps caps;
55
56         /* Pixel clock limitations reported by the SDVO device, in kHz */
57         int pixel_clock_min, pixel_clock_max;
58
59         /**
60          * This is set if we're going to treat the device as TV-out.
61          *
62          * While we have these nice friendly flags for output types that ought
63          * to decide this for us, the S-Video output on our HDMI+S-Video card
64          * shows up as RGB1 (VGA).
65          */
66         bool is_tv;
67
68         /**
69          * This is set if we treat the device as HDMI, instead of DVI.
70          */
71         bool is_hdmi;
72         /**
73          * This is set if we detect output of sdvo device as LVDS.
74          */
75         bool is_lvds;
76
77         /**
78          * Returned SDTV resolutions allowed for the current format, if the
79          * device reported it.
80          */
81         struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
82
83         /**
84          * Current selected TV format.
85          *
86          * This is stored in the same structure that's passed to the device, for
87          * convenience.
88          */
89         struct intel_sdvo_tv_format tv_format;
90
91         /*
92          * supported encoding mode, used to determine whether HDMI is
93          * supported
94          */
95         struct intel_sdvo_encode encode;
96
97         /* DDC bus used by this SDVO output */
98         uint8_t ddc_bus;
99
100         int save_sdvo_mult;
101         u16 save_active_outputs;
102         struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
103         struct intel_sdvo_dtd save_output_dtd[16];
104         u32 save_SDVOX;
105 };
106
107 /**
108  * Writes the SDVOB or SDVOC with the given value, but always writes both
109  * SDVOB and SDVOC to work around apparent hardware issues (according to
110  * comments in the BIOS).
111  */
112 static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
113 {
114         struct drm_device *dev = intel_output->base.dev;
115         struct drm_i915_private *dev_priv = dev->dev_private;
116         struct intel_sdvo_priv   *sdvo_priv = intel_output->dev_priv;
117         u32 bval = val, cval = val;
118         int i;
119
120         if (sdvo_priv->output_device == SDVOB) {
121                 cval = I915_READ(SDVOC);
122         } else {
123                 bval = I915_READ(SDVOB);
124         }
125         /*
126          * Write the registers twice for luck. Sometimes,
127          * writing them only once doesn't appear to 'stick'.
128          * The BIOS does this too. Yay, magic
129          */
130         for (i = 0; i < 2; i++)
131         {
132                 I915_WRITE(SDVOB, bval);
133                 I915_READ(SDVOB);
134                 I915_WRITE(SDVOC, cval);
135                 I915_READ(SDVOC);
136         }
137 }
138
139 static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
140                                  u8 *ch)
141 {
142         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
143         u8 out_buf[2];
144         u8 buf[2];
145         int ret;
146
147         struct i2c_msg msgs[] = {
148                 {
149                         .addr = sdvo_priv->i2c_bus->slave_addr,
150                         .flags = 0,
151                         .len = 1,
152                         .buf = out_buf,
153                 },
154                 {
155                         .addr = sdvo_priv->i2c_bus->slave_addr,
156                         .flags = I2C_M_RD,
157                         .len = 1,
158                         .buf = buf,
159                 }
160         };
161
162         out_buf[0] = addr;
163         out_buf[1] = 0;
164
165         if ((ret = i2c_transfer(&sdvo_priv->i2c_bus->adapter, msgs, 2)) == 2)
166         {
167                 *ch = buf[0];
168                 return true;
169         }
170
171         DRM_DEBUG("i2c transfer returned %d\n", ret);
172         return false;
173 }
174
175 static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
176                                   u8 ch)
177 {
178         u8 out_buf[2];
179         struct i2c_msg msgs[] = {
180                 {
181                         .addr = intel_output->i2c_bus->slave_addr,
182                         .flags = 0,
183                         .len = 2,
184                         .buf = out_buf,
185                 }
186         };
187
188         out_buf[0] = addr;
189         out_buf[1] = ch;
190
191         if (i2c_transfer(&intel_output->i2c_bus->adapter, msgs, 1) == 1)
192         {
193                 return true;
194         }
195         return false;
196 }
197
198 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
199 /** Mapping of command numbers to names, for debug output */
200 static const struct _sdvo_cmd_name {
201         u8 cmd;
202         char *name;
203 } sdvo_cmd_names[] = {
204     SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
205     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
206     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
207     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
208     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
209     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
210     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
211     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
212     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
213     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
214     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
215     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
216     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
217     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
218     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
219     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
220     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
221     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
222     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
223     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
224     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
225     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
226     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
227     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
228     SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
229     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
230     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
231     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
232     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
233     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
234     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
235     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
236     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
237     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
238     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
239     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
240     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
241     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
242     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
243     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
244     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
245     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
246     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
247     /* HDMI op code */
248     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
249     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
250     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
251     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
252     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
253     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
254     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
255     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
256     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
257     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
258     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
259     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
260     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
261     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
262     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
263     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
264     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
265     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
266     SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
267     SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
268 };
269
270 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
271 #define SDVO_PRIV(output)   ((struct intel_sdvo_priv *) (output)->dev_priv)
272
273 #ifdef SDVO_DEBUG
274 static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
275                                    void *args, int args_len)
276 {
277         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
278         int i;
279
280         printk(KERN_DEBUG "%s: W: %02X ", SDVO_NAME(sdvo_priv), cmd);
281         for (i = 0; i < args_len; i++)
282                 printk(KERN_DEBUG "%02X ", ((u8 *)args)[i]);
283         for (; i < 8; i++)
284                 printk(KERN_DEBUG "   ");
285         for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
286                 if (cmd == sdvo_cmd_names[i].cmd) {
287                         printk(KERN_DEBUG "(%s)", sdvo_cmd_names[i].name);
288                         break;
289                 }
290         }
291         if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
292                 printk(KERN_DEBUG "(%02X)", cmd);
293         printk(KERN_DEBUG "\n");
294 }
295 #else
296 #define intel_sdvo_debug_write(o, c, a, l)
297 #endif
298
299 static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
300                                  void *args, int args_len)
301 {
302         int i;
303
304         intel_sdvo_debug_write(intel_output, cmd, args, args_len);
305
306         for (i = 0; i < args_len; i++) {
307                 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
308                                       ((u8*)args)[i]);
309         }
310
311         intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
312 }
313
314 #ifdef SDVO_DEBUG
315 static const char *cmd_status_names[] = {
316         "Power on",
317         "Success",
318         "Not supported",
319         "Invalid arg",
320         "Pending",
321         "Target not specified",
322         "Scaling not supported"
323 };
324
325 static void intel_sdvo_debug_response(struct intel_output *intel_output,
326                                       void *response, int response_len,
327                                       u8 status)
328 {
329         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
330         int i;
331
332         printk(KERN_DEBUG "%s: R: ", SDVO_NAME(sdvo_priv));
333         for (i = 0; i < response_len; i++)
334                 printk(KERN_DEBUG "%02X ", ((u8 *)response)[i]);
335         for (; i < 8; i++)
336                 printk(KERN_DEBUG "   ");
337         if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
338                 printk(KERN_DEBUG "(%s)", cmd_status_names[status]);
339         else
340                 printk(KERN_DEBUG "(??? %d)", status);
341         printk(KERN_DEBUG "\n");
342 }
343 #else
344 #define intel_sdvo_debug_response(o, r, l, s)
345 #endif
346
347 static u8 intel_sdvo_read_response(struct intel_output *intel_output,
348                                    void *response, int response_len)
349 {
350         int i;
351         u8 status;
352         u8 retry = 50;
353
354         while (retry--) {
355                 /* Read the command response */
356                 for (i = 0; i < response_len; i++) {
357                         intel_sdvo_read_byte(intel_output,
358                                              SDVO_I2C_RETURN_0 + i,
359                                              &((u8 *)response)[i]);
360                 }
361
362                 /* read the return status */
363                 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
364                                      &status);
365
366                 intel_sdvo_debug_response(intel_output, response, response_len,
367                                           status);
368                 if (status != SDVO_CMD_STATUS_PENDING)
369                         return status;
370
371                 mdelay(50);
372         }
373
374         return status;
375 }
376
377 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
378 {
379         if (mode->clock >= 100000)
380                 return 1;
381         else if (mode->clock >= 50000)
382                 return 2;
383         else
384                 return 4;
385 }
386
387 /**
388  * Don't check status code from this as it switches the bus back to the
389  * SDVO chips which defeats the purpose of doing a bus switch in the first
390  * place.
391  */
392 static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
393                                               u8 target)
394 {
395         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
396 }
397
398 static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
399 {
400         struct intel_sdvo_set_target_input_args targets = {0};
401         u8 status;
402
403         if (target_0 && target_1)
404                 return SDVO_CMD_STATUS_NOTSUPP;
405
406         if (target_1)
407                 targets.target_1 = 1;
408
409         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
410                              sizeof(targets));
411
412         status = intel_sdvo_read_response(intel_output, NULL, 0);
413
414         return (status == SDVO_CMD_STATUS_SUCCESS);
415 }
416
417 /**
418  * Return whether each input is trained.
419  *
420  * This function is making an assumption about the layout of the response,
421  * which should be checked against the docs.
422  */
423 static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
424 {
425         struct intel_sdvo_get_trained_inputs_response response;
426         u8 status;
427
428         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
429         status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
430         if (status != SDVO_CMD_STATUS_SUCCESS)
431                 return false;
432
433         *input_1 = response.input0_trained;
434         *input_2 = response.input1_trained;
435         return true;
436 }
437
438 static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
439                                           u16 *outputs)
440 {
441         u8 status;
442
443         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
444         status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
445
446         return (status == SDVO_CMD_STATUS_SUCCESS);
447 }
448
449 static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
450                                           u16 outputs)
451 {
452         u8 status;
453
454         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
455                              sizeof(outputs));
456         status = intel_sdvo_read_response(intel_output, NULL, 0);
457         return (status == SDVO_CMD_STATUS_SUCCESS);
458 }
459
460 static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
461                                                int mode)
462 {
463         u8 status, state = SDVO_ENCODER_STATE_ON;
464
465         switch (mode) {
466         case DRM_MODE_DPMS_ON:
467                 state = SDVO_ENCODER_STATE_ON;
468                 break;
469         case DRM_MODE_DPMS_STANDBY:
470                 state = SDVO_ENCODER_STATE_STANDBY;
471                 break;
472         case DRM_MODE_DPMS_SUSPEND:
473                 state = SDVO_ENCODER_STATE_SUSPEND;
474                 break;
475         case DRM_MODE_DPMS_OFF:
476                 state = SDVO_ENCODER_STATE_OFF;
477                 break;
478         }
479
480         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
481                              sizeof(state));
482         status = intel_sdvo_read_response(intel_output, NULL, 0);
483
484         return (status == SDVO_CMD_STATUS_SUCCESS);
485 }
486
487 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
488                                                    int *clock_min,
489                                                    int *clock_max)
490 {
491         struct intel_sdvo_pixel_clock_range clocks;
492         u8 status;
493
494         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
495                              NULL, 0);
496
497         status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
498
499         if (status != SDVO_CMD_STATUS_SUCCESS)
500                 return false;
501
502         /* Convert the values from units of 10 kHz to kHz. */
503         *clock_min = clocks.min * 10;
504         *clock_max = clocks.max * 10;
505
506         return true;
507 }
508
509 static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
510                                          u16 outputs)
511 {
512         u8 status;
513
514         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
515                              sizeof(outputs));
516
517         status = intel_sdvo_read_response(intel_output, NULL, 0);
518         return (status == SDVO_CMD_STATUS_SUCCESS);
519 }
520
521 static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
522                                   struct intel_sdvo_dtd *dtd)
523 {
524         u8 status;
525
526         intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
527         status = intel_sdvo_read_response(intel_output, &dtd->part1,
528                                           sizeof(dtd->part1));
529         if (status != SDVO_CMD_STATUS_SUCCESS)
530                 return false;
531
532         intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
533         status = intel_sdvo_read_response(intel_output, &dtd->part2,
534                                           sizeof(dtd->part2));
535         if (status != SDVO_CMD_STATUS_SUCCESS)
536                 return false;
537
538         return true;
539 }
540
541 static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
542                                          struct intel_sdvo_dtd *dtd)
543 {
544         return intel_sdvo_get_timing(intel_output,
545                                      SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
546 }
547
548 static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
549                                          struct intel_sdvo_dtd *dtd)
550 {
551         return intel_sdvo_get_timing(intel_output,
552                                      SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
553 }
554
555 static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
556                                   struct intel_sdvo_dtd *dtd)
557 {
558         u8 status;
559
560         intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
561         status = intel_sdvo_read_response(intel_output, NULL, 0);
562         if (status != SDVO_CMD_STATUS_SUCCESS)
563                 return false;
564
565         intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
566         status = intel_sdvo_read_response(intel_output, NULL, 0);
567         if (status != SDVO_CMD_STATUS_SUCCESS)
568                 return false;
569
570         return true;
571 }
572
573 static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
574                                          struct intel_sdvo_dtd *dtd)
575 {
576         return intel_sdvo_set_timing(intel_output,
577                                      SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
578 }
579
580 static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
581                                          struct intel_sdvo_dtd *dtd)
582 {
583         return intel_sdvo_set_timing(intel_output,
584                                      SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
585 }
586
587 static bool
588 intel_sdvo_create_preferred_input_timing(struct intel_output *output,
589                                          uint16_t clock,
590                                          uint16_t width,
591                                          uint16_t height)
592 {
593         struct intel_sdvo_preferred_input_timing_args args;
594         uint8_t status;
595
596         memset(&args, 0, sizeof(args));
597         args.clock = clock;
598         args.width = width;
599         args.height = height;
600         args.interlace = 0;
601         args.scaled = 0;
602         intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
603                              &args, sizeof(args));
604         status = intel_sdvo_read_response(output, NULL, 0);
605         if (status != SDVO_CMD_STATUS_SUCCESS)
606                 return false;
607
608         return true;
609 }
610
611 static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
612                                                   struct intel_sdvo_dtd *dtd)
613 {
614         bool status;
615
616         intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
617                              NULL, 0);
618
619         status = intel_sdvo_read_response(output, &dtd->part1,
620                                           sizeof(dtd->part1));
621         if (status != SDVO_CMD_STATUS_SUCCESS)
622                 return false;
623
624         intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
625                              NULL, 0);
626
627         status = intel_sdvo_read_response(output, &dtd->part2,
628                                           sizeof(dtd->part2));
629         if (status != SDVO_CMD_STATUS_SUCCESS)
630                 return false;
631
632         return false;
633 }
634
635 static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
636 {
637         u8 response, status;
638
639         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
640         status = intel_sdvo_read_response(intel_output, &response, 1);
641
642         if (status != SDVO_CMD_STATUS_SUCCESS) {
643                 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
644                 return SDVO_CLOCK_RATE_MULT_1X;
645         } else {
646                 DRM_DEBUG("Current clock rate multiplier: %d\n", response);
647         }
648
649         return response;
650 }
651
652 static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
653 {
654         u8 status;
655
656         intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
657         status = intel_sdvo_read_response(intel_output, NULL, 0);
658         if (status != SDVO_CMD_STATUS_SUCCESS)
659                 return false;
660
661         return true;
662 }
663
664 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
665                                          struct drm_display_mode *mode)
666 {
667         uint16_t width, height;
668         uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
669         uint16_t h_sync_offset, v_sync_offset;
670
671         width = mode->crtc_hdisplay;
672         height = mode->crtc_vdisplay;
673
674         /* do some mode translations */
675         h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
676         h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
677
678         v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
679         v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
680
681         h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
682         v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
683
684         dtd->part1.clock = mode->clock / 10;
685         dtd->part1.h_active = width & 0xff;
686         dtd->part1.h_blank = h_blank_len & 0xff;
687         dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
688                 ((h_blank_len >> 8) & 0xf);
689         dtd->part1.v_active = height & 0xff;
690         dtd->part1.v_blank = v_blank_len & 0xff;
691         dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
692                 ((v_blank_len >> 8) & 0xf);
693
694         dtd->part2.h_sync_off = h_sync_offset & 0xff;
695         dtd->part2.h_sync_width = h_sync_len & 0xff;
696         dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
697                 (v_sync_len & 0xf);
698         dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
699                 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
700                 ((v_sync_len & 0x30) >> 4);
701
702         dtd->part2.dtd_flags = 0x18;
703         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
704                 dtd->part2.dtd_flags |= 0x2;
705         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
706                 dtd->part2.dtd_flags |= 0x4;
707
708         dtd->part2.sdvo_flags = 0;
709         dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
710         dtd->part2.reserved = 0;
711 }
712
713 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
714                                          struct intel_sdvo_dtd *dtd)
715 {
716         mode->hdisplay = dtd->part1.h_active;
717         mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
718         mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
719         mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
720         mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
721         mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
722         mode->htotal = mode->hdisplay + dtd->part1.h_blank;
723         mode->htotal += (dtd->part1.h_high & 0xf) << 8;
724
725         mode->vdisplay = dtd->part1.v_active;
726         mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
727         mode->vsync_start = mode->vdisplay;
728         mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
729         mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
730         mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
731         mode->vsync_end = mode->vsync_start +
732                 (dtd->part2.v_sync_off_width & 0xf);
733         mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
734         mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
735         mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
736
737         mode->clock = dtd->part1.clock * 10;
738
739         mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
740         if (dtd->part2.dtd_flags & 0x2)
741                 mode->flags |= DRM_MODE_FLAG_PHSYNC;
742         if (dtd->part2.dtd_flags & 0x4)
743                 mode->flags |= DRM_MODE_FLAG_PVSYNC;
744 }
745
746 static bool intel_sdvo_get_supp_encode(struct intel_output *output,
747                                        struct intel_sdvo_encode *encode)
748 {
749         uint8_t status;
750
751         intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
752         status = intel_sdvo_read_response(output, encode, sizeof(*encode));
753         if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
754                 memset(encode, 0, sizeof(*encode));
755                 return false;
756         }
757
758         return true;
759 }
760
761 static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
762 {
763         uint8_t status;
764
765         intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
766         status = intel_sdvo_read_response(output, NULL, 0);
767
768         return (status == SDVO_CMD_STATUS_SUCCESS);
769 }
770
771 static bool intel_sdvo_set_colorimetry(struct intel_output *output,
772                                        uint8_t mode)
773 {
774         uint8_t status;
775
776         intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
777         status = intel_sdvo_read_response(output, NULL, 0);
778
779         return (status == SDVO_CMD_STATUS_SUCCESS);
780 }
781
782 #if 0
783 static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
784 {
785         int i, j;
786         uint8_t set_buf_index[2];
787         uint8_t av_split;
788         uint8_t buf_size;
789         uint8_t buf[48];
790         uint8_t *pos;
791
792         intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
793         intel_sdvo_read_response(output, &av_split, 1);
794
795         for (i = 0; i <= av_split; i++) {
796                 set_buf_index[0] = i; set_buf_index[1] = 0;
797                 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
798                                      set_buf_index, 2);
799                 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
800                 intel_sdvo_read_response(output, &buf_size, 1);
801
802                 pos = buf;
803                 for (j = 0; j <= buf_size; j += 8) {
804                         intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
805                                              NULL, 0);
806                         intel_sdvo_read_response(output, pos, 8);
807                         pos += 8;
808                 }
809         }
810 }
811 #endif
812
813 static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
814                                 uint8_t *data, int8_t size, uint8_t tx_rate)
815 {
816     uint8_t set_buf_index[2];
817
818     set_buf_index[0] = index;
819     set_buf_index[1] = 0;
820
821     intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
822
823     for (; size > 0; size -= 8) {
824         intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
825         data += 8;
826     }
827
828     intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
829 }
830
831 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
832 {
833         uint8_t csum = 0;
834         int i;
835
836         for (i = 0; i < size; i++)
837                 csum += data[i];
838
839         return 0x100 - csum;
840 }
841
842 #define DIP_TYPE_AVI    0x82
843 #define DIP_VERSION_AVI 0x2
844 #define DIP_LEN_AVI     13
845
846 struct dip_infoframe {
847         uint8_t type;
848         uint8_t version;
849         uint8_t len;
850         uint8_t checksum;
851         union {
852                 struct {
853                         /* Packet Byte #1 */
854                         uint8_t S:2;
855                         uint8_t B:2;
856                         uint8_t A:1;
857                         uint8_t Y:2;
858                         uint8_t rsvd1:1;
859                         /* Packet Byte #2 */
860                         uint8_t R:4;
861                         uint8_t M:2;
862                         uint8_t C:2;
863                         /* Packet Byte #3 */
864                         uint8_t SC:2;
865                         uint8_t Q:2;
866                         uint8_t EC:3;
867                         uint8_t ITC:1;
868                         /* Packet Byte #4 */
869                         uint8_t VIC:7;
870                         uint8_t rsvd2:1;
871                         /* Packet Byte #5 */
872                         uint8_t PR:4;
873                         uint8_t rsvd3:4;
874                         /* Packet Byte #6~13 */
875                         uint16_t top_bar_end;
876                         uint16_t bottom_bar_start;
877                         uint16_t left_bar_end;
878                         uint16_t right_bar_start;
879                 } avi;
880                 struct {
881                         /* Packet Byte #1 */
882                         uint8_t channel_count:3;
883                         uint8_t rsvd1:1;
884                         uint8_t coding_type:4;
885                         /* Packet Byte #2 */
886                         uint8_t sample_size:2; /* SS0, SS1 */
887                         uint8_t sample_frequency:3;
888                         uint8_t rsvd2:3;
889                         /* Packet Byte #3 */
890                         uint8_t coding_type_private:5;
891                         uint8_t rsvd3:3;
892                         /* Packet Byte #4 */
893                         uint8_t channel_allocation;
894                         /* Packet Byte #5 */
895                         uint8_t rsvd4:3;
896                         uint8_t level_shift:4;
897                         uint8_t downmix_inhibit:1;
898                 } audio;
899                 uint8_t payload[28];
900         } __attribute__ ((packed)) u;
901 } __attribute__((packed));
902
903 static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
904                                          struct drm_display_mode * mode)
905 {
906         struct dip_infoframe avi_if = {
907                 .type = DIP_TYPE_AVI,
908                 .version = DIP_VERSION_AVI,
909                 .len = DIP_LEN_AVI,
910         };
911
912         avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
913                                                     4 + avi_if.len);
914         intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
915                                 SDVO_HBUF_TX_VSYNC);
916 }
917
918 static void intel_sdvo_set_tv_format(struct intel_output *output)
919 {
920         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
921         struct intel_sdvo_tv_format *format, unset;
922         u8 status;
923
924         format = &sdvo_priv->tv_format;
925         memset(&unset, 0, sizeof(unset));
926         if (memcmp(format, &unset, sizeof(*format))) {
927                 DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n",
928                                 SDVO_NAME(sdvo_priv));
929                 format->ntsc_m = 1;
930                 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format,
931                                 sizeof(*format));
932                 status = intel_sdvo_read_response(output, NULL, 0);
933                 if (status != SDVO_CMD_STATUS_SUCCESS)
934                         DRM_DEBUG("%s: Failed to set TV format\n",
935                                         SDVO_NAME(sdvo_priv));
936         }
937 }
938
939 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
940                                   struct drm_display_mode *mode,
941                                   struct drm_display_mode *adjusted_mode)
942 {
943         struct intel_output *output = enc_to_intel_output(encoder);
944         struct intel_sdvo_priv *dev_priv = output->dev_priv;
945
946         if (!dev_priv->is_tv) {
947                 /* Make the CRTC code factor in the SDVO pixel multiplier.  The
948                  * SDVO device will be told of the multiplier during mode_set.
949                  */
950                 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
951         } else {
952                 struct intel_sdvo_dtd output_dtd;
953                 bool success;
954
955                 /* We need to construct preferred input timings based on our
956                  * output timings.  To do that, we have to set the output
957                  * timings, even though this isn't really the right place in
958                  * the sequence to do it. Oh well.
959                  */
960
961
962                 /* Set output timings */
963                 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
964                 intel_sdvo_set_target_output(output,
965                                              dev_priv->controlled_output);
966                 intel_sdvo_set_output_timing(output, &output_dtd);
967
968                 /* Set the input timing to the screen. Assume always input 0. */
969                 intel_sdvo_set_target_input(output, true, false);
970
971
972                 success = intel_sdvo_create_preferred_input_timing(output,
973                                                                    mode->clock / 10,
974                                                                    mode->hdisplay,
975                                                                    mode->vdisplay);
976                 if (success) {
977                         struct intel_sdvo_dtd input_dtd;
978
979                         intel_sdvo_get_preferred_input_timing(output,
980                                                              &input_dtd);
981                         intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
982
983                         drm_mode_set_crtcinfo(adjusted_mode, 0);
984
985                         mode->clock = adjusted_mode->clock;
986
987                         adjusted_mode->clock *=
988                                 intel_sdvo_get_pixel_multiplier(mode);
989                 } else {
990                         return false;
991                 }
992         }
993         return true;
994 }
995
996 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
997                                 struct drm_display_mode *mode,
998                                 struct drm_display_mode *adjusted_mode)
999 {
1000         struct drm_device *dev = encoder->dev;
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002         struct drm_crtc *crtc = encoder->crtc;
1003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1004         struct intel_output *output = enc_to_intel_output(encoder);
1005         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1006         u32 sdvox = 0;
1007         int sdvo_pixel_multiply;
1008         struct intel_sdvo_in_out_map in_out;
1009         struct intel_sdvo_dtd input_dtd;
1010         u8 status;
1011
1012         if (!mode)
1013                 return;
1014
1015         /* First, set the input mapping for the first input to our controlled
1016          * output. This is only correct if we're a single-input device, in
1017          * which case the first input is the output from the appropriate SDVO
1018          * channel on the motherboard.  In a two-input device, the first input
1019          * will be SDVOB and the second SDVOC.
1020          */
1021         in_out.in0 = sdvo_priv->controlled_output;
1022         in_out.in1 = 0;
1023
1024         intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
1025                              &in_out, sizeof(in_out));
1026         status = intel_sdvo_read_response(output, NULL, 0);
1027
1028         if (sdvo_priv->is_hdmi) {
1029                 intel_sdvo_set_avi_infoframe(output, mode);
1030                 sdvox |= SDVO_AUDIO_ENABLE;
1031         }
1032
1033         /* We have tried to get input timing in mode_fixup, and filled into
1034            adjusted_mode */
1035         if (sdvo_priv->is_tv)
1036                 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1037         else
1038                 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1039
1040         /* If it's a TV, we already set the output timing in mode_fixup.
1041          * Otherwise, the output timing is equal to the input timing.
1042          */
1043         if (!sdvo_priv->is_tv) {
1044                 /* Set the output timing to the screen */
1045                 intel_sdvo_set_target_output(output,
1046                                              sdvo_priv->controlled_output);
1047                 intel_sdvo_set_output_timing(output, &input_dtd);
1048         }
1049
1050         /* Set the input timing to the screen. Assume always input 0. */
1051         intel_sdvo_set_target_input(output, true, false);
1052
1053         if (sdvo_priv->is_tv)
1054                 intel_sdvo_set_tv_format(output);
1055
1056         /* We would like to use intel_sdvo_create_preferred_input_timing() to
1057          * provide the device with a timing it can support, if it supports that
1058          * feature.  However, presumably we would need to adjust the CRTC to
1059          * output the preferred timing, and we don't support that currently.
1060          */
1061 #if 0
1062         success = intel_sdvo_create_preferred_input_timing(output, clock,
1063                                                            width, height);
1064         if (success) {
1065                 struct intel_sdvo_dtd *input_dtd;
1066
1067                 intel_sdvo_get_preferred_input_timing(output, &input_dtd);
1068                 intel_sdvo_set_input_timing(output, &input_dtd);
1069         }
1070 #else
1071         intel_sdvo_set_input_timing(output, &input_dtd);
1072 #endif
1073
1074         switch (intel_sdvo_get_pixel_multiplier(mode)) {
1075         case 1:
1076                 intel_sdvo_set_clock_rate_mult(output,
1077                                                SDVO_CLOCK_RATE_MULT_1X);
1078                 break;
1079         case 2:
1080                 intel_sdvo_set_clock_rate_mult(output,
1081                                                SDVO_CLOCK_RATE_MULT_2X);
1082                 break;
1083         case 4:
1084                 intel_sdvo_set_clock_rate_mult(output,
1085                                                SDVO_CLOCK_RATE_MULT_4X);
1086                 break;
1087         }
1088
1089         /* Set the SDVO control regs. */
1090         if (IS_I965G(dev)) {
1091                 sdvox |= SDVO_BORDER_ENABLE |
1092                         SDVO_VSYNC_ACTIVE_HIGH |
1093                         SDVO_HSYNC_ACTIVE_HIGH;
1094         } else {
1095                 sdvox |= I915_READ(sdvo_priv->output_device);
1096                 switch (sdvo_priv->output_device) {
1097                 case SDVOB:
1098                         sdvox &= SDVOB_PRESERVE_MASK;
1099                         break;
1100                 case SDVOC:
1101                         sdvox &= SDVOC_PRESERVE_MASK;
1102                         break;
1103                 }
1104                 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1105         }
1106         if (intel_crtc->pipe == 1)
1107                 sdvox |= SDVO_PIPE_B_SELECT;
1108
1109         sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1110         if (IS_I965G(dev)) {
1111                 /* done in crtc_mode_set as the dpll_md reg must be written early */
1112         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1113                 /* done in crtc_mode_set as it lives inside the dpll register */
1114         } else {
1115                 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1116         }
1117
1118         intel_sdvo_write_sdvox(output, sdvox);
1119 }
1120
1121 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1122 {
1123         struct drm_device *dev = encoder->dev;
1124         struct drm_i915_private *dev_priv = dev->dev_private;
1125         struct intel_output *intel_output = enc_to_intel_output(encoder);
1126         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1127         u32 temp;
1128
1129         if (mode != DRM_MODE_DPMS_ON) {
1130                 intel_sdvo_set_active_outputs(intel_output, 0);
1131                 if (0)
1132                         intel_sdvo_set_encoder_power_state(intel_output, mode);
1133
1134                 if (mode == DRM_MODE_DPMS_OFF) {
1135                         temp = I915_READ(sdvo_priv->output_device);
1136                         if ((temp & SDVO_ENABLE) != 0) {
1137                                 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
1138                         }
1139                 }
1140         } else {
1141                 bool input1, input2;
1142                 int i;
1143                 u8 status;
1144
1145                 temp = I915_READ(sdvo_priv->output_device);
1146                 if ((temp & SDVO_ENABLE) == 0)
1147                         intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
1148                 for (i = 0; i < 2; i++)
1149                   intel_wait_for_vblank(dev);
1150
1151                 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
1152                                                        &input2);
1153
1154
1155                 /* Warn if the device reported failure to sync.
1156                  * A lot of SDVO devices fail to notify of sync, but it's
1157                  * a given it the status is a success, we succeeded.
1158                  */
1159                 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1160                         DRM_DEBUG("First %s output reported failure to sync\n",
1161                                    SDVO_NAME(sdvo_priv));
1162                 }
1163
1164                 if (0)
1165                         intel_sdvo_set_encoder_power_state(intel_output, mode);
1166                 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
1167         }
1168         return;
1169 }
1170
1171 static void intel_sdvo_save(struct drm_connector *connector)
1172 {
1173         struct drm_device *dev = connector->dev;
1174         struct drm_i915_private *dev_priv = dev->dev_private;
1175         struct intel_output *intel_output = to_intel_output(connector);
1176         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1177         int o;
1178
1179         sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
1180         intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
1181
1182         if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1183                 intel_sdvo_set_target_input(intel_output, true, false);
1184                 intel_sdvo_get_input_timing(intel_output,
1185                                             &sdvo_priv->save_input_dtd_1);
1186         }
1187
1188         if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1189                 intel_sdvo_set_target_input(intel_output, false, true);
1190                 intel_sdvo_get_input_timing(intel_output,
1191                                             &sdvo_priv->save_input_dtd_2);
1192         }
1193
1194         for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1195         {
1196                 u16  this_output = (1 << o);
1197                 if (sdvo_priv->caps.output_flags & this_output)
1198                 {
1199                         intel_sdvo_set_target_output(intel_output, this_output);
1200                         intel_sdvo_get_output_timing(intel_output,
1201                                                      &sdvo_priv->save_output_dtd[o]);
1202                 }
1203         }
1204         if (sdvo_priv->is_tv) {
1205                 /* XXX: Save TV format/enhancements. */
1206         }
1207
1208         sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
1209 }
1210
1211 static void intel_sdvo_restore(struct drm_connector *connector)
1212 {
1213         struct drm_device *dev = connector->dev;
1214         struct intel_output *intel_output = to_intel_output(connector);
1215         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1216         int o;
1217         int i;
1218         bool input1, input2;
1219         u8 status;
1220
1221         intel_sdvo_set_active_outputs(intel_output, 0);
1222
1223         for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1224         {
1225                 u16  this_output = (1 << o);
1226                 if (sdvo_priv->caps.output_flags & this_output) {
1227                         intel_sdvo_set_target_output(intel_output, this_output);
1228                         intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
1229                 }
1230         }
1231
1232         if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1233                 intel_sdvo_set_target_input(intel_output, true, false);
1234                 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
1235         }
1236
1237         if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1238                 intel_sdvo_set_target_input(intel_output, false, true);
1239                 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
1240         }
1241
1242         intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
1243
1244         if (sdvo_priv->is_tv) {
1245                 /* XXX: Restore TV format/enhancements. */
1246         }
1247
1248         intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
1249
1250         if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1251         {
1252                 for (i = 0; i < 2; i++)
1253                         intel_wait_for_vblank(dev);
1254                 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
1255                 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1256                         DRM_DEBUG("First %s output reported failure to sync\n",
1257                                    SDVO_NAME(sdvo_priv));
1258         }
1259
1260         intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
1261 }
1262
1263 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1264                                  struct drm_display_mode *mode)
1265 {
1266         struct intel_output *intel_output = to_intel_output(connector);
1267         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1268
1269         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1270                 return MODE_NO_DBLESCAN;
1271
1272         if (sdvo_priv->pixel_clock_min > mode->clock)
1273                 return MODE_CLOCK_LOW;
1274
1275         if (sdvo_priv->pixel_clock_max < mode->clock)
1276                 return MODE_CLOCK_HIGH;
1277
1278         return MODE_OK;
1279 }
1280
1281 static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
1282 {
1283         u8 status;
1284
1285         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1286         status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
1287         if (status != SDVO_CMD_STATUS_SUCCESS)
1288                 return false;
1289
1290         return true;
1291 }
1292
1293 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1294 {
1295         struct drm_connector *connector = NULL;
1296         struct intel_output *iout = NULL;
1297         struct intel_sdvo_priv *sdvo;
1298
1299         /* find the sdvo connector */
1300         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1301                 iout = to_intel_output(connector);
1302
1303                 if (iout->type != INTEL_OUTPUT_SDVO)
1304                         continue;
1305
1306                 sdvo = iout->dev_priv;
1307
1308                 if (sdvo->output_device == SDVOB && sdvoB)
1309                         return connector;
1310
1311                 if (sdvo->output_device == SDVOC && !sdvoB)
1312                         return connector;
1313
1314         }
1315
1316         return NULL;
1317 }
1318
1319 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1320 {
1321         u8 response[2];
1322         u8 status;
1323         struct intel_output *intel_output;
1324         DRM_DEBUG("\n");
1325
1326         if (!connector)
1327                 return 0;
1328
1329         intel_output = to_intel_output(connector);
1330
1331         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1332         status = intel_sdvo_read_response(intel_output, &response, 2);
1333
1334         if (response[0] !=0)
1335                 return 1;
1336
1337         return 0;
1338 }
1339
1340 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1341 {
1342         u8 response[2];
1343         u8 status;
1344         struct intel_output *intel_output = to_intel_output(connector);
1345
1346         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1347         intel_sdvo_read_response(intel_output, &response, 2);
1348
1349         if (on) {
1350                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1351                 status = intel_sdvo_read_response(intel_output, &response, 2);
1352
1353                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1354         } else {
1355                 response[0] = 0;
1356                 response[1] = 0;
1357                 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1358         }
1359
1360         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1361         intel_sdvo_read_response(intel_output, &response, 2);
1362 }
1363
1364 static void
1365 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
1366 {
1367         struct intel_output *intel_output = to_intel_output(connector);
1368         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1369         struct edid *edid = NULL;
1370
1371         intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
1372         edid = drm_get_edid(&intel_output->base,
1373                             &intel_output->ddc_bus->adapter);
1374         if (edid != NULL) {
1375                 sdvo_priv->is_hdmi = drm_detect_hdmi_monitor(edid);
1376                 kfree(edid);
1377                 intel_output->base.display_info.raw_edid = NULL;
1378         }
1379 }
1380
1381 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1382 {
1383         u8 response[2];
1384         u8 status;
1385         struct intel_output *intel_output = to_intel_output(connector);
1386
1387         intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1388         status = intel_sdvo_read_response(intel_output, &response, 2);
1389
1390         DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]);
1391
1392         if (status != SDVO_CMD_STATUS_SUCCESS)
1393                 return connector_status_unknown;
1394
1395         if ((response[0] != 0) || (response[1] != 0)) {
1396                 intel_sdvo_hdmi_sink_detect(connector);
1397                 return connector_status_connected;
1398         } else
1399                 return connector_status_disconnected;
1400 }
1401
1402 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1403 {
1404         struct intel_output *intel_output = to_intel_output(connector);
1405
1406         /* set the bus switch and get the modes */
1407         intel_ddc_get_modes(intel_output);
1408
1409 #if 0
1410         struct drm_device *dev = encoder->dev;
1411         struct drm_i915_private *dev_priv = dev->dev_private;
1412         /* Mac mini hack.  On this device, I get DDC through the analog, which
1413          * load-detects as disconnected.  I fail to DDC through the SDVO DDC,
1414          * but it does load-detect as connected.  So, just steal the DDC bits
1415          * from analog when we fail at finding it the right way.
1416          */
1417         crt = xf86_config->output[0];
1418         intel_output = crt->driver_private;
1419         if (intel_output->type == I830_OUTPUT_ANALOG &&
1420             crt->funcs->detect(crt) == XF86OutputStatusDisconnected) {
1421                 I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A");
1422                 edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus);
1423                 xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true);
1424         }
1425         if (edid_mon) {
1426                 xf86OutputSetEDID(output, edid_mon);
1427                 modes = xf86OutputGetEDIDModes(output);
1428         }
1429 #endif
1430 }
1431
1432 /**
1433  * This function checks the current TV format, and chooses a default if
1434  * it hasn't been set.
1435  */
1436 static void
1437 intel_sdvo_check_tv_format(struct intel_output *output)
1438 {
1439         struct intel_sdvo_priv *dev_priv = output->dev_priv;
1440         struct intel_sdvo_tv_format format;
1441         uint8_t status;
1442
1443         intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0);
1444         status = intel_sdvo_read_response(output, &format, sizeof(format));
1445         if (status != SDVO_CMD_STATUS_SUCCESS)
1446                 return;
1447
1448         memcpy(&dev_priv->tv_format, &format, sizeof(format));
1449 }
1450
1451 /*
1452  * Set of SDVO TV modes.
1453  * Note!  This is in reply order (see loop in get_tv_modes).
1454  * XXX: all 60Hz refresh?
1455  */
1456 struct drm_display_mode sdvo_tv_modes[] = {
1457         { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1458                    416, 0, 200, 201, 232, 233, 0,
1459                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1460         { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1461                    416, 0, 240, 241, 272, 273, 0,
1462                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1463         { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1464                    496, 0, 300, 301, 332, 333, 0,
1465                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1466         { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1467                    736, 0, 350, 351, 382, 383, 0,
1468                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1469         { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1470                    736, 0, 400, 401, 432, 433, 0,
1471                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1472         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1473                    736, 0, 480, 481, 512, 513, 0,
1474                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1475         { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1476                    800, 0, 480, 481, 512, 513, 0,
1477                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1478         { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1479                    800, 0, 576, 577, 608, 609, 0,
1480                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1481         { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1482                    816, 0, 350, 351, 382, 383, 0,
1483                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1484         { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1485                    816, 0, 400, 401, 432, 433, 0,
1486                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1487         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1488                    816, 0, 480, 481, 512, 513, 0,
1489                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1490         { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1491                    816, 0, 540, 541, 572, 573, 0,
1492                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1493         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1494                    816, 0, 576, 577, 608, 609, 0,
1495                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1496         { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1497                    864, 0, 576, 577, 608, 609, 0,
1498                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1499         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1500                    896, 0, 600, 601, 632, 633, 0,
1501                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1502         { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1503                    928, 0, 624, 625, 656, 657, 0,
1504                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1505         { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1506                    1016, 0, 766, 767, 798, 799, 0,
1507                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1508         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1509                    1120, 0, 768, 769, 800, 801, 0,
1510                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1511         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1512                    1376, 0, 1024, 1025, 1056, 1057, 0,
1513                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1514 };
1515
1516 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1517 {
1518         struct intel_output *output = to_intel_output(connector);
1519         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1520         struct intel_sdvo_sdtv_resolution_request tv_res;
1521         uint32_t reply = 0;
1522         uint8_t status;
1523         int i = 0;
1524
1525         intel_sdvo_check_tv_format(output);
1526
1527         /* Read the list of supported input resolutions for the selected TV
1528          * format.
1529          */
1530         memset(&tv_res, 0, sizeof(tv_res));
1531         memcpy(&tv_res, &sdvo_priv->tv_format, sizeof(tv_res));
1532         intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1533                              &tv_res, sizeof(tv_res));
1534         status = intel_sdvo_read_response(output, &reply, 3);
1535         if (status != SDVO_CMD_STATUS_SUCCESS)
1536                 return;
1537
1538         for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1539                 if (reply & (1 << i)) {
1540                         struct drm_display_mode *nmode;
1541                         nmode = drm_mode_duplicate(connector->dev,
1542                                         &sdvo_tv_modes[i]);
1543                         if (nmode)
1544                                 drm_mode_probed_add(connector, nmode);
1545                 }
1546 }
1547
1548 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1549 {
1550         struct intel_output *intel_output = to_intel_output(connector);
1551         struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1552         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1553
1554         /*
1555          * Attempt to get the mode list from DDC.
1556          * Assume that the preferred modes are
1557          * arranged in priority order.
1558          */
1559         /* set the bus switch and get the modes */
1560         intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
1561         intel_ddc_get_modes(intel_output);
1562         if (list_empty(&connector->probed_modes) == false)
1563                 return;
1564
1565         /* Fetch modes from VBT */
1566         if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
1567                 struct drm_display_mode *newmode;
1568                 newmode = drm_mode_duplicate(connector->dev,
1569                                              dev_priv->sdvo_lvds_vbt_mode);
1570                 if (newmode != NULL) {
1571                         /* Guarantee the mode is preferred */
1572                         newmode->type = (DRM_MODE_TYPE_PREFERRED |
1573                                          DRM_MODE_TYPE_DRIVER);
1574                         drm_mode_probed_add(connector, newmode);
1575                 }
1576         }
1577 }
1578
1579 static int intel_sdvo_get_modes(struct drm_connector *connector)
1580 {
1581         struct intel_output *output = to_intel_output(connector);
1582         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1583
1584         if (sdvo_priv->is_tv)
1585                 intel_sdvo_get_tv_modes(connector);
1586         else if (sdvo_priv->is_lvds == true)
1587                 intel_sdvo_get_lvds_modes(connector);
1588         else
1589                 intel_sdvo_get_ddc_modes(connector);
1590
1591         if (list_empty(&connector->probed_modes))
1592                 return 0;
1593         return 1;
1594 }
1595
1596 static void intel_sdvo_destroy(struct drm_connector *connector)
1597 {
1598         struct intel_output *intel_output = to_intel_output(connector);
1599
1600         if (intel_output->i2c_bus)
1601                 intel_i2c_destroy(intel_output->i2c_bus);
1602         if (intel_output->ddc_bus)
1603                 intel_i2c_destroy(intel_output->ddc_bus);
1604
1605         drm_sysfs_connector_remove(connector);
1606         drm_connector_cleanup(connector);
1607         kfree(intel_output);
1608 }
1609
1610 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1611         .dpms = intel_sdvo_dpms,
1612         .mode_fixup = intel_sdvo_mode_fixup,
1613         .prepare = intel_encoder_prepare,
1614         .mode_set = intel_sdvo_mode_set,
1615         .commit = intel_encoder_commit,
1616 };
1617
1618 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
1619         .dpms = drm_helper_connector_dpms,
1620         .save = intel_sdvo_save,
1621         .restore = intel_sdvo_restore,
1622         .detect = intel_sdvo_detect,
1623         .fill_modes = drm_helper_probe_single_connector_modes,
1624         .destroy = intel_sdvo_destroy,
1625 };
1626
1627 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1628         .get_modes = intel_sdvo_get_modes,
1629         .mode_valid = intel_sdvo_mode_valid,
1630         .best_encoder = intel_best_encoder,
1631 };
1632
1633 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
1634 {
1635         drm_encoder_cleanup(encoder);
1636 }
1637
1638 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1639         .destroy = intel_sdvo_enc_destroy,
1640 };
1641
1642
1643 /**
1644  * Choose the appropriate DDC bus for control bus switch command for this
1645  * SDVO output based on the controlled output.
1646  *
1647  * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1648  * outputs, then LVDS outputs.
1649  */
1650 static void
1651 intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
1652 {
1653         uint16_t mask = 0;
1654         unsigned int num_bits;
1655
1656         /* Make a mask of outputs less than or equal to our own priority in the
1657          * list.
1658          */
1659         switch (dev_priv->controlled_output) {
1660         case SDVO_OUTPUT_LVDS1:
1661                 mask |= SDVO_OUTPUT_LVDS1;
1662         case SDVO_OUTPUT_LVDS0:
1663                 mask |= SDVO_OUTPUT_LVDS0;
1664         case SDVO_OUTPUT_TMDS1:
1665                 mask |= SDVO_OUTPUT_TMDS1;
1666         case SDVO_OUTPUT_TMDS0:
1667                 mask |= SDVO_OUTPUT_TMDS0;
1668         case SDVO_OUTPUT_RGB1:
1669                 mask |= SDVO_OUTPUT_RGB1;
1670         case SDVO_OUTPUT_RGB0:
1671                 mask |= SDVO_OUTPUT_RGB0;
1672                 break;
1673         }
1674
1675         /* Count bits to find what number we are in the priority list. */
1676         mask &= dev_priv->caps.output_flags;
1677         num_bits = hweight16(mask);
1678         if (num_bits > 3) {
1679                 /* if more than 3 outputs, default to DDC bus 3 for now */
1680                 num_bits = 3;
1681         }
1682
1683         /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1684         dev_priv->ddc_bus = 1 << num_bits;
1685 }
1686
1687 static bool
1688 intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
1689 {
1690         struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1691         uint8_t status;
1692
1693         intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1694
1695         intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
1696         status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
1697         if (status != SDVO_CMD_STATUS_SUCCESS)
1698                 return false;
1699         return true;
1700 }
1701
1702 static struct intel_output *
1703 intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan)
1704 {
1705         struct drm_device *dev = chan->drm_dev;
1706         struct drm_connector *connector;
1707         struct intel_output *intel_output = NULL;
1708
1709         list_for_each_entry(connector,
1710                         &dev->mode_config.connector_list, head) {
1711                 if (to_intel_output(connector)->ddc_bus == chan) {
1712                         intel_output = to_intel_output(connector);
1713                         break;
1714                 }
1715         }
1716         return intel_output;
1717 }
1718
1719 static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
1720                                   struct i2c_msg msgs[], int num)
1721 {
1722         struct intel_output *intel_output;
1723         struct intel_sdvo_priv *sdvo_priv;
1724         struct i2c_algo_bit_data *algo_data;
1725         struct i2c_algorithm *algo;
1726
1727         algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
1728         intel_output =
1729                 intel_sdvo_chan_to_intel_output(
1730                                 (struct intel_i2c_chan *)(algo_data->data));
1731         if (intel_output == NULL)
1732                 return -EINVAL;
1733
1734         sdvo_priv = intel_output->dev_priv;
1735         algo = (struct i2c_algorithm *)intel_output->i2c_bus->adapter.algo;
1736
1737         intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
1738         return algo->master_xfer(i2c_adap, msgs, num);
1739 }
1740
1741 static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
1742         .master_xfer    = intel_sdvo_master_xfer,
1743 };
1744
1745 bool intel_sdvo_init(struct drm_device *dev, int output_device)
1746 {
1747         struct drm_connector *connector;
1748         struct intel_output *intel_output;
1749         struct intel_sdvo_priv *sdvo_priv;
1750         struct intel_i2c_chan *i2cbus = NULL;
1751         struct intel_i2c_chan *ddcbus = NULL;
1752         int connector_type;
1753         u8 ch[0x40];
1754         int i;
1755         int encoder_type, output_id;
1756
1757         intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
1758         if (!intel_output) {
1759                 return false;
1760         }
1761
1762         sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
1763         intel_output->type = INTEL_OUTPUT_SDVO;
1764
1765         /* setup the DDC bus. */
1766         if (output_device == SDVOB)
1767                 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
1768         else
1769                 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
1770
1771         if (!i2cbus)
1772                 goto err_inteloutput;
1773
1774         sdvo_priv->i2c_bus = i2cbus;
1775
1776         if (output_device == SDVOB) {
1777                 output_id = 1;
1778                 sdvo_priv->i2c_bus->slave_addr = 0x38;
1779         } else {
1780                 output_id = 2;
1781                 sdvo_priv->i2c_bus->slave_addr = 0x39;
1782         }
1783
1784         sdvo_priv->output_device = output_device;
1785         intel_output->i2c_bus = i2cbus;
1786         intel_output->dev_priv = sdvo_priv;
1787
1788         /* Read the regs to test if we can talk to the device */
1789         for (i = 0; i < 0x40; i++) {
1790                 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
1791                         DRM_DEBUG("No SDVO device found on SDVO%c\n",
1792                                   output_device == SDVOB ? 'B' : 'C');
1793                         goto err_i2c;
1794                 }
1795         }
1796
1797         /* setup the DDC bus. */
1798         if (output_device == SDVOB)
1799                 ddcbus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
1800         else
1801                 ddcbus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
1802
1803         if (ddcbus == NULL)
1804                 goto err_i2c;
1805
1806         intel_sdvo_i2c_bit_algo.functionality =
1807                 intel_output->i2c_bus->adapter.algo->functionality;
1808         ddcbus->adapter.algo = &intel_sdvo_i2c_bit_algo;
1809         intel_output->ddc_bus = ddcbus;
1810
1811         /* In defaut case sdvo lvds is false */
1812         sdvo_priv->is_lvds = false;
1813         intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
1814
1815         if (sdvo_priv->caps.output_flags &
1816             (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1817                 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
1818                         sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
1819                 else
1820                         sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
1821
1822                 encoder_type = DRM_MODE_ENCODER_TMDS;
1823                 connector_type = DRM_MODE_CONNECTOR_DVID;
1824
1825                 if (intel_sdvo_get_supp_encode(intel_output,
1826                                                &sdvo_priv->encode) &&
1827                     intel_sdvo_get_digital_encoding_mode(intel_output) &&
1828                     sdvo_priv->is_hdmi) {
1829                         /* enable hdmi encoding mode if supported */
1830                         intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
1831                         intel_sdvo_set_colorimetry(intel_output,
1832                                                    SDVO_COLORIMETRY_RGB256);
1833                         connector_type = DRM_MODE_CONNECTOR_HDMIA;
1834                 }
1835         }
1836         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_SVID0)
1837         {
1838                 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
1839                 encoder_type = DRM_MODE_ENCODER_TVDAC;
1840                 connector_type = DRM_MODE_CONNECTOR_SVIDEO;
1841                 sdvo_priv->is_tv = true;
1842                 intel_output->needs_tv_clock = true;
1843         }
1844         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0)
1845         {
1846                 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
1847                 encoder_type = DRM_MODE_ENCODER_DAC;
1848                 connector_type = DRM_MODE_CONNECTOR_VGA;
1849         }
1850         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1)
1851         {
1852                 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
1853                 encoder_type = DRM_MODE_ENCODER_DAC;
1854                 connector_type = DRM_MODE_CONNECTOR_VGA;
1855         }
1856         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS0)
1857         {
1858                 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
1859                 encoder_type = DRM_MODE_ENCODER_LVDS;
1860                 connector_type = DRM_MODE_CONNECTOR_LVDS;
1861                 sdvo_priv->is_lvds = true;
1862         }
1863         else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS1)
1864         {
1865                 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
1866                 encoder_type = DRM_MODE_ENCODER_LVDS;
1867                 connector_type = DRM_MODE_CONNECTOR_LVDS;
1868                 sdvo_priv->is_lvds = true;
1869         }
1870         else
1871         {
1872                 unsigned char bytes[2];
1873
1874                 sdvo_priv->controlled_output = 0;
1875                 memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
1876                 DRM_DEBUG("%s: Unknown SDVO output type (0x%02x%02x)\n",
1877                           SDVO_NAME(sdvo_priv),
1878                           bytes[0], bytes[1]);
1879                 encoder_type = DRM_MODE_ENCODER_NONE;
1880                 connector_type = DRM_MODE_CONNECTOR_Unknown;
1881                 goto err_i2c;
1882         }
1883
1884         connector = &intel_output->base;
1885         drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
1886                            connector_type);
1887         drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
1888         connector->interlace_allowed = 0;
1889         connector->doublescan_allowed = 0;
1890         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1891
1892         drm_encoder_init(dev, &intel_output->enc, &intel_sdvo_enc_funcs, encoder_type);
1893         drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
1894
1895         drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
1896         drm_sysfs_connector_add(connector);
1897
1898         intel_sdvo_select_ddc_bus(sdvo_priv);
1899
1900         /* Set the input timing to the screen. Assume always input 0. */
1901         intel_sdvo_set_target_input(intel_output, true, false);
1902
1903         intel_sdvo_get_input_pixel_clock_range(intel_output,
1904                                                &sdvo_priv->pixel_clock_min,
1905                                                &sdvo_priv->pixel_clock_max);
1906
1907
1908         DRM_DEBUG("%s device VID/DID: %02X:%02X.%02X, "
1909                   "clock range %dMHz - %dMHz, "
1910                   "input 1: %c, input 2: %c, "
1911                   "output 1: %c, output 2: %c\n",
1912                   SDVO_NAME(sdvo_priv),
1913                   sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
1914                   sdvo_priv->caps.device_rev_id,
1915                   sdvo_priv->pixel_clock_min / 1000,
1916                   sdvo_priv->pixel_clock_max / 1000,
1917                   (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
1918                   (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
1919                   /* check currently supported outputs */
1920                   sdvo_priv->caps.output_flags &
1921                         (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
1922                   sdvo_priv->caps.output_flags &
1923                         (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
1924
1925         return true;
1926
1927 err_i2c:
1928         if (ddcbus != NULL)
1929                 intel_i2c_destroy(intel_output->ddc_bus);
1930         intel_i2c_destroy(intel_output->i2c_bus);
1931 err_inteloutput:
1932         kfree(intel_output);
1933
1934         return false;
1935 }