Merge branch 'drm-for-2.6.35' of git://git.kernel.org/pub/scm/linux/kernel/git/airlie...
[linux-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include "drmP.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "drm_dp_helper.h"
37
38 #include "drm_crtc_helper.h"
39
40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
41
42 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
43 static void intel_update_watermarks(struct drm_device *dev);
44 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
45
46 typedef struct {
47     /* given values */
48     int n;
49     int m1, m2;
50     int p1, p2;
51     /* derived values */
52     int dot;
53     int vco;
54     int m;
55     int p;
56 } intel_clock_t;
57
58 typedef struct {
59     int min, max;
60 } intel_range_t;
61
62 typedef struct {
63     int dot_limit;
64     int p2_slow, p2_fast;
65 } intel_p2_t;
66
67 #define INTEL_P2_NUM                  2
68 typedef struct intel_limit intel_limit_t;
69 struct intel_limit {
70     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
71     intel_p2_t      p2;
72     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
73                       int, int, intel_clock_t *);
74 };
75
76 #define I8XX_DOT_MIN              25000
77 #define I8XX_DOT_MAX             350000
78 #define I8XX_VCO_MIN             930000
79 #define I8XX_VCO_MAX            1400000
80 #define I8XX_N_MIN                    3
81 #define I8XX_N_MAX                   16
82 #define I8XX_M_MIN                   96
83 #define I8XX_M_MAX                  140
84 #define I8XX_M1_MIN                  18
85 #define I8XX_M1_MAX                  26
86 #define I8XX_M2_MIN                   6
87 #define I8XX_M2_MAX                  16
88 #define I8XX_P_MIN                    4
89 #define I8XX_P_MAX                  128
90 #define I8XX_P1_MIN                   2
91 #define I8XX_P1_MAX                  33
92 #define I8XX_P1_LVDS_MIN              1
93 #define I8XX_P1_LVDS_MAX              6
94 #define I8XX_P2_SLOW                  4
95 #define I8XX_P2_FAST                  2
96 #define I8XX_P2_LVDS_SLOW             14
97 #define I8XX_P2_LVDS_FAST             7
98 #define I8XX_P2_SLOW_LIMIT       165000
99
100 #define I9XX_DOT_MIN              20000
101 #define I9XX_DOT_MAX             400000
102 #define I9XX_VCO_MIN            1400000
103 #define I9XX_VCO_MAX            2800000
104 #define PINEVIEW_VCO_MIN                1700000
105 #define PINEVIEW_VCO_MAX                3500000
106 #define I9XX_N_MIN                    1
107 #define I9XX_N_MAX                    6
108 /* Pineview's Ncounter is a ring counter */
109 #define PINEVIEW_N_MIN                3
110 #define PINEVIEW_N_MAX                6
111 #define I9XX_M_MIN                   70
112 #define I9XX_M_MAX                  120
113 #define PINEVIEW_M_MIN                2
114 #define PINEVIEW_M_MAX              256
115 #define I9XX_M1_MIN                  10
116 #define I9XX_M1_MAX                  22
117 #define I9XX_M2_MIN                   5
118 #define I9XX_M2_MAX                   9
119 /* Pineview M1 is reserved, and must be 0 */
120 #define PINEVIEW_M1_MIN               0
121 #define PINEVIEW_M1_MAX               0
122 #define PINEVIEW_M2_MIN               0
123 #define PINEVIEW_M2_MAX               254
124 #define I9XX_P_SDVO_DAC_MIN           5
125 #define I9XX_P_SDVO_DAC_MAX          80
126 #define I9XX_P_LVDS_MIN               7
127 #define I9XX_P_LVDS_MAX              98
128 #define PINEVIEW_P_LVDS_MIN                   7
129 #define PINEVIEW_P_LVDS_MAX                  112
130 #define I9XX_P1_MIN                   1
131 #define I9XX_P1_MAX                   8
132 #define I9XX_P2_SDVO_DAC_SLOW                10
133 #define I9XX_P2_SDVO_DAC_FAST                 5
134 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
135 #define I9XX_P2_LVDS_SLOW                    14
136 #define I9XX_P2_LVDS_FAST                     7
137 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
138
139 /*The parameter is for SDVO on G4x platform*/
140 #define G4X_DOT_SDVO_MIN           25000
141 #define G4X_DOT_SDVO_MAX           270000
142 #define G4X_VCO_MIN                1750000
143 #define G4X_VCO_MAX                3500000
144 #define G4X_N_SDVO_MIN             1
145 #define G4X_N_SDVO_MAX             4
146 #define G4X_M_SDVO_MIN             104
147 #define G4X_M_SDVO_MAX             138
148 #define G4X_M1_SDVO_MIN            17
149 #define G4X_M1_SDVO_MAX            23
150 #define G4X_M2_SDVO_MIN            5
151 #define G4X_M2_SDVO_MAX            11
152 #define G4X_P_SDVO_MIN             10
153 #define G4X_P_SDVO_MAX             30
154 #define G4X_P1_SDVO_MIN            1
155 #define G4X_P1_SDVO_MAX            3
156 #define G4X_P2_SDVO_SLOW           10
157 #define G4X_P2_SDVO_FAST           10
158 #define G4X_P2_SDVO_LIMIT          270000
159
160 /*The parameter is for HDMI_DAC on G4x platform*/
161 #define G4X_DOT_HDMI_DAC_MIN           22000
162 #define G4X_DOT_HDMI_DAC_MAX           400000
163 #define G4X_N_HDMI_DAC_MIN             1
164 #define G4X_N_HDMI_DAC_MAX             4
165 #define G4X_M_HDMI_DAC_MIN             104
166 #define G4X_M_HDMI_DAC_MAX             138
167 #define G4X_M1_HDMI_DAC_MIN            16
168 #define G4X_M1_HDMI_DAC_MAX            23
169 #define G4X_M2_HDMI_DAC_MIN            5
170 #define G4X_M2_HDMI_DAC_MAX            11
171 #define G4X_P_HDMI_DAC_MIN             5
172 #define G4X_P_HDMI_DAC_MAX             80
173 #define G4X_P1_HDMI_DAC_MIN            1
174 #define G4X_P1_HDMI_DAC_MAX            8
175 #define G4X_P2_HDMI_DAC_SLOW           10
176 #define G4X_P2_HDMI_DAC_FAST           5
177 #define G4X_P2_HDMI_DAC_LIMIT          165000
178
179 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
197
198 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
201 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
202 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
203 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
204 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
209 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
210 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
213 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
216
217 /*The parameter is for DISPLAY PORT on G4x platform*/
218 #define G4X_DOT_DISPLAY_PORT_MIN           161670
219 #define G4X_DOT_DISPLAY_PORT_MAX           227000
220 #define G4X_N_DISPLAY_PORT_MIN             1
221 #define G4X_N_DISPLAY_PORT_MAX             2
222 #define G4X_M_DISPLAY_PORT_MIN             97
223 #define G4X_M_DISPLAY_PORT_MAX             108
224 #define G4X_M1_DISPLAY_PORT_MIN            0x10
225 #define G4X_M1_DISPLAY_PORT_MAX            0x12
226 #define G4X_M2_DISPLAY_PORT_MIN            0x05
227 #define G4X_M2_DISPLAY_PORT_MAX            0x06
228 #define G4X_P_DISPLAY_PORT_MIN             10
229 #define G4X_P_DISPLAY_PORT_MAX             20
230 #define G4X_P1_DISPLAY_PORT_MIN            1
231 #define G4X_P1_DISPLAY_PORT_MAX            2
232 #define G4X_P2_DISPLAY_PORT_SLOW           10
233 #define G4X_P2_DISPLAY_PORT_FAST           10
234 #define G4X_P2_DISPLAY_PORT_LIMIT          0
235
236 /* Ironlake / Sandybridge */
237 /* as we calculate clock using (register_value + 2) for
238    N/M1/M2, so here the range value for them is (actual_value-2).
239  */
240 #define IRONLAKE_DOT_MIN         25000
241 #define IRONLAKE_DOT_MAX         350000
242 #define IRONLAKE_VCO_MIN         1760000
243 #define IRONLAKE_VCO_MAX         3510000
244 #define IRONLAKE_M1_MIN          12
245 #define IRONLAKE_M1_MAX          22
246 #define IRONLAKE_M2_MIN          5
247 #define IRONLAKE_M2_MAX          9
248 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
249
250 /* We have parameter ranges for different type of outputs. */
251
252 /* DAC & HDMI Refclk 120Mhz */
253 #define IRONLAKE_DAC_N_MIN      1
254 #define IRONLAKE_DAC_N_MAX      5
255 #define IRONLAKE_DAC_M_MIN      79
256 #define IRONLAKE_DAC_M_MAX      127
257 #define IRONLAKE_DAC_P_MIN      5
258 #define IRONLAKE_DAC_P_MAX      80
259 #define IRONLAKE_DAC_P1_MIN     1
260 #define IRONLAKE_DAC_P1_MAX     8
261 #define IRONLAKE_DAC_P2_SLOW    10
262 #define IRONLAKE_DAC_P2_FAST    5
263
264 /* LVDS single-channel 120Mhz refclk */
265 #define IRONLAKE_LVDS_S_N_MIN   1
266 #define IRONLAKE_LVDS_S_N_MAX   3
267 #define IRONLAKE_LVDS_S_M_MIN   79
268 #define IRONLAKE_LVDS_S_M_MAX   118
269 #define IRONLAKE_LVDS_S_P_MIN   28
270 #define IRONLAKE_LVDS_S_P_MAX   112
271 #define IRONLAKE_LVDS_S_P1_MIN  2
272 #define IRONLAKE_LVDS_S_P1_MAX  8
273 #define IRONLAKE_LVDS_S_P2_SLOW 14
274 #define IRONLAKE_LVDS_S_P2_FAST 14
275
276 /* LVDS dual-channel 120Mhz refclk */
277 #define IRONLAKE_LVDS_D_N_MIN   1
278 #define IRONLAKE_LVDS_D_N_MAX   3
279 #define IRONLAKE_LVDS_D_M_MIN   79
280 #define IRONLAKE_LVDS_D_M_MAX   127
281 #define IRONLAKE_LVDS_D_P_MIN   14
282 #define IRONLAKE_LVDS_D_P_MAX   56
283 #define IRONLAKE_LVDS_D_P1_MIN  2
284 #define IRONLAKE_LVDS_D_P1_MAX  8
285 #define IRONLAKE_LVDS_D_P2_SLOW 7
286 #define IRONLAKE_LVDS_D_P2_FAST 7
287
288 /* LVDS single-channel 100Mhz refclk */
289 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
290 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
291 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
292 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
293 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
294 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
295 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
296 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
297 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
298 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
299
300 /* LVDS dual-channel 100Mhz refclk */
301 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
302 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
303 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
304 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
305 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
306 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
307 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
308 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
309 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
310 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
311
312 /* DisplayPort */
313 #define IRONLAKE_DP_N_MIN               1
314 #define IRONLAKE_DP_N_MAX               2
315 #define IRONLAKE_DP_M_MIN               81
316 #define IRONLAKE_DP_M_MAX               90
317 #define IRONLAKE_DP_P_MIN               10
318 #define IRONLAKE_DP_P_MAX               20
319 #define IRONLAKE_DP_P2_FAST             10
320 #define IRONLAKE_DP_P2_SLOW             10
321 #define IRONLAKE_DP_P2_LIMIT            0
322 #define IRONLAKE_DP_P1_MIN              1
323 #define IRONLAKE_DP_P1_MAX              2
324
325 static bool
326 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
327                     int target, int refclk, intel_clock_t *best_clock);
328 static bool
329 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
330                         int target, int refclk, intel_clock_t *best_clock);
331
332 static bool
333 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
334                       int target, int refclk, intel_clock_t *best_clock);
335 static bool
336 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
337                            int target, int refclk, intel_clock_t *best_clock);
338
339 static const intel_limit_t intel_limits_i8xx_dvo = {
340         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
341         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
342         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
343         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
344         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
345         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
346         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
347         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
348         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
349                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
350         .find_pll = intel_find_best_PLL,
351 };
352
353 static const intel_limit_t intel_limits_i8xx_lvds = {
354         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
355         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
356         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
357         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
358         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
359         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
360         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
361         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
362         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
363                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
364         .find_pll = intel_find_best_PLL,
365 };
366         
367 static const intel_limit_t intel_limits_i9xx_sdvo = {
368         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
369         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
370         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
371         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
372         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
373         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
374         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
375         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
376         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
377                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
378         .find_pll = intel_find_best_PLL,
379 };
380
381 static const intel_limit_t intel_limits_i9xx_lvds = {
382         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
383         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
384         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
385         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
386         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
387         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
388         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
389         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
390         /* The single-channel range is 25-112Mhz, and dual-channel
391          * is 80-224Mhz.  Prefer single channel as much as possible.
392          */
393         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
394                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
395         .find_pll = intel_find_best_PLL,
396 };
397
398     /* below parameter and function is for G4X Chipset Family*/
399 static const intel_limit_t intel_limits_g4x_sdvo = {
400         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
401         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
402         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
403         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
404         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
405         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
406         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
407         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
408         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
409                  .p2_slow = G4X_P2_SDVO_SLOW,
410                  .p2_fast = G4X_P2_SDVO_FAST
411         },
412         .find_pll = intel_g4x_find_best_PLL,
413 };
414
415 static const intel_limit_t intel_limits_g4x_hdmi = {
416         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
418         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
419         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
420         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
421         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
422         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
423         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
424         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
425                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
426                  .p2_fast = G4X_P2_HDMI_DAC_FAST
427         },
428         .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
432         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
433                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
434         .vco = { .min = G4X_VCO_MIN,
435                  .max = G4X_VCO_MAX },
436         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
437                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
438         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
439                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
440         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
441                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
442         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
443                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
444         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
445                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
446         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
447                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
448         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
449                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
450                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
451         },
452         .find_pll = intel_g4x_find_best_PLL,
453 };
454
455 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
456         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
457                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
458         .vco = { .min = G4X_VCO_MIN,
459                  .max = G4X_VCO_MAX },
460         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
461                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
462         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
463                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
464         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
465                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
466         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
467                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
468         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
469                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
470         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
471                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
472         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
473                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
474                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
475         },
476         .find_pll = intel_g4x_find_best_PLL,
477 };
478
479 static const intel_limit_t intel_limits_g4x_display_port = {
480         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
481                  .max = G4X_DOT_DISPLAY_PORT_MAX },
482         .vco = { .min = G4X_VCO_MIN,
483                  .max = G4X_VCO_MAX},
484         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
485                  .max = G4X_N_DISPLAY_PORT_MAX },
486         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
487                  .max = G4X_M_DISPLAY_PORT_MAX },
488         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
489                  .max = G4X_M1_DISPLAY_PORT_MAX },
490         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
491                  .max = G4X_M2_DISPLAY_PORT_MAX },
492         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
493                  .max = G4X_P_DISPLAY_PORT_MAX },
494         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
495                  .max = G4X_P1_DISPLAY_PORT_MAX},
496         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
497                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
498                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
499         .find_pll = intel_find_pll_g4x_dp,
500 };
501
502 static const intel_limit_t intel_limits_pineview_sdvo = {
503         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
504         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
505         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
506         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
507         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
508         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
509         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
510         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
511         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
512                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
513         .find_pll = intel_find_best_PLL,
514 };
515
516 static const intel_limit_t intel_limits_pineview_lvds = {
517         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
518         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
519         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
520         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
521         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
522         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
523         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
524         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
525         /* Pineview only supports single-channel mode. */
526         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
527                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
528         .find_pll = intel_find_best_PLL,
529 };
530
531 static const intel_limit_t intel_limits_ironlake_dac = {
532         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
533         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
534         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
535         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
536         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
537         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
538         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
539         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
540         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
541                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
542                  .p2_fast = IRONLAKE_DAC_P2_FAST },
543         .find_pll = intel_g4x_find_best_PLL,
544 };
545
546 static const intel_limit_t intel_limits_ironlake_single_lvds = {
547         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
548         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
549         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
550         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
551         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
552         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
553         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
554         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
555         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
556                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
557                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
558         .find_pll = intel_g4x_find_best_PLL,
559 };
560
561 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
562         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
563         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
564         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
565         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
566         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
567         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
568         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
569         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
570         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
571                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
572                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
573         .find_pll = intel_g4x_find_best_PLL,
574 };
575
576 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
577         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
578         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
579         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
580         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
581         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
582         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
583         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
584         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
585         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
586                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
587                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
588         .find_pll = intel_g4x_find_best_PLL,
589 };
590
591 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
592         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
593         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
594         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
595         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
596         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
597         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
598         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
599         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
600         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
601                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
602                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
603         .find_pll = intel_g4x_find_best_PLL,
604 };
605
606 static const intel_limit_t intel_limits_ironlake_display_port = {
607         .dot = { .min = IRONLAKE_DOT_MIN,
608                  .max = IRONLAKE_DOT_MAX },
609         .vco = { .min = IRONLAKE_VCO_MIN,
610                  .max = IRONLAKE_VCO_MAX},
611         .n   = { .min = IRONLAKE_DP_N_MIN,
612                  .max = IRONLAKE_DP_N_MAX },
613         .m   = { .min = IRONLAKE_DP_M_MIN,
614                  .max = IRONLAKE_DP_M_MAX },
615         .m1  = { .min = IRONLAKE_M1_MIN,
616                  .max = IRONLAKE_M1_MAX },
617         .m2  = { .min = IRONLAKE_M2_MIN,
618                  .max = IRONLAKE_M2_MAX },
619         .p   = { .min = IRONLAKE_DP_P_MIN,
620                  .max = IRONLAKE_DP_P_MAX },
621         .p1  = { .min = IRONLAKE_DP_P1_MIN,
622                  .max = IRONLAKE_DP_P1_MAX},
623         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
624                  .p2_slow = IRONLAKE_DP_P2_SLOW,
625                  .p2_fast = IRONLAKE_DP_P2_FAST },
626         .find_pll = intel_find_pll_ironlake_dp,
627 };
628
629 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
630 {
631         struct drm_device *dev = crtc->dev;
632         struct drm_i915_private *dev_priv = dev->dev_private;
633         const intel_limit_t *limit;
634         int refclk = 120;
635
636         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
637                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
638                         refclk = 100;
639
640                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
641                     LVDS_CLKB_POWER_UP) {
642                         /* LVDS dual channel */
643                         if (refclk == 100)
644                                 limit = &intel_limits_ironlake_dual_lvds_100m;
645                         else
646                                 limit = &intel_limits_ironlake_dual_lvds;
647                 } else {
648                         if (refclk == 100)
649                                 limit = &intel_limits_ironlake_single_lvds_100m;
650                         else
651                                 limit = &intel_limits_ironlake_single_lvds;
652                 }
653         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
654                         HAS_eDP)
655                 limit = &intel_limits_ironlake_display_port;
656         else
657                 limit = &intel_limits_ironlake_dac;
658
659         return limit;
660 }
661
662 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
663 {
664         struct drm_device *dev = crtc->dev;
665         struct drm_i915_private *dev_priv = dev->dev_private;
666         const intel_limit_t *limit;
667
668         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
669                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
670                     LVDS_CLKB_POWER_UP)
671                         /* LVDS with dual channel */
672                         limit = &intel_limits_g4x_dual_channel_lvds;
673                 else
674                         /* LVDS with dual channel */
675                         limit = &intel_limits_g4x_single_channel_lvds;
676         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
677                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
678                 limit = &intel_limits_g4x_hdmi;
679         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
680                 limit = &intel_limits_g4x_sdvo;
681         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
682                 limit = &intel_limits_g4x_display_port;
683         } else /* The option is for other outputs */
684                 limit = &intel_limits_i9xx_sdvo;
685
686         return limit;
687 }
688
689 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
690 {
691         struct drm_device *dev = crtc->dev;
692         const intel_limit_t *limit;
693
694         if (HAS_PCH_SPLIT(dev))
695                 limit = intel_ironlake_limit(crtc);
696         else if (IS_G4X(dev)) {
697                 limit = intel_g4x_limit(crtc);
698         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
699                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
700                         limit = &intel_limits_i9xx_lvds;
701                 else
702                         limit = &intel_limits_i9xx_sdvo;
703         } else if (IS_PINEVIEW(dev)) {
704                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
705                         limit = &intel_limits_pineview_lvds;
706                 else
707                         limit = &intel_limits_pineview_sdvo;
708         } else {
709                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
710                         limit = &intel_limits_i8xx_lvds;
711                 else
712                         limit = &intel_limits_i8xx_dvo;
713         }
714         return limit;
715 }
716
717 /* m1 is reserved as 0 in Pineview, n is a ring counter */
718 static void pineview_clock(int refclk, intel_clock_t *clock)
719 {
720         clock->m = clock->m2 + 2;
721         clock->p = clock->p1 * clock->p2;
722         clock->vco = refclk * clock->m / clock->n;
723         clock->dot = clock->vco / clock->p;
724 }
725
726 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
727 {
728         if (IS_PINEVIEW(dev)) {
729                 pineview_clock(refclk, clock);
730                 return;
731         }
732         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
733         clock->p = clock->p1 * clock->p2;
734         clock->vco = refclk * clock->m / (clock->n + 2);
735         clock->dot = clock->vco / clock->p;
736 }
737
738 /**
739  * Returns whether any output on the specified pipe is of the specified type
740  */
741 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
742 {
743     struct drm_device *dev = crtc->dev;
744     struct drm_mode_config *mode_config = &dev->mode_config;
745     struct drm_encoder *l_entry;
746
747     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
748             if (l_entry && l_entry->crtc == crtc) {
749                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
750                     if (intel_encoder->type == type)
751                             return true;
752             }
753     }
754     return false;
755 }
756
757 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
758 /**
759  * Returns whether the given set of divisors are valid for a given refclk with
760  * the given connectors.
761  */
762
763 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
764 {
765         const intel_limit_t *limit = intel_limit (crtc);
766         struct drm_device *dev = crtc->dev;
767
768         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
769                 INTELPllInvalid ("p1 out of range\n");
770         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
771                 INTELPllInvalid ("p out of range\n");
772         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
773                 INTELPllInvalid ("m2 out of range\n");
774         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
775                 INTELPllInvalid ("m1 out of range\n");
776         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
777                 INTELPllInvalid ("m1 <= m2\n");
778         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
779                 INTELPllInvalid ("m out of range\n");
780         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
781                 INTELPllInvalid ("n out of range\n");
782         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
783                 INTELPllInvalid ("vco out of range\n");
784         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
785          * connector, etc., rather than just a single range.
786          */
787         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
788                 INTELPllInvalid ("dot out of range\n");
789
790         return true;
791 }
792
793 static bool
794 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
795                     int target, int refclk, intel_clock_t *best_clock)
796
797 {
798         struct drm_device *dev = crtc->dev;
799         struct drm_i915_private *dev_priv = dev->dev_private;
800         intel_clock_t clock;
801         int err = target;
802
803         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
804             (I915_READ(LVDS)) != 0) {
805                 /*
806                  * For LVDS, if the panel is on, just rely on its current
807                  * settings for dual-channel.  We haven't figured out how to
808                  * reliably set up different single/dual channel state, if we
809                  * even can.
810                  */
811                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
812                     LVDS_CLKB_POWER_UP)
813                         clock.p2 = limit->p2.p2_fast;
814                 else
815                         clock.p2 = limit->p2.p2_slow;
816         } else {
817                 if (target < limit->p2.dot_limit)
818                         clock.p2 = limit->p2.p2_slow;
819                 else
820                         clock.p2 = limit->p2.p2_fast;
821         }
822
823         memset (best_clock, 0, sizeof (*best_clock));
824
825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826              clock.m1++) {
827                 for (clock.m2 = limit->m2.min;
828                      clock.m2 <= limit->m2.max; clock.m2++) {
829                         /* m1 is always 0 in Pineview */
830                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
831                                 break;
832                         for (clock.n = limit->n.min;
833                              clock.n <= limit->n.max; clock.n++) {
834                                 for (clock.p1 = limit->p1.min;
835                                         clock.p1 <= limit->p1.max; clock.p1++) {
836                                         int this_err;
837
838                                         intel_clock(dev, refclk, &clock);
839
840                                         if (!intel_PLL_is_valid(crtc, &clock))
841                                                 continue;
842
843                                         this_err = abs(clock.dot - target);
844                                         if (this_err < err) {
845                                                 *best_clock = clock;
846                                                 err = this_err;
847                                         }
848                                 }
849                         }
850                 }
851         }
852
853         return (err != target);
854 }
855
856 static bool
857 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
858                         int target, int refclk, intel_clock_t *best_clock)
859 {
860         struct drm_device *dev = crtc->dev;
861         struct drm_i915_private *dev_priv = dev->dev_private;
862         intel_clock_t clock;
863         int max_n;
864         bool found;
865         /* approximately equals target * 0.00488 */
866         int err_most = (target >> 8) + (target >> 10);
867         found = false;
868
869         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
870                 int lvds_reg;
871
872                 if (HAS_PCH_SPLIT(dev))
873                         lvds_reg = PCH_LVDS;
874                 else
875                         lvds_reg = LVDS;
876                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
877                     LVDS_CLKB_POWER_UP)
878                         clock.p2 = limit->p2.p2_fast;
879                 else
880                         clock.p2 = limit->p2.p2_slow;
881         } else {
882                 if (target < limit->p2.dot_limit)
883                         clock.p2 = limit->p2.p2_slow;
884                 else
885                         clock.p2 = limit->p2.p2_fast;
886         }
887
888         memset(best_clock, 0, sizeof(*best_clock));
889         max_n = limit->n.max;
890         /* based on hardware requirement, prefer smaller n to precision */
891         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
892                 /* based on hardware requirement, prefere larger m1,m2 */
893                 for (clock.m1 = limit->m1.max;
894                      clock.m1 >= limit->m1.min; clock.m1--) {
895                         for (clock.m2 = limit->m2.max;
896                              clock.m2 >= limit->m2.min; clock.m2--) {
897                                 for (clock.p1 = limit->p1.max;
898                                      clock.p1 >= limit->p1.min; clock.p1--) {
899                                         int this_err;
900
901                                         intel_clock(dev, refclk, &clock);
902                                         if (!intel_PLL_is_valid(crtc, &clock))
903                                                 continue;
904                                         this_err = abs(clock.dot - target) ;
905                                         if (this_err < err_most) {
906                                                 *best_clock = clock;
907                                                 err_most = this_err;
908                                                 max_n = clock.n;
909                                                 found = true;
910                                         }
911                                 }
912                         }
913                 }
914         }
915         return found;
916 }
917
918 static bool
919 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
920                            int target, int refclk, intel_clock_t *best_clock)
921 {
922         struct drm_device *dev = crtc->dev;
923         intel_clock_t clock;
924
925         /* return directly when it is eDP */
926         if (HAS_eDP)
927                 return true;
928
929         if (target < 200000) {
930                 clock.n = 1;
931                 clock.p1 = 2;
932                 clock.p2 = 10;
933                 clock.m1 = 12;
934                 clock.m2 = 9;
935         } else {
936                 clock.n = 2;
937                 clock.p1 = 1;
938                 clock.p2 = 10;
939                 clock.m1 = 14;
940                 clock.m2 = 8;
941         }
942         intel_clock(dev, refclk, &clock);
943         memcpy(best_clock, &clock, sizeof(intel_clock_t));
944         return true;
945 }
946
947 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
948 static bool
949 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
950                       int target, int refclk, intel_clock_t *best_clock)
951 {
952     intel_clock_t clock;
953     if (target < 200000) {
954         clock.p1 = 2;
955         clock.p2 = 10;
956         clock.n = 2;
957         clock.m1 = 23;
958         clock.m2 = 8;
959     } else {
960         clock.p1 = 1;
961         clock.p2 = 10;
962         clock.n = 1;
963         clock.m1 = 14;
964         clock.m2 = 2;
965     }
966     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
967     clock.p = (clock.p1 * clock.p2);
968     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
969     clock.vco = 0;
970     memcpy(best_clock, &clock, sizeof(intel_clock_t));
971     return true;
972 }
973
974 void
975 intel_wait_for_vblank(struct drm_device *dev)
976 {
977         /* Wait for 20ms, i.e. one cycle at 50hz. */
978         msleep(20);
979 }
980
981 /* Parameters have changed, update FBC info */
982 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
983 {
984         struct drm_device *dev = crtc->dev;
985         struct drm_i915_private *dev_priv = dev->dev_private;
986         struct drm_framebuffer *fb = crtc->fb;
987         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
988         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
989         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
990         int plane, i;
991         u32 fbc_ctl, fbc_ctl2;
992
993         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
994
995         if (fb->pitch < dev_priv->cfb_pitch)
996                 dev_priv->cfb_pitch = fb->pitch;
997
998         /* FBC_CTL wants 64B units */
999         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1000         dev_priv->cfb_fence = obj_priv->fence_reg;
1001         dev_priv->cfb_plane = intel_crtc->plane;
1002         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1003
1004         /* Clear old tags */
1005         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1006                 I915_WRITE(FBC_TAG + (i * 4), 0);
1007
1008         /* Set it up... */
1009         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1010         if (obj_priv->tiling_mode != I915_TILING_NONE)
1011                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1012         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1013         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1014
1015         /* enable it... */
1016         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1017         if (IS_I945GM(dev))
1018                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1019         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1020         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1021         if (obj_priv->tiling_mode != I915_TILING_NONE)
1022                 fbc_ctl |= dev_priv->cfb_fence;
1023         I915_WRITE(FBC_CONTROL, fbc_ctl);
1024
1025         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1026                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1027 }
1028
1029 void i8xx_disable_fbc(struct drm_device *dev)
1030 {
1031         struct drm_i915_private *dev_priv = dev->dev_private;
1032         u32 fbc_ctl;
1033
1034         if (!I915_HAS_FBC(dev))
1035                 return;
1036
1037         /* Disable compression */
1038         fbc_ctl = I915_READ(FBC_CONTROL);
1039         fbc_ctl &= ~FBC_CTL_EN;
1040         I915_WRITE(FBC_CONTROL, fbc_ctl);
1041
1042         /* Wait for compressing bit to clear */
1043         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1044                 ; /* nothing */
1045
1046         intel_wait_for_vblank(dev);
1047
1048         DRM_DEBUG_KMS("disabled FBC\n");
1049 }
1050
1051 static bool i8xx_fbc_enabled(struct drm_device *dev)
1052 {
1053         struct drm_i915_private *dev_priv = dev->dev_private;
1054
1055         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1056 }
1057
1058 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1059 {
1060         struct drm_device *dev = crtc->dev;
1061         struct drm_i915_private *dev_priv = dev->dev_private;
1062         struct drm_framebuffer *fb = crtc->fb;
1063         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1064         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1066         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1067                      DPFC_CTL_PLANEB);
1068         unsigned long stall_watermark = 200;
1069         u32 dpfc_ctl;
1070
1071         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1072         dev_priv->cfb_fence = obj_priv->fence_reg;
1073         dev_priv->cfb_plane = intel_crtc->plane;
1074
1075         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1076         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1077                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1078                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1079         } else {
1080                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1081         }
1082
1083         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1084         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1085                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1086                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1087         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1088
1089         /* enable it... */
1090         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1091
1092         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1093 }
1094
1095 void g4x_disable_fbc(struct drm_device *dev)
1096 {
1097         struct drm_i915_private *dev_priv = dev->dev_private;
1098         u32 dpfc_ctl;
1099
1100         /* Disable compression */
1101         dpfc_ctl = I915_READ(DPFC_CONTROL);
1102         dpfc_ctl &= ~DPFC_CTL_EN;
1103         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1104         intel_wait_for_vblank(dev);
1105
1106         DRM_DEBUG_KMS("disabled FBC\n");
1107 }
1108
1109 static bool g4x_fbc_enabled(struct drm_device *dev)
1110 {
1111         struct drm_i915_private *dev_priv = dev->dev_private;
1112
1113         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1114 }
1115
1116 bool intel_fbc_enabled(struct drm_device *dev)
1117 {
1118         struct drm_i915_private *dev_priv = dev->dev_private;
1119
1120         if (!dev_priv->display.fbc_enabled)
1121                 return false;
1122
1123         return dev_priv->display.fbc_enabled(dev);
1124 }
1125
1126 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1127 {
1128         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1129
1130         if (!dev_priv->display.enable_fbc)
1131                 return;
1132
1133         dev_priv->display.enable_fbc(crtc, interval);
1134 }
1135
1136 void intel_disable_fbc(struct drm_device *dev)
1137 {
1138         struct drm_i915_private *dev_priv = dev->dev_private;
1139
1140         if (!dev_priv->display.disable_fbc)
1141                 return;
1142
1143         dev_priv->display.disable_fbc(dev);
1144 }
1145
1146 /**
1147  * intel_update_fbc - enable/disable FBC as needed
1148  * @crtc: CRTC to point the compressor at
1149  * @mode: mode in use
1150  *
1151  * Set up the framebuffer compression hardware at mode set time.  We
1152  * enable it if possible:
1153  *   - plane A only (on pre-965)
1154  *   - no pixel mulitply/line duplication
1155  *   - no alpha buffer discard
1156  *   - no dual wide
1157  *   - framebuffer <= 2048 in width, 1536 in height
1158  *
1159  * We can't assume that any compression will take place (worst case),
1160  * so the compressed buffer has to be the same size as the uncompressed
1161  * one.  It also must reside (along with the line length buffer) in
1162  * stolen memory.
1163  *
1164  * We need to enable/disable FBC on a global basis.
1165  */
1166 static void intel_update_fbc(struct drm_crtc *crtc,
1167                              struct drm_display_mode *mode)
1168 {
1169         struct drm_device *dev = crtc->dev;
1170         struct drm_i915_private *dev_priv = dev->dev_private;
1171         struct drm_framebuffer *fb = crtc->fb;
1172         struct intel_framebuffer *intel_fb;
1173         struct drm_i915_gem_object *obj_priv;
1174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1175         int plane = intel_crtc->plane;
1176
1177         if (!i915_powersave)
1178                 return;
1179
1180         if (!I915_HAS_FBC(dev))
1181                 return;
1182
1183         if (!crtc->fb)
1184                 return;
1185
1186         intel_fb = to_intel_framebuffer(fb);
1187         obj_priv = to_intel_bo(intel_fb->obj);
1188
1189         /*
1190          * If FBC is already on, we just have to verify that we can
1191          * keep it that way...
1192          * Need to disable if:
1193          *   - changing FBC params (stride, fence, mode)
1194          *   - new fb is too large to fit in compressed buffer
1195          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1196          */
1197         if (intel_fb->obj->size > dev_priv->cfb_size) {
1198                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1199                                 "compression\n");
1200                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1201                 goto out_disable;
1202         }
1203         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1204             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1205                 DRM_DEBUG_KMS("mode incompatible with compression, "
1206                                 "disabling\n");
1207                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1208                 goto out_disable;
1209         }
1210         if ((mode->hdisplay > 2048) ||
1211             (mode->vdisplay > 1536)) {
1212                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1213                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1214                 goto out_disable;
1215         }
1216         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1217                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1218                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1219                 goto out_disable;
1220         }
1221         if (obj_priv->tiling_mode != I915_TILING_X) {
1222                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1223                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1224                 goto out_disable;
1225         }
1226
1227         if (intel_fbc_enabled(dev)) {
1228                 /* We can re-enable it in this case, but need to update pitch */
1229                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1230                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1231                     (plane != dev_priv->cfb_plane))
1232                         intel_disable_fbc(dev);
1233         }
1234
1235         /* Now try to turn it back on if possible */
1236         if (!intel_fbc_enabled(dev))
1237                 intel_enable_fbc(crtc, 500);
1238
1239         return;
1240
1241 out_disable:
1242         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1243         /* Multiple disables should be harmless */
1244         if (intel_fbc_enabled(dev))
1245                 intel_disable_fbc(dev);
1246 }
1247
1248 static int
1249 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1250 {
1251         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1252         u32 alignment;
1253         int ret;
1254
1255         switch (obj_priv->tiling_mode) {
1256         case I915_TILING_NONE:
1257                 alignment = 64 * 1024;
1258                 break;
1259         case I915_TILING_X:
1260                 /* pin() will align the object as required by fence */
1261                 alignment = 0;
1262                 break;
1263         case I915_TILING_Y:
1264                 /* FIXME: Is this true? */
1265                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1266                 return -EINVAL;
1267         default:
1268                 BUG();
1269         }
1270
1271         ret = i915_gem_object_pin(obj, alignment);
1272         if (ret != 0)
1273                 return ret;
1274
1275         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1276          * fence, whereas 965+ only requires a fence if using
1277          * framebuffer compression.  For simplicity, we always install
1278          * a fence as the cost is not that onerous.
1279          */
1280         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1281             obj_priv->tiling_mode != I915_TILING_NONE) {
1282                 ret = i915_gem_object_get_fence_reg(obj);
1283                 if (ret != 0) {
1284                         i915_gem_object_unpin(obj);
1285                         return ret;
1286                 }
1287         }
1288
1289         return 0;
1290 }
1291
1292 static int
1293 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1294                     struct drm_framebuffer *old_fb)
1295 {
1296         struct drm_device *dev = crtc->dev;
1297         struct drm_i915_private *dev_priv = dev->dev_private;
1298         struct drm_i915_master_private *master_priv;
1299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1300         struct intel_framebuffer *intel_fb;
1301         struct drm_i915_gem_object *obj_priv;
1302         struct drm_gem_object *obj;
1303         int pipe = intel_crtc->pipe;
1304         int plane = intel_crtc->plane;
1305         unsigned long Start, Offset;
1306         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1307         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1308         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1309         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1310         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1311         u32 dspcntr;
1312         int ret;
1313
1314         /* no fb bound */
1315         if (!crtc->fb) {
1316                 DRM_DEBUG_KMS("No FB bound\n");
1317                 return 0;
1318         }
1319
1320         switch (plane) {
1321         case 0:
1322         case 1:
1323                 break;
1324         default:
1325                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1326                 return -EINVAL;
1327         }
1328
1329         intel_fb = to_intel_framebuffer(crtc->fb);
1330         obj = intel_fb->obj;
1331         obj_priv = to_intel_bo(obj);
1332
1333         mutex_lock(&dev->struct_mutex);
1334         ret = intel_pin_and_fence_fb_obj(dev, obj);
1335         if (ret != 0) {
1336                 mutex_unlock(&dev->struct_mutex);
1337                 return ret;
1338         }
1339
1340         ret = i915_gem_object_set_to_display_plane(obj);
1341         if (ret != 0) {
1342                 i915_gem_object_unpin(obj);
1343                 mutex_unlock(&dev->struct_mutex);
1344                 return ret;
1345         }
1346
1347         dspcntr = I915_READ(dspcntr_reg);
1348         /* Mask out pixel format bits in case we change it */
1349         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1350         switch (crtc->fb->bits_per_pixel) {
1351         case 8:
1352                 dspcntr |= DISPPLANE_8BPP;
1353                 break;
1354         case 16:
1355                 if (crtc->fb->depth == 15)
1356                         dspcntr |= DISPPLANE_15_16BPP;
1357                 else
1358                         dspcntr |= DISPPLANE_16BPP;
1359                 break;
1360         case 24:
1361         case 32:
1362                 if (crtc->fb->depth == 30)
1363                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1364                 else
1365                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1366                 break;
1367         default:
1368                 DRM_ERROR("Unknown color depth\n");
1369                 i915_gem_object_unpin(obj);
1370                 mutex_unlock(&dev->struct_mutex);
1371                 return -EINVAL;
1372         }
1373         if (IS_I965G(dev)) {
1374                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1375                         dspcntr |= DISPPLANE_TILED;
1376                 else
1377                         dspcntr &= ~DISPPLANE_TILED;
1378         }
1379
1380         if (HAS_PCH_SPLIT(dev))
1381                 /* must disable */
1382                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1383
1384         I915_WRITE(dspcntr_reg, dspcntr);
1385
1386         Start = obj_priv->gtt_offset;
1387         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1388
1389         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1390         I915_WRITE(dspstride, crtc->fb->pitch);
1391         if (IS_I965G(dev)) {
1392                 I915_WRITE(dspbase, Offset);
1393                 I915_READ(dspbase);
1394                 I915_WRITE(dspsurf, Start);
1395                 I915_READ(dspsurf);
1396                 I915_WRITE(dsptileoff, (y << 16) | x);
1397         } else {
1398                 I915_WRITE(dspbase, Start + Offset);
1399                 I915_READ(dspbase);
1400         }
1401
1402         if ((IS_I965G(dev) || plane == 0))
1403                 intel_update_fbc(crtc, &crtc->mode);
1404
1405         intel_wait_for_vblank(dev);
1406
1407         if (old_fb) {
1408                 intel_fb = to_intel_framebuffer(old_fb);
1409                 obj_priv = to_intel_bo(intel_fb->obj);
1410                 i915_gem_object_unpin(intel_fb->obj);
1411         }
1412         intel_increase_pllclock(crtc, true);
1413
1414         mutex_unlock(&dev->struct_mutex);
1415
1416         if (!dev->primary->master)
1417                 return 0;
1418
1419         master_priv = dev->primary->master->driver_priv;
1420         if (!master_priv->sarea_priv)
1421                 return 0;
1422
1423         if (pipe) {
1424                 master_priv->sarea_priv->pipeB_x = x;
1425                 master_priv->sarea_priv->pipeB_y = y;
1426         } else {
1427                 master_priv->sarea_priv->pipeA_x = x;
1428                 master_priv->sarea_priv->pipeA_y = y;
1429         }
1430
1431         return 0;
1432 }
1433
1434 /* Disable the VGA plane that we never use */
1435 static void i915_disable_vga (struct drm_device *dev)
1436 {
1437         struct drm_i915_private *dev_priv = dev->dev_private;
1438         u8 sr1;
1439         u32 vga_reg;
1440
1441         if (HAS_PCH_SPLIT(dev))
1442                 vga_reg = CPU_VGACNTRL;
1443         else
1444                 vga_reg = VGACNTRL;
1445
1446         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1447                 return;
1448
1449         I915_WRITE8(VGA_SR_INDEX, 1);
1450         sr1 = I915_READ8(VGA_SR_DATA);
1451         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1452         udelay(100);
1453
1454         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1455 }
1456
1457 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1458 {
1459         struct drm_device *dev = crtc->dev;
1460         struct drm_i915_private *dev_priv = dev->dev_private;
1461         u32 dpa_ctl;
1462
1463         DRM_DEBUG_KMS("\n");
1464         dpa_ctl = I915_READ(DP_A);
1465         dpa_ctl &= ~DP_PLL_ENABLE;
1466         I915_WRITE(DP_A, dpa_ctl);
1467 }
1468
1469 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1470 {
1471         struct drm_device *dev = crtc->dev;
1472         struct drm_i915_private *dev_priv = dev->dev_private;
1473         u32 dpa_ctl;
1474
1475         dpa_ctl = I915_READ(DP_A);
1476         dpa_ctl |= DP_PLL_ENABLE;
1477         I915_WRITE(DP_A, dpa_ctl);
1478         udelay(200);
1479 }
1480
1481
1482 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1483 {
1484         struct drm_device *dev = crtc->dev;
1485         struct drm_i915_private *dev_priv = dev->dev_private;
1486         u32 dpa_ctl;
1487
1488         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1489         dpa_ctl = I915_READ(DP_A);
1490         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1491
1492         if (clock < 200000) {
1493                 u32 temp;
1494                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1495                 /* workaround for 160Mhz:
1496                    1) program 0x4600c bits 15:0 = 0x8124
1497                    2) program 0x46010 bit 0 = 1
1498                    3) program 0x46034 bit 24 = 1
1499                    4) program 0x64000 bit 14 = 1
1500                    */
1501                 temp = I915_READ(0x4600c);
1502                 temp &= 0xffff0000;
1503                 I915_WRITE(0x4600c, temp | 0x8124);
1504
1505                 temp = I915_READ(0x46010);
1506                 I915_WRITE(0x46010, temp | 1);
1507
1508                 temp = I915_READ(0x46034);
1509                 I915_WRITE(0x46034, temp | (1 << 24));
1510         } else {
1511                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1512         }
1513         I915_WRITE(DP_A, dpa_ctl);
1514
1515         udelay(500);
1516 }
1517
1518 /* The FDI link training functions for ILK/Ibexpeak. */
1519 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1520 {
1521         struct drm_device *dev = crtc->dev;
1522         struct drm_i915_private *dev_priv = dev->dev_private;
1523         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1524         int pipe = intel_crtc->pipe;
1525         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1526         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1527         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1528         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1529         u32 temp, tries = 0;
1530
1531         /* enable CPU FDI TX and PCH FDI RX */
1532         temp = I915_READ(fdi_tx_reg);
1533         temp |= FDI_TX_ENABLE;
1534         temp &= ~(7 << 19);
1535         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1536         temp &= ~FDI_LINK_TRAIN_NONE;
1537         temp |= FDI_LINK_TRAIN_PATTERN_1;
1538         I915_WRITE(fdi_tx_reg, temp);
1539         I915_READ(fdi_tx_reg);
1540
1541         temp = I915_READ(fdi_rx_reg);
1542         temp &= ~FDI_LINK_TRAIN_NONE;
1543         temp |= FDI_LINK_TRAIN_PATTERN_1;
1544         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1545         I915_READ(fdi_rx_reg);
1546         udelay(150);
1547
1548         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1549            for train result */
1550         temp = I915_READ(fdi_rx_imr_reg);
1551         temp &= ~FDI_RX_SYMBOL_LOCK;
1552         temp &= ~FDI_RX_BIT_LOCK;
1553         I915_WRITE(fdi_rx_imr_reg, temp);
1554         I915_READ(fdi_rx_imr_reg);
1555         udelay(150);
1556
1557         for (;;) {
1558                 temp = I915_READ(fdi_rx_iir_reg);
1559                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1560
1561                 if ((temp & FDI_RX_BIT_LOCK)) {
1562                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1563                         I915_WRITE(fdi_rx_iir_reg,
1564                                    temp | FDI_RX_BIT_LOCK);
1565                         break;
1566                 }
1567
1568                 tries++;
1569
1570                 if (tries > 5) {
1571                         DRM_DEBUG_KMS("FDI train 1 fail!\n");
1572                         break;
1573                 }
1574         }
1575
1576         /* Train 2 */
1577         temp = I915_READ(fdi_tx_reg);
1578         temp &= ~FDI_LINK_TRAIN_NONE;
1579         temp |= FDI_LINK_TRAIN_PATTERN_2;
1580         I915_WRITE(fdi_tx_reg, temp);
1581
1582         temp = I915_READ(fdi_rx_reg);
1583         temp &= ~FDI_LINK_TRAIN_NONE;
1584         temp |= FDI_LINK_TRAIN_PATTERN_2;
1585         I915_WRITE(fdi_rx_reg, temp);
1586         udelay(150);
1587
1588         tries = 0;
1589
1590         for (;;) {
1591                 temp = I915_READ(fdi_rx_iir_reg);
1592                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1593
1594                 if (temp & FDI_RX_SYMBOL_LOCK) {
1595                         I915_WRITE(fdi_rx_iir_reg,
1596                                    temp | FDI_RX_SYMBOL_LOCK);
1597                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1598                         break;
1599                 }
1600
1601                 tries++;
1602
1603                 if (tries > 5) {
1604                         DRM_DEBUG_KMS("FDI train 2 fail!\n");
1605                         break;
1606                 }
1607         }
1608
1609         DRM_DEBUG_KMS("FDI train done\n");
1610 }
1611
1612 static int snb_b_fdi_train_param [] = {
1613         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1614         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1615         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1616         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1617 };
1618
1619 /* The FDI link training functions for SNB/Cougarpoint. */
1620 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1621 {
1622         struct drm_device *dev = crtc->dev;
1623         struct drm_i915_private *dev_priv = dev->dev_private;
1624         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1625         int pipe = intel_crtc->pipe;
1626         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1627         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1628         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1629         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1630         u32 temp, i;
1631
1632         /* enable CPU FDI TX and PCH FDI RX */
1633         temp = I915_READ(fdi_tx_reg);
1634         temp |= FDI_TX_ENABLE;
1635         temp &= ~(7 << 19);
1636         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1637         temp &= ~FDI_LINK_TRAIN_NONE;
1638         temp |= FDI_LINK_TRAIN_PATTERN_1;
1639         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1640         /* SNB-B */
1641         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1642         I915_WRITE(fdi_tx_reg, temp);
1643         I915_READ(fdi_tx_reg);
1644
1645         temp = I915_READ(fdi_rx_reg);
1646         if (HAS_PCH_CPT(dev)) {
1647                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1648                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1649         } else {
1650                 temp &= ~FDI_LINK_TRAIN_NONE;
1651                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1652         }
1653         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1654         I915_READ(fdi_rx_reg);
1655         udelay(150);
1656
1657         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1658            for train result */
1659         temp = I915_READ(fdi_rx_imr_reg);
1660         temp &= ~FDI_RX_SYMBOL_LOCK;
1661         temp &= ~FDI_RX_BIT_LOCK;
1662         I915_WRITE(fdi_rx_imr_reg, temp);
1663         I915_READ(fdi_rx_imr_reg);
1664         udelay(150);
1665
1666         for (i = 0; i < 4; i++ ) {
1667                 temp = I915_READ(fdi_tx_reg);
1668                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1669                 temp |= snb_b_fdi_train_param[i];
1670                 I915_WRITE(fdi_tx_reg, temp);
1671                 udelay(500);
1672
1673                 temp = I915_READ(fdi_rx_iir_reg);
1674                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1675
1676                 if (temp & FDI_RX_BIT_LOCK) {
1677                         I915_WRITE(fdi_rx_iir_reg,
1678                                    temp | FDI_RX_BIT_LOCK);
1679                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1680                         break;
1681                 }
1682         }
1683         if (i == 4)
1684                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1685
1686         /* Train 2 */
1687         temp = I915_READ(fdi_tx_reg);
1688         temp &= ~FDI_LINK_TRAIN_NONE;
1689         temp |= FDI_LINK_TRAIN_PATTERN_2;
1690         if (IS_GEN6(dev)) {
1691                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1692                 /* SNB-B */
1693                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1694         }
1695         I915_WRITE(fdi_tx_reg, temp);
1696
1697         temp = I915_READ(fdi_rx_reg);
1698         if (HAS_PCH_CPT(dev)) {
1699                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1700                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1701         } else {
1702                 temp &= ~FDI_LINK_TRAIN_NONE;
1703                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1704         }
1705         I915_WRITE(fdi_rx_reg, temp);
1706         udelay(150);
1707
1708         for (i = 0; i < 4; i++ ) {
1709                 temp = I915_READ(fdi_tx_reg);
1710                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1711                 temp |= snb_b_fdi_train_param[i];
1712                 I915_WRITE(fdi_tx_reg, temp);
1713                 udelay(500);
1714
1715                 temp = I915_READ(fdi_rx_iir_reg);
1716                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1717
1718                 if (temp & FDI_RX_SYMBOL_LOCK) {
1719                         I915_WRITE(fdi_rx_iir_reg,
1720                                    temp | FDI_RX_SYMBOL_LOCK);
1721                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1722                         break;
1723                 }
1724         }
1725         if (i == 4)
1726                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1727
1728         DRM_DEBUG_KMS("FDI train done.\n");
1729 }
1730
1731 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1732 {
1733         struct drm_device *dev = crtc->dev;
1734         struct drm_i915_private *dev_priv = dev->dev_private;
1735         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1736         int pipe = intel_crtc->pipe;
1737         int plane = intel_crtc->plane;
1738         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1739         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1740         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1741         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1742         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1743         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1744         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1745         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1746         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1747         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1748         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1749         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1750         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1751         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1752         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1753         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1754         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1755         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1756         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1757         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1758         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1759         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1760         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1761         u32 temp;
1762         int n;
1763         u32 pipe_bpc;
1764
1765         temp = I915_READ(pipeconf_reg);
1766         pipe_bpc = temp & PIPE_BPC_MASK;
1767
1768         /* XXX: When our outputs are all unaware of DPMS modes other than off
1769          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1770          */
1771         switch (mode) {
1772         case DRM_MODE_DPMS_ON:
1773         case DRM_MODE_DPMS_STANDBY:
1774         case DRM_MODE_DPMS_SUSPEND:
1775                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1776
1777                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1778                         temp = I915_READ(PCH_LVDS);
1779                         if ((temp & LVDS_PORT_EN) == 0) {
1780                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1781                                 POSTING_READ(PCH_LVDS);
1782                         }
1783                 }
1784
1785                 if (HAS_eDP) {
1786                         /* enable eDP PLL */
1787                         ironlake_enable_pll_edp(crtc);
1788                 } else {
1789
1790                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1791                         temp = I915_READ(fdi_rx_reg);
1792                         /*
1793                          * make the BPC in FDI Rx be consistent with that in
1794                          * pipeconf reg.
1795                          */
1796                         temp &= ~(0x7 << 16);
1797                         temp |= (pipe_bpc << 11);
1798                         temp &= ~(7 << 19);
1799                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1800                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1801                         I915_READ(fdi_rx_reg);
1802                         udelay(200);
1803
1804                         /* Switch from Rawclk to PCDclk */
1805                         temp = I915_READ(fdi_rx_reg);
1806                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1807                         I915_READ(fdi_rx_reg);
1808                         udelay(200);
1809
1810                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1811                         temp = I915_READ(fdi_tx_reg);
1812                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1813                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1814                                 I915_READ(fdi_tx_reg);
1815                                 udelay(100);
1816                         }
1817                 }
1818
1819                 /* Enable panel fitting for LVDS */
1820                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1821                         temp = I915_READ(pf_ctl_reg);
1822                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1823
1824                         /* currently full aspect */
1825                         I915_WRITE(pf_win_pos, 0);
1826
1827                         I915_WRITE(pf_win_size,
1828                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1829                                    (dev_priv->panel_fixed_mode->vdisplay));
1830                 }
1831
1832                 /* Enable CPU pipe */
1833                 temp = I915_READ(pipeconf_reg);
1834                 if ((temp & PIPEACONF_ENABLE) == 0) {
1835                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1836                         I915_READ(pipeconf_reg);
1837                         udelay(100);
1838                 }
1839
1840                 /* configure and enable CPU plane */
1841                 temp = I915_READ(dspcntr_reg);
1842                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1843                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1844                         /* Flush the plane changes */
1845                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1846                 }
1847
1848                 if (!HAS_eDP) {
1849                         /* For PCH output, training FDI link */
1850                         if (IS_GEN6(dev))
1851                                 gen6_fdi_link_train(crtc);
1852                         else
1853                                 ironlake_fdi_link_train(crtc);
1854
1855                         /* enable PCH DPLL */
1856                         temp = I915_READ(pch_dpll_reg);
1857                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1858                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1859                                 I915_READ(pch_dpll_reg);
1860                         }
1861                         udelay(200);
1862
1863                         if (HAS_PCH_CPT(dev)) {
1864                                 /* Be sure PCH DPLL SEL is set */
1865                                 temp = I915_READ(PCH_DPLL_SEL);
1866                                 if (trans_dpll_sel == 0 &&
1867                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1868                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1869                                 else if (trans_dpll_sel == 1 &&
1870                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1871                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1872                                 I915_WRITE(PCH_DPLL_SEL, temp);
1873                                 I915_READ(PCH_DPLL_SEL);
1874                         }
1875
1876                         /* set transcoder timing */
1877                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1878                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1879                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1880
1881                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1882                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1883                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1884
1885                         /* enable normal train */
1886                         temp = I915_READ(fdi_tx_reg);
1887                         temp &= ~FDI_LINK_TRAIN_NONE;
1888                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1889                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1890                         I915_READ(fdi_tx_reg);
1891
1892                         temp = I915_READ(fdi_rx_reg);
1893                         if (HAS_PCH_CPT(dev)) {
1894                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1895                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1896                         } else {
1897                                 temp &= ~FDI_LINK_TRAIN_NONE;
1898                                 temp |= FDI_LINK_TRAIN_NONE;
1899                         }
1900                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1901                         I915_READ(fdi_rx_reg);
1902
1903                         /* wait one idle pattern time */
1904                         udelay(100);
1905
1906                         /* For PCH DP, enable TRANS_DP_CTL */
1907                         if (HAS_PCH_CPT(dev) &&
1908                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1909                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1910                                 int reg;
1911
1912                                 reg = I915_READ(trans_dp_ctl);
1913                                 reg &= ~TRANS_DP_PORT_SEL_MASK;
1914                                 reg = TRANS_DP_OUTPUT_ENABLE |
1915                                       TRANS_DP_ENH_FRAMING |
1916                                       TRANS_DP_VSYNC_ACTIVE_HIGH |
1917                                       TRANS_DP_HSYNC_ACTIVE_HIGH;
1918
1919                                 switch (intel_trans_dp_port_sel(crtc)) {
1920                                 case PCH_DP_B:
1921                                         reg |= TRANS_DP_PORT_SEL_B;
1922                                         break;
1923                                 case PCH_DP_C:
1924                                         reg |= TRANS_DP_PORT_SEL_C;
1925                                         break;
1926                                 case PCH_DP_D:
1927                                         reg |= TRANS_DP_PORT_SEL_D;
1928                                         break;
1929                                 default:
1930                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1931                                         reg |= TRANS_DP_PORT_SEL_B;
1932                                         break;
1933                                 }
1934
1935                                 I915_WRITE(trans_dp_ctl, reg);
1936                                 POSTING_READ(trans_dp_ctl);
1937                         }
1938
1939                         /* enable PCH transcoder */
1940                         temp = I915_READ(transconf_reg);
1941                         /*
1942                          * make the BPC in transcoder be consistent with
1943                          * that in pipeconf reg.
1944                          */
1945                         temp &= ~PIPE_BPC_MASK;
1946                         temp |= pipe_bpc;
1947                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1948                         I915_READ(transconf_reg);
1949
1950                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1951                                 ;
1952
1953                 }
1954
1955                 intel_crtc_load_lut(crtc);
1956
1957         break;
1958         case DRM_MODE_DPMS_OFF:
1959                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1960
1961                 drm_vblank_off(dev, pipe);
1962                 /* Disable display plane */
1963                 temp = I915_READ(dspcntr_reg);
1964                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1965                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1966                         /* Flush the plane changes */
1967                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1968                         I915_READ(dspbase_reg);
1969                 }
1970
1971                 i915_disable_vga(dev);
1972
1973                 /* disable cpu pipe, disable after all planes disabled */
1974                 temp = I915_READ(pipeconf_reg);
1975                 if ((temp & PIPEACONF_ENABLE) != 0) {
1976                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1977                         I915_READ(pipeconf_reg);
1978                         n = 0;
1979                         /* wait for cpu pipe off, pipe state */
1980                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1981                                 n++;
1982                                 if (n < 60) {
1983                                         udelay(500);
1984                                         continue;
1985                                 } else {
1986                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1987                                                                 pipe);
1988                                         break;
1989                                 }
1990                         }
1991                 } else
1992                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1993
1994                 udelay(100);
1995
1996                 /* Disable PF */
1997                 temp = I915_READ(pf_ctl_reg);
1998                 if ((temp & PF_ENABLE) != 0) {
1999                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2000                         I915_READ(pf_ctl_reg);
2001                 }
2002                 I915_WRITE(pf_win_size, 0);
2003                 POSTING_READ(pf_win_size);
2004
2005
2006                 /* disable CPU FDI tx and PCH FDI rx */
2007                 temp = I915_READ(fdi_tx_reg);
2008                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2009                 I915_READ(fdi_tx_reg);
2010
2011                 temp = I915_READ(fdi_rx_reg);
2012                 /* BPC in FDI rx is consistent with that in pipeconf */
2013                 temp &= ~(0x07 << 16);
2014                 temp |= (pipe_bpc << 11);
2015                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2016                 I915_READ(fdi_rx_reg);
2017
2018                 udelay(100);
2019
2020                 /* still set train pattern 1 */
2021                 temp = I915_READ(fdi_tx_reg);
2022                 temp &= ~FDI_LINK_TRAIN_NONE;
2023                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2024                 I915_WRITE(fdi_tx_reg, temp);
2025                 POSTING_READ(fdi_tx_reg);
2026
2027                 temp = I915_READ(fdi_rx_reg);
2028                 if (HAS_PCH_CPT(dev)) {
2029                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2030                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2031                 } else {
2032                         temp &= ~FDI_LINK_TRAIN_NONE;
2033                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2034                 }
2035                 I915_WRITE(fdi_rx_reg, temp);
2036                 POSTING_READ(fdi_rx_reg);
2037
2038                 udelay(100);
2039
2040                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2041                         temp = I915_READ(PCH_LVDS);
2042                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2043                         I915_READ(PCH_LVDS);
2044                         udelay(100);
2045                 }
2046
2047                 /* disable PCH transcoder */
2048                 temp = I915_READ(transconf_reg);
2049                 if ((temp & TRANS_ENABLE) != 0) {
2050                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2051                         I915_READ(transconf_reg);
2052                         n = 0;
2053                         /* wait for PCH transcoder off, transcoder state */
2054                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2055                                 n++;
2056                                 if (n < 60) {
2057                                         udelay(500);
2058                                         continue;
2059                                 } else {
2060                                         DRM_DEBUG_KMS("transcoder %d off "
2061                                                         "delay\n", pipe);
2062                                         break;
2063                                 }
2064                         }
2065                 }
2066
2067                 temp = I915_READ(transconf_reg);
2068                 /* BPC in transcoder is consistent with that in pipeconf */
2069                 temp &= ~PIPE_BPC_MASK;
2070                 temp |= pipe_bpc;
2071                 I915_WRITE(transconf_reg, temp);
2072                 I915_READ(transconf_reg);
2073                 udelay(100);
2074
2075                 if (HAS_PCH_CPT(dev)) {
2076                         /* disable TRANS_DP_CTL */
2077                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2078                         int reg;
2079
2080                         reg = I915_READ(trans_dp_ctl);
2081                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2082                         I915_WRITE(trans_dp_ctl, reg);
2083                         POSTING_READ(trans_dp_ctl);
2084
2085                         /* disable DPLL_SEL */
2086                         temp = I915_READ(PCH_DPLL_SEL);
2087                         if (trans_dpll_sel == 0)
2088                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2089                         else
2090                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2091                         I915_WRITE(PCH_DPLL_SEL, temp);
2092                         I915_READ(PCH_DPLL_SEL);
2093
2094                 }
2095
2096                 /* disable PCH DPLL */
2097                 temp = I915_READ(pch_dpll_reg);
2098                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2099                 I915_READ(pch_dpll_reg);
2100
2101                 if (HAS_eDP) {
2102                         ironlake_disable_pll_edp(crtc);
2103                 }
2104
2105                 /* Switch from PCDclk to Rawclk */
2106                 temp = I915_READ(fdi_rx_reg);
2107                 temp &= ~FDI_SEL_PCDCLK;
2108                 I915_WRITE(fdi_rx_reg, temp);
2109                 I915_READ(fdi_rx_reg);
2110
2111                 /* Disable CPU FDI TX PLL */
2112                 temp = I915_READ(fdi_tx_reg);
2113                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2114                 I915_READ(fdi_tx_reg);
2115                 udelay(100);
2116
2117                 temp = I915_READ(fdi_rx_reg);
2118                 temp &= ~FDI_RX_PLL_ENABLE;
2119                 I915_WRITE(fdi_rx_reg, temp);
2120                 I915_READ(fdi_rx_reg);
2121
2122                 /* Wait for the clocks to turn off. */
2123                 udelay(100);
2124                 break;
2125         }
2126 }
2127
2128 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2129 {
2130         struct intel_overlay *overlay;
2131         int ret;
2132
2133         if (!enable && intel_crtc->overlay) {
2134                 overlay = intel_crtc->overlay;
2135                 mutex_lock(&overlay->dev->struct_mutex);
2136                 for (;;) {
2137                         ret = intel_overlay_switch_off(overlay);
2138                         if (ret == 0)
2139                                 break;
2140
2141                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2142                         if (ret != 0) {
2143                                 /* overlay doesn't react anymore. Usually
2144                                  * results in a black screen and an unkillable
2145                                  * X server. */
2146                                 BUG();
2147                                 overlay->hw_wedged = HW_WEDGED;
2148                                 break;
2149                         }
2150                 }
2151                 mutex_unlock(&overlay->dev->struct_mutex);
2152         }
2153         /* Let userspace switch the overlay on again. In most cases userspace
2154          * has to recompute where to put it anyway. */
2155
2156         return;
2157 }
2158
2159 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2160 {
2161         struct drm_device *dev = crtc->dev;
2162         struct drm_i915_private *dev_priv = dev->dev_private;
2163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2164         int pipe = intel_crtc->pipe;
2165         int plane = intel_crtc->plane;
2166         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2167         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2168         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2169         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2170         u32 temp;
2171
2172         /* XXX: When our outputs are all unaware of DPMS modes other than off
2173          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2174          */
2175         switch (mode) {
2176         case DRM_MODE_DPMS_ON:
2177         case DRM_MODE_DPMS_STANDBY:
2178         case DRM_MODE_DPMS_SUSPEND:
2179                 intel_update_watermarks(dev);
2180
2181                 /* Enable the DPLL */
2182                 temp = I915_READ(dpll_reg);
2183                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2184                         I915_WRITE(dpll_reg, temp);
2185                         I915_READ(dpll_reg);
2186                         /* Wait for the clocks to stabilize. */
2187                         udelay(150);
2188                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2189                         I915_READ(dpll_reg);
2190                         /* Wait for the clocks to stabilize. */
2191                         udelay(150);
2192                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2193                         I915_READ(dpll_reg);
2194                         /* Wait for the clocks to stabilize. */
2195                         udelay(150);
2196                 }
2197
2198                 /* Enable the pipe */
2199                 temp = I915_READ(pipeconf_reg);
2200                 if ((temp & PIPEACONF_ENABLE) == 0)
2201                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2202
2203                 /* Enable the plane */
2204                 temp = I915_READ(dspcntr_reg);
2205                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2206                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2207                         /* Flush the plane changes */
2208                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2209                 }
2210
2211                 intel_crtc_load_lut(crtc);
2212
2213                 if ((IS_I965G(dev) || plane == 0))
2214                         intel_update_fbc(crtc, &crtc->mode);
2215
2216                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2217                 intel_crtc_dpms_overlay(intel_crtc, true);
2218         break;
2219         case DRM_MODE_DPMS_OFF:
2220                 intel_update_watermarks(dev);
2221
2222                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2223                 intel_crtc_dpms_overlay(intel_crtc, false);
2224                 drm_vblank_off(dev, pipe);
2225
2226                 if (dev_priv->cfb_plane == plane &&
2227                     dev_priv->display.disable_fbc)
2228                         dev_priv->display.disable_fbc(dev);
2229
2230                 /* Disable the VGA plane that we never use */
2231                 i915_disable_vga(dev);
2232
2233                 /* Disable display plane */
2234                 temp = I915_READ(dspcntr_reg);
2235                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2236                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2237                         /* Flush the plane changes */
2238                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2239                         I915_READ(dspbase_reg);
2240                 }
2241
2242                 if (!IS_I9XX(dev)) {
2243                         /* Wait for vblank for the disable to take effect */
2244                         intel_wait_for_vblank(dev);
2245                 }
2246
2247                 /* Next, disable display pipes */
2248                 temp = I915_READ(pipeconf_reg);
2249                 if ((temp & PIPEACONF_ENABLE) != 0) {
2250                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2251                         I915_READ(pipeconf_reg);
2252                 }
2253
2254                 /* Wait for vblank for the disable to take effect. */
2255                 intel_wait_for_vblank(dev);
2256
2257                 temp = I915_READ(dpll_reg);
2258                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2259                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2260                         I915_READ(dpll_reg);
2261                 }
2262
2263                 /* Wait for the clocks to turn off. */
2264                 udelay(150);
2265                 break;
2266         }
2267 }
2268
2269 /**
2270  * Sets the power management mode of the pipe and plane.
2271  *
2272  * This code should probably grow support for turning the cursor off and back
2273  * on appropriately at the same time as we're turning the pipe off/on.
2274  */
2275 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2276 {
2277         struct drm_device *dev = crtc->dev;
2278         struct drm_i915_private *dev_priv = dev->dev_private;
2279         struct drm_i915_master_private *master_priv;
2280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2281         int pipe = intel_crtc->pipe;
2282         bool enabled;
2283
2284         dev_priv->display.dpms(crtc, mode);
2285
2286         intel_crtc->dpms_mode = mode;
2287
2288         if (!dev->primary->master)
2289                 return;
2290
2291         master_priv = dev->primary->master->driver_priv;
2292         if (!master_priv->sarea_priv)
2293                 return;
2294
2295         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2296
2297         switch (pipe) {
2298         case 0:
2299                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2300                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2301                 break;
2302         case 1:
2303                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2304                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2305                 break;
2306         default:
2307                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2308                 break;
2309         }
2310 }
2311
2312 static void intel_crtc_prepare (struct drm_crtc *crtc)
2313 {
2314         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2315         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2316 }
2317
2318 static void intel_crtc_commit (struct drm_crtc *crtc)
2319 {
2320         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2321         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2322 }
2323
2324 void intel_encoder_prepare (struct drm_encoder *encoder)
2325 {
2326         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2327         /* lvds has its own version of prepare see intel_lvds_prepare */
2328         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2329 }
2330
2331 void intel_encoder_commit (struct drm_encoder *encoder)
2332 {
2333         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2334         /* lvds has its own version of commit see intel_lvds_commit */
2335         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2336 }
2337
2338 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2339                                   struct drm_display_mode *mode,
2340                                   struct drm_display_mode *adjusted_mode)
2341 {
2342         struct drm_device *dev = crtc->dev;
2343         if (HAS_PCH_SPLIT(dev)) {
2344                 /* FDI link clock is fixed at 2.7G */
2345                 if (mode->clock * 3 > 27000 * 4)
2346                         return MODE_CLOCK_HIGH;
2347         }
2348         return true;
2349 }
2350
2351 static int i945_get_display_clock_speed(struct drm_device *dev)
2352 {
2353         return 400000;
2354 }
2355
2356 static int i915_get_display_clock_speed(struct drm_device *dev)
2357 {
2358         return 333000;
2359 }
2360
2361 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2362 {
2363         return 200000;
2364 }
2365
2366 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2367 {
2368         u16 gcfgc = 0;
2369
2370         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2371
2372         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2373                 return 133000;
2374         else {
2375                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2376                 case GC_DISPLAY_CLOCK_333_MHZ:
2377                         return 333000;
2378                 default:
2379                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2380                         return 190000;
2381                 }
2382         }
2383 }
2384
2385 static int i865_get_display_clock_speed(struct drm_device *dev)
2386 {
2387         return 266000;
2388 }
2389
2390 static int i855_get_display_clock_speed(struct drm_device *dev)
2391 {
2392         u16 hpllcc = 0;
2393         /* Assume that the hardware is in the high speed state.  This
2394          * should be the default.
2395          */
2396         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2397         case GC_CLOCK_133_200:
2398         case GC_CLOCK_100_200:
2399                 return 200000;
2400         case GC_CLOCK_166_250:
2401                 return 250000;
2402         case GC_CLOCK_100_133:
2403                 return 133000;
2404         }
2405
2406         /* Shouldn't happen */
2407         return 0;
2408 }
2409
2410 static int i830_get_display_clock_speed(struct drm_device *dev)
2411 {
2412         return 133000;
2413 }
2414
2415 /**
2416  * Return the pipe currently connected to the panel fitter,
2417  * or -1 if the panel fitter is not present or not in use
2418  */
2419 int intel_panel_fitter_pipe (struct drm_device *dev)
2420 {
2421         struct drm_i915_private *dev_priv = dev->dev_private;
2422         u32  pfit_control;
2423
2424         /* i830 doesn't have a panel fitter */
2425         if (IS_I830(dev))
2426                 return -1;
2427
2428         pfit_control = I915_READ(PFIT_CONTROL);
2429
2430         /* See if the panel fitter is in use */
2431         if ((pfit_control & PFIT_ENABLE) == 0)
2432                 return -1;
2433
2434         /* 965 can place panel fitter on either pipe */
2435         if (IS_I965G(dev))
2436                 return (pfit_control >> 29) & 0x3;
2437
2438         /* older chips can only use pipe 1 */
2439         return 1;
2440 }
2441
2442 struct fdi_m_n {
2443         u32        tu;
2444         u32        gmch_m;
2445         u32        gmch_n;
2446         u32        link_m;
2447         u32        link_n;
2448 };
2449
2450 static void
2451 fdi_reduce_ratio(u32 *num, u32 *den)
2452 {
2453         while (*num > 0xffffff || *den > 0xffffff) {
2454                 *num >>= 1;
2455                 *den >>= 1;
2456         }
2457 }
2458
2459 #define DATA_N 0x800000
2460 #define LINK_N 0x80000
2461
2462 static void
2463 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2464                      int link_clock, struct fdi_m_n *m_n)
2465 {
2466         u64 temp;
2467
2468         m_n->tu = 64; /* default size */
2469
2470         temp = (u64) DATA_N * pixel_clock;
2471         temp = div_u64(temp, link_clock);
2472         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2473         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2474         m_n->gmch_n = DATA_N;
2475         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2476
2477         temp = (u64) LINK_N * pixel_clock;
2478         m_n->link_m = div_u64(temp, link_clock);
2479         m_n->link_n = LINK_N;
2480         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2481 }
2482
2483
2484 struct intel_watermark_params {
2485         unsigned long fifo_size;
2486         unsigned long max_wm;
2487         unsigned long default_wm;
2488         unsigned long guard_size;
2489         unsigned long cacheline_size;
2490 };
2491
2492 /* Pineview has different values for various configs */
2493 static struct intel_watermark_params pineview_display_wm = {
2494         PINEVIEW_DISPLAY_FIFO,
2495         PINEVIEW_MAX_WM,
2496         PINEVIEW_DFT_WM,
2497         PINEVIEW_GUARD_WM,
2498         PINEVIEW_FIFO_LINE_SIZE
2499 };
2500 static struct intel_watermark_params pineview_display_hplloff_wm = {
2501         PINEVIEW_DISPLAY_FIFO,
2502         PINEVIEW_MAX_WM,
2503         PINEVIEW_DFT_HPLLOFF_WM,
2504         PINEVIEW_GUARD_WM,
2505         PINEVIEW_FIFO_LINE_SIZE
2506 };
2507 static struct intel_watermark_params pineview_cursor_wm = {
2508         PINEVIEW_CURSOR_FIFO,
2509         PINEVIEW_CURSOR_MAX_WM,
2510         PINEVIEW_CURSOR_DFT_WM,
2511         PINEVIEW_CURSOR_GUARD_WM,
2512         PINEVIEW_FIFO_LINE_SIZE,
2513 };
2514 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2515         PINEVIEW_CURSOR_FIFO,
2516         PINEVIEW_CURSOR_MAX_WM,
2517         PINEVIEW_CURSOR_DFT_WM,
2518         PINEVIEW_CURSOR_GUARD_WM,
2519         PINEVIEW_FIFO_LINE_SIZE
2520 };
2521 static struct intel_watermark_params g4x_wm_info = {
2522         G4X_FIFO_SIZE,
2523         G4X_MAX_WM,
2524         G4X_MAX_WM,
2525         2,
2526         G4X_FIFO_LINE_SIZE,
2527 };
2528 static struct intel_watermark_params i945_wm_info = {
2529         I945_FIFO_SIZE,
2530         I915_MAX_WM,
2531         1,
2532         2,
2533         I915_FIFO_LINE_SIZE
2534 };
2535 static struct intel_watermark_params i915_wm_info = {
2536         I915_FIFO_SIZE,
2537         I915_MAX_WM,
2538         1,
2539         2,
2540         I915_FIFO_LINE_SIZE
2541 };
2542 static struct intel_watermark_params i855_wm_info = {
2543         I855GM_FIFO_SIZE,
2544         I915_MAX_WM,
2545         1,
2546         2,
2547         I830_FIFO_LINE_SIZE
2548 };
2549 static struct intel_watermark_params i830_wm_info = {
2550         I830_FIFO_SIZE,
2551         I915_MAX_WM,
2552         1,
2553         2,
2554         I830_FIFO_LINE_SIZE
2555 };
2556
2557 static struct intel_watermark_params ironlake_display_wm_info = {
2558         ILK_DISPLAY_FIFO,
2559         ILK_DISPLAY_MAXWM,
2560         ILK_DISPLAY_DFTWM,
2561         2,
2562         ILK_FIFO_LINE_SIZE
2563 };
2564
2565 static struct intel_watermark_params ironlake_display_srwm_info = {
2566         ILK_DISPLAY_SR_FIFO,
2567         ILK_DISPLAY_MAX_SRWM,
2568         ILK_DISPLAY_DFT_SRWM,
2569         2,
2570         ILK_FIFO_LINE_SIZE
2571 };
2572
2573 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2574         ILK_CURSOR_SR_FIFO,
2575         ILK_CURSOR_MAX_SRWM,
2576         ILK_CURSOR_DFT_SRWM,
2577         2,
2578         ILK_FIFO_LINE_SIZE
2579 };
2580
2581 /**
2582  * intel_calculate_wm - calculate watermark level
2583  * @clock_in_khz: pixel clock
2584  * @wm: chip FIFO params
2585  * @pixel_size: display pixel size
2586  * @latency_ns: memory latency for the platform
2587  *
2588  * Calculate the watermark level (the level at which the display plane will
2589  * start fetching from memory again).  Each chip has a different display
2590  * FIFO size and allocation, so the caller needs to figure that out and pass
2591  * in the correct intel_watermark_params structure.
2592  *
2593  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2594  * on the pixel size.  When it reaches the watermark level, it'll start
2595  * fetching FIFO line sized based chunks from memory until the FIFO fills
2596  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2597  * will occur, and a display engine hang could result.
2598  */
2599 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2600                                         struct intel_watermark_params *wm,
2601                                         int pixel_size,
2602                                         unsigned long latency_ns)
2603 {
2604         long entries_required, wm_size;
2605
2606         /*
2607          * Note: we need to make sure we don't overflow for various clock &
2608          * latency values.
2609          * clocks go from a few thousand to several hundred thousand.
2610          * latency is usually a few thousand
2611          */
2612         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2613                 1000;
2614         entries_required /= wm->cacheline_size;
2615
2616         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2617
2618         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2619
2620         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2621
2622         /* Don't promote wm_size to unsigned... */
2623         if (wm_size > (long)wm->max_wm)
2624                 wm_size = wm->max_wm;
2625         if (wm_size <= 0)
2626                 wm_size = wm->default_wm;
2627         return wm_size;
2628 }
2629
2630 struct cxsr_latency {
2631         int is_desktop;
2632         unsigned long fsb_freq;
2633         unsigned long mem_freq;
2634         unsigned long display_sr;
2635         unsigned long display_hpll_disable;
2636         unsigned long cursor_sr;
2637         unsigned long cursor_hpll_disable;
2638 };
2639
2640 static struct cxsr_latency cxsr_latency_table[] = {
2641         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2642         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2643         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2644
2645         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2646         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2647         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2648
2649         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2650         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2651         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2652
2653         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2654         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2655         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2656
2657         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2658         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2659         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2660
2661         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2662         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2663         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2664 };
2665
2666 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2667                                                    int mem)
2668 {
2669         int i;
2670         struct cxsr_latency *latency;
2671
2672         if (fsb == 0 || mem == 0)
2673                 return NULL;
2674
2675         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2676                 latency = &cxsr_latency_table[i];
2677                 if (is_desktop == latency->is_desktop &&
2678                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2679                         return latency;
2680         }
2681
2682         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2683
2684         return NULL;
2685 }
2686
2687 static void pineview_disable_cxsr(struct drm_device *dev)
2688 {
2689         struct drm_i915_private *dev_priv = dev->dev_private;
2690         u32 reg;
2691
2692         /* deactivate cxsr */
2693         reg = I915_READ(DSPFW3);
2694         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2695         I915_WRITE(DSPFW3, reg);
2696         DRM_INFO("Big FIFO is disabled\n");
2697 }
2698
2699 /*
2700  * Latency for FIFO fetches is dependent on several factors:
2701  *   - memory configuration (speed, channels)
2702  *   - chipset
2703  *   - current MCH state
2704  * It can be fairly high in some situations, so here we assume a fairly
2705  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2706  * set this value too high, the FIFO will fetch frequently to stay full)
2707  * and power consumption (set it too low to save power and we might see
2708  * FIFO underruns and display "flicker").
2709  *
2710  * A value of 5us seems to be a good balance; safe for very low end
2711  * platforms but not overly aggressive on lower latency configs.
2712  */
2713 static const int latency_ns = 5000;
2714
2715 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2716 {
2717         struct drm_i915_private *dev_priv = dev->dev_private;
2718         uint32_t dsparb = I915_READ(DSPARB);
2719         int size;
2720
2721         if (plane == 0)
2722                 size = dsparb & 0x7f;
2723         else
2724                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2725                         (dsparb & 0x7f);
2726
2727         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2728                         plane ? "B" : "A", size);
2729
2730         return size;
2731 }
2732
2733 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2734 {
2735         struct drm_i915_private *dev_priv = dev->dev_private;
2736         uint32_t dsparb = I915_READ(DSPARB);
2737         int size;
2738
2739         if (plane == 0)
2740                 size = dsparb & 0x1ff;
2741         else
2742                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2743                         (dsparb & 0x1ff);
2744         size >>= 1; /* Convert to cachelines */
2745
2746         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2747                         plane ? "B" : "A", size);
2748
2749         return size;
2750 }
2751
2752 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2753 {
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755         uint32_t dsparb = I915_READ(DSPARB);
2756         int size;
2757
2758         size = dsparb & 0x7f;
2759         size >>= 2; /* Convert to cachelines */
2760
2761         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2762                         plane ? "B" : "A",
2763                   size);
2764
2765         return size;
2766 }
2767
2768 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2769 {
2770         struct drm_i915_private *dev_priv = dev->dev_private;
2771         uint32_t dsparb = I915_READ(DSPARB);
2772         int size;
2773
2774         size = dsparb & 0x7f;
2775         size >>= 1; /* Convert to cachelines */
2776
2777         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2778                         plane ? "B" : "A", size);
2779
2780         return size;
2781 }
2782
2783 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2784                           int planeb_clock, int sr_hdisplay, int pixel_size)
2785 {
2786         struct drm_i915_private *dev_priv = dev->dev_private;
2787         u32 reg;
2788         unsigned long wm;
2789         struct cxsr_latency *latency;
2790         int sr_clock;
2791
2792         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2793                                          dev_priv->mem_freq);
2794         if (!latency) {
2795                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2796                 pineview_disable_cxsr(dev);
2797                 return;
2798         }
2799
2800         if (!planea_clock || !planeb_clock) {
2801                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2802
2803                 /* Display SR */
2804                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2805                                         pixel_size, latency->display_sr);
2806                 reg = I915_READ(DSPFW1);
2807                 reg &= ~DSPFW_SR_MASK;
2808                 reg |= wm << DSPFW_SR_SHIFT;
2809                 I915_WRITE(DSPFW1, reg);
2810                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2811
2812                 /* cursor SR */
2813                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2814                                         pixel_size, latency->cursor_sr);
2815                 reg = I915_READ(DSPFW3);
2816                 reg &= ~DSPFW_CURSOR_SR_MASK;
2817                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2818                 I915_WRITE(DSPFW3, reg);
2819
2820                 /* Display HPLL off SR */
2821                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2822                                         pixel_size, latency->display_hpll_disable);
2823                 reg = I915_READ(DSPFW3);
2824                 reg &= ~DSPFW_HPLL_SR_MASK;
2825                 reg |= wm & DSPFW_HPLL_SR_MASK;
2826                 I915_WRITE(DSPFW3, reg);
2827
2828                 /* cursor HPLL off SR */
2829                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2830                                         pixel_size, latency->cursor_hpll_disable);
2831                 reg = I915_READ(DSPFW3);
2832                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2833                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2834                 I915_WRITE(DSPFW3, reg);
2835                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2836
2837                 /* activate cxsr */
2838                 reg = I915_READ(DSPFW3);
2839                 reg |= PINEVIEW_SELF_REFRESH_EN;
2840                 I915_WRITE(DSPFW3, reg);
2841                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2842         } else {
2843                 pineview_disable_cxsr(dev);
2844                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2845         }
2846 }
2847
2848 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2849                           int planeb_clock, int sr_hdisplay, int pixel_size)
2850 {
2851         struct drm_i915_private *dev_priv = dev->dev_private;
2852         int total_size, cacheline_size;
2853         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2854         struct intel_watermark_params planea_params, planeb_params;
2855         unsigned long line_time_us;
2856         int sr_clock, sr_entries = 0, entries_required;
2857
2858         /* Create copies of the base settings for each pipe */
2859         planea_params = planeb_params = g4x_wm_info;
2860
2861         /* Grab a couple of global values before we overwrite them */
2862         total_size = planea_params.fifo_size;
2863         cacheline_size = planea_params.cacheline_size;
2864
2865         /*
2866          * Note: we need to make sure we don't overflow for various clock &
2867          * latency values.
2868          * clocks go from a few thousand to several hundred thousand.
2869          * latency is usually a few thousand
2870          */
2871         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2872                 1000;
2873         entries_required /= G4X_FIFO_LINE_SIZE;
2874         planea_wm = entries_required + planea_params.guard_size;
2875
2876         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2877                 1000;
2878         entries_required /= G4X_FIFO_LINE_SIZE;
2879         planeb_wm = entries_required + planeb_params.guard_size;
2880
2881         cursora_wm = cursorb_wm = 16;
2882         cursor_sr = 32;
2883
2884         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2885
2886         /* Calc sr entries for one plane configs */
2887         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2888                 /* self-refresh has much higher latency */
2889                 static const int sr_latency_ns = 12000;
2890
2891                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2892                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2893
2894                 /* Use ns/us then divide to preserve precision */
2895                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2896                               pixel_size * sr_hdisplay) / 1000;
2897                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2898                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2899                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2900         } else {
2901                 /* Turn off self refresh if both pipes are enabled */
2902                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2903                                         & ~FW_BLC_SELF_EN);
2904         }
2905
2906         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2907                   planea_wm, planeb_wm, sr_entries);
2908
2909         planea_wm &= 0x3f;
2910         planeb_wm &= 0x3f;
2911
2912         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2913                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2914                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2915         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2916                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2917         /* HPLL off in SR has some issues on G4x... disable it */
2918         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2919                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2920 }
2921
2922 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2923                            int planeb_clock, int sr_hdisplay, int pixel_size)
2924 {
2925         struct drm_i915_private *dev_priv = dev->dev_private;
2926         unsigned long line_time_us;
2927         int sr_clock, sr_entries, srwm = 1;
2928
2929         /* Calc sr entries for one plane configs */
2930         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2931                 /* self-refresh has much higher latency */
2932                 static const int sr_latency_ns = 12000;
2933
2934                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2935                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2936
2937                 /* Use ns/us then divide to preserve precision */
2938                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2939                               pixel_size * sr_hdisplay) / 1000;
2940                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2941                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2942                 srwm = I945_FIFO_SIZE - sr_entries;
2943                 if (srwm < 0)
2944                         srwm = 1;
2945                 srwm &= 0x3f;
2946                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2947         } else {
2948                 /* Turn off self refresh if both pipes are enabled */
2949                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2950                                         & ~FW_BLC_SELF_EN);
2951         }
2952
2953         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2954                       srwm);
2955
2956         /* 965 has limitations... */
2957         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2958                    (8 << 0));
2959         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2960 }
2961
2962 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2963                            int planeb_clock, int sr_hdisplay, int pixel_size)
2964 {
2965         struct drm_i915_private *dev_priv = dev->dev_private;
2966         uint32_t fwater_lo;
2967         uint32_t fwater_hi;
2968         int total_size, cacheline_size, cwm, srwm = 1;
2969         int planea_wm, planeb_wm;
2970         struct intel_watermark_params planea_params, planeb_params;
2971         unsigned long line_time_us;
2972         int sr_clock, sr_entries = 0;
2973
2974         /* Create copies of the base settings for each pipe */
2975         if (IS_I965GM(dev) || IS_I945GM(dev))
2976                 planea_params = planeb_params = i945_wm_info;
2977         else if (IS_I9XX(dev))
2978                 planea_params = planeb_params = i915_wm_info;
2979         else
2980                 planea_params = planeb_params = i855_wm_info;
2981
2982         /* Grab a couple of global values before we overwrite them */
2983         total_size = planea_params.fifo_size;
2984         cacheline_size = planea_params.cacheline_size;
2985
2986         /* Update per-plane FIFO sizes */
2987         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2988         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2989
2990         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2991                                        pixel_size, latency_ns);
2992         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2993                                        pixel_size, latency_ns);
2994         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2995
2996         /*
2997          * Overlay gets an aggressive default since video jitter is bad.
2998          */
2999         cwm = 2;
3000
3001         /* Calc sr entries for one plane configs */
3002         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3003             (!planea_clock || !planeb_clock)) {
3004                 /* self-refresh has much higher latency */
3005                 static const int sr_latency_ns = 6000;
3006
3007                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3008                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3009
3010                 /* Use ns/us then divide to preserve precision */
3011                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
3012                               pixel_size * sr_hdisplay) / 1000;
3013                 sr_entries = roundup(sr_entries / cacheline_size, 1);
3014                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3015                 srwm = total_size - sr_entries;
3016                 if (srwm < 0)
3017                         srwm = 1;
3018
3019                 if (IS_I945G(dev) || IS_I945GM(dev))
3020                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3021                 else if (IS_I915GM(dev)) {
3022                         /* 915M has a smaller SRWM field */
3023                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3024                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3025                 }
3026         } else {
3027                 /* Turn off self refresh if both pipes are enabled */
3028                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3029                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3030                                    & ~FW_BLC_SELF_EN);
3031                 } else if (IS_I915GM(dev)) {
3032                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3033                 }
3034         }
3035
3036         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3037                   planea_wm, planeb_wm, cwm, srwm);
3038
3039         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3040         fwater_hi = (cwm & 0x1f);
3041
3042         /* Set request length to 8 cachelines per fetch */
3043         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3044         fwater_hi = fwater_hi | (1 << 8);
3045
3046         I915_WRITE(FW_BLC, fwater_lo);
3047         I915_WRITE(FW_BLC2, fwater_hi);
3048 }
3049
3050 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3051                            int unused2, int pixel_size)
3052 {
3053         struct drm_i915_private *dev_priv = dev->dev_private;
3054         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3055         int planea_wm;
3056
3057         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3058
3059         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3060                                        pixel_size, latency_ns);
3061         fwater_lo |= (3<<8) | planea_wm;
3062
3063         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3064
3065         I915_WRITE(FW_BLC, fwater_lo);
3066 }
3067
3068 #define ILK_LP0_PLANE_LATENCY           700
3069
3070 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3071                        int planeb_clock, int sr_hdisplay, int pixel_size)
3072 {
3073         struct drm_i915_private *dev_priv = dev->dev_private;
3074         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3075         int sr_wm, cursor_wm;
3076         unsigned long line_time_us;
3077         int sr_clock, entries_required;
3078         u32 reg_value;
3079
3080         /* Calculate and update the watermark for plane A */
3081         if (planea_clock) {
3082                 entries_required = ((planea_clock / 1000) * pixel_size *
3083                                      ILK_LP0_PLANE_LATENCY) / 1000;
3084                 entries_required = DIV_ROUND_UP(entries_required,
3085                                    ironlake_display_wm_info.cacheline_size);
3086                 planea_wm = entries_required +
3087                             ironlake_display_wm_info.guard_size;
3088
3089                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3090                         planea_wm = ironlake_display_wm_info.max_wm;
3091
3092                 cursora_wm = 16;
3093                 reg_value = I915_READ(WM0_PIPEA_ILK);
3094                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3095                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3096                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3097                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3098                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3099                                 "cursor: %d\n", planea_wm, cursora_wm);
3100         }
3101         /* Calculate and update the watermark for plane B */
3102         if (planeb_clock) {
3103                 entries_required = ((planeb_clock / 1000) * pixel_size *
3104                                      ILK_LP0_PLANE_LATENCY) / 1000;
3105                 entries_required = DIV_ROUND_UP(entries_required,
3106                                    ironlake_display_wm_info.cacheline_size);
3107                 planeb_wm = entries_required +
3108                             ironlake_display_wm_info.guard_size;
3109
3110                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3111                         planeb_wm = ironlake_display_wm_info.max_wm;
3112
3113                 cursorb_wm = 16;
3114                 reg_value = I915_READ(WM0_PIPEB_ILK);
3115                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3116                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3117                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3118                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3119                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3120                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3121         }
3122
3123         /*
3124          * Calculate and update the self-refresh watermark only when one
3125          * display plane is used.
3126          */
3127         if (!planea_clock || !planeb_clock) {
3128                 int line_count;
3129                 /* Read the self-refresh latency. The unit is 0.5us */
3130                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3131
3132                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3133                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3134
3135                 /* Use ns/us then divide to preserve precision */
3136                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3137                                / 1000;
3138
3139                 /* calculate the self-refresh watermark for display plane */
3140                 entries_required = line_count * sr_hdisplay * pixel_size;
3141                 entries_required = DIV_ROUND_UP(entries_required,
3142                                    ironlake_display_srwm_info.cacheline_size);
3143                 sr_wm = entries_required +
3144                         ironlake_display_srwm_info.guard_size;
3145
3146                 /* calculate the self-refresh watermark for display cursor */
3147                 entries_required = line_count * pixel_size * 64;
3148                 entries_required = DIV_ROUND_UP(entries_required,
3149                                    ironlake_cursor_srwm_info.cacheline_size);
3150                 cursor_wm = entries_required +
3151                             ironlake_cursor_srwm_info.guard_size;
3152
3153                 /* configure watermark and enable self-refresh */
3154                 reg_value = I915_READ(WM1_LP_ILK);
3155                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3156                                WM1_LP_CURSOR_MASK);
3157                 reg_value |= WM1_LP_SR_EN |
3158                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3159                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3160
3161                 I915_WRITE(WM1_LP_ILK, reg_value);
3162                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3163                                 "cursor %d\n", sr_wm, cursor_wm);
3164
3165         } else {
3166                 /* Turn off self refresh if both pipes are enabled */
3167                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3168         }
3169 }
3170 /**
3171  * intel_update_watermarks - update FIFO watermark values based on current modes
3172  *
3173  * Calculate watermark values for the various WM regs based on current mode
3174  * and plane configuration.
3175  *
3176  * There are several cases to deal with here:
3177  *   - normal (i.e. non-self-refresh)
3178  *   - self-refresh (SR) mode
3179  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3180  *   - lines are small relative to FIFO size (buffer can hold more than 2
3181  *     lines), so need to account for TLB latency
3182  *
3183  *   The normal calculation is:
3184  *     watermark = dotclock * bytes per pixel * latency
3185  *   where latency is platform & configuration dependent (we assume pessimal
3186  *   values here).
3187  *
3188  *   The SR calculation is:
3189  *     watermark = (trunc(latency/line time)+1) * surface width *
3190  *       bytes per pixel
3191  *   where
3192  *     line time = htotal / dotclock
3193  *   and latency is assumed to be high, as above.
3194  *
3195  * The final value programmed to the register should always be rounded up,
3196  * and include an extra 2 entries to account for clock crossings.
3197  *
3198  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3199  * to set the non-SR watermarks to 8.
3200   */
3201 static void intel_update_watermarks(struct drm_device *dev)
3202 {
3203         struct drm_i915_private *dev_priv = dev->dev_private;
3204         struct drm_crtc *crtc;
3205         struct intel_crtc *intel_crtc;
3206         int sr_hdisplay = 0;
3207         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3208         int enabled = 0, pixel_size = 0;
3209
3210         if (!dev_priv->display.update_wm)
3211                 return;
3212
3213         /* Get the clock config from both planes */
3214         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3215                 intel_crtc = to_intel_crtc(crtc);
3216                 if (crtc->enabled) {
3217                         enabled++;
3218                         if (intel_crtc->plane == 0) {
3219                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3220                                           intel_crtc->pipe, crtc->mode.clock);
3221                                 planea_clock = crtc->mode.clock;
3222                         } else {
3223                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3224                                           intel_crtc->pipe, crtc->mode.clock);
3225                                 planeb_clock = crtc->mode.clock;
3226                         }
3227                         sr_hdisplay = crtc->mode.hdisplay;
3228                         sr_clock = crtc->mode.clock;
3229                         if (crtc->fb)
3230                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3231                         else
3232                                 pixel_size = 4; /* by default */
3233                 }
3234         }
3235
3236         if (enabled <= 0)
3237                 return;
3238
3239         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3240                                     sr_hdisplay, pixel_size);
3241 }
3242
3243 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3244                                struct drm_display_mode *mode,
3245                                struct drm_display_mode *adjusted_mode,
3246                                int x, int y,
3247                                struct drm_framebuffer *old_fb)
3248 {
3249         struct drm_device *dev = crtc->dev;
3250         struct drm_i915_private *dev_priv = dev->dev_private;
3251         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3252         int pipe = intel_crtc->pipe;
3253         int plane = intel_crtc->plane;
3254         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3255         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3256         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3257         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3258         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3259         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3260         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3261         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3262         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3263         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3264         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3265         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3266         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3267         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3268         int refclk, num_connectors = 0;
3269         intel_clock_t clock, reduced_clock;
3270         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3271         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3272         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3273         bool is_edp = false;
3274         struct drm_mode_config *mode_config = &dev->mode_config;
3275         struct drm_encoder *encoder;
3276         struct intel_encoder *intel_encoder = NULL;
3277         const intel_limit_t *limit;
3278         int ret;
3279         struct fdi_m_n m_n = {0};
3280         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3281         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3282         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3283         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3284         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3285         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3286         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3287         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3288         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3289         int lvds_reg = LVDS;
3290         u32 temp;
3291         int sdvo_pixel_multiply;
3292         int target_clock;
3293
3294         drm_vblank_pre_modeset(dev, pipe);
3295
3296         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3297
3298                 if (!encoder || encoder->crtc != crtc)
3299                         continue;
3300
3301                 intel_encoder = enc_to_intel_encoder(encoder);
3302
3303                 switch (intel_encoder->type) {
3304                 case INTEL_OUTPUT_LVDS:
3305                         is_lvds = true;
3306                         break;
3307                 case INTEL_OUTPUT_SDVO:
3308                 case INTEL_OUTPUT_HDMI:
3309                         is_sdvo = true;
3310                         if (intel_encoder->needs_tv_clock)
3311                                 is_tv = true;
3312                         break;
3313                 case INTEL_OUTPUT_DVO:
3314                         is_dvo = true;
3315                         break;
3316                 case INTEL_OUTPUT_TVOUT:
3317                         is_tv = true;
3318                         break;
3319                 case INTEL_OUTPUT_ANALOG:
3320                         is_crt = true;
3321                         break;
3322                 case INTEL_OUTPUT_DISPLAYPORT:
3323                         is_dp = true;
3324                         break;
3325                 case INTEL_OUTPUT_EDP:
3326                         is_edp = true;
3327                         break;
3328                 }
3329
3330                 num_connectors++;
3331         }
3332
3333         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3334                 refclk = dev_priv->lvds_ssc_freq * 1000;
3335                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3336                                         refclk / 1000);
3337         } else if (IS_I9XX(dev)) {
3338                 refclk = 96000;
3339                 if (HAS_PCH_SPLIT(dev))
3340                         refclk = 120000; /* 120Mhz refclk */
3341         } else {
3342                 refclk = 48000;
3343         }
3344         
3345
3346         /*
3347          * Returns a set of divisors for the desired target clock with the given
3348          * refclk, or FALSE.  The returned values represent the clock equation:
3349          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3350          */
3351         limit = intel_limit(crtc);
3352         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3353         if (!ok) {
3354                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3355                 drm_vblank_post_modeset(dev, pipe);
3356                 return -EINVAL;
3357         }
3358
3359         if (is_lvds && dev_priv->lvds_downclock_avail) {
3360                 has_reduced_clock = limit->find_pll(limit, crtc,
3361                                                             dev_priv->lvds_downclock,
3362                                                             refclk,
3363                                                             &reduced_clock);
3364                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3365                         /*
3366                          * If the different P is found, it means that we can't
3367                          * switch the display clock by using the FP0/FP1.
3368                          * In such case we will disable the LVDS downclock
3369                          * feature.
3370                          */
3371                         DRM_DEBUG_KMS("Different P is found for "
3372                                                 "LVDS clock/downclock\n");
3373                         has_reduced_clock = 0;
3374                 }
3375         }
3376         /* SDVO TV has fixed PLL values depend on its clock range,
3377            this mirrors vbios setting. */
3378         if (is_sdvo && is_tv) {
3379                 if (adjusted_mode->clock >= 100000
3380                                 && adjusted_mode->clock < 140500) {
3381                         clock.p1 = 2;
3382                         clock.p2 = 10;
3383                         clock.n = 3;
3384                         clock.m1 = 16;
3385                         clock.m2 = 8;
3386                 } else if (adjusted_mode->clock >= 140500
3387                                 && adjusted_mode->clock <= 200000) {
3388                         clock.p1 = 1;
3389                         clock.p2 = 10;
3390                         clock.n = 6;
3391                         clock.m1 = 12;
3392                         clock.m2 = 8;
3393                 }
3394         }
3395
3396         /* FDI link */
3397         if (HAS_PCH_SPLIT(dev)) {
3398                 int lane = 0, link_bw, bpp;
3399                 /* eDP doesn't require FDI link, so just set DP M/N
3400                    according to current link config */
3401                 if (is_edp) {
3402                         target_clock = mode->clock;
3403                         intel_edp_link_config(intel_encoder,
3404                                         &lane, &link_bw);
3405                 } else {
3406                         /* DP over FDI requires target mode clock
3407                            instead of link clock */
3408                         if (is_dp)
3409                                 target_clock = mode->clock;
3410                         else
3411                                 target_clock = adjusted_mode->clock;
3412                         link_bw = 270000;
3413                 }
3414
3415                 /* determine panel color depth */
3416                 temp = I915_READ(pipeconf_reg);
3417                 temp &= ~PIPE_BPC_MASK;
3418                 if (is_lvds) {
3419                         int lvds_reg = I915_READ(PCH_LVDS);
3420                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3421                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3422                                 temp |= PIPE_8BPC;
3423                         else
3424                                 temp |= PIPE_6BPC;
3425                 } else if (is_edp) {
3426                         switch (dev_priv->edp_bpp/3) {
3427                         case 8:
3428                                 temp |= PIPE_8BPC;
3429                                 break;
3430                         case 10:
3431                                 temp |= PIPE_10BPC;
3432                                 break;
3433                         case 6:
3434                                 temp |= PIPE_6BPC;
3435                                 break;
3436                         case 12:
3437                                 temp |= PIPE_12BPC;
3438                                 break;
3439                         }
3440                 } else
3441                         temp |= PIPE_8BPC;
3442                 I915_WRITE(pipeconf_reg, temp);
3443                 I915_READ(pipeconf_reg);
3444
3445                 switch (temp & PIPE_BPC_MASK) {
3446                 case PIPE_8BPC:
3447                         bpp = 24;
3448                         break;
3449                 case PIPE_10BPC:
3450                         bpp = 30;
3451                         break;
3452                 case PIPE_6BPC:
3453                         bpp = 18;
3454                         break;
3455                 case PIPE_12BPC:
3456                         bpp = 36;
3457                         break;
3458                 default:
3459                         DRM_ERROR("unknown pipe bpc value\n");
3460                         bpp = 24;
3461                 }
3462
3463                 if (!lane) {
3464                         /* 
3465                          * Account for spread spectrum to avoid
3466                          * oversubscribing the link. Max center spread
3467                          * is 2.5%; use 5% for safety's sake.
3468                          */
3469                         u32 bps = target_clock * bpp * 21 / 20;
3470                         lane = bps / (link_bw * 8) + 1;
3471                 }
3472
3473                 intel_crtc->fdi_lanes = lane;
3474
3475                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3476         }
3477
3478         /* Ironlake: try to setup display ref clock before DPLL
3479          * enabling. This is only under driver's control after
3480          * PCH B stepping, previous chipset stepping should be
3481          * ignoring this setting.
3482          */
3483         if (HAS_PCH_SPLIT(dev)) {
3484                 temp = I915_READ(PCH_DREF_CONTROL);
3485                 /* Always enable nonspread source */
3486                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3487                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3488                 I915_WRITE(PCH_DREF_CONTROL, temp);
3489                 POSTING_READ(PCH_DREF_CONTROL);
3490
3491                 temp &= ~DREF_SSC_SOURCE_MASK;
3492                 temp |= DREF_SSC_SOURCE_ENABLE;
3493                 I915_WRITE(PCH_DREF_CONTROL, temp);
3494                 POSTING_READ(PCH_DREF_CONTROL);
3495
3496                 udelay(200);
3497
3498                 if (is_edp) {
3499                         if (dev_priv->lvds_use_ssc) {
3500                                 temp |= DREF_SSC1_ENABLE;
3501                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3502                                 POSTING_READ(PCH_DREF_CONTROL);
3503
3504                                 udelay(200);
3505
3506                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3507                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3508                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3509                                 POSTING_READ(PCH_DREF_CONTROL);
3510                         } else {
3511                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3512                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3513                                 POSTING_READ(PCH_DREF_CONTROL);
3514                         }
3515                 }
3516         }
3517
3518         if (IS_PINEVIEW(dev)) {
3519                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3520                 if (has_reduced_clock)
3521                         fp2 = (1 << reduced_clock.n) << 16 |
3522                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3523         } else {
3524                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3525                 if (has_reduced_clock)
3526                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3527                                 reduced_clock.m2;
3528         }
3529
3530         if (!HAS_PCH_SPLIT(dev))
3531                 dpll = DPLL_VGA_MODE_DIS;
3532
3533         if (IS_I9XX(dev)) {
3534                 if (is_lvds)
3535                         dpll |= DPLLB_MODE_LVDS;
3536                 else
3537                         dpll |= DPLLB_MODE_DAC_SERIAL;
3538                 if (is_sdvo) {
3539                         dpll |= DPLL_DVO_HIGH_SPEED;
3540                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3541                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3542                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3543                         else if (HAS_PCH_SPLIT(dev))
3544                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3545                 }
3546                 if (is_dp)
3547                         dpll |= DPLL_DVO_HIGH_SPEED;
3548
3549                 /* compute bitmask from p1 value */
3550                 if (IS_PINEVIEW(dev))
3551                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3552                 else {
3553                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3554                         /* also FPA1 */
3555                         if (HAS_PCH_SPLIT(dev))
3556                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3557                         if (IS_G4X(dev) && has_reduced_clock)
3558                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3559                 }
3560                 switch (clock.p2) {
3561                 case 5:
3562                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3563                         break;
3564                 case 7:
3565                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3566                         break;
3567                 case 10:
3568                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3569                         break;
3570                 case 14:
3571                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3572                         break;
3573                 }
3574                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3575                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3576         } else {
3577                 if (is_lvds) {
3578                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3579                 } else {
3580                         if (clock.p1 == 2)
3581                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3582                         else
3583                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3584                         if (clock.p2 == 4)
3585                                 dpll |= PLL_P2_DIVIDE_BY_4;
3586                 }
3587         }
3588
3589         if (is_sdvo && is_tv)
3590                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3591         else if (is_tv)
3592                 /* XXX: just matching BIOS for now */
3593                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3594                 dpll |= 3;
3595         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3596                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3597         else
3598                 dpll |= PLL_REF_INPUT_DREFCLK;
3599
3600         /* setup pipeconf */
3601         pipeconf = I915_READ(pipeconf_reg);
3602
3603         /* Set up the display plane register */
3604         dspcntr = DISPPLANE_GAMMA_ENABLE;
3605
3606         /* Ironlake's plane is forced to pipe, bit 24 is to
3607            enable color space conversion */
3608         if (!HAS_PCH_SPLIT(dev)) {
3609                 if (pipe == 0)
3610                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3611                 else
3612                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3613         }
3614
3615         if (pipe == 0 && !IS_I965G(dev)) {
3616                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3617                  * core speed.
3618                  *
3619                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3620                  * pipe == 0 check?
3621                  */
3622                 if (mode->clock >
3623                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3624                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3625                 else
3626                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3627         }
3628
3629         /* Disable the panel fitter if it was on our pipe */
3630         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3631                 I915_WRITE(PFIT_CONTROL, 0);
3632
3633         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3634         drm_mode_debug_printmodeline(mode);
3635
3636         /* assign to Ironlake registers */
3637         if (HAS_PCH_SPLIT(dev)) {
3638                 fp_reg = pch_fp_reg;
3639                 dpll_reg = pch_dpll_reg;
3640         }
3641
3642         if (is_edp) {
3643                 ironlake_disable_pll_edp(crtc);
3644         } else if ((dpll & DPLL_VCO_ENABLE)) {
3645                 I915_WRITE(fp_reg, fp);
3646                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3647                 I915_READ(dpll_reg);
3648                 udelay(150);
3649         }
3650
3651         /* enable transcoder DPLL */
3652         if (HAS_PCH_CPT(dev)) {
3653                 temp = I915_READ(PCH_DPLL_SEL);
3654                 if (trans_dpll_sel == 0)
3655                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3656                 else
3657                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3658                 I915_WRITE(PCH_DPLL_SEL, temp);
3659                 I915_READ(PCH_DPLL_SEL);
3660                 udelay(150);
3661         }
3662
3663         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3664          * This is an exception to the general rule that mode_set doesn't turn
3665          * things on.
3666          */
3667         if (is_lvds) {
3668                 u32 lvds;
3669
3670                 if (HAS_PCH_SPLIT(dev))
3671                         lvds_reg = PCH_LVDS;
3672
3673                 lvds = I915_READ(lvds_reg);
3674                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3675                 if (pipe == 1) {
3676                         if (HAS_PCH_CPT(dev))
3677                                 lvds |= PORT_TRANS_B_SEL_CPT;
3678                         else
3679                                 lvds |= LVDS_PIPEB_SELECT;
3680                 } else {
3681                         if (HAS_PCH_CPT(dev))
3682                                 lvds &= ~PORT_TRANS_SEL_MASK;
3683                         else
3684                                 lvds &= ~LVDS_PIPEB_SELECT;
3685                 }
3686                 /* set the corresponsding LVDS_BORDER bit */
3687                 lvds |= dev_priv->lvds_border_bits;
3688                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3689                  * set the DPLLs for dual-channel mode or not.
3690                  */
3691                 if (clock.p2 == 7)
3692                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3693                 else
3694                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3695
3696                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3697                  * appropriately here, but we need to look more thoroughly into how
3698                  * panels behave in the two modes.
3699                  */
3700                 /* set the dithering flag */
3701                 if (IS_I965G(dev)) {
3702                         if (dev_priv->lvds_dither) {
3703                                 if (HAS_PCH_SPLIT(dev)) {
3704                                         pipeconf |= PIPE_ENABLE_DITHER;
3705                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
3706                                 } else
3707                                         lvds |= LVDS_ENABLE_DITHER;
3708                         } else {
3709                                 if (HAS_PCH_SPLIT(dev)) {
3710                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3711                                         pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3712                                 } else
3713                                         lvds &= ~LVDS_ENABLE_DITHER;
3714                         }
3715                 }
3716                 I915_WRITE(lvds_reg, lvds);
3717                 I915_READ(lvds_reg);
3718         }
3719         if (is_dp)
3720                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3721         else if (HAS_PCH_SPLIT(dev)) {
3722                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3723                 if (pipe == 0) {
3724                         I915_WRITE(TRANSA_DATA_M1, 0);
3725                         I915_WRITE(TRANSA_DATA_N1, 0);
3726                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3727                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3728                 } else {
3729                         I915_WRITE(TRANSB_DATA_M1, 0);
3730                         I915_WRITE(TRANSB_DATA_N1, 0);
3731                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3732                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
3733                 }
3734         }
3735
3736         if (!is_edp) {
3737                 I915_WRITE(fp_reg, fp);
3738                 I915_WRITE(dpll_reg, dpll);
3739                 I915_READ(dpll_reg);
3740                 /* Wait for the clocks to stabilize. */
3741                 udelay(150);
3742
3743                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3744                         if (is_sdvo) {
3745                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3746                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3747                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3748                         } else
3749                                 I915_WRITE(dpll_md_reg, 0);
3750                 } else {
3751                         /* write it again -- the BIOS does, after all */
3752                         I915_WRITE(dpll_reg, dpll);
3753                 }
3754                 I915_READ(dpll_reg);
3755                 /* Wait for the clocks to stabilize. */
3756                 udelay(150);
3757         }
3758
3759         if (is_lvds && has_reduced_clock && i915_powersave) {
3760                 I915_WRITE(fp_reg + 4, fp2);
3761                 intel_crtc->lowfreq_avail = true;
3762                 if (HAS_PIPE_CXSR(dev)) {
3763                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3764                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3765                 }
3766         } else {
3767                 I915_WRITE(fp_reg + 4, fp);
3768                 intel_crtc->lowfreq_avail = false;
3769                 if (HAS_PIPE_CXSR(dev)) {
3770                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3771                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3772                 }
3773         }
3774
3775         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3776                    ((adjusted_mode->crtc_htotal - 1) << 16));
3777         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3778                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3779         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3780                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3781         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3782                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3783         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3784                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3785         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3786                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3787         /* pipesrc and dspsize control the size that is scaled from, which should
3788          * always be the user's requested size.
3789          */
3790         if (!HAS_PCH_SPLIT(dev)) {
3791                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3792                                 (mode->hdisplay - 1));
3793                 I915_WRITE(dsppos_reg, 0);
3794         }
3795         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3796
3797         if (HAS_PCH_SPLIT(dev)) {
3798                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3799                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3800                 I915_WRITE(link_m1_reg, m_n.link_m);
3801                 I915_WRITE(link_n1_reg, m_n.link_n);
3802
3803                 if (is_edp) {
3804                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3805                 } else {
3806                         /* enable FDI RX PLL too */
3807                         temp = I915_READ(fdi_rx_reg);
3808                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3809                         I915_READ(fdi_rx_reg);
3810                         udelay(200);
3811
3812                         /* enable FDI TX PLL too */
3813                         temp = I915_READ(fdi_tx_reg);
3814                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
3815                         I915_READ(fdi_tx_reg);
3816
3817                         /* enable FDI RX PCDCLK */
3818                         temp = I915_READ(fdi_rx_reg);
3819                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
3820                         I915_READ(fdi_rx_reg);
3821                         udelay(200);
3822                 }
3823         }
3824
3825         I915_WRITE(pipeconf_reg, pipeconf);
3826         I915_READ(pipeconf_reg);
3827
3828         intel_wait_for_vblank(dev);
3829
3830         if (IS_IRONLAKE(dev)) {
3831                 /* enable address swizzle for tiling buffer */
3832                 temp = I915_READ(DISP_ARB_CTL);
3833                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3834         }
3835
3836         I915_WRITE(dspcntr_reg, dspcntr);
3837
3838         /* Flush the plane changes */
3839         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3840
3841         if ((IS_I965G(dev) || plane == 0))
3842                 intel_update_fbc(crtc, &crtc->mode);
3843
3844         intel_update_watermarks(dev);
3845
3846         drm_vblank_post_modeset(dev, pipe);
3847
3848         return ret;
3849 }
3850
3851 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3852 void intel_crtc_load_lut(struct drm_crtc *crtc)
3853 {
3854         struct drm_device *dev = crtc->dev;
3855         struct drm_i915_private *dev_priv = dev->dev_private;
3856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3857         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3858         int i;
3859
3860         /* The clocks have to be on to load the palette. */
3861         if (!crtc->enabled)
3862                 return;
3863
3864         /* use legacy palette for Ironlake */
3865         if (HAS_PCH_SPLIT(dev))
3866                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3867                                                    LGC_PALETTE_B;
3868
3869         for (i = 0; i < 256; i++) {
3870                 I915_WRITE(palreg + 4 * i,
3871                            (intel_crtc->lut_r[i] << 16) |
3872                            (intel_crtc->lut_g[i] << 8) |
3873                            intel_crtc->lut_b[i]);
3874         }
3875 }
3876
3877 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3878                                  struct drm_file *file_priv,
3879                                  uint32_t handle,
3880                                  uint32_t width, uint32_t height)
3881 {
3882         struct drm_device *dev = crtc->dev;
3883         struct drm_i915_private *dev_priv = dev->dev_private;
3884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3885         struct drm_gem_object *bo;
3886         struct drm_i915_gem_object *obj_priv;
3887         int pipe = intel_crtc->pipe;
3888         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3889         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3890         uint32_t temp = I915_READ(control);
3891         size_t addr;
3892         int ret;
3893
3894         DRM_DEBUG_KMS("\n");
3895
3896         /* if we want to turn off the cursor ignore width and height */
3897         if (!handle) {
3898                 DRM_DEBUG_KMS("cursor off\n");
3899                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3900                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3901                         temp |= CURSOR_MODE_DISABLE;
3902                 } else {
3903                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3904                 }
3905                 addr = 0;
3906                 bo = NULL;
3907                 mutex_lock(&dev->struct_mutex);
3908                 goto finish;
3909         }
3910
3911         /* Currently we only support 64x64 cursors */
3912         if (width != 64 || height != 64) {
3913                 DRM_ERROR("we currently only support 64x64 cursors\n");
3914                 return -EINVAL;
3915         }
3916
3917         bo = drm_gem_object_lookup(dev, file_priv, handle);
3918         if (!bo)
3919                 return -ENOENT;
3920
3921         obj_priv = to_intel_bo(bo);
3922
3923         if (bo->size < width * height * 4) {
3924                 DRM_ERROR("buffer is to small\n");
3925                 ret = -ENOMEM;
3926                 goto fail;
3927         }
3928
3929         /* we only need to pin inside GTT if cursor is non-phy */
3930         mutex_lock(&dev->struct_mutex);
3931         if (!dev_priv->info->cursor_needs_physical) {
3932                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3933                 if (ret) {
3934                         DRM_ERROR("failed to pin cursor bo\n");
3935                         goto fail_locked;
3936                 }
3937                 addr = obj_priv->gtt_offset;
3938         } else {
3939                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3940                 if (ret) {
3941                         DRM_ERROR("failed to attach phys object\n");
3942                         goto fail_locked;
3943                 }
3944                 addr = obj_priv->phys_obj->handle->busaddr;
3945         }
3946
3947         if (!IS_I9XX(dev))
3948                 I915_WRITE(CURSIZE, (height << 12) | width);
3949
3950         /* Hooray for CUR*CNTR differences */
3951         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3952                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3953                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3954                 temp |= (pipe << 28); /* Connect to correct pipe */
3955         } else {
3956                 temp &= ~(CURSOR_FORMAT_MASK);
3957                 temp |= CURSOR_ENABLE;
3958                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3959         }
3960
3961  finish:
3962         I915_WRITE(control, temp);
3963         I915_WRITE(base, addr);
3964
3965         if (intel_crtc->cursor_bo) {
3966                 if (dev_priv->info->cursor_needs_physical) {
3967                         if (intel_crtc->cursor_bo != bo)
3968                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3969                 } else
3970                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3971                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3972         }
3973
3974         mutex_unlock(&dev->struct_mutex);
3975
3976         intel_crtc->cursor_addr = addr;
3977         intel_crtc->cursor_bo = bo;
3978
3979         return 0;
3980 fail_locked:
3981         mutex_unlock(&dev->struct_mutex);
3982 fail:
3983         drm_gem_object_unreference_unlocked(bo);
3984         return ret;
3985 }
3986
3987 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3988 {
3989         struct drm_device *dev = crtc->dev;
3990         struct drm_i915_private *dev_priv = dev->dev_private;
3991         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3992         struct intel_framebuffer *intel_fb;
3993         int pipe = intel_crtc->pipe;
3994         uint32_t temp = 0;
3995         uint32_t adder;
3996
3997         if (crtc->fb) {
3998                 intel_fb = to_intel_framebuffer(crtc->fb);
3999                 intel_mark_busy(dev, intel_fb->obj);
4000         }
4001
4002         if (x < 0) {
4003                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4004                 x = -x;
4005         }
4006         if (y < 0) {
4007                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4008                 y = -y;
4009         }
4010
4011         temp |= x << CURSOR_X_SHIFT;
4012         temp |= y << CURSOR_Y_SHIFT;
4013
4014         adder = intel_crtc->cursor_addr;
4015         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
4016         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
4017
4018         return 0;
4019 }
4020
4021 /** Sets the color ramps on behalf of RandR */
4022 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4023                                  u16 blue, int regno)
4024 {
4025         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4026
4027         intel_crtc->lut_r[regno] = red >> 8;
4028         intel_crtc->lut_g[regno] = green >> 8;
4029         intel_crtc->lut_b[regno] = blue >> 8;
4030 }
4031
4032 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4033                              u16 *blue, int regno)
4034 {
4035         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4036
4037         *red = intel_crtc->lut_r[regno] << 8;
4038         *green = intel_crtc->lut_g[regno] << 8;
4039         *blue = intel_crtc->lut_b[regno] << 8;
4040 }
4041
4042 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4043                                  u16 *blue, uint32_t size)
4044 {
4045         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4046         int i;
4047
4048         if (size != 256)
4049                 return;
4050
4051         for (i = 0; i < 256; i++) {
4052                 intel_crtc->lut_r[i] = red[i] >> 8;
4053                 intel_crtc->lut_g[i] = green[i] >> 8;
4054                 intel_crtc->lut_b[i] = blue[i] >> 8;
4055         }
4056
4057         intel_crtc_load_lut(crtc);
4058 }
4059
4060 /**
4061  * Get a pipe with a simple mode set on it for doing load-based monitor
4062  * detection.
4063  *
4064  * It will be up to the load-detect code to adjust the pipe as appropriate for
4065  * its requirements.  The pipe will be connected to no other encoders.
4066  *
4067  * Currently this code will only succeed if there is a pipe with no encoders
4068  * configured for it.  In the future, it could choose to temporarily disable
4069  * some outputs to free up a pipe for its use.
4070  *
4071  * \return crtc, or NULL if no pipes are available.
4072  */
4073
4074 /* VESA 640x480x72Hz mode to set on the pipe */
4075 static struct drm_display_mode load_detect_mode = {
4076         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4077                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4078 };
4079
4080 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4081                                             struct drm_connector *connector,
4082                                             struct drm_display_mode *mode,
4083                                             int *dpms_mode)
4084 {
4085         struct intel_crtc *intel_crtc;
4086         struct drm_crtc *possible_crtc;
4087         struct drm_crtc *supported_crtc =NULL;
4088         struct drm_encoder *encoder = &intel_encoder->enc;
4089         struct drm_crtc *crtc = NULL;
4090         struct drm_device *dev = encoder->dev;
4091         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4092         struct drm_crtc_helper_funcs *crtc_funcs;
4093         int i = -1;
4094
4095         /*
4096          * Algorithm gets a little messy:
4097          *   - if the connector already has an assigned crtc, use it (but make
4098          *     sure it's on first)
4099          *   - try to find the first unused crtc that can drive this connector,
4100          *     and use that if we find one
4101          *   - if there are no unused crtcs available, try to use the first
4102          *     one we found that supports the connector
4103          */
4104
4105         /* See if we already have a CRTC for this connector */
4106         if (encoder->crtc) {
4107                 crtc = encoder->crtc;
4108                 /* Make sure the crtc and connector are running */
4109                 intel_crtc = to_intel_crtc(crtc);
4110                 *dpms_mode = intel_crtc->dpms_mode;
4111                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4112                         crtc_funcs = crtc->helper_private;
4113                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4114                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4115                 }
4116                 return crtc;
4117         }
4118
4119         /* Find an unused one (if possible) */
4120         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4121                 i++;
4122                 if (!(encoder->possible_crtcs & (1 << i)))
4123                         continue;
4124                 if (!possible_crtc->enabled) {
4125                         crtc = possible_crtc;
4126                         break;
4127                 }
4128                 if (!supported_crtc)
4129                         supported_crtc = possible_crtc;
4130         }
4131
4132         /*
4133          * If we didn't find an unused CRTC, don't use any.
4134          */
4135         if (!crtc) {
4136                 return NULL;
4137         }
4138
4139         encoder->crtc = crtc;
4140         connector->encoder = encoder;
4141         intel_encoder->load_detect_temp = true;
4142
4143         intel_crtc = to_intel_crtc(crtc);
4144         *dpms_mode = intel_crtc->dpms_mode;
4145
4146         if (!crtc->enabled) {
4147                 if (!mode)
4148                         mode = &load_detect_mode;
4149                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4150         } else {
4151                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4152                         crtc_funcs = crtc->helper_private;
4153                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4154                 }
4155
4156                 /* Add this connector to the crtc */
4157                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4158                 encoder_funcs->commit(encoder);
4159         }
4160         /* let the connector get through one full cycle before testing */
4161         intel_wait_for_vblank(dev);
4162
4163         return crtc;
4164 }
4165
4166 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4167                                     struct drm_connector *connector, int dpms_mode)
4168 {
4169         struct drm_encoder *encoder = &intel_encoder->enc;
4170         struct drm_device *dev = encoder->dev;
4171         struct drm_crtc *crtc = encoder->crtc;
4172         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4173         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4174
4175         if (intel_encoder->load_detect_temp) {
4176                 encoder->crtc = NULL;
4177                 connector->encoder = NULL;
4178                 intel_encoder->load_detect_temp = false;
4179                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4180                 drm_helper_disable_unused_functions(dev);
4181         }
4182
4183         /* Switch crtc and encoder back off if necessary */
4184         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4185                 if (encoder->crtc == crtc)
4186                         encoder_funcs->dpms(encoder, dpms_mode);
4187                 crtc_funcs->dpms(crtc, dpms_mode);
4188         }
4189 }
4190
4191 /* Returns the clock of the currently programmed mode of the given pipe. */
4192 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4193 {
4194         struct drm_i915_private *dev_priv = dev->dev_private;
4195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4196         int pipe = intel_crtc->pipe;
4197         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4198         u32 fp;
4199         intel_clock_t clock;
4200
4201         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4202                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4203         else
4204                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4205
4206         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4207         if (IS_PINEVIEW(dev)) {
4208                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4209                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4210         } else {
4211                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4212                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4213         }
4214
4215         if (IS_I9XX(dev)) {
4216                 if (IS_PINEVIEW(dev))
4217                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4218                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4219                 else
4220                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4221                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4222
4223                 switch (dpll & DPLL_MODE_MASK) {
4224                 case DPLLB_MODE_DAC_SERIAL:
4225                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4226                                 5 : 10;
4227                         break;
4228                 case DPLLB_MODE_LVDS:
4229                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4230                                 7 : 14;
4231                         break;
4232                 default:
4233                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4234                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4235                         return 0;
4236                 }
4237
4238                 /* XXX: Handle the 100Mhz refclk */
4239                 intel_clock(dev, 96000, &clock);
4240         } else {
4241                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4242
4243                 if (is_lvds) {
4244                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4245                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4246                         clock.p2 = 14;
4247
4248                         if ((dpll & PLL_REF_INPUT_MASK) ==
4249                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4250                                 /* XXX: might not be 66MHz */
4251                                 intel_clock(dev, 66000, &clock);
4252                         } else
4253                                 intel_clock(dev, 48000, &clock);
4254                 } else {
4255                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4256                                 clock.p1 = 2;
4257                         else {
4258                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4259                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4260                         }
4261                         if (dpll & PLL_P2_DIVIDE_BY_4)
4262                                 clock.p2 = 4;
4263                         else
4264                                 clock.p2 = 2;
4265
4266                         intel_clock(dev, 48000, &clock);
4267                 }
4268         }
4269
4270         /* XXX: It would be nice to validate the clocks, but we can't reuse
4271          * i830PllIsValid() because it relies on the xf86_config connector
4272          * configuration being accurate, which it isn't necessarily.
4273          */
4274
4275         return clock.dot;
4276 }
4277
4278 /** Returns the currently programmed mode of the given pipe. */
4279 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4280                                              struct drm_crtc *crtc)
4281 {
4282         struct drm_i915_private *dev_priv = dev->dev_private;
4283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4284         int pipe = intel_crtc->pipe;
4285         struct drm_display_mode *mode;
4286         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4287         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4288         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4289         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4290
4291         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4292         if (!mode)
4293                 return NULL;
4294
4295         mode->clock = intel_crtc_clock_get(dev, crtc);
4296         mode->hdisplay = (htot & 0xffff) + 1;
4297         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4298         mode->hsync_start = (hsync & 0xffff) + 1;
4299         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4300         mode->vdisplay = (vtot & 0xffff) + 1;
4301         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4302         mode->vsync_start = (vsync & 0xffff) + 1;
4303         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4304
4305         drm_mode_set_name(mode);
4306         drm_mode_set_crtcinfo(mode, 0);
4307
4308         return mode;
4309 }
4310
4311 #define GPU_IDLE_TIMEOUT 500 /* ms */
4312
4313 /* When this timer fires, we've been idle for awhile */
4314 static void intel_gpu_idle_timer(unsigned long arg)
4315 {
4316         struct drm_device *dev = (struct drm_device *)arg;
4317         drm_i915_private_t *dev_priv = dev->dev_private;
4318
4319         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4320
4321         dev_priv->busy = false;
4322
4323         queue_work(dev_priv->wq, &dev_priv->idle_work);
4324 }
4325
4326 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4327
4328 static void intel_crtc_idle_timer(unsigned long arg)
4329 {
4330         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4331         struct drm_crtc *crtc = &intel_crtc->base;
4332         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4333
4334         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4335
4336         intel_crtc->busy = false;
4337
4338         queue_work(dev_priv->wq, &dev_priv->idle_work);
4339 }
4340
4341 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4342 {
4343         struct drm_device *dev = crtc->dev;
4344         drm_i915_private_t *dev_priv = dev->dev_private;
4345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4346         int pipe = intel_crtc->pipe;
4347         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4348         int dpll = I915_READ(dpll_reg);
4349
4350         if (HAS_PCH_SPLIT(dev))
4351                 return;
4352
4353         if (!dev_priv->lvds_downclock_avail)
4354                 return;
4355
4356         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4357                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4358
4359                 /* Unlock panel regs */
4360                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4361
4362                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4363                 I915_WRITE(dpll_reg, dpll);
4364                 dpll = I915_READ(dpll_reg);
4365                 intel_wait_for_vblank(dev);
4366                 dpll = I915_READ(dpll_reg);
4367                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4368                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4369
4370                 /* ...and lock them again */
4371                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4372         }
4373
4374         /* Schedule downclock */
4375         if (schedule)
4376                 mod_timer(&intel_crtc->idle_timer, jiffies +
4377                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4378 }
4379
4380 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4381 {
4382         struct drm_device *dev = crtc->dev;
4383         drm_i915_private_t *dev_priv = dev->dev_private;
4384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4385         int pipe = intel_crtc->pipe;
4386         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4387         int dpll = I915_READ(dpll_reg);
4388
4389         if (HAS_PCH_SPLIT(dev))
4390                 return;
4391
4392         if (!dev_priv->lvds_downclock_avail)
4393                 return;
4394
4395         /*
4396          * Since this is called by a timer, we should never get here in
4397          * the manual case.
4398          */
4399         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4400                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4401
4402                 /* Unlock panel regs */
4403                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4404
4405                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4406                 I915_WRITE(dpll_reg, dpll);
4407                 dpll = I915_READ(dpll_reg);
4408                 intel_wait_for_vblank(dev);
4409                 dpll = I915_READ(dpll_reg);
4410                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4411                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4412
4413                 /* ...and lock them again */
4414                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4415         }
4416
4417 }
4418
4419 /**
4420  * intel_idle_update - adjust clocks for idleness
4421  * @work: work struct
4422  *
4423  * Either the GPU or display (or both) went idle.  Check the busy status
4424  * here and adjust the CRTC and GPU clocks as necessary.
4425  */
4426 static void intel_idle_update(struct work_struct *work)
4427 {
4428         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4429                                                     idle_work);
4430         struct drm_device *dev = dev_priv->dev;
4431         struct drm_crtc *crtc;
4432         struct intel_crtc *intel_crtc;
4433
4434         if (!i915_powersave)
4435                 return;
4436
4437         mutex_lock(&dev->struct_mutex);
4438
4439         if (IS_I945G(dev) || IS_I945GM(dev)) {
4440                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4441                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4442         }
4443
4444         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4445                 /* Skip inactive CRTCs */
4446                 if (!crtc->fb)
4447                         continue;
4448
4449                 intel_crtc = to_intel_crtc(crtc);
4450                 if (!intel_crtc->busy)
4451                         intel_decrease_pllclock(crtc);
4452         }
4453
4454         mutex_unlock(&dev->struct_mutex);
4455 }
4456
4457 /**
4458  * intel_mark_busy - mark the GPU and possibly the display busy
4459  * @dev: drm device
4460  * @obj: object we're operating on
4461  *
4462  * Callers can use this function to indicate that the GPU is busy processing
4463  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4464  * buffer), we'll also mark the display as busy, so we know to increase its
4465  * clock frequency.
4466  */
4467 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4468 {
4469         drm_i915_private_t *dev_priv = dev->dev_private;
4470         struct drm_crtc *crtc = NULL;
4471         struct intel_framebuffer *intel_fb;
4472         struct intel_crtc *intel_crtc;
4473
4474         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4475                 return;
4476
4477         if (!dev_priv->busy) {
4478                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4479                         u32 fw_blc_self;
4480
4481                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4482                         fw_blc_self = I915_READ(FW_BLC_SELF);
4483                         fw_blc_self &= ~FW_BLC_SELF_EN;
4484                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4485                 }
4486                 dev_priv->busy = true;
4487         } else
4488                 mod_timer(&dev_priv->idle_timer, jiffies +
4489                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4490
4491         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4492                 if (!crtc->fb)
4493                         continue;
4494
4495                 intel_crtc = to_intel_crtc(crtc);
4496                 intel_fb = to_intel_framebuffer(crtc->fb);
4497                 if (intel_fb->obj == obj) {
4498                         if (!intel_crtc->busy) {
4499                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4500                                         u32 fw_blc_self;
4501
4502                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4503                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4504                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4505                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4506                                 }
4507                                 /* Non-busy -> busy, upclock */
4508                                 intel_increase_pllclock(crtc, true);
4509                                 intel_crtc->busy = true;
4510                         } else {
4511                                 /* Busy -> busy, put off timer */
4512                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4513                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4514                         }
4515                 }
4516         }
4517 }
4518
4519 static void intel_crtc_destroy(struct drm_crtc *crtc)
4520 {
4521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4522
4523         drm_crtc_cleanup(crtc);
4524         kfree(intel_crtc);
4525 }
4526
4527 struct intel_unpin_work {
4528         struct work_struct work;
4529         struct drm_device *dev;
4530         struct drm_gem_object *old_fb_obj;
4531         struct drm_gem_object *pending_flip_obj;
4532         struct drm_pending_vblank_event *event;
4533         int pending;
4534 };
4535
4536 static void intel_unpin_work_fn(struct work_struct *__work)
4537 {
4538         struct intel_unpin_work *work =
4539                 container_of(__work, struct intel_unpin_work, work);
4540
4541         mutex_lock(&work->dev->struct_mutex);
4542         i915_gem_object_unpin(work->old_fb_obj);
4543         drm_gem_object_unreference(work->pending_flip_obj);
4544         drm_gem_object_unreference(work->old_fb_obj);
4545         mutex_unlock(&work->dev->struct_mutex);
4546         kfree(work);
4547 }
4548
4549 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4550 {
4551         drm_i915_private_t *dev_priv = dev->dev_private;
4552         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4553         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4554         struct intel_unpin_work *work;
4555         struct drm_i915_gem_object *obj_priv;
4556         struct drm_pending_vblank_event *e;
4557         struct timeval now;
4558         unsigned long flags;
4559
4560         /* Ignore early vblank irqs */
4561         if (intel_crtc == NULL)
4562                 return;
4563
4564         spin_lock_irqsave(&dev->event_lock, flags);
4565         work = intel_crtc->unpin_work;
4566         if (work == NULL || !work->pending) {
4567                 if (work && !work->pending) {
4568                         obj_priv = to_intel_bo(work->pending_flip_obj);
4569                         DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4570                                          obj_priv,
4571                                          atomic_read(&obj_priv->pending_flip));
4572                 }
4573                 spin_unlock_irqrestore(&dev->event_lock, flags);
4574                 return;
4575         }
4576
4577         intel_crtc->unpin_work = NULL;
4578         drm_vblank_put(dev, intel_crtc->pipe);
4579
4580         if (work->event) {
4581                 e = work->event;
4582                 do_gettimeofday(&now);
4583                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4584                 e->event.tv_sec = now.tv_sec;
4585                 e->event.tv_usec = now.tv_usec;
4586                 list_add_tail(&e->base.link,
4587                               &e->base.file_priv->event_list);
4588                 wake_up_interruptible(&e->base.file_priv->event_wait);
4589         }
4590
4591         spin_unlock_irqrestore(&dev->event_lock, flags);
4592
4593         obj_priv = to_intel_bo(work->pending_flip_obj);
4594
4595         /* Initial scanout buffer will have a 0 pending flip count */
4596         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4597             atomic_dec_and_test(&obj_priv->pending_flip))
4598                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4599         schedule_work(&work->work);
4600 }
4601
4602 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4603 {
4604         drm_i915_private_t *dev_priv = dev->dev_private;
4605         struct intel_crtc *intel_crtc =
4606                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4607         unsigned long flags;
4608
4609         spin_lock_irqsave(&dev->event_lock, flags);
4610         if (intel_crtc->unpin_work) {
4611                 intel_crtc->unpin_work->pending = 1;
4612         } else {
4613                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4614         }
4615         spin_unlock_irqrestore(&dev->event_lock, flags);
4616 }
4617
4618 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4619                                 struct drm_framebuffer *fb,
4620                                 struct drm_pending_vblank_event *event)
4621 {
4622         struct drm_device *dev = crtc->dev;
4623         struct drm_i915_private *dev_priv = dev->dev_private;
4624         struct intel_framebuffer *intel_fb;
4625         struct drm_i915_gem_object *obj_priv;
4626         struct drm_gem_object *obj;
4627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4628         struct intel_unpin_work *work;
4629         unsigned long flags;
4630         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4631         int ret, pipesrc;
4632         RING_LOCALS;
4633
4634         work = kzalloc(sizeof *work, GFP_KERNEL);
4635         if (work == NULL)
4636                 return -ENOMEM;
4637
4638         mutex_lock(&dev->struct_mutex);
4639
4640         work->event = event;
4641         work->dev = crtc->dev;
4642         intel_fb = to_intel_framebuffer(crtc->fb);
4643         work->old_fb_obj = intel_fb->obj;
4644         INIT_WORK(&work->work, intel_unpin_work_fn);
4645
4646         /* We borrow the event spin lock for protecting unpin_work */
4647         spin_lock_irqsave(&dev->event_lock, flags);
4648         if (intel_crtc->unpin_work) {
4649                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4650                 spin_unlock_irqrestore(&dev->event_lock, flags);
4651                 kfree(work);
4652                 mutex_unlock(&dev->struct_mutex);
4653                 return -EBUSY;
4654         }
4655         intel_crtc->unpin_work = work;
4656         spin_unlock_irqrestore(&dev->event_lock, flags);
4657
4658         intel_fb = to_intel_framebuffer(fb);
4659         obj = intel_fb->obj;
4660
4661         ret = intel_pin_and_fence_fb_obj(dev, obj);
4662         if (ret != 0) {
4663                 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4664                           to_intel_bo(obj));
4665                 kfree(work);
4666                 intel_crtc->unpin_work = NULL;
4667                 mutex_unlock(&dev->struct_mutex);
4668                 return ret;
4669         }
4670
4671         /* Reference the objects for the scheduled work. */
4672         drm_gem_object_reference(work->old_fb_obj);
4673         drm_gem_object_reference(obj);
4674
4675         crtc->fb = fb;
4676         i915_gem_object_flush_write_domain(obj);
4677         drm_vblank_get(dev, intel_crtc->pipe);
4678         obj_priv = to_intel_bo(obj);
4679         atomic_inc(&obj_priv->pending_flip);
4680         work->pending_flip_obj = obj;
4681
4682         BEGIN_LP_RING(4);
4683         OUT_RING(MI_DISPLAY_FLIP |
4684                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4685         OUT_RING(fb->pitch);
4686         if (IS_I965G(dev)) {
4687                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4688                 pipesrc = I915_READ(pipesrc_reg); 
4689                 OUT_RING(pipesrc & 0x0fff0fff);
4690         } else {
4691                 OUT_RING(obj_priv->gtt_offset);
4692                 OUT_RING(MI_NOOP);
4693         }
4694         ADVANCE_LP_RING();
4695
4696         mutex_unlock(&dev->struct_mutex);
4697
4698         return 0;
4699 }
4700
4701 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4702         .dpms = intel_crtc_dpms,
4703         .mode_fixup = intel_crtc_mode_fixup,
4704         .mode_set = intel_crtc_mode_set,
4705         .mode_set_base = intel_pipe_set_base,
4706         .prepare = intel_crtc_prepare,
4707         .commit = intel_crtc_commit,
4708         .load_lut = intel_crtc_load_lut,
4709 };
4710
4711 static const struct drm_crtc_funcs intel_crtc_funcs = {
4712         .cursor_set = intel_crtc_cursor_set,
4713         .cursor_move = intel_crtc_cursor_move,
4714         .gamma_set = intel_crtc_gamma_set,
4715         .set_config = drm_crtc_helper_set_config,
4716         .destroy = intel_crtc_destroy,
4717         .page_flip = intel_crtc_page_flip,
4718 };
4719
4720
4721 static void intel_crtc_init(struct drm_device *dev, int pipe)
4722 {
4723         drm_i915_private_t *dev_priv = dev->dev_private;
4724         struct intel_crtc *intel_crtc;
4725         int i;
4726
4727         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4728         if (intel_crtc == NULL)
4729                 return;
4730
4731         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4732
4733         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4734         intel_crtc->pipe = pipe;
4735         intel_crtc->plane = pipe;
4736         for (i = 0; i < 256; i++) {
4737                 intel_crtc->lut_r[i] = i;
4738                 intel_crtc->lut_g[i] = i;
4739                 intel_crtc->lut_b[i] = i;
4740         }
4741
4742         /* Swap pipes & planes for FBC on pre-965 */
4743         intel_crtc->pipe = pipe;
4744         intel_crtc->plane = pipe;
4745         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4746                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4747                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4748         }
4749
4750         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4751                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4752         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4753         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4754
4755         intel_crtc->cursor_addr = 0;
4756         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4757         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4758
4759         intel_crtc->busy = false;
4760
4761         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4762                     (unsigned long)intel_crtc);
4763 }
4764
4765 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4766                                 struct drm_file *file_priv)
4767 {
4768         drm_i915_private_t *dev_priv = dev->dev_private;
4769         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4770         struct drm_mode_object *drmmode_obj;
4771         struct intel_crtc *crtc;
4772
4773         if (!dev_priv) {
4774                 DRM_ERROR("called with no initialization\n");
4775                 return -EINVAL;
4776         }
4777
4778         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4779                         DRM_MODE_OBJECT_CRTC);
4780
4781         if (!drmmode_obj) {
4782                 DRM_ERROR("no such CRTC id\n");
4783                 return -EINVAL;
4784         }
4785
4786         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4787         pipe_from_crtc_id->pipe = crtc->pipe;
4788
4789         return 0;
4790 }
4791
4792 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4793 {
4794         struct drm_crtc *crtc = NULL;
4795
4796         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4797                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4798                 if (intel_crtc->pipe == pipe)
4799                         break;
4800         }
4801         return crtc;
4802 }
4803
4804 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
4805 {
4806         int index_mask = 0;
4807         struct drm_encoder *encoder;
4808         int entry = 0;
4809
4810         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4811                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4812                 if (type_mask & intel_encoder->clone_mask)
4813                         index_mask |= (1 << entry);
4814                 entry++;
4815         }
4816         return index_mask;
4817 }
4818
4819
4820 static void intel_setup_outputs(struct drm_device *dev)
4821 {
4822         struct drm_i915_private *dev_priv = dev->dev_private;
4823         struct drm_encoder *encoder;
4824
4825         intel_crt_init(dev);
4826
4827         /* Set up integrated LVDS */
4828         if (IS_MOBILE(dev) && !IS_I830(dev))
4829                 intel_lvds_init(dev);
4830
4831         if (HAS_PCH_SPLIT(dev)) {
4832                 int found;
4833
4834                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4835                         intel_dp_init(dev, DP_A);
4836
4837                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4838                         /* PCH SDVOB multiplex with HDMIB */
4839                         found = intel_sdvo_init(dev, PCH_SDVOB);
4840                         if (!found)
4841                                 intel_hdmi_init(dev, HDMIB);
4842                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4843                                 intel_dp_init(dev, PCH_DP_B);
4844                 }
4845
4846                 if (I915_READ(HDMIC) & PORT_DETECTED)
4847                         intel_hdmi_init(dev, HDMIC);
4848
4849                 if (I915_READ(HDMID) & PORT_DETECTED)
4850                         intel_hdmi_init(dev, HDMID);
4851
4852                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4853                         intel_dp_init(dev, PCH_DP_C);
4854
4855                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4856                         intel_dp_init(dev, PCH_DP_D);
4857
4858         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4859                 bool found = false;
4860
4861                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4862                         DRM_DEBUG_KMS("probing SDVOB\n");
4863                         found = intel_sdvo_init(dev, SDVOB);
4864                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4865                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4866                                 intel_hdmi_init(dev, SDVOB);
4867                         }
4868
4869                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4870                                 DRM_DEBUG_KMS("probing DP_B\n");
4871                                 intel_dp_init(dev, DP_B);
4872                         }
4873                 }
4874
4875                 /* Before G4X SDVOC doesn't have its own detect register */
4876
4877                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4878                         DRM_DEBUG_KMS("probing SDVOC\n");
4879                         found = intel_sdvo_init(dev, SDVOC);
4880                 }
4881
4882                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4883
4884                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4885                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4886                                 intel_hdmi_init(dev, SDVOC);
4887                         }
4888                         if (SUPPORTS_INTEGRATED_DP(dev)) {
4889                                 DRM_DEBUG_KMS("probing DP_C\n");
4890                                 intel_dp_init(dev, DP_C);
4891                         }
4892                 }
4893
4894                 if (SUPPORTS_INTEGRATED_DP(dev) &&
4895                     (I915_READ(DP_D) & DP_DETECTED)) {
4896                         DRM_DEBUG_KMS("probing DP_D\n");
4897                         intel_dp_init(dev, DP_D);
4898                 }
4899         } else if (IS_GEN2(dev))
4900                 intel_dvo_init(dev);
4901
4902         if (SUPPORTS_TV(dev))
4903                 intel_tv_init(dev);
4904
4905         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4906                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4907
4908                 encoder->possible_crtcs = intel_encoder->crtc_mask;
4909                 encoder->possible_clones = intel_encoder_clones(dev,
4910                                                 intel_encoder->clone_mask);
4911         }
4912 }
4913
4914 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4915 {
4916         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4917
4918         drm_framebuffer_cleanup(fb);
4919         drm_gem_object_unreference_unlocked(intel_fb->obj);
4920
4921         kfree(intel_fb);
4922 }
4923
4924 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4925                                                 struct drm_file *file_priv,
4926                                                 unsigned int *handle)
4927 {
4928         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4929         struct drm_gem_object *object = intel_fb->obj;
4930
4931         return drm_gem_handle_create(file_priv, object, handle);
4932 }
4933
4934 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4935         .destroy = intel_user_framebuffer_destroy,
4936         .create_handle = intel_user_framebuffer_create_handle,
4937 };
4938
4939 int intel_framebuffer_init(struct drm_device *dev,
4940                            struct intel_framebuffer *intel_fb,
4941                            struct drm_mode_fb_cmd *mode_cmd,
4942                            struct drm_gem_object *obj)
4943 {
4944         int ret;
4945
4946         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4947         if (ret) {
4948                 DRM_ERROR("framebuffer init failed %d\n", ret);
4949                 return ret;
4950         }
4951
4952         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4953         intel_fb->obj = obj;
4954         return 0;
4955 }
4956
4957 static struct drm_framebuffer *
4958 intel_user_framebuffer_create(struct drm_device *dev,
4959                               struct drm_file *filp,
4960                               struct drm_mode_fb_cmd *mode_cmd)
4961 {
4962         struct drm_gem_object *obj;
4963         struct intel_framebuffer *intel_fb;
4964         int ret;
4965
4966         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4967         if (!obj)
4968                 return NULL;
4969
4970         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4971         if (!intel_fb)
4972                 return NULL;
4973
4974         ret = intel_framebuffer_init(dev, intel_fb,
4975                                      mode_cmd, obj);
4976         if (ret) {
4977                 drm_gem_object_unreference_unlocked(obj);
4978                 kfree(intel_fb);
4979                 return NULL;
4980         }
4981
4982         return &intel_fb->base;
4983 }
4984
4985 static const struct drm_mode_config_funcs intel_mode_funcs = {
4986         .fb_create = intel_user_framebuffer_create,
4987         .output_poll_changed = intel_fb_output_poll_changed,
4988 };
4989
4990 static struct drm_gem_object *
4991 intel_alloc_power_context(struct drm_device *dev)
4992 {
4993         struct drm_gem_object *pwrctx;
4994         int ret;
4995
4996         pwrctx = i915_gem_alloc_object(dev, 4096);
4997         if (!pwrctx) {
4998                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4999                 return NULL;
5000         }
5001
5002         mutex_lock(&dev->struct_mutex);
5003         ret = i915_gem_object_pin(pwrctx, 4096);
5004         if (ret) {
5005                 DRM_ERROR("failed to pin power context: %d\n", ret);
5006                 goto err_unref;
5007         }
5008
5009         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5010         if (ret) {
5011                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5012                 goto err_unpin;
5013         }
5014         mutex_unlock(&dev->struct_mutex);
5015
5016         return pwrctx;
5017
5018 err_unpin:
5019         i915_gem_object_unpin(pwrctx);
5020 err_unref:
5021         drm_gem_object_unreference(pwrctx);
5022         mutex_unlock(&dev->struct_mutex);
5023         return NULL;
5024 }
5025
5026 void ironlake_enable_drps(struct drm_device *dev)
5027 {
5028         struct drm_i915_private *dev_priv = dev->dev_private;
5029         u32 rgvmodectl = I915_READ(MEMMODECTL), rgvswctl;
5030         u8 fmax, fmin, fstart, vstart;
5031         int i = 0;
5032
5033         /* 100ms RC evaluation intervals */
5034         I915_WRITE(RCUPEI, 100000);
5035         I915_WRITE(RCDNEI, 100000);
5036
5037         /* Set max/min thresholds to 90ms and 80ms respectively */
5038         I915_WRITE(RCBMAXAVG, 90000);
5039         I915_WRITE(RCBMINAVG, 80000);
5040
5041         I915_WRITE(MEMIHYST, 1);
5042
5043         /* Set up min, max, and cur for interrupt handling */
5044         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5045         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5046         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5047                 MEMMODE_FSTART_SHIFT;
5048         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5049                 PXVFREQ_PX_SHIFT;
5050
5051         dev_priv->max_delay = fstart; /* can't go to fmax w/o IPS */
5052         dev_priv->min_delay = fmin;
5053         dev_priv->cur_delay = fstart;
5054
5055         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5056
5057         /*
5058          * Interrupts will be enabled in ironlake_irq_postinstall
5059          */
5060
5061         I915_WRITE(VIDSTART, vstart);
5062         POSTING_READ(VIDSTART);
5063
5064         rgvmodectl |= MEMMODE_SWMODE_EN;
5065         I915_WRITE(MEMMODECTL, rgvmodectl);
5066
5067         while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5068                 if (i++ > 100) {
5069                         DRM_ERROR("stuck trying to change perf mode\n");
5070                         break;
5071                 }
5072                 msleep(1);
5073         }
5074         msleep(1);
5075
5076         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5077                 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5078         I915_WRITE(MEMSWCTL, rgvswctl);
5079         POSTING_READ(MEMSWCTL);
5080
5081         rgvswctl |= MEMCTL_CMD_STS;
5082         I915_WRITE(MEMSWCTL, rgvswctl);
5083 }
5084
5085 void ironlake_disable_drps(struct drm_device *dev)
5086 {
5087         struct drm_i915_private *dev_priv = dev->dev_private;
5088         u32 rgvswctl;
5089         u8 fstart;
5090
5091         /* Ack interrupts, disable EFC interrupt */
5092         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5093         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5094         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5095         I915_WRITE(DEIIR, DE_PCU_EVENT);
5096         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5097
5098         /* Go back to the starting frequency */
5099         fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >>
5100                 MEMMODE_FSTART_SHIFT;
5101         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5102                 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5103         I915_WRITE(MEMSWCTL, rgvswctl);
5104         msleep(1);
5105         rgvswctl |= MEMCTL_CMD_STS;
5106         I915_WRITE(MEMSWCTL, rgvswctl);
5107         msleep(1);
5108
5109 }
5110
5111 void intel_init_clock_gating(struct drm_device *dev)
5112 {
5113         struct drm_i915_private *dev_priv = dev->dev_private;
5114
5115         /*
5116          * Disable clock gating reported to work incorrectly according to the
5117          * specs, but enable as much else as we can.
5118          */
5119         if (HAS_PCH_SPLIT(dev)) {
5120                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5121
5122                 if (IS_IRONLAKE(dev)) {
5123                         /* Required for FBC */
5124                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5125                         /* Required for CxSR */
5126                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5127
5128                         I915_WRITE(PCH_3DCGDIS0,
5129                                    MARIUNIT_CLOCK_GATE_DISABLE |
5130                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5131                 }
5132
5133                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5134
5135                 /*
5136                  * According to the spec the following bits should be set in
5137                  * order to enable memory self-refresh
5138                  * The bit 22/21 of 0x42004
5139                  * The bit 5 of 0x42020
5140                  * The bit 15 of 0x45000
5141                  */
5142                 if (IS_IRONLAKE(dev)) {
5143                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5144                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5145                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5146                         I915_WRITE(ILK_DSPCLK_GATE,
5147                                         (I915_READ(ILK_DSPCLK_GATE) |
5148                                                 ILK_DPARB_CLK_GATE));
5149                         I915_WRITE(DISP_ARB_CTL,
5150                                         (I915_READ(DISP_ARB_CTL) |
5151                                                 DISP_FBC_WM_DIS));
5152                 }
5153                 return;
5154         } else if (IS_G4X(dev)) {
5155                 uint32_t dspclk_gate;
5156                 I915_WRITE(RENCLK_GATE_D1, 0);
5157                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5158                        GS_UNIT_CLOCK_GATE_DISABLE |
5159                        CL_UNIT_CLOCK_GATE_DISABLE);
5160                 I915_WRITE(RAMCLK_GATE_D, 0);
5161                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5162                         OVRUNIT_CLOCK_GATE_DISABLE |
5163                         OVCUNIT_CLOCK_GATE_DISABLE;
5164                 if (IS_GM45(dev))
5165                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5166                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5167         } else if (IS_I965GM(dev)) {
5168                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5169                 I915_WRITE(RENCLK_GATE_D2, 0);
5170                 I915_WRITE(DSPCLK_GATE_D, 0);
5171                 I915_WRITE(RAMCLK_GATE_D, 0);
5172                 I915_WRITE16(DEUC, 0);
5173         } else if (IS_I965G(dev)) {
5174                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5175                        I965_RCC_CLOCK_GATE_DISABLE |
5176                        I965_RCPB_CLOCK_GATE_DISABLE |
5177                        I965_ISC_CLOCK_GATE_DISABLE |
5178                        I965_FBC_CLOCK_GATE_DISABLE);
5179                 I915_WRITE(RENCLK_GATE_D2, 0);
5180         } else if (IS_I9XX(dev)) {
5181                 u32 dstate = I915_READ(D_STATE);
5182
5183                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5184                         DSTATE_DOT_CLOCK_GATING;
5185                 I915_WRITE(D_STATE, dstate);
5186         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5187                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5188         } else if (IS_I830(dev)) {
5189                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5190         }
5191
5192         /*
5193          * GPU can automatically power down the render unit if given a page
5194          * to save state.
5195          */
5196         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5197                 struct drm_i915_gem_object *obj_priv = NULL;
5198
5199                 if (dev_priv->pwrctx) {
5200                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5201                 } else {
5202                         struct drm_gem_object *pwrctx;
5203
5204                         pwrctx = intel_alloc_power_context(dev);
5205                         if (pwrctx) {
5206                                 dev_priv->pwrctx = pwrctx;
5207                                 obj_priv = to_intel_bo(pwrctx);
5208                         }
5209                 }
5210
5211                 if (obj_priv) {
5212                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5213                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5214                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5215                 }
5216         }
5217 }
5218
5219 /* Set up chip specific display functions */
5220 static void intel_init_display(struct drm_device *dev)
5221 {
5222         struct drm_i915_private *dev_priv = dev->dev_private;
5223
5224         /* We always want a DPMS function */
5225         if (HAS_PCH_SPLIT(dev))
5226                 dev_priv->display.dpms = ironlake_crtc_dpms;
5227         else
5228                 dev_priv->display.dpms = i9xx_crtc_dpms;
5229
5230         if (I915_HAS_FBC(dev)) {
5231                 if (IS_GM45(dev)) {
5232                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5233                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5234                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5235                 } else if (IS_I965GM(dev)) {
5236                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5237                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5238                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5239                 }
5240                 /* 855GM needs testing */
5241         }
5242
5243         /* Returns the core display clock speed */
5244         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5245                 dev_priv->display.get_display_clock_speed =
5246                         i945_get_display_clock_speed;
5247         else if (IS_I915G(dev))
5248                 dev_priv->display.get_display_clock_speed =
5249                         i915_get_display_clock_speed;
5250         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5251                 dev_priv->display.get_display_clock_speed =
5252                         i9xx_misc_get_display_clock_speed;
5253         else if (IS_I915GM(dev))
5254                 dev_priv->display.get_display_clock_speed =
5255                         i915gm_get_display_clock_speed;
5256         else if (IS_I865G(dev))
5257                 dev_priv->display.get_display_clock_speed =
5258                         i865_get_display_clock_speed;
5259         else if (IS_I85X(dev))
5260                 dev_priv->display.get_display_clock_speed =
5261                         i855_get_display_clock_speed;
5262         else /* 852, 830 */
5263                 dev_priv->display.get_display_clock_speed =
5264                         i830_get_display_clock_speed;
5265
5266         /* For FIFO watermark updates */
5267         if (HAS_PCH_SPLIT(dev)) {
5268                 if (IS_IRONLAKE(dev)) {
5269                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5270                                 dev_priv->display.update_wm = ironlake_update_wm;
5271                         else {
5272                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5273                                               "Disable CxSR\n");
5274                                 dev_priv->display.update_wm = NULL;
5275                         }
5276                 } else
5277                         dev_priv->display.update_wm = NULL;
5278         } else if (IS_PINEVIEW(dev)) {
5279                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5280                                             dev_priv->fsb_freq,
5281                                             dev_priv->mem_freq)) {
5282                         DRM_INFO("failed to find known CxSR latency "
5283                                  "(found fsb freq %d, mem freq %d), "
5284                                  "disabling CxSR\n",
5285                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5286                         /* Disable CxSR and never update its watermark again */
5287                         pineview_disable_cxsr(dev);
5288                         dev_priv->display.update_wm = NULL;
5289                 } else
5290                         dev_priv->display.update_wm = pineview_update_wm;
5291         } else if (IS_G4X(dev))
5292                 dev_priv->display.update_wm = g4x_update_wm;
5293         else if (IS_I965G(dev))
5294                 dev_priv->display.update_wm = i965_update_wm;
5295         else if (IS_I9XX(dev)) {
5296                 dev_priv->display.update_wm = i9xx_update_wm;
5297                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5298         } else if (IS_I85X(dev)) {
5299                 dev_priv->display.update_wm = i9xx_update_wm;
5300                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5301         } else {
5302                 dev_priv->display.update_wm = i830_update_wm;
5303                 if (IS_845G(dev))
5304                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5305                 else
5306                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5307         }
5308 }
5309
5310 void intel_modeset_init(struct drm_device *dev)
5311 {
5312         struct drm_i915_private *dev_priv = dev->dev_private;
5313         int num_pipe;
5314         int i;
5315
5316         drm_mode_config_init(dev);
5317
5318         dev->mode_config.min_width = 0;
5319         dev->mode_config.min_height = 0;
5320
5321         dev->mode_config.funcs = (void *)&intel_mode_funcs;
5322
5323         intel_init_display(dev);
5324
5325         if (IS_I965G(dev)) {
5326                 dev->mode_config.max_width = 8192;
5327                 dev->mode_config.max_height = 8192;
5328         } else if (IS_I9XX(dev)) {
5329                 dev->mode_config.max_width = 4096;
5330                 dev->mode_config.max_height = 4096;
5331         } else {
5332                 dev->mode_config.max_width = 2048;
5333                 dev->mode_config.max_height = 2048;
5334         }
5335
5336         /* set memory base */
5337         if (IS_I9XX(dev))
5338                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5339         else
5340                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5341
5342         if (IS_MOBILE(dev) || IS_I9XX(dev))
5343                 num_pipe = 2;
5344         else
5345                 num_pipe = 1;
5346         DRM_DEBUG_KMS("%d display pipe%s available.\n",
5347                   num_pipe, num_pipe > 1 ? "s" : "");
5348
5349         for (i = 0; i < num_pipe; i++) {
5350                 intel_crtc_init(dev, i);
5351         }
5352
5353         intel_setup_outputs(dev);
5354
5355         intel_init_clock_gating(dev);
5356
5357         if (IS_IRONLAKE_M(dev))
5358                 ironlake_enable_drps(dev);
5359
5360         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
5361         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
5362                     (unsigned long)dev);
5363
5364         intel_setup_overlay(dev);
5365 }
5366
5367 void intel_modeset_cleanup(struct drm_device *dev)
5368 {
5369         struct drm_i915_private *dev_priv = dev->dev_private;
5370         struct drm_crtc *crtc;
5371         struct intel_crtc *intel_crtc;
5372
5373         mutex_lock(&dev->struct_mutex);
5374
5375         drm_kms_helper_poll_fini(dev);
5376         intel_fbdev_fini(dev);
5377
5378         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5379                 /* Skip inactive CRTCs */
5380                 if (!crtc->fb)
5381                         continue;
5382
5383                 intel_crtc = to_intel_crtc(crtc);
5384                 intel_increase_pllclock(crtc, false);
5385                 del_timer_sync(&intel_crtc->idle_timer);
5386         }
5387
5388         del_timer_sync(&dev_priv->idle_timer);
5389
5390         if (dev_priv->display.disable_fbc)
5391                 dev_priv->display.disable_fbc(dev);
5392
5393         if (dev_priv->pwrctx) {
5394                 struct drm_i915_gem_object *obj_priv;
5395
5396                 obj_priv = to_intel_bo(dev_priv->pwrctx);
5397                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
5398                 I915_READ(PWRCTXA);
5399                 i915_gem_object_unpin(dev_priv->pwrctx);
5400                 drm_gem_object_unreference(dev_priv->pwrctx);
5401         }
5402
5403         if (IS_IRONLAKE_M(dev))
5404                 ironlake_disable_drps(dev);
5405
5406         mutex_unlock(&dev->struct_mutex);
5407
5408         drm_mode_config_cleanup(dev);
5409 }
5410
5411
5412 /*
5413  * Return which encoder is currently attached for connector.
5414  */
5415 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
5416 {
5417         struct drm_mode_object *obj;
5418         struct drm_encoder *encoder;
5419         int i;
5420
5421         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5422                 if (connector->encoder_ids[i] == 0)
5423                         break;
5424
5425                 obj = drm_mode_object_find(connector->dev,
5426                                            connector->encoder_ids[i],
5427                                            DRM_MODE_OBJECT_ENCODER);
5428                 if (!obj)
5429                         continue;
5430
5431                 encoder = obj_to_encoder(obj);
5432                 return encoder;
5433         }
5434         return NULL;
5435 }
5436
5437 /*
5438  * set vga decode state - true == enable VGA decode
5439  */
5440 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5441 {
5442         struct drm_i915_private *dev_priv = dev->dev_private;
5443         u16 gmch_ctrl;
5444
5445         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5446         if (state)
5447                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5448         else
5449                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5450         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5451         return 0;
5452 }