dbd9f09465f84cca420c0e3774ce5b9511ce0786
[linux-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include "drmP.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "drm_dp_helper.h"
37
38 #include "drm_crtc_helper.h"
39
40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
41
42 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
43 static void intel_update_watermarks(struct drm_device *dev);
44 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
45
46 typedef struct {
47     /* given values */
48     int n;
49     int m1, m2;
50     int p1, p2;
51     /* derived values */
52     int dot;
53     int vco;
54     int m;
55     int p;
56 } intel_clock_t;
57
58 typedef struct {
59     int min, max;
60 } intel_range_t;
61
62 typedef struct {
63     int dot_limit;
64     int p2_slow, p2_fast;
65 } intel_p2_t;
66
67 #define INTEL_P2_NUM                  2
68 typedef struct intel_limit intel_limit_t;
69 struct intel_limit {
70     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
71     intel_p2_t      p2;
72     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
73                       int, int, intel_clock_t *);
74 };
75
76 #define I8XX_DOT_MIN              25000
77 #define I8XX_DOT_MAX             350000
78 #define I8XX_VCO_MIN             930000
79 #define I8XX_VCO_MAX            1400000
80 #define I8XX_N_MIN                    3
81 #define I8XX_N_MAX                   16
82 #define I8XX_M_MIN                   96
83 #define I8XX_M_MAX                  140
84 #define I8XX_M1_MIN                  18
85 #define I8XX_M1_MAX                  26
86 #define I8XX_M2_MIN                   6
87 #define I8XX_M2_MAX                  16
88 #define I8XX_P_MIN                    4
89 #define I8XX_P_MAX                  128
90 #define I8XX_P1_MIN                   2
91 #define I8XX_P1_MAX                  33
92 #define I8XX_P1_LVDS_MIN              1
93 #define I8XX_P1_LVDS_MAX              6
94 #define I8XX_P2_SLOW                  4
95 #define I8XX_P2_FAST                  2
96 #define I8XX_P2_LVDS_SLOW             14
97 #define I8XX_P2_LVDS_FAST             7
98 #define I8XX_P2_SLOW_LIMIT       165000
99
100 #define I9XX_DOT_MIN              20000
101 #define I9XX_DOT_MAX             400000
102 #define I9XX_VCO_MIN            1400000
103 #define I9XX_VCO_MAX            2800000
104 #define PINEVIEW_VCO_MIN                1700000
105 #define PINEVIEW_VCO_MAX                3500000
106 #define I9XX_N_MIN                    1
107 #define I9XX_N_MAX                    6
108 /* Pineview's Ncounter is a ring counter */
109 #define PINEVIEW_N_MIN                3
110 #define PINEVIEW_N_MAX                6
111 #define I9XX_M_MIN                   70
112 #define I9XX_M_MAX                  120
113 #define PINEVIEW_M_MIN                2
114 #define PINEVIEW_M_MAX              256
115 #define I9XX_M1_MIN                  10
116 #define I9XX_M1_MAX                  22
117 #define I9XX_M2_MIN                   5
118 #define I9XX_M2_MAX                   9
119 /* Pineview M1 is reserved, and must be 0 */
120 #define PINEVIEW_M1_MIN               0
121 #define PINEVIEW_M1_MAX               0
122 #define PINEVIEW_M2_MIN               0
123 #define PINEVIEW_M2_MAX               254
124 #define I9XX_P_SDVO_DAC_MIN           5
125 #define I9XX_P_SDVO_DAC_MAX          80
126 #define I9XX_P_LVDS_MIN               7
127 #define I9XX_P_LVDS_MAX              98
128 #define PINEVIEW_P_LVDS_MIN                   7
129 #define PINEVIEW_P_LVDS_MAX                  112
130 #define I9XX_P1_MIN                   1
131 #define I9XX_P1_MAX                   8
132 #define I9XX_P2_SDVO_DAC_SLOW                10
133 #define I9XX_P2_SDVO_DAC_FAST                 5
134 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
135 #define I9XX_P2_LVDS_SLOW                    14
136 #define I9XX_P2_LVDS_FAST                     7
137 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
138
139 /*The parameter is for SDVO on G4x platform*/
140 #define G4X_DOT_SDVO_MIN           25000
141 #define G4X_DOT_SDVO_MAX           270000
142 #define G4X_VCO_MIN                1750000
143 #define G4X_VCO_MAX                3500000
144 #define G4X_N_SDVO_MIN             1
145 #define G4X_N_SDVO_MAX             4
146 #define G4X_M_SDVO_MIN             104
147 #define G4X_M_SDVO_MAX             138
148 #define G4X_M1_SDVO_MIN            17
149 #define G4X_M1_SDVO_MAX            23
150 #define G4X_M2_SDVO_MIN            5
151 #define G4X_M2_SDVO_MAX            11
152 #define G4X_P_SDVO_MIN             10
153 #define G4X_P_SDVO_MAX             30
154 #define G4X_P1_SDVO_MIN            1
155 #define G4X_P1_SDVO_MAX            3
156 #define G4X_P2_SDVO_SLOW           10
157 #define G4X_P2_SDVO_FAST           10
158 #define G4X_P2_SDVO_LIMIT          270000
159
160 /*The parameter is for HDMI_DAC on G4x platform*/
161 #define G4X_DOT_HDMI_DAC_MIN           22000
162 #define G4X_DOT_HDMI_DAC_MAX           400000
163 #define G4X_N_HDMI_DAC_MIN             1
164 #define G4X_N_HDMI_DAC_MAX             4
165 #define G4X_M_HDMI_DAC_MIN             104
166 #define G4X_M_HDMI_DAC_MAX             138
167 #define G4X_M1_HDMI_DAC_MIN            16
168 #define G4X_M1_HDMI_DAC_MAX            23
169 #define G4X_M2_HDMI_DAC_MIN            5
170 #define G4X_M2_HDMI_DAC_MAX            11
171 #define G4X_P_HDMI_DAC_MIN             5
172 #define G4X_P_HDMI_DAC_MAX             80
173 #define G4X_P1_HDMI_DAC_MIN            1
174 #define G4X_P1_HDMI_DAC_MAX            8
175 #define G4X_P2_HDMI_DAC_SLOW           10
176 #define G4X_P2_HDMI_DAC_FAST           5
177 #define G4X_P2_HDMI_DAC_LIMIT          165000
178
179 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
197
198 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
201 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
202 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
203 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
204 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
209 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
210 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
213 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
216
217 /*The parameter is for DISPLAY PORT on G4x platform*/
218 #define G4X_DOT_DISPLAY_PORT_MIN           161670
219 #define G4X_DOT_DISPLAY_PORT_MAX           227000
220 #define G4X_N_DISPLAY_PORT_MIN             1
221 #define G4X_N_DISPLAY_PORT_MAX             2
222 #define G4X_M_DISPLAY_PORT_MIN             97
223 #define G4X_M_DISPLAY_PORT_MAX             108
224 #define G4X_M1_DISPLAY_PORT_MIN            0x10
225 #define G4X_M1_DISPLAY_PORT_MAX            0x12
226 #define G4X_M2_DISPLAY_PORT_MIN            0x05
227 #define G4X_M2_DISPLAY_PORT_MAX            0x06
228 #define G4X_P_DISPLAY_PORT_MIN             10
229 #define G4X_P_DISPLAY_PORT_MAX             20
230 #define G4X_P1_DISPLAY_PORT_MIN            1
231 #define G4X_P1_DISPLAY_PORT_MAX            2
232 #define G4X_P2_DISPLAY_PORT_SLOW           10
233 #define G4X_P2_DISPLAY_PORT_FAST           10
234 #define G4X_P2_DISPLAY_PORT_LIMIT          0
235
236 /* Ironlake / Sandybridge */
237 /* as we calculate clock using (register_value + 2) for
238    N/M1/M2, so here the range value for them is (actual_value-2).
239  */
240 #define IRONLAKE_DOT_MIN         25000
241 #define IRONLAKE_DOT_MAX         350000
242 #define IRONLAKE_VCO_MIN         1760000
243 #define IRONLAKE_VCO_MAX         3510000
244 #define IRONLAKE_M1_MIN          12
245 #define IRONLAKE_M1_MAX          22
246 #define IRONLAKE_M2_MIN          5
247 #define IRONLAKE_M2_MAX          9
248 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
249
250 /* We have parameter ranges for different type of outputs. */
251
252 /* DAC & HDMI Refclk 120Mhz */
253 #define IRONLAKE_DAC_N_MIN      1
254 #define IRONLAKE_DAC_N_MAX      5
255 #define IRONLAKE_DAC_M_MIN      79
256 #define IRONLAKE_DAC_M_MAX      127
257 #define IRONLAKE_DAC_P_MIN      5
258 #define IRONLAKE_DAC_P_MAX      80
259 #define IRONLAKE_DAC_P1_MIN     1
260 #define IRONLAKE_DAC_P1_MAX     8
261 #define IRONLAKE_DAC_P2_SLOW    10
262 #define IRONLAKE_DAC_P2_FAST    5
263
264 /* LVDS single-channel 120Mhz refclk */
265 #define IRONLAKE_LVDS_S_N_MIN   1
266 #define IRONLAKE_LVDS_S_N_MAX   3
267 #define IRONLAKE_LVDS_S_M_MIN   79
268 #define IRONLAKE_LVDS_S_M_MAX   118
269 #define IRONLAKE_LVDS_S_P_MIN   28
270 #define IRONLAKE_LVDS_S_P_MAX   112
271 #define IRONLAKE_LVDS_S_P1_MIN  2
272 #define IRONLAKE_LVDS_S_P1_MAX  8
273 #define IRONLAKE_LVDS_S_P2_SLOW 14
274 #define IRONLAKE_LVDS_S_P2_FAST 14
275
276 /* LVDS dual-channel 120Mhz refclk */
277 #define IRONLAKE_LVDS_D_N_MIN   1
278 #define IRONLAKE_LVDS_D_N_MAX   3
279 #define IRONLAKE_LVDS_D_M_MIN   79
280 #define IRONLAKE_LVDS_D_M_MAX   127
281 #define IRONLAKE_LVDS_D_P_MIN   14
282 #define IRONLAKE_LVDS_D_P_MAX   56
283 #define IRONLAKE_LVDS_D_P1_MIN  2
284 #define IRONLAKE_LVDS_D_P1_MAX  8
285 #define IRONLAKE_LVDS_D_P2_SLOW 7
286 #define IRONLAKE_LVDS_D_P2_FAST 7
287
288 /* LVDS single-channel 100Mhz refclk */
289 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
290 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
291 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
292 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
293 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
294 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
295 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
296 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
297 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
298 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
299
300 /* LVDS dual-channel 100Mhz refclk */
301 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
302 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
303 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
304 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
305 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
306 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
307 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
308 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
309 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
310 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
311
312 /* DisplayPort */
313 #define IRONLAKE_DP_N_MIN               1
314 #define IRONLAKE_DP_N_MAX               2
315 #define IRONLAKE_DP_M_MIN               81
316 #define IRONLAKE_DP_M_MAX               90
317 #define IRONLAKE_DP_P_MIN               10
318 #define IRONLAKE_DP_P_MAX               20
319 #define IRONLAKE_DP_P2_FAST             10
320 #define IRONLAKE_DP_P2_SLOW             10
321 #define IRONLAKE_DP_P2_LIMIT            0
322 #define IRONLAKE_DP_P1_MIN              1
323 #define IRONLAKE_DP_P1_MAX              2
324
325 static bool
326 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
327                     int target, int refclk, intel_clock_t *best_clock);
328 static bool
329 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
330                         int target, int refclk, intel_clock_t *best_clock);
331
332 static bool
333 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
334                       int target, int refclk, intel_clock_t *best_clock);
335 static bool
336 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
337                            int target, int refclk, intel_clock_t *best_clock);
338
339 static const intel_limit_t intel_limits_i8xx_dvo = {
340         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
341         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
342         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
343         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
344         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
345         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
346         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
347         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
348         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
349                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
350         .find_pll = intel_find_best_PLL,
351 };
352
353 static const intel_limit_t intel_limits_i8xx_lvds = {
354         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
355         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
356         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
357         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
358         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
359         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
360         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
361         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
362         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
363                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
364         .find_pll = intel_find_best_PLL,
365 };
366         
367 static const intel_limit_t intel_limits_i9xx_sdvo = {
368         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
369         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
370         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
371         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
372         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
373         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
374         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
375         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
376         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
377                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
378         .find_pll = intel_find_best_PLL,
379 };
380
381 static const intel_limit_t intel_limits_i9xx_lvds = {
382         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
383         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
384         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
385         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
386         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
387         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
388         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
389         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
390         /* The single-channel range is 25-112Mhz, and dual-channel
391          * is 80-224Mhz.  Prefer single channel as much as possible.
392          */
393         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
394                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
395         .find_pll = intel_find_best_PLL,
396 };
397
398     /* below parameter and function is for G4X Chipset Family*/
399 static const intel_limit_t intel_limits_g4x_sdvo = {
400         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
401         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
402         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
403         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
404         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
405         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
406         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
407         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
408         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
409                  .p2_slow = G4X_P2_SDVO_SLOW,
410                  .p2_fast = G4X_P2_SDVO_FAST
411         },
412         .find_pll = intel_g4x_find_best_PLL,
413 };
414
415 static const intel_limit_t intel_limits_g4x_hdmi = {
416         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
418         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
419         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
420         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
421         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
422         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
423         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
424         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
425                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
426                  .p2_fast = G4X_P2_HDMI_DAC_FAST
427         },
428         .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
432         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
433                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
434         .vco = { .min = G4X_VCO_MIN,
435                  .max = G4X_VCO_MAX },
436         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
437                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
438         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
439                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
440         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
441                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
442         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
443                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
444         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
445                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
446         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
447                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
448         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
449                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
450                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
451         },
452         .find_pll = intel_g4x_find_best_PLL,
453 };
454
455 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
456         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
457                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
458         .vco = { .min = G4X_VCO_MIN,
459                  .max = G4X_VCO_MAX },
460         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
461                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
462         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
463                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
464         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
465                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
466         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
467                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
468         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
469                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
470         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
471                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
472         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
473                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
474                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
475         },
476         .find_pll = intel_g4x_find_best_PLL,
477 };
478
479 static const intel_limit_t intel_limits_g4x_display_port = {
480         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
481                  .max = G4X_DOT_DISPLAY_PORT_MAX },
482         .vco = { .min = G4X_VCO_MIN,
483                  .max = G4X_VCO_MAX},
484         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
485                  .max = G4X_N_DISPLAY_PORT_MAX },
486         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
487                  .max = G4X_M_DISPLAY_PORT_MAX },
488         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
489                  .max = G4X_M1_DISPLAY_PORT_MAX },
490         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
491                  .max = G4X_M2_DISPLAY_PORT_MAX },
492         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
493                  .max = G4X_P_DISPLAY_PORT_MAX },
494         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
495                  .max = G4X_P1_DISPLAY_PORT_MAX},
496         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
497                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
498                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
499         .find_pll = intel_find_pll_g4x_dp,
500 };
501
502 static const intel_limit_t intel_limits_pineview_sdvo = {
503         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
504         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
505         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
506         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
507         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
508         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
509         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
510         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
511         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
512                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
513         .find_pll = intel_find_best_PLL,
514 };
515
516 static const intel_limit_t intel_limits_pineview_lvds = {
517         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
518         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
519         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
520         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
521         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
522         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
523         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
524         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
525         /* Pineview only supports single-channel mode. */
526         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
527                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
528         .find_pll = intel_find_best_PLL,
529 };
530
531 static const intel_limit_t intel_limits_ironlake_dac = {
532         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
533         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
534         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
535         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
536         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
537         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
538         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
539         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
540         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
541                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
542                  .p2_fast = IRONLAKE_DAC_P2_FAST },
543         .find_pll = intel_g4x_find_best_PLL,
544 };
545
546 static const intel_limit_t intel_limits_ironlake_single_lvds = {
547         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
548         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
549         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
550         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
551         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
552         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
553         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
554         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
555         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
556                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
557                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
558         .find_pll = intel_g4x_find_best_PLL,
559 };
560
561 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
562         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
563         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
564         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
565         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
566         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
567         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
568         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
569         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
570         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
571                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
572                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
573         .find_pll = intel_g4x_find_best_PLL,
574 };
575
576 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
577         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
578         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
579         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
580         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
581         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
582         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
583         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
584         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
585         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
586                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
587                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
588         .find_pll = intel_g4x_find_best_PLL,
589 };
590
591 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
592         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
593         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
594         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
595         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
596         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
597         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
598         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
599         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
600         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
601                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
602                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
603         .find_pll = intel_g4x_find_best_PLL,
604 };
605
606 static const intel_limit_t intel_limits_ironlake_display_port = {
607         .dot = { .min = IRONLAKE_DOT_MIN,
608                  .max = IRONLAKE_DOT_MAX },
609         .vco = { .min = IRONLAKE_VCO_MIN,
610                  .max = IRONLAKE_VCO_MAX},
611         .n   = { .min = IRONLAKE_DP_N_MIN,
612                  .max = IRONLAKE_DP_N_MAX },
613         .m   = { .min = IRONLAKE_DP_M_MIN,
614                  .max = IRONLAKE_DP_M_MAX },
615         .m1  = { .min = IRONLAKE_M1_MIN,
616                  .max = IRONLAKE_M1_MAX },
617         .m2  = { .min = IRONLAKE_M2_MIN,
618                  .max = IRONLAKE_M2_MAX },
619         .p   = { .min = IRONLAKE_DP_P_MIN,
620                  .max = IRONLAKE_DP_P_MAX },
621         .p1  = { .min = IRONLAKE_DP_P1_MIN,
622                  .max = IRONLAKE_DP_P1_MAX},
623         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
624                  .p2_slow = IRONLAKE_DP_P2_SLOW,
625                  .p2_fast = IRONLAKE_DP_P2_FAST },
626         .find_pll = intel_find_pll_ironlake_dp,
627 };
628
629 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
630 {
631         struct drm_device *dev = crtc->dev;
632         struct drm_i915_private *dev_priv = dev->dev_private;
633         const intel_limit_t *limit;
634         int refclk = 120;
635
636         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
637                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
638                         refclk = 100;
639
640                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
641                     LVDS_CLKB_POWER_UP) {
642                         /* LVDS dual channel */
643                         if (refclk == 100)
644                                 limit = &intel_limits_ironlake_dual_lvds_100m;
645                         else
646                                 limit = &intel_limits_ironlake_dual_lvds;
647                 } else {
648                         if (refclk == 100)
649                                 limit = &intel_limits_ironlake_single_lvds_100m;
650                         else
651                                 limit = &intel_limits_ironlake_single_lvds;
652                 }
653         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
654                         HAS_eDP)
655                 limit = &intel_limits_ironlake_display_port;
656         else
657                 limit = &intel_limits_ironlake_dac;
658
659         return limit;
660 }
661
662 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
663 {
664         struct drm_device *dev = crtc->dev;
665         struct drm_i915_private *dev_priv = dev->dev_private;
666         const intel_limit_t *limit;
667
668         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
669                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
670                     LVDS_CLKB_POWER_UP)
671                         /* LVDS with dual channel */
672                         limit = &intel_limits_g4x_dual_channel_lvds;
673                 else
674                         /* LVDS with dual channel */
675                         limit = &intel_limits_g4x_single_channel_lvds;
676         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
677                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
678                 limit = &intel_limits_g4x_hdmi;
679         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
680                 limit = &intel_limits_g4x_sdvo;
681         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
682                 limit = &intel_limits_g4x_display_port;
683         } else /* The option is for other outputs */
684                 limit = &intel_limits_i9xx_sdvo;
685
686         return limit;
687 }
688
689 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
690 {
691         struct drm_device *dev = crtc->dev;
692         const intel_limit_t *limit;
693
694         if (HAS_PCH_SPLIT(dev))
695                 limit = intel_ironlake_limit(crtc);
696         else if (IS_G4X(dev)) {
697                 limit = intel_g4x_limit(crtc);
698         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
699                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
700                         limit = &intel_limits_i9xx_lvds;
701                 else
702                         limit = &intel_limits_i9xx_sdvo;
703         } else if (IS_PINEVIEW(dev)) {
704                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
705                         limit = &intel_limits_pineview_lvds;
706                 else
707                         limit = &intel_limits_pineview_sdvo;
708         } else {
709                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
710                         limit = &intel_limits_i8xx_lvds;
711                 else
712                         limit = &intel_limits_i8xx_dvo;
713         }
714         return limit;
715 }
716
717 /* m1 is reserved as 0 in Pineview, n is a ring counter */
718 static void pineview_clock(int refclk, intel_clock_t *clock)
719 {
720         clock->m = clock->m2 + 2;
721         clock->p = clock->p1 * clock->p2;
722         clock->vco = refclk * clock->m / clock->n;
723         clock->dot = clock->vco / clock->p;
724 }
725
726 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
727 {
728         if (IS_PINEVIEW(dev)) {
729                 pineview_clock(refclk, clock);
730                 return;
731         }
732         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
733         clock->p = clock->p1 * clock->p2;
734         clock->vco = refclk * clock->m / (clock->n + 2);
735         clock->dot = clock->vco / clock->p;
736 }
737
738 /**
739  * Returns whether any output on the specified pipe is of the specified type
740  */
741 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
742 {
743     struct drm_device *dev = crtc->dev;
744     struct drm_mode_config *mode_config = &dev->mode_config;
745     struct drm_encoder *l_entry;
746
747     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
748             if (l_entry && l_entry->crtc == crtc) {
749                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
750                     if (intel_encoder->type == type)
751                             return true;
752             }
753     }
754     return false;
755 }
756
757 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
758 /**
759  * Returns whether the given set of divisors are valid for a given refclk with
760  * the given connectors.
761  */
762
763 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
764 {
765         const intel_limit_t *limit = intel_limit (crtc);
766         struct drm_device *dev = crtc->dev;
767
768         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
769                 INTELPllInvalid ("p1 out of range\n");
770         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
771                 INTELPllInvalid ("p out of range\n");
772         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
773                 INTELPllInvalid ("m2 out of range\n");
774         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
775                 INTELPllInvalid ("m1 out of range\n");
776         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
777                 INTELPllInvalid ("m1 <= m2\n");
778         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
779                 INTELPllInvalid ("m out of range\n");
780         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
781                 INTELPllInvalid ("n out of range\n");
782         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
783                 INTELPllInvalid ("vco out of range\n");
784         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
785          * connector, etc., rather than just a single range.
786          */
787         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
788                 INTELPllInvalid ("dot out of range\n");
789
790         return true;
791 }
792
793 static bool
794 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
795                     int target, int refclk, intel_clock_t *best_clock)
796
797 {
798         struct drm_device *dev = crtc->dev;
799         struct drm_i915_private *dev_priv = dev->dev_private;
800         intel_clock_t clock;
801         int err = target;
802
803         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
804             (I915_READ(LVDS)) != 0) {
805                 /*
806                  * For LVDS, if the panel is on, just rely on its current
807                  * settings for dual-channel.  We haven't figured out how to
808                  * reliably set up different single/dual channel state, if we
809                  * even can.
810                  */
811                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
812                     LVDS_CLKB_POWER_UP)
813                         clock.p2 = limit->p2.p2_fast;
814                 else
815                         clock.p2 = limit->p2.p2_slow;
816         } else {
817                 if (target < limit->p2.dot_limit)
818                         clock.p2 = limit->p2.p2_slow;
819                 else
820                         clock.p2 = limit->p2.p2_fast;
821         }
822
823         memset (best_clock, 0, sizeof (*best_clock));
824
825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826              clock.m1++) {
827                 for (clock.m2 = limit->m2.min;
828                      clock.m2 <= limit->m2.max; clock.m2++) {
829                         /* m1 is always 0 in Pineview */
830                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
831                                 break;
832                         for (clock.n = limit->n.min;
833                              clock.n <= limit->n.max; clock.n++) {
834                                 for (clock.p1 = limit->p1.min;
835                                         clock.p1 <= limit->p1.max; clock.p1++) {
836                                         int this_err;
837
838                                         intel_clock(dev, refclk, &clock);
839
840                                         if (!intel_PLL_is_valid(crtc, &clock))
841                                                 continue;
842
843                                         this_err = abs(clock.dot - target);
844                                         if (this_err < err) {
845                                                 *best_clock = clock;
846                                                 err = this_err;
847                                         }
848                                 }
849                         }
850                 }
851         }
852
853         return (err != target);
854 }
855
856 static bool
857 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
858                         int target, int refclk, intel_clock_t *best_clock)
859 {
860         struct drm_device *dev = crtc->dev;
861         struct drm_i915_private *dev_priv = dev->dev_private;
862         intel_clock_t clock;
863         int max_n;
864         bool found;
865         /* approximately equals target * 0.00585 */
866         int err_most = (target >> 8) + (target >> 9);
867         found = false;
868
869         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
870                 int lvds_reg;
871
872                 if (HAS_PCH_SPLIT(dev))
873                         lvds_reg = PCH_LVDS;
874                 else
875                         lvds_reg = LVDS;
876                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
877                     LVDS_CLKB_POWER_UP)
878                         clock.p2 = limit->p2.p2_fast;
879                 else
880                         clock.p2 = limit->p2.p2_slow;
881         } else {
882                 if (target < limit->p2.dot_limit)
883                         clock.p2 = limit->p2.p2_slow;
884                 else
885                         clock.p2 = limit->p2.p2_fast;
886         }
887
888         memset(best_clock, 0, sizeof(*best_clock));
889         max_n = limit->n.max;
890         /* based on hardware requirement, prefer smaller n to precision */
891         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
892                 /* based on hardware requirement, prefere larger m1,m2 */
893                 for (clock.m1 = limit->m1.max;
894                      clock.m1 >= limit->m1.min; clock.m1--) {
895                         for (clock.m2 = limit->m2.max;
896                              clock.m2 >= limit->m2.min; clock.m2--) {
897                                 for (clock.p1 = limit->p1.max;
898                                      clock.p1 >= limit->p1.min; clock.p1--) {
899                                         int this_err;
900
901                                         intel_clock(dev, refclk, &clock);
902                                         if (!intel_PLL_is_valid(crtc, &clock))
903                                                 continue;
904                                         this_err = abs(clock.dot - target) ;
905                                         if (this_err < err_most) {
906                                                 *best_clock = clock;
907                                                 err_most = this_err;
908                                                 max_n = clock.n;
909                                                 found = true;
910                                         }
911                                 }
912                         }
913                 }
914         }
915         return found;
916 }
917
918 static bool
919 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
920                            int target, int refclk, intel_clock_t *best_clock)
921 {
922         struct drm_device *dev = crtc->dev;
923         intel_clock_t clock;
924
925         /* return directly when it is eDP */
926         if (HAS_eDP)
927                 return true;
928
929         if (target < 200000) {
930                 clock.n = 1;
931                 clock.p1 = 2;
932                 clock.p2 = 10;
933                 clock.m1 = 12;
934                 clock.m2 = 9;
935         } else {
936                 clock.n = 2;
937                 clock.p1 = 1;
938                 clock.p2 = 10;
939                 clock.m1 = 14;
940                 clock.m2 = 8;
941         }
942         intel_clock(dev, refclk, &clock);
943         memcpy(best_clock, &clock, sizeof(intel_clock_t));
944         return true;
945 }
946
947 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
948 static bool
949 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
950                       int target, int refclk, intel_clock_t *best_clock)
951 {
952     intel_clock_t clock;
953     if (target < 200000) {
954         clock.p1 = 2;
955         clock.p2 = 10;
956         clock.n = 2;
957         clock.m1 = 23;
958         clock.m2 = 8;
959     } else {
960         clock.p1 = 1;
961         clock.p2 = 10;
962         clock.n = 1;
963         clock.m1 = 14;
964         clock.m2 = 2;
965     }
966     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
967     clock.p = (clock.p1 * clock.p2);
968     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
969     clock.vco = 0;
970     memcpy(best_clock, &clock, sizeof(intel_clock_t));
971     return true;
972 }
973
974 void
975 intel_wait_for_vblank(struct drm_device *dev)
976 {
977         /* Wait for 20ms, i.e. one cycle at 50hz. */
978         msleep(20);
979 }
980
981 /* Parameters have changed, update FBC info */
982 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
983 {
984         struct drm_device *dev = crtc->dev;
985         struct drm_i915_private *dev_priv = dev->dev_private;
986         struct drm_framebuffer *fb = crtc->fb;
987         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
988         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
989         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
990         int plane, i;
991         u32 fbc_ctl, fbc_ctl2;
992
993         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
994
995         if (fb->pitch < dev_priv->cfb_pitch)
996                 dev_priv->cfb_pitch = fb->pitch;
997
998         /* FBC_CTL wants 64B units */
999         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1000         dev_priv->cfb_fence = obj_priv->fence_reg;
1001         dev_priv->cfb_plane = intel_crtc->plane;
1002         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1003
1004         /* Clear old tags */
1005         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1006                 I915_WRITE(FBC_TAG + (i * 4), 0);
1007
1008         /* Set it up... */
1009         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1010         if (obj_priv->tiling_mode != I915_TILING_NONE)
1011                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1012         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1013         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1014
1015         /* enable it... */
1016         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1017         if (IS_I945GM(dev))
1018                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1019         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1020         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1021         if (obj_priv->tiling_mode != I915_TILING_NONE)
1022                 fbc_ctl |= dev_priv->cfb_fence;
1023         I915_WRITE(FBC_CONTROL, fbc_ctl);
1024
1025         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1026                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1027 }
1028
1029 void i8xx_disable_fbc(struct drm_device *dev)
1030 {
1031         struct drm_i915_private *dev_priv = dev->dev_private;
1032         unsigned long timeout = jiffies + msecs_to_jiffies(1);
1033         u32 fbc_ctl;
1034
1035         if (!I915_HAS_FBC(dev))
1036                 return;
1037
1038         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1039                 return; /* Already off, just return */
1040
1041         /* Disable compression */
1042         fbc_ctl = I915_READ(FBC_CONTROL);
1043         fbc_ctl &= ~FBC_CTL_EN;
1044         I915_WRITE(FBC_CONTROL, fbc_ctl);
1045
1046         /* Wait for compressing bit to clear */
1047         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1048                 if (time_after(jiffies, timeout)) {
1049                         DRM_DEBUG_DRIVER("FBC idle timed out\n");
1050                         break;
1051                 }
1052                 ; /* do nothing */
1053         }
1054
1055         intel_wait_for_vblank(dev);
1056
1057         DRM_DEBUG_KMS("disabled FBC\n");
1058 }
1059
1060 static bool i8xx_fbc_enabled(struct drm_device *dev)
1061 {
1062         struct drm_i915_private *dev_priv = dev->dev_private;
1063
1064         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1065 }
1066
1067 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1068 {
1069         struct drm_device *dev = crtc->dev;
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071         struct drm_framebuffer *fb = crtc->fb;
1072         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1073         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1075         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1076                      DPFC_CTL_PLANEB);
1077         unsigned long stall_watermark = 200;
1078         u32 dpfc_ctl;
1079
1080         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1081         dev_priv->cfb_fence = obj_priv->fence_reg;
1082         dev_priv->cfb_plane = intel_crtc->plane;
1083
1084         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1085         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1086                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1087                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1088         } else {
1089                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1090         }
1091
1092         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1093         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1094                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1095                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1096         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1097
1098         /* enable it... */
1099         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1100
1101         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1102 }
1103
1104 void g4x_disable_fbc(struct drm_device *dev)
1105 {
1106         struct drm_i915_private *dev_priv = dev->dev_private;
1107         u32 dpfc_ctl;
1108
1109         /* Disable compression */
1110         dpfc_ctl = I915_READ(DPFC_CONTROL);
1111         dpfc_ctl &= ~DPFC_CTL_EN;
1112         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1113         intel_wait_for_vblank(dev);
1114
1115         DRM_DEBUG_KMS("disabled FBC\n");
1116 }
1117
1118 static bool g4x_fbc_enabled(struct drm_device *dev)
1119 {
1120         struct drm_i915_private *dev_priv = dev->dev_private;
1121
1122         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1123 }
1124
1125 bool intel_fbc_enabled(struct drm_device *dev)
1126 {
1127         struct drm_i915_private *dev_priv = dev->dev_private;
1128
1129         if (!dev_priv->display.fbc_enabled)
1130                 return false;
1131
1132         return dev_priv->display.fbc_enabled(dev);
1133 }
1134
1135 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1136 {
1137         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1138
1139         if (!dev_priv->display.enable_fbc)
1140                 return;
1141
1142         dev_priv->display.enable_fbc(crtc, interval);
1143 }
1144
1145 void intel_disable_fbc(struct drm_device *dev)
1146 {
1147         struct drm_i915_private *dev_priv = dev->dev_private;
1148
1149         if (!dev_priv->display.disable_fbc)
1150                 return;
1151
1152         dev_priv->display.disable_fbc(dev);
1153 }
1154
1155 /**
1156  * intel_update_fbc - enable/disable FBC as needed
1157  * @crtc: CRTC to point the compressor at
1158  * @mode: mode in use
1159  *
1160  * Set up the framebuffer compression hardware at mode set time.  We
1161  * enable it if possible:
1162  *   - plane A only (on pre-965)
1163  *   - no pixel mulitply/line duplication
1164  *   - no alpha buffer discard
1165  *   - no dual wide
1166  *   - framebuffer <= 2048 in width, 1536 in height
1167  *
1168  * We can't assume that any compression will take place (worst case),
1169  * so the compressed buffer has to be the same size as the uncompressed
1170  * one.  It also must reside (along with the line length buffer) in
1171  * stolen memory.
1172  *
1173  * We need to enable/disable FBC on a global basis.
1174  */
1175 static void intel_update_fbc(struct drm_crtc *crtc,
1176                              struct drm_display_mode *mode)
1177 {
1178         struct drm_device *dev = crtc->dev;
1179         struct drm_i915_private *dev_priv = dev->dev_private;
1180         struct drm_framebuffer *fb = crtc->fb;
1181         struct intel_framebuffer *intel_fb;
1182         struct drm_i915_gem_object *obj_priv;
1183         struct drm_crtc *tmp_crtc;
1184         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1185         int plane = intel_crtc->plane;
1186         int crtcs_enabled = 0;
1187
1188         DRM_DEBUG_KMS("\n");
1189
1190         if (!i915_powersave)
1191                 return;
1192
1193         if (!I915_HAS_FBC(dev))
1194                 return;
1195
1196         if (!crtc->fb)
1197                 return;
1198
1199         intel_fb = to_intel_framebuffer(fb);
1200         obj_priv = to_intel_bo(intel_fb->obj);
1201
1202         /*
1203          * If FBC is already on, we just have to verify that we can
1204          * keep it that way...
1205          * Need to disable if:
1206          *   - more than one pipe is active
1207          *   - changing FBC params (stride, fence, mode)
1208          *   - new fb is too large to fit in compressed buffer
1209          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1210          */
1211         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1212                 if (tmp_crtc->enabled)
1213                         crtcs_enabled++;
1214         }
1215         DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1216         if (crtcs_enabled > 1) {
1217                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1218                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1219                 goto out_disable;
1220         }
1221         if (intel_fb->obj->size > dev_priv->cfb_size) {
1222                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1223                                 "compression\n");
1224                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1225                 goto out_disable;
1226         }
1227         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1228             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1229                 DRM_DEBUG_KMS("mode incompatible with compression, "
1230                                 "disabling\n");
1231                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1232                 goto out_disable;
1233         }
1234         if ((mode->hdisplay > 2048) ||
1235             (mode->vdisplay > 1536)) {
1236                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1237                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1238                 goto out_disable;
1239         }
1240         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1241                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1242                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1243                 goto out_disable;
1244         }
1245         if (obj_priv->tiling_mode != I915_TILING_X) {
1246                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1247                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1248                 goto out_disable;
1249         }
1250
1251         if (intel_fbc_enabled(dev)) {
1252                 /* We can re-enable it in this case, but need to update pitch */
1253                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1254                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1255                     (plane != dev_priv->cfb_plane))
1256                         intel_disable_fbc(dev);
1257         }
1258
1259         /* Now try to turn it back on if possible */
1260         if (!intel_fbc_enabled(dev))
1261                 intel_enable_fbc(crtc, 500);
1262
1263         return;
1264
1265 out_disable:
1266         /* Multiple disables should be harmless */
1267         if (intel_fbc_enabled(dev)) {
1268                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1269                 intel_disable_fbc(dev);
1270         }
1271 }
1272
1273 int
1274 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1275 {
1276         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1277         u32 alignment;
1278         int ret;
1279
1280         switch (obj_priv->tiling_mode) {
1281         case I915_TILING_NONE:
1282                 alignment = 64 * 1024;
1283                 break;
1284         case I915_TILING_X:
1285                 /* pin() will align the object as required by fence */
1286                 alignment = 0;
1287                 break;
1288         case I915_TILING_Y:
1289                 /* FIXME: Is this true? */
1290                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1291                 return -EINVAL;
1292         default:
1293                 BUG();
1294         }
1295
1296         ret = i915_gem_object_pin(obj, alignment);
1297         if (ret != 0)
1298                 return ret;
1299
1300         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1301          * fence, whereas 965+ only requires a fence if using
1302          * framebuffer compression.  For simplicity, we always install
1303          * a fence as the cost is not that onerous.
1304          */
1305         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1306             obj_priv->tiling_mode != I915_TILING_NONE) {
1307                 ret = i915_gem_object_get_fence_reg(obj);
1308                 if (ret != 0) {
1309                         i915_gem_object_unpin(obj);
1310                         return ret;
1311                 }
1312         }
1313
1314         return 0;
1315 }
1316
1317 static int
1318 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1319                     struct drm_framebuffer *old_fb)
1320 {
1321         struct drm_device *dev = crtc->dev;
1322         struct drm_i915_private *dev_priv = dev->dev_private;
1323         struct drm_i915_master_private *master_priv;
1324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1325         struct intel_framebuffer *intel_fb;
1326         struct drm_i915_gem_object *obj_priv;
1327         struct drm_gem_object *obj;
1328         int pipe = intel_crtc->pipe;
1329         int plane = intel_crtc->plane;
1330         unsigned long Start, Offset;
1331         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1332         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1333         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1334         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1335         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1336         u32 dspcntr;
1337         int ret;
1338
1339         /* no fb bound */
1340         if (!crtc->fb) {
1341                 DRM_DEBUG_KMS("No FB bound\n");
1342                 return 0;
1343         }
1344
1345         switch (plane) {
1346         case 0:
1347         case 1:
1348                 break;
1349         default:
1350                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1351                 return -EINVAL;
1352         }
1353
1354         intel_fb = to_intel_framebuffer(crtc->fb);
1355         obj = intel_fb->obj;
1356         obj_priv = to_intel_bo(obj);
1357
1358         mutex_lock(&dev->struct_mutex);
1359         ret = intel_pin_and_fence_fb_obj(dev, obj);
1360         if (ret != 0) {
1361                 mutex_unlock(&dev->struct_mutex);
1362                 return ret;
1363         }
1364
1365         ret = i915_gem_object_set_to_display_plane(obj);
1366         if (ret != 0) {
1367                 i915_gem_object_unpin(obj);
1368                 mutex_unlock(&dev->struct_mutex);
1369                 return ret;
1370         }
1371
1372         dspcntr = I915_READ(dspcntr_reg);
1373         /* Mask out pixel format bits in case we change it */
1374         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1375         switch (crtc->fb->bits_per_pixel) {
1376         case 8:
1377                 dspcntr |= DISPPLANE_8BPP;
1378                 break;
1379         case 16:
1380                 if (crtc->fb->depth == 15)
1381                         dspcntr |= DISPPLANE_15_16BPP;
1382                 else
1383                         dspcntr |= DISPPLANE_16BPP;
1384                 break;
1385         case 24:
1386         case 32:
1387                 if (crtc->fb->depth == 30)
1388                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1389                 else
1390                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1391                 break;
1392         default:
1393                 DRM_ERROR("Unknown color depth\n");
1394                 i915_gem_object_unpin(obj);
1395                 mutex_unlock(&dev->struct_mutex);
1396                 return -EINVAL;
1397         }
1398         if (IS_I965G(dev)) {
1399                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1400                         dspcntr |= DISPPLANE_TILED;
1401                 else
1402                         dspcntr &= ~DISPPLANE_TILED;
1403         }
1404
1405         if (HAS_PCH_SPLIT(dev))
1406                 /* must disable */
1407                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1408
1409         I915_WRITE(dspcntr_reg, dspcntr);
1410
1411         Start = obj_priv->gtt_offset;
1412         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1413
1414         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1415                       Start, Offset, x, y, crtc->fb->pitch);
1416         I915_WRITE(dspstride, crtc->fb->pitch);
1417         if (IS_I965G(dev)) {
1418                 I915_WRITE(dspbase, Offset);
1419                 I915_READ(dspbase);
1420                 I915_WRITE(dspsurf, Start);
1421                 I915_READ(dspsurf);
1422                 I915_WRITE(dsptileoff, (y << 16) | x);
1423         } else {
1424                 I915_WRITE(dspbase, Start + Offset);
1425                 I915_READ(dspbase);
1426         }
1427
1428         if ((IS_I965G(dev) || plane == 0))
1429                 intel_update_fbc(crtc, &crtc->mode);
1430
1431         intel_wait_for_vblank(dev);
1432
1433         if (old_fb) {
1434                 intel_fb = to_intel_framebuffer(old_fb);
1435                 obj_priv = to_intel_bo(intel_fb->obj);
1436                 i915_gem_object_unpin(intel_fb->obj);
1437         }
1438         intel_increase_pllclock(crtc, true);
1439
1440         mutex_unlock(&dev->struct_mutex);
1441
1442         if (!dev->primary->master)
1443                 return 0;
1444
1445         master_priv = dev->primary->master->driver_priv;
1446         if (!master_priv->sarea_priv)
1447                 return 0;
1448
1449         if (pipe) {
1450                 master_priv->sarea_priv->pipeB_x = x;
1451                 master_priv->sarea_priv->pipeB_y = y;
1452         } else {
1453                 master_priv->sarea_priv->pipeA_x = x;
1454                 master_priv->sarea_priv->pipeA_y = y;
1455         }
1456
1457         return 0;
1458 }
1459
1460 /* Disable the VGA plane that we never use */
1461 static void i915_disable_vga (struct drm_device *dev)
1462 {
1463         struct drm_i915_private *dev_priv = dev->dev_private;
1464         u8 sr1;
1465         u32 vga_reg;
1466
1467         if (HAS_PCH_SPLIT(dev))
1468                 vga_reg = CPU_VGACNTRL;
1469         else
1470                 vga_reg = VGACNTRL;
1471
1472         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1473                 return;
1474
1475         I915_WRITE8(VGA_SR_INDEX, 1);
1476         sr1 = I915_READ8(VGA_SR_DATA);
1477         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1478         udelay(100);
1479
1480         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1481 }
1482
1483 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1484 {
1485         struct drm_device *dev = crtc->dev;
1486         struct drm_i915_private *dev_priv = dev->dev_private;
1487         u32 dpa_ctl;
1488
1489         DRM_DEBUG_KMS("\n");
1490         dpa_ctl = I915_READ(DP_A);
1491         dpa_ctl &= ~DP_PLL_ENABLE;
1492         I915_WRITE(DP_A, dpa_ctl);
1493 }
1494
1495 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1496 {
1497         struct drm_device *dev = crtc->dev;
1498         struct drm_i915_private *dev_priv = dev->dev_private;
1499         u32 dpa_ctl;
1500
1501         dpa_ctl = I915_READ(DP_A);
1502         dpa_ctl |= DP_PLL_ENABLE;
1503         I915_WRITE(DP_A, dpa_ctl);
1504         udelay(200);
1505 }
1506
1507
1508 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1509 {
1510         struct drm_device *dev = crtc->dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         u32 dpa_ctl;
1513
1514         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1515         dpa_ctl = I915_READ(DP_A);
1516         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1517
1518         if (clock < 200000) {
1519                 u32 temp;
1520                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1521                 /* workaround for 160Mhz:
1522                    1) program 0x4600c bits 15:0 = 0x8124
1523                    2) program 0x46010 bit 0 = 1
1524                    3) program 0x46034 bit 24 = 1
1525                    4) program 0x64000 bit 14 = 1
1526                    */
1527                 temp = I915_READ(0x4600c);
1528                 temp &= 0xffff0000;
1529                 I915_WRITE(0x4600c, temp | 0x8124);
1530
1531                 temp = I915_READ(0x46010);
1532                 I915_WRITE(0x46010, temp | 1);
1533
1534                 temp = I915_READ(0x46034);
1535                 I915_WRITE(0x46034, temp | (1 << 24));
1536         } else {
1537                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1538         }
1539         I915_WRITE(DP_A, dpa_ctl);
1540
1541         udelay(500);
1542 }
1543
1544 /* The FDI link training functions for ILK/Ibexpeak. */
1545 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1546 {
1547         struct drm_device *dev = crtc->dev;
1548         struct drm_i915_private *dev_priv = dev->dev_private;
1549         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1550         int pipe = intel_crtc->pipe;
1551         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1552         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1553         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1554         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1555         u32 temp, tries = 0;
1556
1557         /* enable CPU FDI TX and PCH FDI RX */
1558         temp = I915_READ(fdi_tx_reg);
1559         temp |= FDI_TX_ENABLE;
1560         temp &= ~(7 << 19);
1561         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1562         temp &= ~FDI_LINK_TRAIN_NONE;
1563         temp |= FDI_LINK_TRAIN_PATTERN_1;
1564         I915_WRITE(fdi_tx_reg, temp);
1565         I915_READ(fdi_tx_reg);
1566
1567         temp = I915_READ(fdi_rx_reg);
1568         temp &= ~FDI_LINK_TRAIN_NONE;
1569         temp |= FDI_LINK_TRAIN_PATTERN_1;
1570         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1571         I915_READ(fdi_rx_reg);
1572         udelay(150);
1573
1574         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1575            for train result */
1576         temp = I915_READ(fdi_rx_imr_reg);
1577         temp &= ~FDI_RX_SYMBOL_LOCK;
1578         temp &= ~FDI_RX_BIT_LOCK;
1579         I915_WRITE(fdi_rx_imr_reg, temp);
1580         I915_READ(fdi_rx_imr_reg);
1581         udelay(150);
1582
1583         for (;;) {
1584                 temp = I915_READ(fdi_rx_iir_reg);
1585                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1586
1587                 if ((temp & FDI_RX_BIT_LOCK)) {
1588                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1589                         I915_WRITE(fdi_rx_iir_reg,
1590                                    temp | FDI_RX_BIT_LOCK);
1591                         break;
1592                 }
1593
1594                 tries++;
1595
1596                 if (tries > 5) {
1597                         DRM_DEBUG_KMS("FDI train 1 fail!\n");
1598                         break;
1599                 }
1600         }
1601
1602         /* Train 2 */
1603         temp = I915_READ(fdi_tx_reg);
1604         temp &= ~FDI_LINK_TRAIN_NONE;
1605         temp |= FDI_LINK_TRAIN_PATTERN_2;
1606         I915_WRITE(fdi_tx_reg, temp);
1607
1608         temp = I915_READ(fdi_rx_reg);
1609         temp &= ~FDI_LINK_TRAIN_NONE;
1610         temp |= FDI_LINK_TRAIN_PATTERN_2;
1611         I915_WRITE(fdi_rx_reg, temp);
1612         udelay(150);
1613
1614         tries = 0;
1615
1616         for (;;) {
1617                 temp = I915_READ(fdi_rx_iir_reg);
1618                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1619
1620                 if (temp & FDI_RX_SYMBOL_LOCK) {
1621                         I915_WRITE(fdi_rx_iir_reg,
1622                                    temp | FDI_RX_SYMBOL_LOCK);
1623                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1624                         break;
1625                 }
1626
1627                 tries++;
1628
1629                 if (tries > 5) {
1630                         DRM_DEBUG_KMS("FDI train 2 fail!\n");
1631                         break;
1632                 }
1633         }
1634
1635         DRM_DEBUG_KMS("FDI train done\n");
1636 }
1637
1638 static int snb_b_fdi_train_param [] = {
1639         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1640         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1641         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1642         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1643 };
1644
1645 /* The FDI link training functions for SNB/Cougarpoint. */
1646 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1647 {
1648         struct drm_device *dev = crtc->dev;
1649         struct drm_i915_private *dev_priv = dev->dev_private;
1650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1651         int pipe = intel_crtc->pipe;
1652         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1653         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1654         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1655         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1656         u32 temp, i;
1657
1658         /* enable CPU FDI TX and PCH FDI RX */
1659         temp = I915_READ(fdi_tx_reg);
1660         temp |= FDI_TX_ENABLE;
1661         temp &= ~(7 << 19);
1662         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1663         temp &= ~FDI_LINK_TRAIN_NONE;
1664         temp |= FDI_LINK_TRAIN_PATTERN_1;
1665         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1666         /* SNB-B */
1667         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1668         I915_WRITE(fdi_tx_reg, temp);
1669         I915_READ(fdi_tx_reg);
1670
1671         temp = I915_READ(fdi_rx_reg);
1672         if (HAS_PCH_CPT(dev)) {
1673                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1674                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1675         } else {
1676                 temp &= ~FDI_LINK_TRAIN_NONE;
1677                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1678         }
1679         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1680         I915_READ(fdi_rx_reg);
1681         udelay(150);
1682
1683         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1684            for train result */
1685         temp = I915_READ(fdi_rx_imr_reg);
1686         temp &= ~FDI_RX_SYMBOL_LOCK;
1687         temp &= ~FDI_RX_BIT_LOCK;
1688         I915_WRITE(fdi_rx_imr_reg, temp);
1689         I915_READ(fdi_rx_imr_reg);
1690         udelay(150);
1691
1692         for (i = 0; i < 4; i++ ) {
1693                 temp = I915_READ(fdi_tx_reg);
1694                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1695                 temp |= snb_b_fdi_train_param[i];
1696                 I915_WRITE(fdi_tx_reg, temp);
1697                 udelay(500);
1698
1699                 temp = I915_READ(fdi_rx_iir_reg);
1700                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1701
1702                 if (temp & FDI_RX_BIT_LOCK) {
1703                         I915_WRITE(fdi_rx_iir_reg,
1704                                    temp | FDI_RX_BIT_LOCK);
1705                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1706                         break;
1707                 }
1708         }
1709         if (i == 4)
1710                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1711
1712         /* Train 2 */
1713         temp = I915_READ(fdi_tx_reg);
1714         temp &= ~FDI_LINK_TRAIN_NONE;
1715         temp |= FDI_LINK_TRAIN_PATTERN_2;
1716         if (IS_GEN6(dev)) {
1717                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1718                 /* SNB-B */
1719                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1720         }
1721         I915_WRITE(fdi_tx_reg, temp);
1722
1723         temp = I915_READ(fdi_rx_reg);
1724         if (HAS_PCH_CPT(dev)) {
1725                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1726                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1727         } else {
1728                 temp &= ~FDI_LINK_TRAIN_NONE;
1729                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1730         }
1731         I915_WRITE(fdi_rx_reg, temp);
1732         udelay(150);
1733
1734         for (i = 0; i < 4; i++ ) {
1735                 temp = I915_READ(fdi_tx_reg);
1736                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1737                 temp |= snb_b_fdi_train_param[i];
1738                 I915_WRITE(fdi_tx_reg, temp);
1739                 udelay(500);
1740
1741                 temp = I915_READ(fdi_rx_iir_reg);
1742                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1743
1744                 if (temp & FDI_RX_SYMBOL_LOCK) {
1745                         I915_WRITE(fdi_rx_iir_reg,
1746                                    temp | FDI_RX_SYMBOL_LOCK);
1747                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1748                         break;
1749                 }
1750         }
1751         if (i == 4)
1752                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1753
1754         DRM_DEBUG_KMS("FDI train done.\n");
1755 }
1756
1757 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1758 {
1759         struct drm_device *dev = crtc->dev;
1760         struct drm_i915_private *dev_priv = dev->dev_private;
1761         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1762         int pipe = intel_crtc->pipe;
1763         int plane = intel_crtc->plane;
1764         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1765         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1766         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1767         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1768         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1769         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1770         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1771         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1772         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1773         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1774         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1775         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1776         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1777         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1778         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1779         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1780         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1781         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1782         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1783         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1784         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1785         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1786         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1787         u32 temp;
1788         int n;
1789         u32 pipe_bpc;
1790
1791         temp = I915_READ(pipeconf_reg);
1792         pipe_bpc = temp & PIPE_BPC_MASK;
1793
1794         /* XXX: When our outputs are all unaware of DPMS modes other than off
1795          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1796          */
1797         switch (mode) {
1798         case DRM_MODE_DPMS_ON:
1799         case DRM_MODE_DPMS_STANDBY:
1800         case DRM_MODE_DPMS_SUSPEND:
1801                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1802
1803                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1804                         temp = I915_READ(PCH_LVDS);
1805                         if ((temp & LVDS_PORT_EN) == 0) {
1806                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1807                                 POSTING_READ(PCH_LVDS);
1808                         }
1809                 }
1810
1811                 if (HAS_eDP) {
1812                         /* enable eDP PLL */
1813                         ironlake_enable_pll_edp(crtc);
1814                 } else {
1815
1816                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1817                         temp = I915_READ(fdi_rx_reg);
1818                         /*
1819                          * make the BPC in FDI Rx be consistent with that in
1820                          * pipeconf reg.
1821                          */
1822                         temp &= ~(0x7 << 16);
1823                         temp |= (pipe_bpc << 11);
1824                         temp &= ~(7 << 19);
1825                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1826                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1827                         I915_READ(fdi_rx_reg);
1828                         udelay(200);
1829
1830                         /* Switch from Rawclk to PCDclk */
1831                         temp = I915_READ(fdi_rx_reg);
1832                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1833                         I915_READ(fdi_rx_reg);
1834                         udelay(200);
1835
1836                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1837                         temp = I915_READ(fdi_tx_reg);
1838                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1839                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1840                                 I915_READ(fdi_tx_reg);
1841                                 udelay(100);
1842                         }
1843                 }
1844
1845                 /* Enable panel fitting for LVDS */
1846                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1847                         temp = I915_READ(pf_ctl_reg);
1848                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1849
1850                         /* currently full aspect */
1851                         I915_WRITE(pf_win_pos, 0);
1852
1853                         I915_WRITE(pf_win_size,
1854                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1855                                    (dev_priv->panel_fixed_mode->vdisplay));
1856                 }
1857
1858                 /* Enable CPU pipe */
1859                 temp = I915_READ(pipeconf_reg);
1860                 if ((temp & PIPEACONF_ENABLE) == 0) {
1861                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1862                         I915_READ(pipeconf_reg);
1863                         udelay(100);
1864                 }
1865
1866                 /* configure and enable CPU plane */
1867                 temp = I915_READ(dspcntr_reg);
1868                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1869                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1870                         /* Flush the plane changes */
1871                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1872                 }
1873
1874                 if (!HAS_eDP) {
1875                         /* For PCH output, training FDI link */
1876                         if (IS_GEN6(dev))
1877                                 gen6_fdi_link_train(crtc);
1878                         else
1879                                 ironlake_fdi_link_train(crtc);
1880
1881                         /* enable PCH DPLL */
1882                         temp = I915_READ(pch_dpll_reg);
1883                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1884                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1885                                 I915_READ(pch_dpll_reg);
1886                         }
1887                         udelay(200);
1888
1889                         if (HAS_PCH_CPT(dev)) {
1890                                 /* Be sure PCH DPLL SEL is set */
1891                                 temp = I915_READ(PCH_DPLL_SEL);
1892                                 if (trans_dpll_sel == 0 &&
1893                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
1894                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1895                                 else if (trans_dpll_sel == 1 &&
1896                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
1897                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1898                                 I915_WRITE(PCH_DPLL_SEL, temp);
1899                                 I915_READ(PCH_DPLL_SEL);
1900                         }
1901
1902                         /* set transcoder timing */
1903                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1904                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1905                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1906
1907                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1908                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1909                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1910
1911                         /* enable normal train */
1912                         temp = I915_READ(fdi_tx_reg);
1913                         temp &= ~FDI_LINK_TRAIN_NONE;
1914                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1915                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1916                         I915_READ(fdi_tx_reg);
1917
1918                         temp = I915_READ(fdi_rx_reg);
1919                         if (HAS_PCH_CPT(dev)) {
1920                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1921                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1922                         } else {
1923                                 temp &= ~FDI_LINK_TRAIN_NONE;
1924                                 temp |= FDI_LINK_TRAIN_NONE;
1925                         }
1926                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1927                         I915_READ(fdi_rx_reg);
1928
1929                         /* wait one idle pattern time */
1930                         udelay(100);
1931
1932                         /* For PCH DP, enable TRANS_DP_CTL */
1933                         if (HAS_PCH_CPT(dev) &&
1934                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1935                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1936                                 int reg;
1937
1938                                 reg = I915_READ(trans_dp_ctl);
1939                                 reg &= ~TRANS_DP_PORT_SEL_MASK;
1940                                 reg = TRANS_DP_OUTPUT_ENABLE |
1941                                       TRANS_DP_ENH_FRAMING |
1942                                       TRANS_DP_VSYNC_ACTIVE_HIGH |
1943                                       TRANS_DP_HSYNC_ACTIVE_HIGH;
1944
1945                                 switch (intel_trans_dp_port_sel(crtc)) {
1946                                 case PCH_DP_B:
1947                                         reg |= TRANS_DP_PORT_SEL_B;
1948                                         break;
1949                                 case PCH_DP_C:
1950                                         reg |= TRANS_DP_PORT_SEL_C;
1951                                         break;
1952                                 case PCH_DP_D:
1953                                         reg |= TRANS_DP_PORT_SEL_D;
1954                                         break;
1955                                 default:
1956                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1957                                         reg |= TRANS_DP_PORT_SEL_B;
1958                                         break;
1959                                 }
1960
1961                                 I915_WRITE(trans_dp_ctl, reg);
1962                                 POSTING_READ(trans_dp_ctl);
1963                         }
1964
1965                         /* enable PCH transcoder */
1966                         temp = I915_READ(transconf_reg);
1967                         /*
1968                          * make the BPC in transcoder be consistent with
1969                          * that in pipeconf reg.
1970                          */
1971                         temp &= ~PIPE_BPC_MASK;
1972                         temp |= pipe_bpc;
1973                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1974                         I915_READ(transconf_reg);
1975
1976                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1977                                 ;
1978
1979                 }
1980
1981                 intel_crtc_load_lut(crtc);
1982
1983         break;
1984         case DRM_MODE_DPMS_OFF:
1985                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1986
1987                 drm_vblank_off(dev, pipe);
1988                 /* Disable display plane */
1989                 temp = I915_READ(dspcntr_reg);
1990                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1991                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1992                         /* Flush the plane changes */
1993                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1994                         I915_READ(dspbase_reg);
1995                 }
1996
1997                 i915_disable_vga(dev);
1998
1999                 /* disable cpu pipe, disable after all planes disabled */
2000                 temp = I915_READ(pipeconf_reg);
2001                 if ((temp & PIPEACONF_ENABLE) != 0) {
2002                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2003                         I915_READ(pipeconf_reg);
2004                         n = 0;
2005                         /* wait for cpu pipe off, pipe state */
2006                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
2007                                 n++;
2008                                 if (n < 60) {
2009                                         udelay(500);
2010                                         continue;
2011                                 } else {
2012                                         DRM_DEBUG_KMS("pipe %d off delay\n",
2013                                                                 pipe);
2014                                         break;
2015                                 }
2016                         }
2017                 } else
2018                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2019
2020                 udelay(100);
2021
2022                 /* Disable PF */
2023                 temp = I915_READ(pf_ctl_reg);
2024                 if ((temp & PF_ENABLE) != 0) {
2025                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2026                         I915_READ(pf_ctl_reg);
2027                 }
2028                 I915_WRITE(pf_win_size, 0);
2029                 POSTING_READ(pf_win_size);
2030
2031
2032                 /* disable CPU FDI tx and PCH FDI rx */
2033                 temp = I915_READ(fdi_tx_reg);
2034                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2035                 I915_READ(fdi_tx_reg);
2036
2037                 temp = I915_READ(fdi_rx_reg);
2038                 /* BPC in FDI rx is consistent with that in pipeconf */
2039                 temp &= ~(0x07 << 16);
2040                 temp |= (pipe_bpc << 11);
2041                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2042                 I915_READ(fdi_rx_reg);
2043
2044                 udelay(100);
2045
2046                 /* still set train pattern 1 */
2047                 temp = I915_READ(fdi_tx_reg);
2048                 temp &= ~FDI_LINK_TRAIN_NONE;
2049                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2050                 I915_WRITE(fdi_tx_reg, temp);
2051                 POSTING_READ(fdi_tx_reg);
2052
2053                 temp = I915_READ(fdi_rx_reg);
2054                 if (HAS_PCH_CPT(dev)) {
2055                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2056                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2057                 } else {
2058                         temp &= ~FDI_LINK_TRAIN_NONE;
2059                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2060                 }
2061                 I915_WRITE(fdi_rx_reg, temp);
2062                 POSTING_READ(fdi_rx_reg);
2063
2064                 udelay(100);
2065
2066                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2067                         temp = I915_READ(PCH_LVDS);
2068                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2069                         I915_READ(PCH_LVDS);
2070                         udelay(100);
2071                 }
2072
2073                 /* disable PCH transcoder */
2074                 temp = I915_READ(transconf_reg);
2075                 if ((temp & TRANS_ENABLE) != 0) {
2076                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2077                         I915_READ(transconf_reg);
2078                         n = 0;
2079                         /* wait for PCH transcoder off, transcoder state */
2080                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2081                                 n++;
2082                                 if (n < 60) {
2083                                         udelay(500);
2084                                         continue;
2085                                 } else {
2086                                         DRM_DEBUG_KMS("transcoder %d off "
2087                                                         "delay\n", pipe);
2088                                         break;
2089                                 }
2090                         }
2091                 }
2092
2093                 temp = I915_READ(transconf_reg);
2094                 /* BPC in transcoder is consistent with that in pipeconf */
2095                 temp &= ~PIPE_BPC_MASK;
2096                 temp |= pipe_bpc;
2097                 I915_WRITE(transconf_reg, temp);
2098                 I915_READ(transconf_reg);
2099                 udelay(100);
2100
2101                 if (HAS_PCH_CPT(dev)) {
2102                         /* disable TRANS_DP_CTL */
2103                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2104                         int reg;
2105
2106                         reg = I915_READ(trans_dp_ctl);
2107                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2108                         I915_WRITE(trans_dp_ctl, reg);
2109                         POSTING_READ(trans_dp_ctl);
2110
2111                         /* disable DPLL_SEL */
2112                         temp = I915_READ(PCH_DPLL_SEL);
2113                         if (trans_dpll_sel == 0)
2114                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2115                         else
2116                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2117                         I915_WRITE(PCH_DPLL_SEL, temp);
2118                         I915_READ(PCH_DPLL_SEL);
2119
2120                 }
2121
2122                 /* disable PCH DPLL */
2123                 temp = I915_READ(pch_dpll_reg);
2124                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2125                 I915_READ(pch_dpll_reg);
2126
2127                 if (HAS_eDP) {
2128                         ironlake_disable_pll_edp(crtc);
2129                 }
2130
2131                 /* Switch from PCDclk to Rawclk */
2132                 temp = I915_READ(fdi_rx_reg);
2133                 temp &= ~FDI_SEL_PCDCLK;
2134                 I915_WRITE(fdi_rx_reg, temp);
2135                 I915_READ(fdi_rx_reg);
2136
2137                 /* Disable CPU FDI TX PLL */
2138                 temp = I915_READ(fdi_tx_reg);
2139                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2140                 I915_READ(fdi_tx_reg);
2141                 udelay(100);
2142
2143                 temp = I915_READ(fdi_rx_reg);
2144                 temp &= ~FDI_RX_PLL_ENABLE;
2145                 I915_WRITE(fdi_rx_reg, temp);
2146                 I915_READ(fdi_rx_reg);
2147
2148                 /* Wait for the clocks to turn off. */
2149                 udelay(100);
2150                 break;
2151         }
2152 }
2153
2154 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2155 {
2156         struct intel_overlay *overlay;
2157         int ret;
2158
2159         if (!enable && intel_crtc->overlay) {
2160                 overlay = intel_crtc->overlay;
2161                 mutex_lock(&overlay->dev->struct_mutex);
2162                 for (;;) {
2163                         ret = intel_overlay_switch_off(overlay);
2164                         if (ret == 0)
2165                                 break;
2166
2167                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2168                         if (ret != 0) {
2169                                 /* overlay doesn't react anymore. Usually
2170                                  * results in a black screen and an unkillable
2171                                  * X server. */
2172                                 BUG();
2173                                 overlay->hw_wedged = HW_WEDGED;
2174                                 break;
2175                         }
2176                 }
2177                 mutex_unlock(&overlay->dev->struct_mutex);
2178         }
2179         /* Let userspace switch the overlay on again. In most cases userspace
2180          * has to recompute where to put it anyway. */
2181
2182         return;
2183 }
2184
2185 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2186 {
2187         struct drm_device *dev = crtc->dev;
2188         struct drm_i915_private *dev_priv = dev->dev_private;
2189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2190         int pipe = intel_crtc->pipe;
2191         int plane = intel_crtc->plane;
2192         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2193         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2194         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2195         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2196         u32 temp;
2197
2198         /* XXX: When our outputs are all unaware of DPMS modes other than off
2199          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2200          */
2201         switch (mode) {
2202         case DRM_MODE_DPMS_ON:
2203         case DRM_MODE_DPMS_STANDBY:
2204         case DRM_MODE_DPMS_SUSPEND:
2205                 intel_update_watermarks(dev);
2206
2207                 /* Enable the DPLL */
2208                 temp = I915_READ(dpll_reg);
2209                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2210                         I915_WRITE(dpll_reg, temp);
2211                         I915_READ(dpll_reg);
2212                         /* Wait for the clocks to stabilize. */
2213                         udelay(150);
2214                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2215                         I915_READ(dpll_reg);
2216                         /* Wait for the clocks to stabilize. */
2217                         udelay(150);
2218                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2219                         I915_READ(dpll_reg);
2220                         /* Wait for the clocks to stabilize. */
2221                         udelay(150);
2222                 }
2223
2224                 /* Enable the pipe */
2225                 temp = I915_READ(pipeconf_reg);
2226                 if ((temp & PIPEACONF_ENABLE) == 0)
2227                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2228
2229                 /* Enable the plane */
2230                 temp = I915_READ(dspcntr_reg);
2231                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2232                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2233                         /* Flush the plane changes */
2234                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2235                 }
2236
2237                 intel_crtc_load_lut(crtc);
2238
2239                 if ((IS_I965G(dev) || plane == 0))
2240                         intel_update_fbc(crtc, &crtc->mode);
2241
2242                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2243                 intel_crtc_dpms_overlay(intel_crtc, true);
2244         break;
2245         case DRM_MODE_DPMS_OFF:
2246                 intel_update_watermarks(dev);
2247
2248                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2249                 intel_crtc_dpms_overlay(intel_crtc, false);
2250                 drm_vblank_off(dev, pipe);
2251
2252                 if (dev_priv->cfb_plane == plane &&
2253                     dev_priv->display.disable_fbc)
2254                         dev_priv->display.disable_fbc(dev);
2255
2256                 /* Disable the VGA plane that we never use */
2257                 i915_disable_vga(dev);
2258
2259                 /* Disable display plane */
2260                 temp = I915_READ(dspcntr_reg);
2261                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2262                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2263                         /* Flush the plane changes */
2264                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2265                         I915_READ(dspbase_reg);
2266                 }
2267
2268                 if (!IS_I9XX(dev)) {
2269                         /* Wait for vblank for the disable to take effect */
2270                         intel_wait_for_vblank(dev);
2271                 }
2272
2273                 /* Next, disable display pipes */
2274                 temp = I915_READ(pipeconf_reg);
2275                 if ((temp & PIPEACONF_ENABLE) != 0) {
2276                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2277                         I915_READ(pipeconf_reg);
2278                 }
2279
2280                 /* Wait for vblank for the disable to take effect. */
2281                 intel_wait_for_vblank(dev);
2282
2283                 temp = I915_READ(dpll_reg);
2284                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2285                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2286                         I915_READ(dpll_reg);
2287                 }
2288
2289                 /* Wait for the clocks to turn off. */
2290                 udelay(150);
2291                 break;
2292         }
2293 }
2294
2295 /**
2296  * Sets the power management mode of the pipe and plane.
2297  *
2298  * This code should probably grow support for turning the cursor off and back
2299  * on appropriately at the same time as we're turning the pipe off/on.
2300  */
2301 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2302 {
2303         struct drm_device *dev = crtc->dev;
2304         struct drm_i915_private *dev_priv = dev->dev_private;
2305         struct drm_i915_master_private *master_priv;
2306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2307         int pipe = intel_crtc->pipe;
2308         bool enabled;
2309
2310         dev_priv->display.dpms(crtc, mode);
2311
2312         intel_crtc->dpms_mode = mode;
2313
2314         if (!dev->primary->master)
2315                 return;
2316
2317         master_priv = dev->primary->master->driver_priv;
2318         if (!master_priv->sarea_priv)
2319                 return;
2320
2321         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2322
2323         switch (pipe) {
2324         case 0:
2325                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2326                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2327                 break;
2328         case 1:
2329                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2330                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2331                 break;
2332         default:
2333                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2334                 break;
2335         }
2336 }
2337
2338 static void intel_crtc_prepare (struct drm_crtc *crtc)
2339 {
2340         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2341         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2342 }
2343
2344 static void intel_crtc_commit (struct drm_crtc *crtc)
2345 {
2346         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2347         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2348 }
2349
2350 void intel_encoder_prepare (struct drm_encoder *encoder)
2351 {
2352         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2353         /* lvds has its own version of prepare see intel_lvds_prepare */
2354         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2355 }
2356
2357 void intel_encoder_commit (struct drm_encoder *encoder)
2358 {
2359         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2360         /* lvds has its own version of commit see intel_lvds_commit */
2361         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2362 }
2363
2364 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2365                                   struct drm_display_mode *mode,
2366                                   struct drm_display_mode *adjusted_mode)
2367 {
2368         struct drm_device *dev = crtc->dev;
2369         if (HAS_PCH_SPLIT(dev)) {
2370                 /* FDI link clock is fixed at 2.7G */
2371                 if (mode->clock * 3 > 27000 * 4)
2372                         return MODE_CLOCK_HIGH;
2373         }
2374         return true;
2375 }
2376
2377 static int i945_get_display_clock_speed(struct drm_device *dev)
2378 {
2379         return 400000;
2380 }
2381
2382 static int i915_get_display_clock_speed(struct drm_device *dev)
2383 {
2384         return 333000;
2385 }
2386
2387 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2388 {
2389         return 200000;
2390 }
2391
2392 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2393 {
2394         u16 gcfgc = 0;
2395
2396         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2397
2398         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2399                 return 133000;
2400         else {
2401                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2402                 case GC_DISPLAY_CLOCK_333_MHZ:
2403                         return 333000;
2404                 default:
2405                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2406                         return 190000;
2407                 }
2408         }
2409 }
2410
2411 static int i865_get_display_clock_speed(struct drm_device *dev)
2412 {
2413         return 266000;
2414 }
2415
2416 static int i855_get_display_clock_speed(struct drm_device *dev)
2417 {
2418         u16 hpllcc = 0;
2419         /* Assume that the hardware is in the high speed state.  This
2420          * should be the default.
2421          */
2422         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2423         case GC_CLOCK_133_200:
2424         case GC_CLOCK_100_200:
2425                 return 200000;
2426         case GC_CLOCK_166_250:
2427                 return 250000;
2428         case GC_CLOCK_100_133:
2429                 return 133000;
2430         }
2431
2432         /* Shouldn't happen */
2433         return 0;
2434 }
2435
2436 static int i830_get_display_clock_speed(struct drm_device *dev)
2437 {
2438         return 133000;
2439 }
2440
2441 /**
2442  * Return the pipe currently connected to the panel fitter,
2443  * or -1 if the panel fitter is not present or not in use
2444  */
2445 int intel_panel_fitter_pipe (struct drm_device *dev)
2446 {
2447         struct drm_i915_private *dev_priv = dev->dev_private;
2448         u32  pfit_control;
2449
2450         /* i830 doesn't have a panel fitter */
2451         if (IS_I830(dev))
2452                 return -1;
2453
2454         pfit_control = I915_READ(PFIT_CONTROL);
2455
2456         /* See if the panel fitter is in use */
2457         if ((pfit_control & PFIT_ENABLE) == 0)
2458                 return -1;
2459
2460         /* 965 can place panel fitter on either pipe */
2461         if (IS_I965G(dev))
2462                 return (pfit_control >> 29) & 0x3;
2463
2464         /* older chips can only use pipe 1 */
2465         return 1;
2466 }
2467
2468 struct fdi_m_n {
2469         u32        tu;
2470         u32        gmch_m;
2471         u32        gmch_n;
2472         u32        link_m;
2473         u32        link_n;
2474 };
2475
2476 static void
2477 fdi_reduce_ratio(u32 *num, u32 *den)
2478 {
2479         while (*num > 0xffffff || *den > 0xffffff) {
2480                 *num >>= 1;
2481                 *den >>= 1;
2482         }
2483 }
2484
2485 #define DATA_N 0x800000
2486 #define LINK_N 0x80000
2487
2488 static void
2489 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2490                      int link_clock, struct fdi_m_n *m_n)
2491 {
2492         u64 temp;
2493
2494         m_n->tu = 64; /* default size */
2495
2496         temp = (u64) DATA_N * pixel_clock;
2497         temp = div_u64(temp, link_clock);
2498         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2499         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2500         m_n->gmch_n = DATA_N;
2501         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2502
2503         temp = (u64) LINK_N * pixel_clock;
2504         m_n->link_m = div_u64(temp, link_clock);
2505         m_n->link_n = LINK_N;
2506         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2507 }
2508
2509
2510 struct intel_watermark_params {
2511         unsigned long fifo_size;
2512         unsigned long max_wm;
2513         unsigned long default_wm;
2514         unsigned long guard_size;
2515         unsigned long cacheline_size;
2516 };
2517
2518 /* Pineview has different values for various configs */
2519 static struct intel_watermark_params pineview_display_wm = {
2520         PINEVIEW_DISPLAY_FIFO,
2521         PINEVIEW_MAX_WM,
2522         PINEVIEW_DFT_WM,
2523         PINEVIEW_GUARD_WM,
2524         PINEVIEW_FIFO_LINE_SIZE
2525 };
2526 static struct intel_watermark_params pineview_display_hplloff_wm = {
2527         PINEVIEW_DISPLAY_FIFO,
2528         PINEVIEW_MAX_WM,
2529         PINEVIEW_DFT_HPLLOFF_WM,
2530         PINEVIEW_GUARD_WM,
2531         PINEVIEW_FIFO_LINE_SIZE
2532 };
2533 static struct intel_watermark_params pineview_cursor_wm = {
2534         PINEVIEW_CURSOR_FIFO,
2535         PINEVIEW_CURSOR_MAX_WM,
2536         PINEVIEW_CURSOR_DFT_WM,
2537         PINEVIEW_CURSOR_GUARD_WM,
2538         PINEVIEW_FIFO_LINE_SIZE,
2539 };
2540 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2541         PINEVIEW_CURSOR_FIFO,
2542         PINEVIEW_CURSOR_MAX_WM,
2543         PINEVIEW_CURSOR_DFT_WM,
2544         PINEVIEW_CURSOR_GUARD_WM,
2545         PINEVIEW_FIFO_LINE_SIZE
2546 };
2547 static struct intel_watermark_params g4x_wm_info = {
2548         G4X_FIFO_SIZE,
2549         G4X_MAX_WM,
2550         G4X_MAX_WM,
2551         2,
2552         G4X_FIFO_LINE_SIZE,
2553 };
2554 static struct intel_watermark_params i945_wm_info = {
2555         I945_FIFO_SIZE,
2556         I915_MAX_WM,
2557         1,
2558         2,
2559         I915_FIFO_LINE_SIZE
2560 };
2561 static struct intel_watermark_params i915_wm_info = {
2562         I915_FIFO_SIZE,
2563         I915_MAX_WM,
2564         1,
2565         2,
2566         I915_FIFO_LINE_SIZE
2567 };
2568 static struct intel_watermark_params i855_wm_info = {
2569         I855GM_FIFO_SIZE,
2570         I915_MAX_WM,
2571         1,
2572         2,
2573         I830_FIFO_LINE_SIZE
2574 };
2575 static struct intel_watermark_params i830_wm_info = {
2576         I830_FIFO_SIZE,
2577         I915_MAX_WM,
2578         1,
2579         2,
2580         I830_FIFO_LINE_SIZE
2581 };
2582
2583 static struct intel_watermark_params ironlake_display_wm_info = {
2584         ILK_DISPLAY_FIFO,
2585         ILK_DISPLAY_MAXWM,
2586         ILK_DISPLAY_DFTWM,
2587         2,
2588         ILK_FIFO_LINE_SIZE
2589 };
2590
2591 static struct intel_watermark_params ironlake_display_srwm_info = {
2592         ILK_DISPLAY_SR_FIFO,
2593         ILK_DISPLAY_MAX_SRWM,
2594         ILK_DISPLAY_DFT_SRWM,
2595         2,
2596         ILK_FIFO_LINE_SIZE
2597 };
2598
2599 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2600         ILK_CURSOR_SR_FIFO,
2601         ILK_CURSOR_MAX_SRWM,
2602         ILK_CURSOR_DFT_SRWM,
2603         2,
2604         ILK_FIFO_LINE_SIZE
2605 };
2606
2607 /**
2608  * intel_calculate_wm - calculate watermark level
2609  * @clock_in_khz: pixel clock
2610  * @wm: chip FIFO params
2611  * @pixel_size: display pixel size
2612  * @latency_ns: memory latency for the platform
2613  *
2614  * Calculate the watermark level (the level at which the display plane will
2615  * start fetching from memory again).  Each chip has a different display
2616  * FIFO size and allocation, so the caller needs to figure that out and pass
2617  * in the correct intel_watermark_params structure.
2618  *
2619  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2620  * on the pixel size.  When it reaches the watermark level, it'll start
2621  * fetching FIFO line sized based chunks from memory until the FIFO fills
2622  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2623  * will occur, and a display engine hang could result.
2624  */
2625 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2626                                         struct intel_watermark_params *wm,
2627                                         int pixel_size,
2628                                         unsigned long latency_ns)
2629 {
2630         long entries_required, wm_size;
2631
2632         /*
2633          * Note: we need to make sure we don't overflow for various clock &
2634          * latency values.
2635          * clocks go from a few thousand to several hundred thousand.
2636          * latency is usually a few thousand
2637          */
2638         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2639                 1000;
2640         entries_required /= wm->cacheline_size;
2641
2642         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2643
2644         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2645
2646         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2647
2648         /* Don't promote wm_size to unsigned... */
2649         if (wm_size > (long)wm->max_wm)
2650                 wm_size = wm->max_wm;
2651         if (wm_size <= 0)
2652                 wm_size = wm->default_wm;
2653         return wm_size;
2654 }
2655
2656 struct cxsr_latency {
2657         int is_desktop;
2658         int is_ddr3;
2659         unsigned long fsb_freq;
2660         unsigned long mem_freq;
2661         unsigned long display_sr;
2662         unsigned long display_hpll_disable;
2663         unsigned long cursor_sr;
2664         unsigned long cursor_hpll_disable;
2665 };
2666
2667 static struct cxsr_latency cxsr_latency_table[] = {
2668         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2669         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2670         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2671         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2672         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2673
2674         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2675         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2676         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2677         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2678         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2679
2680         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2681         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2682         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2683         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2684         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2685
2686         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2687         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2688         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2689         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2690         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2691
2692         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2693         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2694         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2695         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2696         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2697
2698         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2699         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2700         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2701         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2702         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2703 };
2704
2705 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3, 
2706                                                    int fsb, int mem)
2707 {
2708         int i;
2709         struct cxsr_latency *latency;
2710
2711         if (fsb == 0 || mem == 0)
2712                 return NULL;
2713
2714         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2715                 latency = &cxsr_latency_table[i];
2716                 if (is_desktop == latency->is_desktop &&
2717                     is_ddr3 == latency->is_ddr3 &&
2718                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2719                         return latency;
2720         }
2721
2722         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2723
2724         return NULL;
2725 }
2726
2727 static void pineview_disable_cxsr(struct drm_device *dev)
2728 {
2729         struct drm_i915_private *dev_priv = dev->dev_private;
2730         u32 reg;
2731
2732         /* deactivate cxsr */
2733         reg = I915_READ(DSPFW3);
2734         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2735         I915_WRITE(DSPFW3, reg);
2736         DRM_INFO("Big FIFO is disabled\n");
2737 }
2738
2739 /*
2740  * Latency for FIFO fetches is dependent on several factors:
2741  *   - memory configuration (speed, channels)
2742  *   - chipset
2743  *   - current MCH state
2744  * It can be fairly high in some situations, so here we assume a fairly
2745  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2746  * set this value too high, the FIFO will fetch frequently to stay full)
2747  * and power consumption (set it too low to save power and we might see
2748  * FIFO underruns and display "flicker").
2749  *
2750  * A value of 5us seems to be a good balance; safe for very low end
2751  * platforms but not overly aggressive on lower latency configs.
2752  */
2753 static const int latency_ns = 5000;
2754
2755 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2756 {
2757         struct drm_i915_private *dev_priv = dev->dev_private;
2758         uint32_t dsparb = I915_READ(DSPARB);
2759         int size;
2760
2761         if (plane == 0)
2762                 size = dsparb & 0x7f;
2763         else
2764                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2765                         (dsparb & 0x7f);
2766
2767         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2768                         plane ? "B" : "A", size);
2769
2770         return size;
2771 }
2772
2773 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2774 {
2775         struct drm_i915_private *dev_priv = dev->dev_private;
2776         uint32_t dsparb = I915_READ(DSPARB);
2777         int size;
2778
2779         if (plane == 0)
2780                 size = dsparb & 0x1ff;
2781         else
2782                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2783                         (dsparb & 0x1ff);
2784         size >>= 1; /* Convert to cachelines */
2785
2786         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2787                         plane ? "B" : "A", size);
2788
2789         return size;
2790 }
2791
2792 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2793 {
2794         struct drm_i915_private *dev_priv = dev->dev_private;
2795         uint32_t dsparb = I915_READ(DSPARB);
2796         int size;
2797
2798         size = dsparb & 0x7f;
2799         size >>= 2; /* Convert to cachelines */
2800
2801         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2802                         plane ? "B" : "A",
2803                   size);
2804
2805         return size;
2806 }
2807
2808 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2809 {
2810         struct drm_i915_private *dev_priv = dev->dev_private;
2811         uint32_t dsparb = I915_READ(DSPARB);
2812         int size;
2813
2814         size = dsparb & 0x7f;
2815         size >>= 1; /* Convert to cachelines */
2816
2817         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2818                         plane ? "B" : "A", size);
2819
2820         return size;
2821 }
2822
2823 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2824                           int planeb_clock, int sr_hdisplay, int pixel_size)
2825 {
2826         struct drm_i915_private *dev_priv = dev->dev_private;
2827         u32 reg;
2828         unsigned long wm;
2829         struct cxsr_latency *latency;
2830         int sr_clock;
2831
2832         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 
2833                                          dev_priv->fsb_freq, dev_priv->mem_freq);
2834         if (!latency) {
2835                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2836                 pineview_disable_cxsr(dev);
2837                 return;
2838         }
2839
2840         if (!planea_clock || !planeb_clock) {
2841                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2842
2843                 /* Display SR */
2844                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2845                                         pixel_size, latency->display_sr);
2846                 reg = I915_READ(DSPFW1);
2847                 reg &= ~DSPFW_SR_MASK;
2848                 reg |= wm << DSPFW_SR_SHIFT;
2849                 I915_WRITE(DSPFW1, reg);
2850                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2851
2852                 /* cursor SR */
2853                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2854                                         pixel_size, latency->cursor_sr);
2855                 reg = I915_READ(DSPFW3);
2856                 reg &= ~DSPFW_CURSOR_SR_MASK;
2857                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2858                 I915_WRITE(DSPFW3, reg);
2859
2860                 /* Display HPLL off SR */
2861                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2862                                         pixel_size, latency->display_hpll_disable);
2863                 reg = I915_READ(DSPFW3);
2864                 reg &= ~DSPFW_HPLL_SR_MASK;
2865                 reg |= wm & DSPFW_HPLL_SR_MASK;
2866                 I915_WRITE(DSPFW3, reg);
2867
2868                 /* cursor HPLL off SR */
2869                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2870                                         pixel_size, latency->cursor_hpll_disable);
2871                 reg = I915_READ(DSPFW3);
2872                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2873                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2874                 I915_WRITE(DSPFW3, reg);
2875                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2876
2877                 /* activate cxsr */
2878                 reg = I915_READ(DSPFW3);
2879                 reg |= PINEVIEW_SELF_REFRESH_EN;
2880                 I915_WRITE(DSPFW3, reg);
2881                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2882         } else {
2883                 pineview_disable_cxsr(dev);
2884                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2885         }
2886 }
2887
2888 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2889                           int planeb_clock, int sr_hdisplay, int pixel_size)
2890 {
2891         struct drm_i915_private *dev_priv = dev->dev_private;
2892         int total_size, cacheline_size;
2893         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2894         struct intel_watermark_params planea_params, planeb_params;
2895         unsigned long line_time_us;
2896         int sr_clock, sr_entries = 0, entries_required;
2897
2898         /* Create copies of the base settings for each pipe */
2899         planea_params = planeb_params = g4x_wm_info;
2900
2901         /* Grab a couple of global values before we overwrite them */
2902         total_size = planea_params.fifo_size;
2903         cacheline_size = planea_params.cacheline_size;
2904
2905         /*
2906          * Note: we need to make sure we don't overflow for various clock &
2907          * latency values.
2908          * clocks go from a few thousand to several hundred thousand.
2909          * latency is usually a few thousand
2910          */
2911         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2912                 1000;
2913         entries_required /= G4X_FIFO_LINE_SIZE;
2914         planea_wm = entries_required + planea_params.guard_size;
2915
2916         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2917                 1000;
2918         entries_required /= G4X_FIFO_LINE_SIZE;
2919         planeb_wm = entries_required + planeb_params.guard_size;
2920
2921         cursora_wm = cursorb_wm = 16;
2922         cursor_sr = 32;
2923
2924         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2925
2926         /* Calc sr entries for one plane configs */
2927         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2928                 /* self-refresh has much higher latency */
2929                 static const int sr_latency_ns = 12000;
2930
2931                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2932                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2933
2934                 /* Use ns/us then divide to preserve precision */
2935                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2936                               pixel_size * sr_hdisplay) / 1000;
2937                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2938                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2939                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2940         } else {
2941                 /* Turn off self refresh if both pipes are enabled */
2942                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2943                                         & ~FW_BLC_SELF_EN);
2944         }
2945
2946         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2947                   planea_wm, planeb_wm, sr_entries);
2948
2949         planea_wm &= 0x3f;
2950         planeb_wm &= 0x3f;
2951
2952         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2953                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2954                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2955         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2956                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2957         /* HPLL off in SR has some issues on G4x... disable it */
2958         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2959                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2960 }
2961
2962 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2963                            int planeb_clock, int sr_hdisplay, int pixel_size)
2964 {
2965         struct drm_i915_private *dev_priv = dev->dev_private;
2966         unsigned long line_time_us;
2967         int sr_clock, sr_entries, srwm = 1;
2968
2969         /* Calc sr entries for one plane configs */
2970         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2971                 /* self-refresh has much higher latency */
2972                 static const int sr_latency_ns = 12000;
2973
2974                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2975                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2976
2977                 /* Use ns/us then divide to preserve precision */
2978                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2979                               pixel_size * sr_hdisplay) / 1000;
2980                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2981                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2982                 srwm = I945_FIFO_SIZE - sr_entries;
2983                 if (srwm < 0)
2984                         srwm = 1;
2985                 srwm &= 0x3f;
2986                 if (IS_I965GM(dev))
2987                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2988         } else {
2989                 /* Turn off self refresh if both pipes are enabled */
2990                 if (IS_I965GM(dev))
2991                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2992                                    & ~FW_BLC_SELF_EN);
2993         }
2994
2995         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2996                       srwm);
2997
2998         /* 965 has limitations... */
2999         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3000                    (8 << 0));
3001         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3002 }
3003
3004 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3005                            int planeb_clock, int sr_hdisplay, int pixel_size)
3006 {
3007         struct drm_i915_private *dev_priv = dev->dev_private;
3008         uint32_t fwater_lo;
3009         uint32_t fwater_hi;
3010         int total_size, cacheline_size, cwm, srwm = 1;
3011         int planea_wm, planeb_wm;
3012         struct intel_watermark_params planea_params, planeb_params;
3013         unsigned long line_time_us;
3014         int sr_clock, sr_entries = 0;
3015
3016         /* Create copies of the base settings for each pipe */
3017         if (IS_I965GM(dev) || IS_I945GM(dev))
3018                 planea_params = planeb_params = i945_wm_info;
3019         else if (IS_I9XX(dev))
3020                 planea_params = planeb_params = i915_wm_info;
3021         else
3022                 planea_params = planeb_params = i855_wm_info;
3023
3024         /* Grab a couple of global values before we overwrite them */
3025         total_size = planea_params.fifo_size;
3026         cacheline_size = planea_params.cacheline_size;
3027
3028         /* Update per-plane FIFO sizes */
3029         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3030         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3031
3032         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3033                                        pixel_size, latency_ns);
3034         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3035                                        pixel_size, latency_ns);
3036         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3037
3038         /*
3039          * Overlay gets an aggressive default since video jitter is bad.
3040          */
3041         cwm = 2;
3042
3043         /* Calc sr entries for one plane configs */
3044         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3045             (!planea_clock || !planeb_clock)) {
3046                 /* self-refresh has much higher latency */
3047                 static const int sr_latency_ns = 6000;
3048
3049                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3050                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3051
3052                 /* Use ns/us then divide to preserve precision */
3053                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
3054                               pixel_size * sr_hdisplay) / 1000;
3055                 sr_entries = roundup(sr_entries / cacheline_size, 1);
3056                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3057                 srwm = total_size - sr_entries;
3058                 if (srwm < 0)
3059                         srwm = 1;
3060
3061                 if (IS_I945G(dev) || IS_I945GM(dev))
3062                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3063                 else if (IS_I915GM(dev)) {
3064                         /* 915M has a smaller SRWM field */
3065                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3066                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3067                 }
3068         } else {
3069                 /* Turn off self refresh if both pipes are enabled */
3070                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3071                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3072                                    & ~FW_BLC_SELF_EN);
3073                 } else if (IS_I915GM(dev)) {
3074                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3075                 }
3076         }
3077
3078         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3079                   planea_wm, planeb_wm, cwm, srwm);
3080
3081         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3082         fwater_hi = (cwm & 0x1f);
3083
3084         /* Set request length to 8 cachelines per fetch */
3085         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3086         fwater_hi = fwater_hi | (1 << 8);
3087
3088         I915_WRITE(FW_BLC, fwater_lo);
3089         I915_WRITE(FW_BLC2, fwater_hi);
3090 }
3091
3092 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3093                            int unused2, int pixel_size)
3094 {
3095         struct drm_i915_private *dev_priv = dev->dev_private;
3096         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3097         int planea_wm;
3098
3099         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3100
3101         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3102                                        pixel_size, latency_ns);
3103         fwater_lo |= (3<<8) | planea_wm;
3104
3105         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3106
3107         I915_WRITE(FW_BLC, fwater_lo);
3108 }
3109
3110 #define ILK_LP0_PLANE_LATENCY           700
3111
3112 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3113                        int planeb_clock, int sr_hdisplay, int pixel_size)
3114 {
3115         struct drm_i915_private *dev_priv = dev->dev_private;
3116         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3117         int sr_wm, cursor_wm;
3118         unsigned long line_time_us;
3119         int sr_clock, entries_required;
3120         u32 reg_value;
3121
3122         /* Calculate and update the watermark for plane A */
3123         if (planea_clock) {
3124                 entries_required = ((planea_clock / 1000) * pixel_size *
3125                                      ILK_LP0_PLANE_LATENCY) / 1000;
3126                 entries_required = DIV_ROUND_UP(entries_required,
3127                                    ironlake_display_wm_info.cacheline_size);
3128                 planea_wm = entries_required +
3129                             ironlake_display_wm_info.guard_size;
3130
3131                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3132                         planea_wm = ironlake_display_wm_info.max_wm;
3133
3134                 cursora_wm = 16;
3135                 reg_value = I915_READ(WM0_PIPEA_ILK);
3136                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3137                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3138                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3139                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3140                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3141                                 "cursor: %d\n", planea_wm, cursora_wm);
3142         }
3143         /* Calculate and update the watermark for plane B */
3144         if (planeb_clock) {
3145                 entries_required = ((planeb_clock / 1000) * pixel_size *
3146                                      ILK_LP0_PLANE_LATENCY) / 1000;
3147                 entries_required = DIV_ROUND_UP(entries_required,
3148                                    ironlake_display_wm_info.cacheline_size);
3149                 planeb_wm = entries_required +
3150                             ironlake_display_wm_info.guard_size;
3151
3152                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3153                         planeb_wm = ironlake_display_wm_info.max_wm;
3154
3155                 cursorb_wm = 16;
3156                 reg_value = I915_READ(WM0_PIPEB_ILK);
3157                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3158                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3159                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3160                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3161                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3162                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3163         }
3164
3165         /*
3166          * Calculate and update the self-refresh watermark only when one
3167          * display plane is used.
3168          */
3169         if (!planea_clock || !planeb_clock) {
3170                 int line_count;
3171                 /* Read the self-refresh latency. The unit is 0.5us */
3172                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3173
3174                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3175                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3176
3177                 /* Use ns/us then divide to preserve precision */
3178                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3179                                / 1000;
3180
3181                 /* calculate the self-refresh watermark for display plane */
3182                 entries_required = line_count * sr_hdisplay * pixel_size;
3183                 entries_required = DIV_ROUND_UP(entries_required,
3184                                    ironlake_display_srwm_info.cacheline_size);
3185                 sr_wm = entries_required +
3186                         ironlake_display_srwm_info.guard_size;
3187
3188                 /* calculate the self-refresh watermark for display cursor */
3189                 entries_required = line_count * pixel_size * 64;
3190                 entries_required = DIV_ROUND_UP(entries_required,
3191                                    ironlake_cursor_srwm_info.cacheline_size);
3192                 cursor_wm = entries_required +
3193                             ironlake_cursor_srwm_info.guard_size;
3194
3195                 /* configure watermark and enable self-refresh */
3196                 reg_value = I915_READ(WM1_LP_ILK);
3197                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3198                                WM1_LP_CURSOR_MASK);
3199                 reg_value |= WM1_LP_SR_EN |
3200                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3201                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3202
3203                 I915_WRITE(WM1_LP_ILK, reg_value);
3204                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3205                                 "cursor %d\n", sr_wm, cursor_wm);
3206
3207         } else {
3208                 /* Turn off self refresh if both pipes are enabled */
3209                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3210         }
3211 }
3212 /**
3213  * intel_update_watermarks - update FIFO watermark values based on current modes
3214  *
3215  * Calculate watermark values for the various WM regs based on current mode
3216  * and plane configuration.
3217  *
3218  * There are several cases to deal with here:
3219  *   - normal (i.e. non-self-refresh)
3220  *   - self-refresh (SR) mode
3221  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3222  *   - lines are small relative to FIFO size (buffer can hold more than 2
3223  *     lines), so need to account for TLB latency
3224  *
3225  *   The normal calculation is:
3226  *     watermark = dotclock * bytes per pixel * latency
3227  *   where latency is platform & configuration dependent (we assume pessimal
3228  *   values here).
3229  *
3230  *   The SR calculation is:
3231  *     watermark = (trunc(latency/line time)+1) * surface width *
3232  *       bytes per pixel
3233  *   where
3234  *     line time = htotal / dotclock
3235  *   and latency is assumed to be high, as above.
3236  *
3237  * The final value programmed to the register should always be rounded up,
3238  * and include an extra 2 entries to account for clock crossings.
3239  *
3240  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3241  * to set the non-SR watermarks to 8.
3242   */
3243 static void intel_update_watermarks(struct drm_device *dev)
3244 {
3245         struct drm_i915_private *dev_priv = dev->dev_private;
3246         struct drm_crtc *crtc;
3247         struct intel_crtc *intel_crtc;
3248         int sr_hdisplay = 0;
3249         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3250         int enabled = 0, pixel_size = 0;
3251
3252         if (!dev_priv->display.update_wm)
3253                 return;
3254
3255         /* Get the clock config from both planes */
3256         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3257                 intel_crtc = to_intel_crtc(crtc);
3258                 if (crtc->enabled) {
3259                         enabled++;
3260                         if (intel_crtc->plane == 0) {
3261                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3262                                           intel_crtc->pipe, crtc->mode.clock);
3263                                 planea_clock = crtc->mode.clock;
3264                         } else {
3265                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3266                                           intel_crtc->pipe, crtc->mode.clock);
3267                                 planeb_clock = crtc->mode.clock;
3268                         }
3269                         sr_hdisplay = crtc->mode.hdisplay;
3270                         sr_clock = crtc->mode.clock;
3271                         if (crtc->fb)
3272                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3273                         else
3274                                 pixel_size = 4; /* by default */
3275                 }
3276         }
3277
3278         if (enabled <= 0)
3279                 return;
3280
3281         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3282                                     sr_hdisplay, pixel_size);
3283 }
3284
3285 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3286                                struct drm_display_mode *mode,
3287                                struct drm_display_mode *adjusted_mode,
3288                                int x, int y,
3289                                struct drm_framebuffer *old_fb)
3290 {
3291         struct drm_device *dev = crtc->dev;
3292         struct drm_i915_private *dev_priv = dev->dev_private;
3293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3294         int pipe = intel_crtc->pipe;
3295         int plane = intel_crtc->plane;
3296         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3297         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3298         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3299         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3300         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3301         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3302         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3303         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3304         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3305         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3306         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3307         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3308         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3309         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3310         int refclk, num_connectors = 0;
3311         intel_clock_t clock, reduced_clock;
3312         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3313         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3314         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3315         bool is_edp = false;
3316         struct drm_mode_config *mode_config = &dev->mode_config;
3317         struct drm_encoder *encoder;
3318         struct intel_encoder *intel_encoder = NULL;
3319         const intel_limit_t *limit;
3320         int ret;
3321         struct fdi_m_n m_n = {0};
3322         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3323         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3324         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3325         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3326         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3327         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3328         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3329         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3330         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3331         int lvds_reg = LVDS;
3332         u32 temp;
3333         int sdvo_pixel_multiply;
3334         int target_clock;
3335
3336         drm_vblank_pre_modeset(dev, pipe);
3337
3338         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3339
3340                 if (!encoder || encoder->crtc != crtc)
3341                         continue;
3342
3343                 intel_encoder = enc_to_intel_encoder(encoder);
3344
3345                 switch (intel_encoder->type) {
3346                 case INTEL_OUTPUT_LVDS:
3347                         is_lvds = true;
3348                         break;
3349                 case INTEL_OUTPUT_SDVO:
3350                 case INTEL_OUTPUT_HDMI:
3351                         is_sdvo = true;
3352                         if (intel_encoder->needs_tv_clock)
3353                                 is_tv = true;
3354                         break;
3355                 case INTEL_OUTPUT_DVO:
3356                         is_dvo = true;
3357                         break;
3358                 case INTEL_OUTPUT_TVOUT:
3359                         is_tv = true;
3360                         break;
3361                 case INTEL_OUTPUT_ANALOG:
3362                         is_crt = true;
3363                         break;
3364                 case INTEL_OUTPUT_DISPLAYPORT:
3365                         is_dp = true;
3366                         break;
3367                 case INTEL_OUTPUT_EDP:
3368                         is_edp = true;
3369                         break;
3370                 }
3371
3372                 num_connectors++;
3373         }
3374
3375         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3376                 refclk = dev_priv->lvds_ssc_freq * 1000;
3377                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3378                                         refclk / 1000);
3379         } else if (IS_I9XX(dev)) {
3380                 refclk = 96000;
3381                 if (HAS_PCH_SPLIT(dev))
3382                         refclk = 120000; /* 120Mhz refclk */
3383         } else {
3384                 refclk = 48000;
3385         }
3386         
3387
3388         /*
3389          * Returns a set of divisors for the desired target clock with the given
3390          * refclk, or FALSE.  The returned values represent the clock equation:
3391          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3392          */
3393         limit = intel_limit(crtc);
3394         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3395         if (!ok) {
3396                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3397                 drm_vblank_post_modeset(dev, pipe);
3398                 return -EINVAL;
3399         }
3400
3401         if (is_lvds && dev_priv->lvds_downclock_avail) {
3402                 has_reduced_clock = limit->find_pll(limit, crtc,
3403                                                             dev_priv->lvds_downclock,
3404                                                             refclk,
3405                                                             &reduced_clock);
3406                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3407                         /*
3408                          * If the different P is found, it means that we can't
3409                          * switch the display clock by using the FP0/FP1.
3410                          * In such case we will disable the LVDS downclock
3411                          * feature.
3412                          */
3413                         DRM_DEBUG_KMS("Different P is found for "
3414                                                 "LVDS clock/downclock\n");
3415                         has_reduced_clock = 0;
3416                 }
3417         }
3418         /* SDVO TV has fixed PLL values depend on its clock range,
3419            this mirrors vbios setting. */
3420         if (is_sdvo && is_tv) {
3421                 if (adjusted_mode->clock >= 100000
3422                                 && adjusted_mode->clock < 140500) {
3423                         clock.p1 = 2;
3424                         clock.p2 = 10;
3425                         clock.n = 3;
3426                         clock.m1 = 16;
3427                         clock.m2 = 8;
3428                 } else if (adjusted_mode->clock >= 140500
3429                                 && adjusted_mode->clock <= 200000) {
3430                         clock.p1 = 1;
3431                         clock.p2 = 10;
3432                         clock.n = 6;
3433                         clock.m1 = 12;
3434                         clock.m2 = 8;
3435                 }
3436         }
3437
3438         /* FDI link */
3439         if (HAS_PCH_SPLIT(dev)) {
3440                 int lane = 0, link_bw, bpp;
3441                 /* eDP doesn't require FDI link, so just set DP M/N
3442                    according to current link config */
3443                 if (is_edp) {
3444                         target_clock = mode->clock;
3445                         intel_edp_link_config(intel_encoder,
3446                                         &lane, &link_bw);
3447                 } else {
3448                         /* DP over FDI requires target mode clock
3449                            instead of link clock */
3450                         if (is_dp)
3451                                 target_clock = mode->clock;
3452                         else
3453                                 target_clock = adjusted_mode->clock;
3454                         link_bw = 270000;
3455                 }
3456
3457                 /* determine panel color depth */
3458                 temp = I915_READ(pipeconf_reg);
3459                 temp &= ~PIPE_BPC_MASK;
3460                 if (is_lvds) {
3461                         int lvds_reg = I915_READ(PCH_LVDS);
3462                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3463                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3464                                 temp |= PIPE_8BPC;
3465                         else
3466                                 temp |= PIPE_6BPC;
3467                 } else if (is_edp) {
3468                         switch (dev_priv->edp_bpp/3) {
3469                         case 8:
3470                                 temp |= PIPE_8BPC;
3471                                 break;
3472                         case 10:
3473                                 temp |= PIPE_10BPC;
3474                                 break;
3475                         case 6:
3476                                 temp |= PIPE_6BPC;
3477                                 break;
3478                         case 12:
3479                                 temp |= PIPE_12BPC;
3480                                 break;
3481                         }
3482                 } else
3483                         temp |= PIPE_8BPC;
3484                 I915_WRITE(pipeconf_reg, temp);
3485                 I915_READ(pipeconf_reg);
3486
3487                 switch (temp & PIPE_BPC_MASK) {
3488                 case PIPE_8BPC:
3489                         bpp = 24;
3490                         break;
3491                 case PIPE_10BPC:
3492                         bpp = 30;
3493                         break;
3494                 case PIPE_6BPC:
3495                         bpp = 18;
3496                         break;
3497                 case PIPE_12BPC:
3498                         bpp = 36;
3499                         break;
3500                 default:
3501                         DRM_ERROR("unknown pipe bpc value\n");
3502                         bpp = 24;
3503                 }
3504
3505                 if (!lane) {
3506                         /* 
3507                          * Account for spread spectrum to avoid
3508                          * oversubscribing the link. Max center spread
3509                          * is 2.5%; use 5% for safety's sake.
3510                          */
3511                         u32 bps = target_clock * bpp * 21 / 20;
3512                         lane = bps / (link_bw * 8) + 1;
3513                 }
3514
3515                 intel_crtc->fdi_lanes = lane;
3516
3517                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3518         }
3519
3520         /* Ironlake: try to setup display ref clock before DPLL
3521          * enabling. This is only under driver's control after
3522          * PCH B stepping, previous chipset stepping should be
3523          * ignoring this setting.
3524          */
3525         if (HAS_PCH_SPLIT(dev)) {
3526                 temp = I915_READ(PCH_DREF_CONTROL);
3527                 /* Always enable nonspread source */
3528                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3529                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3530                 I915_WRITE(PCH_DREF_CONTROL, temp);
3531                 POSTING_READ(PCH_DREF_CONTROL);
3532
3533                 temp &= ~DREF_SSC_SOURCE_MASK;
3534                 temp |= DREF_SSC_SOURCE_ENABLE;
3535                 I915_WRITE(PCH_DREF_CONTROL, temp);
3536                 POSTING_READ(PCH_DREF_CONTROL);
3537
3538                 udelay(200);
3539
3540                 if (is_edp) {
3541                         if (dev_priv->lvds_use_ssc) {
3542                                 temp |= DREF_SSC1_ENABLE;
3543                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3544                                 POSTING_READ(PCH_DREF_CONTROL);
3545
3546                                 udelay(200);
3547
3548                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3549                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3550                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3551                                 POSTING_READ(PCH_DREF_CONTROL);
3552                         } else {
3553                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3554                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3555                                 POSTING_READ(PCH_DREF_CONTROL);
3556                         }
3557                 }
3558         }
3559
3560         if (IS_PINEVIEW(dev)) {
3561                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3562                 if (has_reduced_clock)
3563                         fp2 = (1 << reduced_clock.n) << 16 |
3564                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3565         } else {
3566                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3567                 if (has_reduced_clock)
3568                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3569                                 reduced_clock.m2;
3570         }
3571
3572         if (!HAS_PCH_SPLIT(dev))
3573                 dpll = DPLL_VGA_MODE_DIS;
3574
3575         if (IS_I9XX(dev)) {
3576                 if (is_lvds)
3577                         dpll |= DPLLB_MODE_LVDS;
3578                 else
3579                         dpll |= DPLLB_MODE_DAC_SERIAL;
3580                 if (is_sdvo) {
3581                         dpll |= DPLL_DVO_HIGH_SPEED;
3582                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3583                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3584                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3585                         else if (HAS_PCH_SPLIT(dev))
3586                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3587                 }
3588                 if (is_dp)
3589                         dpll |= DPLL_DVO_HIGH_SPEED;
3590
3591                 /* compute bitmask from p1 value */
3592                 if (IS_PINEVIEW(dev))
3593                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3594                 else {
3595                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3596                         /* also FPA1 */
3597                         if (HAS_PCH_SPLIT(dev))
3598                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3599                         if (IS_G4X(dev) && has_reduced_clock)
3600                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3601                 }
3602                 switch (clock.p2) {
3603                 case 5:
3604                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3605                         break;
3606                 case 7:
3607                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3608                         break;
3609                 case 10:
3610                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3611                         break;
3612                 case 14:
3613                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3614                         break;
3615                 }
3616                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3617                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3618         } else {
3619                 if (is_lvds) {
3620                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3621                 } else {
3622                         if (clock.p1 == 2)
3623                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3624                         else
3625                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3626                         if (clock.p2 == 4)
3627                                 dpll |= PLL_P2_DIVIDE_BY_4;
3628                 }
3629         }
3630
3631         if (is_sdvo && is_tv)
3632                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3633         else if (is_tv)
3634                 /* XXX: just matching BIOS for now */
3635                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3636                 dpll |= 3;
3637         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3638                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3639         else
3640                 dpll |= PLL_REF_INPUT_DREFCLK;
3641
3642         /* setup pipeconf */
3643         pipeconf = I915_READ(pipeconf_reg);
3644
3645         /* Set up the display plane register */
3646         dspcntr = DISPPLANE_GAMMA_ENABLE;
3647
3648         /* Ironlake's plane is forced to pipe, bit 24 is to
3649            enable color space conversion */
3650         if (!HAS_PCH_SPLIT(dev)) {
3651                 if (pipe == 0)
3652                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3653                 else
3654                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3655         }
3656
3657         if (pipe == 0 && !IS_I965G(dev)) {
3658                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3659                  * core speed.
3660                  *
3661                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3662                  * pipe == 0 check?
3663                  */
3664                 if (mode->clock >
3665                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3666                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3667                 else
3668                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3669         }
3670
3671         dspcntr |= DISPLAY_PLANE_ENABLE;
3672         pipeconf |= PIPEACONF_ENABLE;
3673         dpll |= DPLL_VCO_ENABLE;
3674
3675
3676         /* Disable the panel fitter if it was on our pipe */
3677         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3678                 I915_WRITE(PFIT_CONTROL, 0);
3679
3680         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3681         drm_mode_debug_printmodeline(mode);
3682
3683         /* assign to Ironlake registers */
3684         if (HAS_PCH_SPLIT(dev)) {
3685                 fp_reg = pch_fp_reg;
3686                 dpll_reg = pch_dpll_reg;
3687         }
3688
3689         if (is_edp) {
3690                 ironlake_disable_pll_edp(crtc);
3691         } else if ((dpll & DPLL_VCO_ENABLE)) {
3692                 I915_WRITE(fp_reg, fp);
3693                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3694                 I915_READ(dpll_reg);
3695                 udelay(150);
3696         }
3697
3698         /* enable transcoder DPLL */
3699         if (HAS_PCH_CPT(dev)) {
3700                 temp = I915_READ(PCH_DPLL_SEL);
3701                 if (trans_dpll_sel == 0)
3702                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3703                 else
3704                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3705                 I915_WRITE(PCH_DPLL_SEL, temp);
3706                 I915_READ(PCH_DPLL_SEL);
3707                 udelay(150);
3708         }
3709
3710         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3711          * This is an exception to the general rule that mode_set doesn't turn
3712          * things on.
3713          */
3714         if (is_lvds) {
3715                 u32 lvds;
3716
3717                 if (HAS_PCH_SPLIT(dev))
3718                         lvds_reg = PCH_LVDS;
3719
3720                 lvds = I915_READ(lvds_reg);
3721                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3722                 if (pipe == 1) {
3723                         if (HAS_PCH_CPT(dev))
3724                                 lvds |= PORT_TRANS_B_SEL_CPT;
3725                         else
3726                                 lvds |= LVDS_PIPEB_SELECT;
3727                 } else {
3728                         if (HAS_PCH_CPT(dev))
3729                                 lvds &= ~PORT_TRANS_SEL_MASK;
3730                         else
3731                                 lvds &= ~LVDS_PIPEB_SELECT;
3732                 }
3733                 /* set the corresponsding LVDS_BORDER bit */
3734                 lvds |= dev_priv->lvds_border_bits;
3735                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3736                  * set the DPLLs for dual-channel mode or not.
3737                  */
3738                 if (clock.p2 == 7)
3739                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3740                 else
3741                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3742
3743                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3744                  * appropriately here, but we need to look more thoroughly into how
3745                  * panels behave in the two modes.
3746                  */
3747                 /* set the dithering flag */
3748                 if (IS_I965G(dev)) {
3749                         if (dev_priv->lvds_dither) {
3750                                 if (HAS_PCH_SPLIT(dev)) {
3751                                         pipeconf |= PIPE_ENABLE_DITHER;
3752                                         pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3753                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
3754                                 } else
3755                                         lvds |= LVDS_ENABLE_DITHER;
3756                         } else {
3757                                 if (HAS_PCH_SPLIT(dev)) {
3758                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3759                                         pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3760                                 } else
3761                                         lvds &= ~LVDS_ENABLE_DITHER;
3762                         }
3763                 }
3764                 I915_WRITE(lvds_reg, lvds);
3765                 I915_READ(lvds_reg);
3766         }
3767         if (is_dp)
3768                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3769         else if (HAS_PCH_SPLIT(dev)) {
3770                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3771                 if (pipe == 0) {
3772                         I915_WRITE(TRANSA_DATA_M1, 0);
3773                         I915_WRITE(TRANSA_DATA_N1, 0);
3774                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3775                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3776                 } else {
3777                         I915_WRITE(TRANSB_DATA_M1, 0);
3778                         I915_WRITE(TRANSB_DATA_N1, 0);
3779                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3780                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
3781                 }
3782         }
3783
3784         if (!is_edp) {
3785                 I915_WRITE(fp_reg, fp);
3786                 I915_WRITE(dpll_reg, dpll);
3787                 I915_READ(dpll_reg);
3788                 /* Wait for the clocks to stabilize. */
3789                 udelay(150);
3790
3791                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3792                         if (is_sdvo) {
3793                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3794                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3795                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3796                         } else
3797                                 I915_WRITE(dpll_md_reg, 0);
3798                 } else {
3799                         /* write it again -- the BIOS does, after all */
3800                         I915_WRITE(dpll_reg, dpll);
3801                 }
3802                 I915_READ(dpll_reg);
3803                 /* Wait for the clocks to stabilize. */
3804                 udelay(150);
3805         }
3806
3807         if (is_lvds && has_reduced_clock && i915_powersave) {
3808                 I915_WRITE(fp_reg + 4, fp2);
3809                 intel_crtc->lowfreq_avail = true;
3810                 if (HAS_PIPE_CXSR(dev)) {
3811                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3812                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3813                 }
3814         } else {
3815                 I915_WRITE(fp_reg + 4, fp);
3816                 intel_crtc->lowfreq_avail = false;
3817                 if (HAS_PIPE_CXSR(dev)) {
3818                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3819                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3820                 }
3821         }
3822
3823         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3824                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3825                 /* the chip adds 2 halflines automatically */
3826                 adjusted_mode->crtc_vdisplay -= 1;
3827                 adjusted_mode->crtc_vtotal -= 1;
3828                 adjusted_mode->crtc_vblank_start -= 1;
3829                 adjusted_mode->crtc_vblank_end -= 1;
3830                 adjusted_mode->crtc_vsync_end -= 1;
3831                 adjusted_mode->crtc_vsync_start -= 1;
3832         } else
3833                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
3834
3835         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3836                    ((adjusted_mode->crtc_htotal - 1) << 16));
3837         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3838                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3839         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3840                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3841         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3842                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3843         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3844                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3845         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3846                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3847         /* pipesrc and dspsize control the size that is scaled from, which should
3848          * always be the user's requested size.
3849          */
3850         if (!HAS_PCH_SPLIT(dev)) {
3851                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3852                                 (mode->hdisplay - 1));
3853                 I915_WRITE(dsppos_reg, 0);
3854         }
3855         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3856
3857         if (HAS_PCH_SPLIT(dev)) {
3858                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3859                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3860                 I915_WRITE(link_m1_reg, m_n.link_m);
3861                 I915_WRITE(link_n1_reg, m_n.link_n);
3862
3863                 if (is_edp) {
3864                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3865                 } else {
3866                         /* enable FDI RX PLL too */
3867                         temp = I915_READ(fdi_rx_reg);
3868                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3869                         I915_READ(fdi_rx_reg);
3870                         udelay(200);
3871
3872                         /* enable FDI TX PLL too */
3873                         temp = I915_READ(fdi_tx_reg);
3874                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
3875                         I915_READ(fdi_tx_reg);
3876
3877                         /* enable FDI RX PCDCLK */
3878                         temp = I915_READ(fdi_rx_reg);
3879                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
3880                         I915_READ(fdi_rx_reg);
3881                         udelay(200);
3882                 }
3883         }
3884
3885         I915_WRITE(pipeconf_reg, pipeconf);
3886         I915_READ(pipeconf_reg);
3887
3888         intel_wait_for_vblank(dev);
3889
3890         if (IS_IRONLAKE(dev)) {
3891                 /* enable address swizzle for tiling buffer */
3892                 temp = I915_READ(DISP_ARB_CTL);
3893                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3894         }
3895
3896         I915_WRITE(dspcntr_reg, dspcntr);
3897
3898         /* Flush the plane changes */
3899         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3900
3901         if ((IS_I965G(dev) || plane == 0))
3902                 intel_update_fbc(crtc, &crtc->mode);
3903
3904         intel_update_watermarks(dev);
3905
3906         drm_vblank_post_modeset(dev, pipe);
3907
3908         return ret;
3909 }
3910
3911 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3912 void intel_crtc_load_lut(struct drm_crtc *crtc)
3913 {
3914         struct drm_device *dev = crtc->dev;
3915         struct drm_i915_private *dev_priv = dev->dev_private;
3916         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3917         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3918         int i;
3919
3920         /* The clocks have to be on to load the palette. */
3921         if (!crtc->enabled)
3922                 return;
3923
3924         /* use legacy palette for Ironlake */
3925         if (HAS_PCH_SPLIT(dev))
3926                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3927                                                    LGC_PALETTE_B;
3928
3929         for (i = 0; i < 256; i++) {
3930                 I915_WRITE(palreg + 4 * i,
3931                            (intel_crtc->lut_r[i] << 16) |
3932                            (intel_crtc->lut_g[i] << 8) |
3933                            intel_crtc->lut_b[i]);
3934         }
3935 }
3936
3937 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3938                                  struct drm_file *file_priv,
3939                                  uint32_t handle,
3940                                  uint32_t width, uint32_t height)
3941 {
3942         struct drm_device *dev = crtc->dev;
3943         struct drm_i915_private *dev_priv = dev->dev_private;
3944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3945         struct drm_gem_object *bo;
3946         struct drm_i915_gem_object *obj_priv;
3947         int pipe = intel_crtc->pipe;
3948         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3949         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3950         uint32_t temp = I915_READ(control);
3951         size_t addr;
3952         int ret;
3953
3954         DRM_DEBUG_KMS("\n");
3955
3956         /* if we want to turn off the cursor ignore width and height */
3957         if (!handle) {
3958                 DRM_DEBUG_KMS("cursor off\n");
3959                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3960                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3961                         temp |= CURSOR_MODE_DISABLE;
3962                 } else {
3963                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3964                 }
3965                 addr = 0;
3966                 bo = NULL;
3967                 mutex_lock(&dev->struct_mutex);
3968                 goto finish;
3969         }
3970
3971         /* Currently we only support 64x64 cursors */
3972         if (width != 64 || height != 64) {
3973                 DRM_ERROR("we currently only support 64x64 cursors\n");
3974                 return -EINVAL;
3975         }
3976
3977         bo = drm_gem_object_lookup(dev, file_priv, handle);
3978         if (!bo)
3979                 return -ENOENT;
3980
3981         obj_priv = to_intel_bo(bo);
3982
3983         if (bo->size < width * height * 4) {
3984                 DRM_ERROR("buffer is to small\n");
3985                 ret = -ENOMEM;
3986                 goto fail;
3987         }
3988
3989         /* we only need to pin inside GTT if cursor is non-phy */
3990         mutex_lock(&dev->struct_mutex);
3991         if (!dev_priv->info->cursor_needs_physical) {
3992                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3993                 if (ret) {
3994                         DRM_ERROR("failed to pin cursor bo\n");
3995                         goto fail_locked;
3996                 }
3997
3998                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
3999                 if (ret) {
4000                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4001                         goto fail_unpin;
4002                 }
4003
4004                 addr = obj_priv->gtt_offset;
4005         } else {
4006                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
4007                 if (ret) {
4008                         DRM_ERROR("failed to attach phys object\n");
4009                         goto fail_locked;
4010                 }
4011                 addr = obj_priv->phys_obj->handle->busaddr;
4012         }
4013
4014         if (!IS_I9XX(dev))
4015                 I915_WRITE(CURSIZE, (height << 12) | width);
4016
4017         /* Hooray for CUR*CNTR differences */
4018         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4019                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4020                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4021                 temp |= (pipe << 28); /* Connect to correct pipe */
4022         } else {
4023                 temp &= ~(CURSOR_FORMAT_MASK);
4024                 temp |= CURSOR_ENABLE;
4025                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4026         }
4027
4028  finish:
4029         I915_WRITE(control, temp);
4030         I915_WRITE(base, addr);
4031
4032         if (intel_crtc->cursor_bo) {
4033                 if (dev_priv->info->cursor_needs_physical) {
4034                         if (intel_crtc->cursor_bo != bo)
4035                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4036                 } else
4037                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4038                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4039         }
4040
4041         mutex_unlock(&dev->struct_mutex);
4042
4043         intel_crtc->cursor_addr = addr;
4044         intel_crtc->cursor_bo = bo;
4045
4046         return 0;
4047 fail_unpin:
4048         i915_gem_object_unpin(bo);
4049 fail_locked:
4050         mutex_unlock(&dev->struct_mutex);
4051 fail:
4052         drm_gem_object_unreference_unlocked(bo);
4053         return ret;
4054 }
4055
4056 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4057 {
4058         struct drm_device *dev = crtc->dev;
4059         struct drm_i915_private *dev_priv = dev->dev_private;
4060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4061         struct intel_framebuffer *intel_fb;
4062         int pipe = intel_crtc->pipe;
4063         uint32_t temp = 0;
4064         uint32_t adder;
4065
4066         if (crtc->fb) {
4067                 intel_fb = to_intel_framebuffer(crtc->fb);
4068                 intel_mark_busy(dev, intel_fb->obj);
4069         }
4070
4071         if (x < 0) {
4072                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4073                 x = -x;
4074         }
4075         if (y < 0) {
4076                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4077                 y = -y;
4078         }
4079
4080         temp |= x << CURSOR_X_SHIFT;
4081         temp |= y << CURSOR_Y_SHIFT;
4082
4083         adder = intel_crtc->cursor_addr;
4084         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
4085         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
4086
4087         return 0;
4088 }
4089
4090 /** Sets the color ramps on behalf of RandR */
4091 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4092                                  u16 blue, int regno)
4093 {
4094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4095
4096         intel_crtc->lut_r[regno] = red >> 8;
4097         intel_crtc->lut_g[regno] = green >> 8;
4098         intel_crtc->lut_b[regno] = blue >> 8;
4099 }
4100
4101 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4102                              u16 *blue, int regno)
4103 {
4104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4105
4106         *red = intel_crtc->lut_r[regno] << 8;
4107         *green = intel_crtc->lut_g[regno] << 8;
4108         *blue = intel_crtc->lut_b[regno] << 8;
4109 }
4110
4111 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4112                                  u16 *blue, uint32_t size)
4113 {
4114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4115         int i;
4116
4117         if (size != 256)
4118                 return;
4119
4120         for (i = 0; i < 256; i++) {
4121                 intel_crtc->lut_r[i] = red[i] >> 8;
4122                 intel_crtc->lut_g[i] = green[i] >> 8;
4123                 intel_crtc->lut_b[i] = blue[i] >> 8;
4124         }
4125
4126         intel_crtc_load_lut(crtc);
4127 }
4128
4129 /**
4130  * Get a pipe with a simple mode set on it for doing load-based monitor
4131  * detection.
4132  *
4133  * It will be up to the load-detect code to adjust the pipe as appropriate for
4134  * its requirements.  The pipe will be connected to no other encoders.
4135  *
4136  * Currently this code will only succeed if there is a pipe with no encoders
4137  * configured for it.  In the future, it could choose to temporarily disable
4138  * some outputs to free up a pipe for its use.
4139  *
4140  * \return crtc, or NULL if no pipes are available.
4141  */
4142
4143 /* VESA 640x480x72Hz mode to set on the pipe */
4144 static struct drm_display_mode load_detect_mode = {
4145         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4146                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4147 };
4148
4149 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4150                                             struct drm_connector *connector,
4151                                             struct drm_display_mode *mode,
4152                                             int *dpms_mode)
4153 {
4154         struct intel_crtc *intel_crtc;
4155         struct drm_crtc *possible_crtc;
4156         struct drm_crtc *supported_crtc =NULL;
4157         struct drm_encoder *encoder = &intel_encoder->enc;
4158         struct drm_crtc *crtc = NULL;
4159         struct drm_device *dev = encoder->dev;
4160         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4161         struct drm_crtc_helper_funcs *crtc_funcs;
4162         int i = -1;
4163
4164         /*
4165          * Algorithm gets a little messy:
4166          *   - if the connector already has an assigned crtc, use it (but make
4167          *     sure it's on first)
4168          *   - try to find the first unused crtc that can drive this connector,
4169          *     and use that if we find one
4170          *   - if there are no unused crtcs available, try to use the first
4171          *     one we found that supports the connector
4172          */
4173
4174         /* See if we already have a CRTC for this connector */
4175         if (encoder->crtc) {
4176                 crtc = encoder->crtc;
4177                 /* Make sure the crtc and connector are running */
4178                 intel_crtc = to_intel_crtc(crtc);
4179                 *dpms_mode = intel_crtc->dpms_mode;
4180                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4181                         crtc_funcs = crtc->helper_private;
4182                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4183                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4184                 }
4185                 return crtc;
4186         }
4187
4188         /* Find an unused one (if possible) */
4189         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4190                 i++;
4191                 if (!(encoder->possible_crtcs & (1 << i)))
4192                         continue;
4193                 if (!possible_crtc->enabled) {
4194                         crtc = possible_crtc;
4195                         break;
4196                 }
4197                 if (!supported_crtc)
4198                         supported_crtc = possible_crtc;
4199         }
4200
4201         /*
4202          * If we didn't find an unused CRTC, don't use any.
4203          */
4204         if (!crtc) {
4205                 return NULL;
4206         }
4207
4208         encoder->crtc = crtc;
4209         connector->encoder = encoder;
4210         intel_encoder->load_detect_temp = true;
4211
4212         intel_crtc = to_intel_crtc(crtc);
4213         *dpms_mode = intel_crtc->dpms_mode;
4214
4215         if (!crtc->enabled) {
4216                 if (!mode)
4217                         mode = &load_detect_mode;
4218                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4219         } else {
4220                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4221                         crtc_funcs = crtc->helper_private;
4222                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4223                 }
4224
4225                 /* Add this connector to the crtc */
4226                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4227                 encoder_funcs->commit(encoder);
4228         }
4229         /* let the connector get through one full cycle before testing */
4230         intel_wait_for_vblank(dev);
4231
4232         return crtc;
4233 }
4234
4235 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4236                                     struct drm_connector *connector, int dpms_mode)
4237 {
4238         struct drm_encoder *encoder = &intel_encoder->enc;
4239         struct drm_device *dev = encoder->dev;
4240         struct drm_crtc *crtc = encoder->crtc;
4241         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4242         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4243
4244         if (intel_encoder->load_detect_temp) {
4245                 encoder->crtc = NULL;
4246                 connector->encoder = NULL;
4247                 intel_encoder->load_detect_temp = false;
4248                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4249                 drm_helper_disable_unused_functions(dev);
4250         }
4251
4252         /* Switch crtc and encoder back off if necessary */
4253         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4254                 if (encoder->crtc == crtc)
4255                         encoder_funcs->dpms(encoder, dpms_mode);
4256                 crtc_funcs->dpms(crtc, dpms_mode);
4257         }
4258 }
4259
4260 /* Returns the clock of the currently programmed mode of the given pipe. */
4261 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4262 {
4263         struct drm_i915_private *dev_priv = dev->dev_private;
4264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4265         int pipe = intel_crtc->pipe;
4266         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4267         u32 fp;
4268         intel_clock_t clock;
4269
4270         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4271                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4272         else
4273                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4274
4275         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4276         if (IS_PINEVIEW(dev)) {
4277                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4278                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4279         } else {
4280                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4281                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4282         }
4283
4284         if (IS_I9XX(dev)) {
4285                 if (IS_PINEVIEW(dev))
4286                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4287                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4288                 else
4289                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4290                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4291
4292                 switch (dpll & DPLL_MODE_MASK) {
4293                 case DPLLB_MODE_DAC_SERIAL:
4294                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4295                                 5 : 10;
4296                         break;
4297                 case DPLLB_MODE_LVDS:
4298                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4299                                 7 : 14;
4300                         break;
4301                 default:
4302                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4303                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4304                         return 0;
4305                 }
4306
4307                 /* XXX: Handle the 100Mhz refclk */
4308                 intel_clock(dev, 96000, &clock);
4309         } else {
4310                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4311
4312                 if (is_lvds) {
4313                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4314                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4315                         clock.p2 = 14;
4316
4317                         if ((dpll & PLL_REF_INPUT_MASK) ==
4318                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4319                                 /* XXX: might not be 66MHz */
4320                                 intel_clock(dev, 66000, &clock);
4321                         } else
4322                                 intel_clock(dev, 48000, &clock);
4323                 } else {
4324                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4325                                 clock.p1 = 2;
4326                         else {
4327                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4328                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4329                         }
4330                         if (dpll & PLL_P2_DIVIDE_BY_4)
4331                                 clock.p2 = 4;
4332                         else
4333                                 clock.p2 = 2;
4334
4335                         intel_clock(dev, 48000, &clock);
4336                 }
4337         }
4338
4339         /* XXX: It would be nice to validate the clocks, but we can't reuse
4340          * i830PllIsValid() because it relies on the xf86_config connector
4341          * configuration being accurate, which it isn't necessarily.
4342          */
4343
4344         return clock.dot;
4345 }
4346
4347 /** Returns the currently programmed mode of the given pipe. */
4348 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4349                                              struct drm_crtc *crtc)
4350 {
4351         struct drm_i915_private *dev_priv = dev->dev_private;
4352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4353         int pipe = intel_crtc->pipe;
4354         struct drm_display_mode *mode;
4355         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4356         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4357         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4358         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4359
4360         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4361         if (!mode)
4362                 return NULL;
4363
4364         mode->clock = intel_crtc_clock_get(dev, crtc);
4365         mode->hdisplay = (htot & 0xffff) + 1;
4366         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4367         mode->hsync_start = (hsync & 0xffff) + 1;
4368         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4369         mode->vdisplay = (vtot & 0xffff) + 1;
4370         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4371         mode->vsync_start = (vsync & 0xffff) + 1;
4372         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4373
4374         drm_mode_set_name(mode);
4375         drm_mode_set_crtcinfo(mode, 0);
4376
4377         return mode;
4378 }
4379
4380 #define GPU_IDLE_TIMEOUT 500 /* ms */
4381
4382 /* When this timer fires, we've been idle for awhile */
4383 static void intel_gpu_idle_timer(unsigned long arg)
4384 {
4385         struct drm_device *dev = (struct drm_device *)arg;
4386         drm_i915_private_t *dev_priv = dev->dev_private;
4387
4388         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4389
4390         dev_priv->busy = false;
4391
4392         queue_work(dev_priv->wq, &dev_priv->idle_work);
4393 }
4394
4395 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4396
4397 static void intel_crtc_idle_timer(unsigned long arg)
4398 {
4399         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4400         struct drm_crtc *crtc = &intel_crtc->base;
4401         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4402
4403         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4404
4405         intel_crtc->busy = false;
4406
4407         queue_work(dev_priv->wq, &dev_priv->idle_work);
4408 }
4409
4410 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4411 {
4412         struct drm_device *dev = crtc->dev;
4413         drm_i915_private_t *dev_priv = dev->dev_private;
4414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4415         int pipe = intel_crtc->pipe;
4416         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4417         int dpll = I915_READ(dpll_reg);
4418
4419         if (HAS_PCH_SPLIT(dev))
4420                 return;
4421
4422         if (!dev_priv->lvds_downclock_avail)
4423                 return;
4424
4425         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4426                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4427
4428                 /* Unlock panel regs */
4429                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4430                            PANEL_UNLOCK_REGS);
4431
4432                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4433                 I915_WRITE(dpll_reg, dpll);
4434                 dpll = I915_READ(dpll_reg);
4435                 intel_wait_for_vblank(dev);
4436                 dpll = I915_READ(dpll_reg);
4437                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4438                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4439
4440                 /* ...and lock them again */
4441                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4442         }
4443
4444         /* Schedule downclock */
4445         if (schedule)
4446                 mod_timer(&intel_crtc->idle_timer, jiffies +
4447                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4448 }
4449
4450 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4451 {
4452         struct drm_device *dev = crtc->dev;
4453         drm_i915_private_t *dev_priv = dev->dev_private;
4454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4455         int pipe = intel_crtc->pipe;
4456         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4457         int dpll = I915_READ(dpll_reg);
4458
4459         if (HAS_PCH_SPLIT(dev))
4460                 return;
4461
4462         if (!dev_priv->lvds_downclock_avail)
4463                 return;
4464
4465         /*
4466          * Since this is called by a timer, we should never get here in
4467          * the manual case.
4468          */
4469         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4470                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4471
4472                 /* Unlock panel regs */
4473                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4474                            PANEL_UNLOCK_REGS);
4475
4476                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4477                 I915_WRITE(dpll_reg, dpll);
4478                 dpll = I915_READ(dpll_reg);
4479                 intel_wait_for_vblank(dev);
4480                 dpll = I915_READ(dpll_reg);
4481                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4482                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4483
4484                 /* ...and lock them again */
4485                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4486         }
4487
4488 }
4489
4490 /**
4491  * intel_idle_update - adjust clocks for idleness
4492  * @work: work struct
4493  *
4494  * Either the GPU or display (or both) went idle.  Check the busy status
4495  * here and adjust the CRTC and GPU clocks as necessary.
4496  */
4497 static void intel_idle_update(struct work_struct *work)
4498 {
4499         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4500                                                     idle_work);
4501         struct drm_device *dev = dev_priv->dev;
4502         struct drm_crtc *crtc;
4503         struct intel_crtc *intel_crtc;
4504         int enabled = 0;
4505
4506         if (!i915_powersave)
4507                 return;
4508
4509         mutex_lock(&dev->struct_mutex);
4510
4511         i915_update_gfx_val(dev_priv);
4512
4513         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4514                 /* Skip inactive CRTCs */
4515                 if (!crtc->fb)
4516                         continue;
4517
4518                 enabled++;
4519                 intel_crtc = to_intel_crtc(crtc);
4520                 if (!intel_crtc->busy)
4521                         intel_decrease_pllclock(crtc);
4522         }
4523
4524         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4525                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4526                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4527         }
4528
4529         mutex_unlock(&dev->struct_mutex);
4530 }
4531
4532 /**
4533  * intel_mark_busy - mark the GPU and possibly the display busy
4534  * @dev: drm device
4535  * @obj: object we're operating on
4536  *
4537  * Callers can use this function to indicate that the GPU is busy processing
4538  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4539  * buffer), we'll also mark the display as busy, so we know to increase its
4540  * clock frequency.
4541  */
4542 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4543 {
4544         drm_i915_private_t *dev_priv = dev->dev_private;
4545         struct drm_crtc *crtc = NULL;
4546         struct intel_framebuffer *intel_fb;
4547         struct intel_crtc *intel_crtc;
4548
4549         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4550                 return;
4551
4552         if (!dev_priv->busy) {
4553                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4554                         u32 fw_blc_self;
4555
4556                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4557                         fw_blc_self = I915_READ(FW_BLC_SELF);
4558                         fw_blc_self &= ~FW_BLC_SELF_EN;
4559                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4560                 }
4561                 dev_priv->busy = true;
4562         } else
4563                 mod_timer(&dev_priv->idle_timer, jiffies +
4564                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4565
4566         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4567                 if (!crtc->fb)
4568                         continue;
4569
4570                 intel_crtc = to_intel_crtc(crtc);
4571                 intel_fb = to_intel_framebuffer(crtc->fb);
4572                 if (intel_fb->obj == obj) {
4573                         if (!intel_crtc->busy) {
4574                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4575                                         u32 fw_blc_self;
4576
4577                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4578                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4579                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4580                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4581                                 }
4582                                 /* Non-busy -> busy, upclock */
4583                                 intel_increase_pllclock(crtc, true);
4584                                 intel_crtc->busy = true;
4585                         } else {
4586                                 /* Busy -> busy, put off timer */
4587                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4588                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4589                         }
4590                 }
4591         }
4592 }
4593
4594 static void intel_crtc_destroy(struct drm_crtc *crtc)
4595 {
4596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4597
4598         drm_crtc_cleanup(crtc);
4599         kfree(intel_crtc);
4600 }
4601
4602 struct intel_unpin_work {
4603         struct work_struct work;
4604         struct drm_device *dev;
4605         struct drm_gem_object *old_fb_obj;
4606         struct drm_gem_object *pending_flip_obj;
4607         struct drm_pending_vblank_event *event;
4608         int pending;
4609 };
4610
4611 static void intel_unpin_work_fn(struct work_struct *__work)
4612 {
4613         struct intel_unpin_work *work =
4614                 container_of(__work, struct intel_unpin_work, work);
4615
4616         mutex_lock(&work->dev->struct_mutex);
4617         i915_gem_object_unpin(work->old_fb_obj);
4618         drm_gem_object_unreference(work->pending_flip_obj);
4619         drm_gem_object_unreference(work->old_fb_obj);
4620         mutex_unlock(&work->dev->struct_mutex);
4621         kfree(work);
4622 }
4623
4624 static void do_intel_finish_page_flip(struct drm_device *dev,
4625                                       struct drm_crtc *crtc)
4626 {
4627         drm_i915_private_t *dev_priv = dev->dev_private;
4628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4629         struct intel_unpin_work *work;
4630         struct drm_i915_gem_object *obj_priv;
4631         struct drm_pending_vblank_event *e;
4632         struct timeval now;
4633         unsigned long flags;
4634
4635         /* Ignore early vblank irqs */
4636         if (intel_crtc == NULL)
4637                 return;
4638
4639         spin_lock_irqsave(&dev->event_lock, flags);
4640         work = intel_crtc->unpin_work;
4641         if (work == NULL || !work->pending) {
4642                 spin_unlock_irqrestore(&dev->event_lock, flags);
4643                 return;
4644         }
4645
4646         intel_crtc->unpin_work = NULL;
4647         drm_vblank_put(dev, intel_crtc->pipe);
4648
4649         if (work->event) {
4650                 e = work->event;
4651                 do_gettimeofday(&now);
4652                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4653                 e->event.tv_sec = now.tv_sec;
4654                 e->event.tv_usec = now.tv_usec;
4655                 list_add_tail(&e->base.link,
4656                               &e->base.file_priv->event_list);
4657                 wake_up_interruptible(&e->base.file_priv->event_wait);
4658         }
4659
4660         spin_unlock_irqrestore(&dev->event_lock, flags);
4661
4662         obj_priv = to_intel_bo(work->pending_flip_obj);
4663
4664         /* Initial scanout buffer will have a 0 pending flip count */
4665         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4666             atomic_dec_and_test(&obj_priv->pending_flip))
4667                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4668         schedule_work(&work->work);
4669 }
4670
4671 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4672 {
4673         drm_i915_private_t *dev_priv = dev->dev_private;
4674         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4675
4676         do_intel_finish_page_flip(dev, crtc);
4677 }
4678
4679 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4680 {
4681         drm_i915_private_t *dev_priv = dev->dev_private;
4682         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4683
4684         do_intel_finish_page_flip(dev, crtc);
4685 }
4686
4687 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4688 {
4689         drm_i915_private_t *dev_priv = dev->dev_private;
4690         struct intel_crtc *intel_crtc =
4691                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4692         unsigned long flags;
4693
4694         spin_lock_irqsave(&dev->event_lock, flags);
4695         if (intel_crtc->unpin_work) {
4696                 intel_crtc->unpin_work->pending = 1;
4697         } else {
4698                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4699         }
4700         spin_unlock_irqrestore(&dev->event_lock, flags);
4701 }
4702
4703 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4704                                 struct drm_framebuffer *fb,
4705                                 struct drm_pending_vblank_event *event)
4706 {
4707         struct drm_device *dev = crtc->dev;
4708         struct drm_i915_private *dev_priv = dev->dev_private;
4709         struct intel_framebuffer *intel_fb;
4710         struct drm_i915_gem_object *obj_priv;
4711         struct drm_gem_object *obj;
4712         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4713         struct intel_unpin_work *work;
4714         unsigned long flags, offset;
4715         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4716         int ret, pipesrc;
4717         u32 flip_mask;
4718
4719         work = kzalloc(sizeof *work, GFP_KERNEL);
4720         if (work == NULL)
4721                 return -ENOMEM;
4722
4723         work->event = event;
4724         work->dev = crtc->dev;
4725         intel_fb = to_intel_framebuffer(crtc->fb);
4726         work->old_fb_obj = intel_fb->obj;
4727         INIT_WORK(&work->work, intel_unpin_work_fn);
4728
4729         /* We borrow the event spin lock for protecting unpin_work */
4730         spin_lock_irqsave(&dev->event_lock, flags);
4731         if (intel_crtc->unpin_work) {
4732                 spin_unlock_irqrestore(&dev->event_lock, flags);
4733                 kfree(work);
4734
4735                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4736                 return -EBUSY;
4737         }
4738         intel_crtc->unpin_work = work;
4739         spin_unlock_irqrestore(&dev->event_lock, flags);
4740
4741         intel_fb = to_intel_framebuffer(fb);
4742         obj = intel_fb->obj;
4743
4744         mutex_lock(&dev->struct_mutex);
4745         ret = intel_pin_and_fence_fb_obj(dev, obj);
4746         if (ret != 0) {
4747                 mutex_unlock(&dev->struct_mutex);
4748
4749                 spin_lock_irqsave(&dev->event_lock, flags);
4750                 intel_crtc->unpin_work = NULL;
4751                 spin_unlock_irqrestore(&dev->event_lock, flags);
4752
4753                 kfree(work);
4754
4755                 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4756                                  to_intel_bo(obj));
4757                 return ret;
4758         }
4759
4760         /* Reference the objects for the scheduled work. */
4761         drm_gem_object_reference(work->old_fb_obj);
4762         drm_gem_object_reference(obj);
4763
4764         crtc->fb = fb;
4765         i915_gem_object_flush_write_domain(obj);
4766         drm_vblank_get(dev, intel_crtc->pipe);
4767         obj_priv = to_intel_bo(obj);
4768         atomic_inc(&obj_priv->pending_flip);
4769         work->pending_flip_obj = obj;
4770
4771         if (intel_crtc->plane)
4772                 flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4773         else
4774                 flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
4775
4776         /* Wait for any previous flip to finish */
4777         if (IS_GEN3(dev))
4778                 while (I915_READ(ISR) & flip_mask)
4779                         ;
4780
4781         /* Offset into the new buffer for cases of shared fbs between CRTCs */
4782         offset = obj_priv->gtt_offset;
4783         offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
4784
4785         BEGIN_LP_RING(4);
4786         if (IS_I965G(dev)) {
4787                 OUT_RING(MI_DISPLAY_FLIP |
4788                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4789                 OUT_RING(fb->pitch);
4790                 OUT_RING(offset | obj_priv->tiling_mode);
4791                 pipesrc = I915_READ(pipesrc_reg); 
4792                 OUT_RING(pipesrc & 0x0fff0fff);
4793         } else {
4794                 OUT_RING(MI_DISPLAY_FLIP_I915 |
4795                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4796                 OUT_RING(fb->pitch);
4797                 OUT_RING(offset);
4798                 OUT_RING(MI_NOOP);
4799         }
4800         ADVANCE_LP_RING();
4801
4802         mutex_unlock(&dev->struct_mutex);
4803
4804         return 0;
4805 }
4806
4807 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4808         .dpms = intel_crtc_dpms,
4809         .mode_fixup = intel_crtc_mode_fixup,
4810         .mode_set = intel_crtc_mode_set,
4811         .mode_set_base = intel_pipe_set_base,
4812         .prepare = intel_crtc_prepare,
4813         .commit = intel_crtc_commit,
4814         .load_lut = intel_crtc_load_lut,
4815 };
4816
4817 static const struct drm_crtc_funcs intel_crtc_funcs = {
4818         .cursor_set = intel_crtc_cursor_set,
4819         .cursor_move = intel_crtc_cursor_move,
4820         .gamma_set = intel_crtc_gamma_set,
4821         .set_config = drm_crtc_helper_set_config,
4822         .destroy = intel_crtc_destroy,
4823         .page_flip = intel_crtc_page_flip,
4824 };
4825
4826
4827 static void intel_crtc_init(struct drm_device *dev, int pipe)
4828 {
4829         drm_i915_private_t *dev_priv = dev->dev_private;
4830         struct intel_crtc *intel_crtc;
4831         int i;
4832
4833         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4834         if (intel_crtc == NULL)
4835                 return;
4836
4837         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4838
4839         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4840         intel_crtc->pipe = pipe;
4841         intel_crtc->plane = pipe;
4842         for (i = 0; i < 256; i++) {
4843                 intel_crtc->lut_r[i] = i;
4844                 intel_crtc->lut_g[i] = i;
4845                 intel_crtc->lut_b[i] = i;
4846         }
4847
4848         /* Swap pipes & planes for FBC on pre-965 */
4849         intel_crtc->pipe = pipe;
4850         intel_crtc->plane = pipe;
4851         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4852                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4853                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4854         }
4855
4856         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4857                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4858         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4859         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4860
4861         intel_crtc->cursor_addr = 0;
4862         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4863         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4864
4865         intel_crtc->busy = false;
4866
4867         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4868                     (unsigned long)intel_crtc);
4869 }
4870
4871 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4872                                 struct drm_file *file_priv)
4873 {
4874         drm_i915_private_t *dev_priv = dev->dev_private;
4875         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4876         struct drm_mode_object *drmmode_obj;
4877         struct intel_crtc *crtc;
4878
4879         if (!dev_priv) {
4880                 DRM_ERROR("called with no initialization\n");
4881                 return -EINVAL;
4882         }
4883
4884         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4885                         DRM_MODE_OBJECT_CRTC);
4886
4887         if (!drmmode_obj) {
4888                 DRM_ERROR("no such CRTC id\n");
4889                 return -EINVAL;
4890         }
4891
4892         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4893         pipe_from_crtc_id->pipe = crtc->pipe;
4894
4895         return 0;
4896 }
4897
4898 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4899 {
4900         struct drm_crtc *crtc = NULL;
4901
4902         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4903                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4904                 if (intel_crtc->pipe == pipe)
4905                         break;
4906         }
4907         return crtc;
4908 }
4909
4910 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
4911 {
4912         int index_mask = 0;
4913         struct drm_encoder *encoder;
4914         int entry = 0;
4915
4916         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4917                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4918                 if (type_mask & intel_encoder->clone_mask)
4919                         index_mask |= (1 << entry);
4920                 entry++;
4921         }
4922         return index_mask;
4923 }
4924
4925
4926 static void intel_setup_outputs(struct drm_device *dev)
4927 {
4928         struct drm_i915_private *dev_priv = dev->dev_private;
4929         struct drm_encoder *encoder;
4930
4931         intel_crt_init(dev);
4932
4933         /* Set up integrated LVDS */
4934         if (IS_MOBILE(dev) && !IS_I830(dev))
4935                 intel_lvds_init(dev);
4936
4937         if (HAS_PCH_SPLIT(dev)) {
4938                 int found;
4939
4940                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4941                         intel_dp_init(dev, DP_A);
4942
4943                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4944                         /* PCH SDVOB multiplex with HDMIB */
4945                         found = intel_sdvo_init(dev, PCH_SDVOB);
4946                         if (!found)
4947                                 intel_hdmi_init(dev, HDMIB);
4948                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4949                                 intel_dp_init(dev, PCH_DP_B);
4950                 }
4951
4952                 if (I915_READ(HDMIC) & PORT_DETECTED)
4953                         intel_hdmi_init(dev, HDMIC);
4954
4955                 if (I915_READ(HDMID) & PORT_DETECTED)
4956                         intel_hdmi_init(dev, HDMID);
4957
4958                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4959                         intel_dp_init(dev, PCH_DP_C);
4960
4961                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4962                         intel_dp_init(dev, PCH_DP_D);
4963
4964         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4965                 bool found = false;
4966
4967                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4968                         DRM_DEBUG_KMS("probing SDVOB\n");
4969                         found = intel_sdvo_init(dev, SDVOB);
4970                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4971                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4972                                 intel_hdmi_init(dev, SDVOB);
4973                         }
4974
4975                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4976                                 DRM_DEBUG_KMS("probing DP_B\n");
4977                                 intel_dp_init(dev, DP_B);
4978                         }
4979                 }
4980
4981                 /* Before G4X SDVOC doesn't have its own detect register */
4982
4983                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4984                         DRM_DEBUG_KMS("probing SDVOC\n");
4985                         found = intel_sdvo_init(dev, SDVOC);
4986                 }
4987
4988                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4989
4990                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4991                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4992                                 intel_hdmi_init(dev, SDVOC);
4993                         }
4994                         if (SUPPORTS_INTEGRATED_DP(dev)) {
4995                                 DRM_DEBUG_KMS("probing DP_C\n");
4996                                 intel_dp_init(dev, DP_C);
4997                         }
4998                 }
4999
5000                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5001                     (I915_READ(DP_D) & DP_DETECTED)) {
5002                         DRM_DEBUG_KMS("probing DP_D\n");
5003                         intel_dp_init(dev, DP_D);
5004                 }
5005         } else if (IS_GEN2(dev))
5006                 intel_dvo_init(dev);
5007
5008         if (SUPPORTS_TV(dev))
5009                 intel_tv_init(dev);
5010
5011         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5012                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5013
5014                 encoder->possible_crtcs = intel_encoder->crtc_mask;
5015                 encoder->possible_clones = intel_encoder_clones(dev,
5016                                                 intel_encoder->clone_mask);
5017         }
5018 }
5019
5020 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5021 {
5022         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5023
5024         drm_framebuffer_cleanup(fb);
5025         drm_gem_object_unreference_unlocked(intel_fb->obj);
5026
5027         kfree(intel_fb);
5028 }
5029
5030 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5031                                                 struct drm_file *file_priv,
5032                                                 unsigned int *handle)
5033 {
5034         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5035         struct drm_gem_object *object = intel_fb->obj;
5036
5037         return drm_gem_handle_create(file_priv, object, handle);
5038 }
5039
5040 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5041         .destroy = intel_user_framebuffer_destroy,
5042         .create_handle = intel_user_framebuffer_create_handle,
5043 };
5044
5045 int intel_framebuffer_init(struct drm_device *dev,
5046                            struct intel_framebuffer *intel_fb,
5047                            struct drm_mode_fb_cmd *mode_cmd,
5048                            struct drm_gem_object *obj)
5049 {
5050         int ret;
5051
5052         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5053         if (ret) {
5054                 DRM_ERROR("framebuffer init failed %d\n", ret);
5055                 return ret;
5056         }
5057
5058         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5059         intel_fb->obj = obj;
5060         return 0;
5061 }
5062
5063 static struct drm_framebuffer *
5064 intel_user_framebuffer_create(struct drm_device *dev,
5065                               struct drm_file *filp,
5066                               struct drm_mode_fb_cmd *mode_cmd)
5067 {
5068         struct drm_gem_object *obj;
5069         struct intel_framebuffer *intel_fb;
5070         int ret;
5071
5072         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5073         if (!obj)
5074                 return NULL;
5075
5076         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5077         if (!intel_fb)
5078                 return NULL;
5079
5080         ret = intel_framebuffer_init(dev, intel_fb,
5081                                      mode_cmd, obj);
5082         if (ret) {
5083                 drm_gem_object_unreference_unlocked(obj);
5084                 kfree(intel_fb);
5085                 return NULL;
5086         }
5087
5088         return &intel_fb->base;
5089 }
5090
5091 static const struct drm_mode_config_funcs intel_mode_funcs = {
5092         .fb_create = intel_user_framebuffer_create,
5093         .output_poll_changed = intel_fb_output_poll_changed,
5094 };
5095
5096 static struct drm_gem_object *
5097 intel_alloc_power_context(struct drm_device *dev)
5098 {
5099         struct drm_gem_object *pwrctx;
5100         int ret;
5101
5102         pwrctx = i915_gem_alloc_object(dev, 4096);
5103         if (!pwrctx) {
5104                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5105                 return NULL;
5106         }
5107
5108         mutex_lock(&dev->struct_mutex);
5109         ret = i915_gem_object_pin(pwrctx, 4096);
5110         if (ret) {
5111                 DRM_ERROR("failed to pin power context: %d\n", ret);
5112                 goto err_unref;
5113         }
5114
5115         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5116         if (ret) {
5117                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5118                 goto err_unpin;
5119         }
5120         mutex_unlock(&dev->struct_mutex);
5121
5122         return pwrctx;
5123
5124 err_unpin:
5125         i915_gem_object_unpin(pwrctx);
5126 err_unref:
5127         drm_gem_object_unreference(pwrctx);
5128         mutex_unlock(&dev->struct_mutex);
5129         return NULL;
5130 }
5131
5132 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5133 {
5134         struct drm_i915_private *dev_priv = dev->dev_private;
5135         u16 rgvswctl;
5136
5137         rgvswctl = I915_READ16(MEMSWCTL);
5138         if (rgvswctl & MEMCTL_CMD_STS) {
5139                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5140                 return false; /* still busy with another command */
5141         }
5142
5143         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5144                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5145         I915_WRITE16(MEMSWCTL, rgvswctl);
5146         POSTING_READ16(MEMSWCTL);
5147
5148         rgvswctl |= MEMCTL_CMD_STS;
5149         I915_WRITE16(MEMSWCTL, rgvswctl);
5150
5151         return true;
5152 }
5153
5154 void ironlake_enable_drps(struct drm_device *dev)
5155 {
5156         struct drm_i915_private *dev_priv = dev->dev_private;
5157         u32 rgvmodectl = I915_READ(MEMMODECTL);
5158         u8 fmax, fmin, fstart, vstart;
5159         int i = 0;
5160
5161         /* 100ms RC evaluation intervals */
5162         I915_WRITE(RCUPEI, 100000);
5163         I915_WRITE(RCDNEI, 100000);
5164
5165         /* Set max/min thresholds to 90ms and 80ms respectively */
5166         I915_WRITE(RCBMAXAVG, 90000);
5167         I915_WRITE(RCBMINAVG, 80000);
5168
5169         I915_WRITE(MEMIHYST, 1);
5170
5171         /* Set up min, max, and cur for interrupt handling */
5172         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5173         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5174         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5175                 MEMMODE_FSTART_SHIFT;
5176         fstart = fmax;
5177
5178         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5179                 PXVFREQ_PX_SHIFT;
5180
5181         dev_priv->fmax = fstart; /* IPS callback will increase this */
5182         dev_priv->fstart = fstart;
5183
5184         dev_priv->max_delay = fmax;
5185         dev_priv->min_delay = fmin;
5186         dev_priv->cur_delay = fstart;
5187
5188         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5189                          fstart);
5190
5191         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5192
5193         /*
5194          * Interrupts will be enabled in ironlake_irq_postinstall
5195          */
5196
5197         I915_WRITE(VIDSTART, vstart);
5198         POSTING_READ(VIDSTART);
5199
5200         rgvmodectl |= MEMMODE_SWMODE_EN;
5201         I915_WRITE(MEMMODECTL, rgvmodectl);
5202
5203         while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5204                 if (i++ > 100) {
5205                         DRM_ERROR("stuck trying to change perf mode\n");
5206                         break;
5207                 }
5208                 msleep(1);
5209         }
5210         msleep(1);
5211
5212         ironlake_set_drps(dev, fstart);
5213
5214         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5215                 I915_READ(0x112e0);
5216         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5217         dev_priv->last_count2 = I915_READ(0x112f4);
5218         getrawmonotonic(&dev_priv->last_time2);
5219 }
5220
5221 void ironlake_disable_drps(struct drm_device *dev)
5222 {
5223         struct drm_i915_private *dev_priv = dev->dev_private;
5224         u16 rgvswctl = I915_READ16(MEMSWCTL);
5225
5226         /* Ack interrupts, disable EFC interrupt */
5227         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5228         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5229         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5230         I915_WRITE(DEIIR, DE_PCU_EVENT);
5231         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5232
5233         /* Go back to the starting frequency */
5234         ironlake_set_drps(dev, dev_priv->fstart);
5235         msleep(1);
5236         rgvswctl |= MEMCTL_CMD_STS;
5237         I915_WRITE(MEMSWCTL, rgvswctl);
5238         msleep(1);
5239
5240 }
5241
5242 static unsigned long intel_pxfreq(u32 vidfreq)
5243 {
5244         unsigned long freq;
5245         int div = (vidfreq & 0x3f0000) >> 16;
5246         int post = (vidfreq & 0x3000) >> 12;
5247         int pre = (vidfreq & 0x7);
5248
5249         if (!pre)
5250                 return 0;
5251
5252         freq = ((div * 133333) / ((1<<post) * pre));
5253
5254         return freq;
5255 }
5256
5257 void intel_init_emon(struct drm_device *dev)
5258 {
5259         struct drm_i915_private *dev_priv = dev->dev_private;
5260         u32 lcfuse;
5261         u8 pxw[16];
5262         int i;
5263
5264         /* Disable to program */
5265         I915_WRITE(ECR, 0);
5266         POSTING_READ(ECR);
5267
5268         /* Program energy weights for various events */
5269         I915_WRITE(SDEW, 0x15040d00);
5270         I915_WRITE(CSIEW0, 0x007f0000);
5271         I915_WRITE(CSIEW1, 0x1e220004);
5272         I915_WRITE(CSIEW2, 0x04000004);
5273
5274         for (i = 0; i < 5; i++)
5275                 I915_WRITE(PEW + (i * 4), 0);
5276         for (i = 0; i < 3; i++)
5277                 I915_WRITE(DEW + (i * 4), 0);
5278
5279         /* Program P-state weights to account for frequency power adjustment */
5280         for (i = 0; i < 16; i++) {
5281                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5282                 unsigned long freq = intel_pxfreq(pxvidfreq);
5283                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5284                         PXVFREQ_PX_SHIFT;
5285                 unsigned long val;
5286
5287                 val = vid * vid;
5288                 val *= (freq / 1000);
5289                 val *= 255;
5290                 val /= (127*127*900);
5291                 if (val > 0xff)
5292                         DRM_ERROR("bad pxval: %ld\n", val);
5293                 pxw[i] = val;
5294         }
5295         /* Render standby states get 0 weight */
5296         pxw[14] = 0;
5297         pxw[15] = 0;
5298
5299         for (i = 0; i < 4; i++) {
5300                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5301                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5302                 I915_WRITE(PXW + (i * 4), val);
5303         }
5304
5305         /* Adjust magic regs to magic values (more experimental results) */
5306         I915_WRITE(OGW0, 0);
5307         I915_WRITE(OGW1, 0);
5308         I915_WRITE(EG0, 0x00007f00);
5309         I915_WRITE(EG1, 0x0000000e);
5310         I915_WRITE(EG2, 0x000e0000);
5311         I915_WRITE(EG3, 0x68000300);
5312         I915_WRITE(EG4, 0x42000000);
5313         I915_WRITE(EG5, 0x00140031);
5314         I915_WRITE(EG6, 0);
5315         I915_WRITE(EG7, 0);
5316
5317         for (i = 0; i < 8; i++)
5318                 I915_WRITE(PXWL + (i * 4), 0);
5319
5320         /* Enable PMON + select events */
5321         I915_WRITE(ECR, 0x80000019);
5322
5323         lcfuse = I915_READ(LCFUSE02);
5324
5325         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5326 }
5327
5328 void intel_init_clock_gating(struct drm_device *dev)
5329 {
5330         struct drm_i915_private *dev_priv = dev->dev_private;
5331
5332         /*
5333          * Disable clock gating reported to work incorrectly according to the
5334          * specs, but enable as much else as we can.
5335          */
5336         if (HAS_PCH_SPLIT(dev)) {
5337                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5338
5339                 if (IS_IRONLAKE(dev)) {
5340                         /* Required for FBC */
5341                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5342                         /* Required for CxSR */
5343                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5344
5345                         I915_WRITE(PCH_3DCGDIS0,
5346                                    MARIUNIT_CLOCK_GATE_DISABLE |
5347                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5348                 }
5349
5350                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5351
5352                 /*
5353                  * According to the spec the following bits should be set in
5354                  * order to enable memory self-refresh
5355                  * The bit 22/21 of 0x42004
5356                  * The bit 5 of 0x42020
5357                  * The bit 15 of 0x45000
5358                  */
5359                 if (IS_IRONLAKE(dev)) {
5360                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5361                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5362                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5363                         I915_WRITE(ILK_DSPCLK_GATE,
5364                                         (I915_READ(ILK_DSPCLK_GATE) |
5365                                                 ILK_DPARB_CLK_GATE));
5366                         I915_WRITE(DISP_ARB_CTL,
5367                                         (I915_READ(DISP_ARB_CTL) |
5368                                                 DISP_FBC_WM_DIS));
5369                 }
5370                 return;
5371         } else if (IS_G4X(dev)) {
5372                 uint32_t dspclk_gate;
5373                 I915_WRITE(RENCLK_GATE_D1, 0);
5374                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5375                        GS_UNIT_CLOCK_GATE_DISABLE |
5376                        CL_UNIT_CLOCK_GATE_DISABLE);
5377                 I915_WRITE(RAMCLK_GATE_D, 0);
5378                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5379                         OVRUNIT_CLOCK_GATE_DISABLE |
5380                         OVCUNIT_CLOCK_GATE_DISABLE;
5381                 if (IS_GM45(dev))
5382                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5383                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5384         } else if (IS_I965GM(dev)) {
5385                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5386                 I915_WRITE(RENCLK_GATE_D2, 0);
5387                 I915_WRITE(DSPCLK_GATE_D, 0);
5388                 I915_WRITE(RAMCLK_GATE_D, 0);
5389                 I915_WRITE16(DEUC, 0);
5390         } else if (IS_I965G(dev)) {
5391                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5392                        I965_RCC_CLOCK_GATE_DISABLE |
5393                        I965_RCPB_CLOCK_GATE_DISABLE |
5394                        I965_ISC_CLOCK_GATE_DISABLE |
5395                        I965_FBC_CLOCK_GATE_DISABLE);
5396                 I915_WRITE(RENCLK_GATE_D2, 0);
5397         } else if (IS_I9XX(dev)) {
5398                 u32 dstate = I915_READ(D_STATE);
5399
5400                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5401                         DSTATE_DOT_CLOCK_GATING;
5402                 I915_WRITE(D_STATE, dstate);
5403         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5404                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5405         } else if (IS_I830(dev)) {
5406                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5407         }
5408
5409         /*
5410          * GPU can automatically power down the render unit if given a page
5411          * to save state.
5412          */
5413         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5414                 struct drm_i915_gem_object *obj_priv = NULL;
5415
5416                 if (dev_priv->pwrctx) {
5417                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5418                 } else {
5419                         struct drm_gem_object *pwrctx;
5420
5421                         pwrctx = intel_alloc_power_context(dev);
5422                         if (pwrctx) {
5423                                 dev_priv->pwrctx = pwrctx;
5424                                 obj_priv = to_intel_bo(pwrctx);
5425                         }
5426                 }
5427
5428                 if (obj_priv) {
5429                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5430                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5431                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5432                 }
5433         }
5434 }
5435
5436 /* Set up chip specific display functions */
5437 static void intel_init_display(struct drm_device *dev)
5438 {
5439         struct drm_i915_private *dev_priv = dev->dev_private;
5440
5441         /* We always want a DPMS function */
5442         if (HAS_PCH_SPLIT(dev))
5443                 dev_priv->display.dpms = ironlake_crtc_dpms;
5444         else
5445                 dev_priv->display.dpms = i9xx_crtc_dpms;
5446
5447         if (I915_HAS_FBC(dev)) {
5448                 if (IS_GM45(dev)) {
5449                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5450                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5451                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5452                 } else if (IS_I965GM(dev)) {
5453                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5454                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5455                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5456                 }
5457                 /* 855GM needs testing */
5458         }
5459
5460         /* Returns the core display clock speed */
5461         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5462                 dev_priv->display.get_display_clock_speed =
5463                         i945_get_display_clock_speed;
5464         else if (IS_I915G(dev))
5465                 dev_priv->display.get_display_clock_speed =
5466                         i915_get_display_clock_speed;
5467         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5468                 dev_priv->display.get_display_clock_speed =
5469                         i9xx_misc_get_display_clock_speed;
5470         else if (IS_I915GM(dev))
5471                 dev_priv->display.get_display_clock_speed =
5472                         i915gm_get_display_clock_speed;
5473         else if (IS_I865G(dev))
5474                 dev_priv->display.get_display_clock_speed =
5475                         i865_get_display_clock_speed;
5476         else if (IS_I85X(dev))
5477                 dev_priv->display.get_display_clock_speed =
5478                         i855_get_display_clock_speed;
5479         else /* 852, 830 */
5480                 dev_priv->display.get_display_clock_speed =
5481                         i830_get_display_clock_speed;
5482
5483         /* For FIFO watermark updates */
5484         if (HAS_PCH_SPLIT(dev)) {
5485                 if (IS_IRONLAKE(dev)) {
5486                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5487                                 dev_priv->display.update_wm = ironlake_update_wm;
5488                         else {
5489                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5490                                               "Disable CxSR\n");
5491                                 dev_priv->display.update_wm = NULL;
5492                         }
5493                 } else
5494                         dev_priv->display.update_wm = NULL;
5495         } else if (IS_PINEVIEW(dev)) {
5496                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5497                                             dev_priv->is_ddr3,
5498                                             dev_priv->fsb_freq,
5499                                             dev_priv->mem_freq)) {
5500                         DRM_INFO("failed to find known CxSR latency "
5501                                  "(found ddr%s fsb freq %d, mem freq %d), "
5502                                  "disabling CxSR\n",
5503                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5504                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5505                         /* Disable CxSR and never update its watermark again */
5506                         pineview_disable_cxsr(dev);
5507                         dev_priv->display.update_wm = NULL;
5508                 } else
5509                         dev_priv->display.update_wm = pineview_update_wm;
5510         } else if (IS_G4X(dev))
5511                 dev_priv->display.update_wm = g4x_update_wm;
5512         else if (IS_I965G(dev))
5513                 dev_priv->display.update_wm = i965_update_wm;
5514         else if (IS_I9XX(dev)) {
5515                 dev_priv->display.update_wm = i9xx_update_wm;
5516                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5517         } else if (IS_I85X(dev)) {
5518                 dev_priv->display.update_wm = i9xx_update_wm;
5519                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5520         } else {
5521                 dev_priv->display.update_wm = i830_update_wm;
5522                 if (IS_845G(dev))
5523                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5524                 else
5525                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5526         }
5527 }
5528
5529 void intel_modeset_init(struct drm_device *dev)
5530 {
5531         struct drm_i915_private *dev_priv = dev->dev_private;
5532         int i;
5533
5534         drm_mode_config_init(dev);
5535
5536         dev->mode_config.min_width = 0;
5537         dev->mode_config.min_height = 0;
5538
5539         dev->mode_config.funcs = (void *)&intel_mode_funcs;
5540
5541         intel_init_display(dev);
5542
5543         if (IS_I965G(dev)) {
5544                 dev->mode_config.max_width = 8192;
5545                 dev->mode_config.max_height = 8192;
5546         } else if (IS_I9XX(dev)) {
5547                 dev->mode_config.max_width = 4096;
5548                 dev->mode_config.max_height = 4096;
5549         } else {
5550                 dev->mode_config.max_width = 2048;
5551                 dev->mode_config.max_height = 2048;
5552         }
5553
5554         /* set memory base */
5555         if (IS_I9XX(dev))
5556                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5557         else
5558                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5559
5560         if (IS_MOBILE(dev) || IS_I9XX(dev))
5561                 dev_priv->num_pipe = 2;
5562         else
5563                 dev_priv->num_pipe = 1;
5564         DRM_DEBUG_KMS("%d display pipe%s available.\n",
5565                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
5566
5567         for (i = 0; i < dev_priv->num_pipe; i++) {
5568                 intel_crtc_init(dev, i);
5569         }
5570
5571         intel_setup_outputs(dev);
5572
5573         intel_init_clock_gating(dev);
5574
5575         if (IS_IRONLAKE_M(dev)) {
5576                 ironlake_enable_drps(dev);
5577                 intel_init_emon(dev);
5578         }
5579
5580         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
5581         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
5582                     (unsigned long)dev);
5583
5584         intel_setup_overlay(dev);
5585 }
5586
5587 void intel_modeset_cleanup(struct drm_device *dev)
5588 {
5589         struct drm_i915_private *dev_priv = dev->dev_private;
5590         struct drm_crtc *crtc;
5591         struct intel_crtc *intel_crtc;
5592
5593         mutex_lock(&dev->struct_mutex);
5594
5595         drm_kms_helper_poll_fini(dev);
5596         intel_fbdev_fini(dev);
5597
5598         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5599                 /* Skip inactive CRTCs */
5600                 if (!crtc->fb)
5601                         continue;
5602
5603                 intel_crtc = to_intel_crtc(crtc);
5604                 intel_increase_pllclock(crtc, false);
5605                 del_timer_sync(&intel_crtc->idle_timer);
5606         }
5607
5608         del_timer_sync(&dev_priv->idle_timer);
5609
5610         if (dev_priv->display.disable_fbc)
5611                 dev_priv->display.disable_fbc(dev);
5612
5613         if (dev_priv->pwrctx) {
5614                 struct drm_i915_gem_object *obj_priv;
5615
5616                 obj_priv = to_intel_bo(dev_priv->pwrctx);
5617                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
5618                 I915_READ(PWRCTXA);
5619                 i915_gem_object_unpin(dev_priv->pwrctx);
5620                 drm_gem_object_unreference(dev_priv->pwrctx);
5621         }
5622
5623         if (IS_IRONLAKE_M(dev))
5624                 ironlake_disable_drps(dev);
5625
5626         mutex_unlock(&dev->struct_mutex);
5627
5628         drm_mode_config_cleanup(dev);
5629 }
5630
5631
5632 /*
5633  * Return which encoder is currently attached for connector.
5634  */
5635 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
5636 {
5637         struct drm_mode_object *obj;
5638         struct drm_encoder *encoder;
5639         int i;
5640
5641         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5642                 if (connector->encoder_ids[i] == 0)
5643                         break;
5644
5645                 obj = drm_mode_object_find(connector->dev,
5646                                            connector->encoder_ids[i],
5647                                            DRM_MODE_OBJECT_ENCODER);
5648                 if (!obj)
5649                         continue;
5650
5651                 encoder = obj_to_encoder(obj);
5652                 return encoder;
5653         }
5654         return NULL;
5655 }
5656
5657 /*
5658  * set vga decode state - true == enable VGA decode
5659  */
5660 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5661 {
5662         struct drm_i915_private *dev_priv = dev->dev_private;
5663         u16 gmch_ctrl;
5664
5665         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5666         if (state)
5667                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5668         else
5669                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5670         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5671         return 0;
5672 }