Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[linux-2.6.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2  */
3 /*
4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sub license, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the
16  * next paragraph) shall be included in all copies or substantial portions
17  * of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26  *
27  */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "i915_drm.h"
32 #include "i915_drv.h"
33 #include "intel_drv.h"
34
35 #define MAX_NOPID ((u32)~0)
36
37 /**
38  * Interrupts that are always left unmasked.
39  *
40  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
41  * we leave them always unmasked in IMR and then control enabling them through
42  * PIPESTAT alone.
43  */
44 #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
45                                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |  \
46                                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
47
48 /** Interrupts that we mask and unmask at runtime. */
49 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
50
51 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
52                                  PIPE_VBLANK_INTERRUPT_STATUS)
53
54 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
55                                  PIPE_VBLANK_INTERRUPT_ENABLE)
56
57 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
58                                          DRM_I915_VBLANK_PIPE_B)
59
60 void
61 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
62 {
63         if ((dev_priv->irq_mask_reg & mask) != 0) {
64                 dev_priv->irq_mask_reg &= ~mask;
65                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
66                 (void) I915_READ(IMR);
67         }
68 }
69
70 static inline void
71 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
72 {
73         if ((dev_priv->irq_mask_reg & mask) != mask) {
74                 dev_priv->irq_mask_reg |= mask;
75                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
76                 (void) I915_READ(IMR);
77         }
78 }
79
80 static inline u32
81 i915_pipestat(int pipe)
82 {
83         if (pipe == 0)
84                 return PIPEASTAT;
85         if (pipe == 1)
86                 return PIPEBSTAT;
87         BUG();
88 }
89
90 void
91 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
92 {
93         if ((dev_priv->pipestat[pipe] & mask) != mask) {
94                 u32 reg = i915_pipestat(pipe);
95
96                 dev_priv->pipestat[pipe] |= mask;
97                 /* Enable the interrupt, clear any pending status */
98                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
99                 (void) I915_READ(reg);
100         }
101 }
102
103 void
104 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
105 {
106         if ((dev_priv->pipestat[pipe] & mask) != 0) {
107                 u32 reg = i915_pipestat(pipe);
108
109                 dev_priv->pipestat[pipe] &= ~mask;
110                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
111                 (void) I915_READ(reg);
112         }
113 }
114
115 /**
116  * i915_pipe_enabled - check if a pipe is enabled
117  * @dev: DRM device
118  * @pipe: pipe to check
119  *
120  * Reading certain registers when the pipe is disabled can hang the chip.
121  * Use this routine to make sure the PLL is running and the pipe is active
122  * before reading such registers if unsure.
123  */
124 static int
125 i915_pipe_enabled(struct drm_device *dev, int pipe)
126 {
127         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
128         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
129
130         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
131                 return 1;
132
133         return 0;
134 }
135
136 /* Called from drm generic code, passed a 'crtc', which
137  * we use as a pipe index
138  */
139 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
140 {
141         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
142         unsigned long high_frame;
143         unsigned long low_frame;
144         u32 high1, high2, low, count;
145
146         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
147         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
148
149         if (!i915_pipe_enabled(dev, pipe)) {
150                 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
151                 return 0;
152         }
153
154         /*
155          * High & low register fields aren't synchronized, so make sure
156          * we get a low value that's stable across two reads of the high
157          * register.
158          */
159         do {
160                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
161                          PIPE_FRAME_HIGH_SHIFT);
162                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
163                         PIPE_FRAME_LOW_SHIFT);
164                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
165                          PIPE_FRAME_HIGH_SHIFT);
166         } while (high1 != high2);
167
168         count = (high1 << 8) | low;
169
170         return count;
171 }
172
173 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
174 {
175         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
176         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
177
178         if (!i915_pipe_enabled(dev, pipe)) {
179                 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
180                 return 0;
181         }
182
183         return I915_READ(reg);
184 }
185
186 /*
187  * Handle hotplug events outside the interrupt handler proper.
188  */
189 static void i915_hotplug_work_func(struct work_struct *work)
190 {
191         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
192                                                     hotplug_work);
193         struct drm_device *dev = dev_priv->dev;
194
195         /* Just fire off a uevent and let userspace tell us what to do */
196         drm_sysfs_hotplug_event(dev);
197 }
198
199 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
200 {
201         struct drm_device *dev = (struct drm_device *) arg;
202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
203         struct drm_i915_master_private *master_priv;
204         u32 iir, new_iir;
205         u32 pipea_stats, pipeb_stats;
206         u32 vblank_status;
207         u32 vblank_enable;
208         int vblank = 0;
209         unsigned long irqflags;
210         int irq_received;
211         int ret = IRQ_NONE;
212
213         atomic_inc(&dev_priv->irq_received);
214
215         iir = I915_READ(IIR);
216
217         if (IS_I965G(dev)) {
218                 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
219                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
220         } else {
221                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
222                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
223         }
224
225         for (;;) {
226                 irq_received = iir != 0;
227
228                 /* Can't rely on pipestat interrupt bit in iir as it might
229                  * have been cleared after the pipestat interrupt was received.
230                  * It doesn't set the bit in iir again, but it still produces
231                  * interrupts (for non-MSI).
232                  */
233                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
234                 pipea_stats = I915_READ(PIPEASTAT);
235                 pipeb_stats = I915_READ(PIPEBSTAT);
236
237                 /*
238                  * Clear the PIPE(A|B)STAT regs before the IIR
239                  */
240                 if (pipea_stats & 0x8000ffff) {
241                         I915_WRITE(PIPEASTAT, pipea_stats);
242                         irq_received = 1;
243                 }
244
245                 if (pipeb_stats & 0x8000ffff) {
246                         I915_WRITE(PIPEBSTAT, pipeb_stats);
247                         irq_received = 1;
248                 }
249                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
250
251                 if (!irq_received)
252                         break;
253
254                 ret = IRQ_HANDLED;
255
256                 /* Consume port.  Then clear IIR or we'll miss events */
257                 if ((I915_HAS_HOTPLUG(dev)) &&
258                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
259                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
260
261                         DRM_DEBUG("hotplug event received, stat 0x%08x\n",
262                                   hotplug_status);
263                         if (hotplug_status & dev_priv->hotplug_supported_mask)
264                                 schedule_work(&dev_priv->hotplug_work);
265
266                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
267                         I915_READ(PORT_HOTPLUG_STAT);
268                 }
269
270                 I915_WRITE(IIR, iir);
271                 new_iir = I915_READ(IIR); /* Flush posted writes */
272
273                 if (dev->primary->master) {
274                         master_priv = dev->primary->master->driver_priv;
275                         if (master_priv->sarea_priv)
276                                 master_priv->sarea_priv->last_dispatch =
277                                         READ_BREADCRUMB(dev_priv);
278                 }
279
280                 if (iir & I915_USER_INTERRUPT) {
281                         dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
282                         DRM_WAKEUP(&dev_priv->irq_queue);
283                 }
284
285                 if (pipea_stats & vblank_status) {
286                         vblank++;
287                         drm_handle_vblank(dev, 0);
288                 }
289
290                 if (pipeb_stats & vblank_status) {
291                         vblank++;
292                         drm_handle_vblank(dev, 1);
293                 }
294
295                 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
296                     (iir & I915_ASLE_INTERRUPT))
297                         opregion_asle_intr(dev);
298
299                 /* With MSI, interrupts are only generated when iir
300                  * transitions from zero to nonzero.  If another bit got
301                  * set while we were handling the existing iir bits, then
302                  * we would never get another interrupt.
303                  *
304                  * This is fine on non-MSI as well, as if we hit this path
305                  * we avoid exiting the interrupt handler only to generate
306                  * another one.
307                  *
308                  * Note that for MSI this could cause a stray interrupt report
309                  * if an interrupt landed in the time between writing IIR and
310                  * the posting read.  This should be rare enough to never
311                  * trigger the 99% of 100,000 interrupts test for disabling
312                  * stray interrupts.
313                  */
314                 iir = new_iir;
315         }
316
317         return ret;
318 }
319
320 static int i915_emit_irq(struct drm_device * dev)
321 {
322         drm_i915_private_t *dev_priv = dev->dev_private;
323         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
324         RING_LOCALS;
325
326         i915_kernel_lost_context(dev);
327
328         DRM_DEBUG("\n");
329
330         dev_priv->counter++;
331         if (dev_priv->counter > 0x7FFFFFFFUL)
332                 dev_priv->counter = 1;
333         if (master_priv->sarea_priv)
334                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
335
336         BEGIN_LP_RING(4);
337         OUT_RING(MI_STORE_DWORD_INDEX);
338         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
339         OUT_RING(dev_priv->counter);
340         OUT_RING(MI_USER_INTERRUPT);
341         ADVANCE_LP_RING();
342
343         return dev_priv->counter;
344 }
345
346 void i915_user_irq_get(struct drm_device *dev)
347 {
348         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
349         unsigned long irqflags;
350
351         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
352         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
353                 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
354         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
355 }
356
357 void i915_user_irq_put(struct drm_device *dev)
358 {
359         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
360         unsigned long irqflags;
361
362         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
363         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
364         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
365                 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
366         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
367 }
368
369 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
370 {
371         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
372         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
373         int ret = 0;
374
375         DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
376                   READ_BREADCRUMB(dev_priv));
377
378         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
379                 if (master_priv->sarea_priv)
380                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
381                 return 0;
382         }
383
384         if (master_priv->sarea_priv)
385                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
386
387         i915_user_irq_get(dev);
388         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
389                     READ_BREADCRUMB(dev_priv) >= irq_nr);
390         i915_user_irq_put(dev);
391
392         if (ret == -EBUSY) {
393                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
394                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
395         }
396
397         return ret;
398 }
399
400 /* Needs the lock as it touches the ring.
401  */
402 int i915_irq_emit(struct drm_device *dev, void *data,
403                          struct drm_file *file_priv)
404 {
405         drm_i915_private_t *dev_priv = dev->dev_private;
406         drm_i915_irq_emit_t *emit = data;
407         int result;
408
409         if (!dev_priv || !dev_priv->ring.virtual_start) {
410                 DRM_ERROR("called with no initialization\n");
411                 return -EINVAL;
412         }
413
414         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
415
416         mutex_lock(&dev->struct_mutex);
417         result = i915_emit_irq(dev);
418         mutex_unlock(&dev->struct_mutex);
419
420         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
421                 DRM_ERROR("copy_to_user\n");
422                 return -EFAULT;
423         }
424
425         return 0;
426 }
427
428 /* Doesn't need the hardware lock.
429  */
430 int i915_irq_wait(struct drm_device *dev, void *data,
431                          struct drm_file *file_priv)
432 {
433         drm_i915_private_t *dev_priv = dev->dev_private;
434         drm_i915_irq_wait_t *irqwait = data;
435
436         if (!dev_priv) {
437                 DRM_ERROR("called with no initialization\n");
438                 return -EINVAL;
439         }
440
441         return i915_wait_irq(dev, irqwait->irq_seq);
442 }
443
444 /* Called from drm generic code, passed 'crtc' which
445  * we use as a pipe index
446  */
447 int i915_enable_vblank(struct drm_device *dev, int pipe)
448 {
449         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
450         unsigned long irqflags;
451         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
452         u32 pipeconf;
453
454         pipeconf = I915_READ(pipeconf_reg);
455         if (!(pipeconf & PIPEACONF_ENABLE))
456                 return -EINVAL;
457
458         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
459         if (IS_I965G(dev))
460                 i915_enable_pipestat(dev_priv, pipe,
461                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
462         else
463                 i915_enable_pipestat(dev_priv, pipe,
464                                      PIPE_VBLANK_INTERRUPT_ENABLE);
465         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
466         return 0;
467 }
468
469 /* Called from drm generic code, passed 'crtc' which
470  * we use as a pipe index
471  */
472 void i915_disable_vblank(struct drm_device *dev, int pipe)
473 {
474         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
475         unsigned long irqflags;
476
477         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
478         i915_disable_pipestat(dev_priv, pipe,
479                               PIPE_VBLANK_INTERRUPT_ENABLE |
480                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
481         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
482 }
483
484 void i915_enable_interrupt (struct drm_device *dev)
485 {
486         struct drm_i915_private *dev_priv = dev->dev_private;
487         opregion_enable_asle(dev);
488         dev_priv->irq_enabled = 1;
489 }
490
491
492 /* Set the vblank monitor pipe
493  */
494 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
495                          struct drm_file *file_priv)
496 {
497         drm_i915_private_t *dev_priv = dev->dev_private;
498
499         if (!dev_priv) {
500                 DRM_ERROR("called with no initialization\n");
501                 return -EINVAL;
502         }
503
504         return 0;
505 }
506
507 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
508                          struct drm_file *file_priv)
509 {
510         drm_i915_private_t *dev_priv = dev->dev_private;
511         drm_i915_vblank_pipe_t *pipe = data;
512
513         if (!dev_priv) {
514                 DRM_ERROR("called with no initialization\n");
515                 return -EINVAL;
516         }
517
518         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
519
520         return 0;
521 }
522
523 /**
524  * Schedule buffer swap at given vertical blank.
525  */
526 int i915_vblank_swap(struct drm_device *dev, void *data,
527                      struct drm_file *file_priv)
528 {
529         /* The delayed swap mechanism was fundamentally racy, and has been
530          * removed.  The model was that the client requested a delayed flip/swap
531          * from the kernel, then waited for vblank before continuing to perform
532          * rendering.  The problem was that the kernel might wake the client
533          * up before it dispatched the vblank swap (since the lock has to be
534          * held while touching the ringbuffer), in which case the client would
535          * clear and start the next frame before the swap occurred, and
536          * flicker would occur in addition to likely missing the vblank.
537          *
538          * In the absence of this ioctl, userland falls back to a correct path
539          * of waiting for a vblank, then dispatching the swap on its own.
540          * Context switching to userland and back is plenty fast enough for
541          * meeting the requirements of vblank swapping.
542          */
543         return -EINVAL;
544 }
545
546 /* drm_dma.h hooks
547 */
548 void i915_driver_irq_preinstall(struct drm_device * dev)
549 {
550         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
551
552         atomic_set(&dev_priv->irq_received, 0);
553
554         if (I915_HAS_HOTPLUG(dev)) {
555                 I915_WRITE(PORT_HOTPLUG_EN, 0);
556                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
557         }
558
559         I915_WRITE(HWSTAM, 0xeffe);
560         I915_WRITE(PIPEASTAT, 0);
561         I915_WRITE(PIPEBSTAT, 0);
562         I915_WRITE(IMR, 0xffffffff);
563         I915_WRITE(IER, 0x0);
564         (void) I915_READ(IER);
565         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
566 }
567
568 int i915_driver_irq_postinstall(struct drm_device *dev)
569 {
570         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
571         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
572
573         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
574
575         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
576
577         /* Unmask the interrupts that we always want on. */
578         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
579
580         dev_priv->pipestat[0] = 0;
581         dev_priv->pipestat[1] = 0;
582
583         if (I915_HAS_HOTPLUG(dev)) {
584                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
585
586                 /* Leave other bits alone */
587                 hotplug_en |= HOTPLUG_EN_MASK;
588                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
589
590                 dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS |
591                         TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS |
592                         SDVOB_HOTPLUG_INT_STATUS;
593                 if (IS_G4X(dev)) {
594                         dev_priv->hotplug_supported_mask |=
595                                 HDMIB_HOTPLUG_INT_STATUS |
596                                 HDMIC_HOTPLUG_INT_STATUS |
597                                 HDMID_HOTPLUG_INT_STATUS;
598                 }
599                 /* Enable in IER... */
600                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
601                 /* and unmask in IMR */
602                 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
603         }
604
605         /* Disable pipe interrupt enables, clear pending pipe status */
606         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
607         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
608         /* Clear pending interrupt status */
609         I915_WRITE(IIR, I915_READ(IIR));
610
611         I915_WRITE(IER, enable_mask);
612         I915_WRITE(IMR, dev_priv->irq_mask_reg);
613         (void) I915_READ(IER);
614
615         opregion_enable_asle(dev);
616         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
617
618         return 0;
619 }
620
621 void i915_driver_irq_uninstall(struct drm_device * dev)
622 {
623         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
624
625         if (!dev_priv)
626                 return;
627
628         dev_priv->vblank_pipe = 0;
629
630         if (I915_HAS_HOTPLUG(dev)) {
631                 I915_WRITE(PORT_HOTPLUG_EN, 0);
632                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
633         }
634
635         I915_WRITE(HWSTAM, 0xffffffff);
636         I915_WRITE(PIPEASTAT, 0);
637         I915_WRITE(PIPEBSTAT, 0);
638         I915_WRITE(IMR, 0xffffffff);
639         I915_WRITE(IER, 0x0);
640
641         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
642         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
643         I915_WRITE(IIR, I915_READ(IIR));
644 }