drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37
  38 static void i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
  42                                              bool write);
  43 static int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
  44                                                      uint64_t offset,
  45                                                      uint64_t size);
  46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
  47 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  48                                        unsigned alignment,
  49                                        bool map_and_fenceable);
  50 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  51                                      struct drm_i915_fence_reg *reg);
  52 static int i915_gem_phys_pwrite(struct drm_device *dev,
  53                                 struct drm_i915_gem_object *obj,
  54                                 struct drm_i915_gem_pwrite *args,
  55                                 struct drm_file *file);
  56 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
  57
  58 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  59                                     int nr_to_scan,
  60                                     gfp_t gfp_mask);
  61
  62
  63 /* some bookkeeping */
  64 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  65                                   size_t size)
  66 {
  67         dev_priv->mm.object_count++;
  68         dev_priv->mm.object_memory += size;
  69 }
  70
  71 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  72                                      size_t size)
  73 {
  74         dev_priv->mm.object_count--;
  75         dev_priv->mm.object_memory -= size;
  76 }
  77
  78 int
  79 i915_gem_check_is_wedged(struct drm_device *dev)
  80 {
  81         struct drm_i915_private *dev_priv = dev->dev_private;
  82         struct completion *x = &dev_priv->error_completion;
  83         unsigned long flags;
  84         int ret;
  85
  86         if (!atomic_read(&dev_priv->mm.wedged))
  87                 return 0;
  88
  89         ret = wait_for_completion_interruptible(x);
  90         if (ret)
  91                 return ret;
  92
  93         /* Success, we reset the GPU! */
  94         if (!atomic_read(&dev_priv->mm.wedged))
  95                 return 0;
  96
  97         /* GPU is hung, bump the completion count to account for
  98          * the token we just consumed so that we never hit zero and
  99          * end up waiting upon a subsequent completion event that
 100          * will never happen.
 101          */
 102         spin_lock_irqsave(&x->wait.lock, flags);
 103         x->done++;
 104         spin_unlock_irqrestore(&x->wait.lock, flags);
 105         return -EIO;
 106 }
 107
 108 int i915_mutex_lock_interruptible(struct drm_device *dev)
 109 {
 110         struct drm_i915_private *dev_priv = dev->dev_private;
 111         int ret;
 112
 113         ret = i915_gem_check_is_wedged(dev);
 114         if (ret)
 115                 return ret;
 116
 117         ret = mutex_lock_interruptible(&dev->struct_mutex);
 118         if (ret)
 119                 return ret;
 120
 121         if (atomic_read(&dev_priv->mm.wedged)) {
 122                 mutex_unlock(&dev->struct_mutex);
 123                 return -EAGAIN;
 124         }
 125
 126         WARN_ON(i915_verify_lists(dev));
 127         return 0;
 128 }
 129
 130 static inline bool
 131 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 132 {
 133         return obj->gtt_space && !obj->active && obj->pin_count == 0;
 134 }
 135
 136 void i915_gem_do_init(struct drm_device *dev,
 137                       unsigned long start,
 138                       unsigned long mappable_end,
 139                       unsigned long end)
 140 {
 141         drm_i915_private_t *dev_priv = dev->dev_private;
 142
 143         drm_mm_init(&dev_priv->mm.gtt_space, start,
 144                     end - start);
 145
 146         dev_priv->mm.gtt_total = end - start;
 147         dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
 148         dev_priv->mm.gtt_mappable_end = mappable_end;
 149 }
 150
 151 int
 152 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 153                     struct drm_file *file)
 154 {
 155         struct drm_i915_gem_init *args = data;
 156
 157         if (args->gtt_start >= args->gtt_end ||
 158             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 159                 return -EINVAL;
 160
 161         mutex_lock(&dev->struct_mutex);
 162         i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
 163         mutex_unlock(&dev->struct_mutex);
 164
 165         return 0;
 166 }
 167
 168 int
 169 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 170                             struct drm_file *file)
 171 {
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173         struct drm_i915_gem_get_aperture *args = data;
 174         struct drm_i915_gem_object *obj;
 175         size_t pinned;
 176
 177         if (!(dev->driver->driver_features & DRIVER_GEM))
 178                 return -ENODEV;
 179
 180         pinned = 0;
 181         mutex_lock(&dev->struct_mutex);
 182         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 183                 pinned += obj->gtt_space->size;
 184         mutex_unlock(&dev->struct_mutex);
 185
 186         args->aper_size = dev_priv->mm.gtt_total;
 187         args->aper_available_size = args->aper_size -pinned;
 188
 189         return 0;
 190 }
 191
 192 /**
 193  * Creates a new mm object and returns a handle to it.
 194  */
 195 int
 196 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 197                       struct drm_file *file)
 198 {
 199         struct drm_i915_gem_create *args = data;
 200         struct drm_i915_gem_object *obj;
 201         int ret;
 202         u32 handle;
 203
 204         args->size = roundup(args->size, PAGE_SIZE);
 205
 206         /* Allocate the new object */
 207         obj = i915_gem_alloc_object(dev, args->size);
 208         if (obj == NULL)
 209                 return -ENOMEM;
 210
 211         ret = drm_gem_handle_create(file, &obj->base, &handle);
 212         if (ret) {
 213                 drm_gem_object_release(&obj->base);
 214                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 215                 kfree(obj);
 216                 return ret;
 217         }
 218
 219         /* drop reference from allocate - handle holds it now */
 220         drm_gem_object_unreference(&obj->base);
 221         trace_i915_gem_object_create(obj);
 222
 223         args->handle = handle;
 224         return 0;
 225 }
 226
 227 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
 228 {
 229         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 230
 231         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 232                 obj->tiling_mode != I915_TILING_NONE;
 233 }
 234
 235 static inline void
 236 slow_shmem_copy(struct page *dst_page,
 237                 int dst_offset,
 238                 struct page *src_page,
 239                 int src_offset,
 240                 int length)
 241 {
 242         char *dst_vaddr, *src_vaddr;
 243
 244         dst_vaddr = kmap(dst_page);
 245         src_vaddr = kmap(src_page);
 246
 247         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 248
 249         kunmap(src_page);
 250         kunmap(dst_page);
 251 }
 252
 253 static inline void
 254 slow_shmem_bit17_copy(struct page *gpu_page,
 255                       int gpu_offset,
 256                       struct page *cpu_page,
 257                       int cpu_offset,
 258                       int length,
 259                       int is_read)
 260 {
 261         char *gpu_vaddr, *cpu_vaddr;
 262
 263         /* Use the unswizzled path if this page isn't affected. */
 264         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 265                 if (is_read)
 266                         return slow_shmem_copy(cpu_page, cpu_offset,
 267                                                gpu_page, gpu_offset, length);
 268                 else
 269                         return slow_shmem_copy(gpu_page, gpu_offset,
 270                                                cpu_page, cpu_offset, length);
 271         }
 272
 273         gpu_vaddr = kmap(gpu_page);
 274         cpu_vaddr = kmap(cpu_page);
 275
 276         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 277          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 278          */
 279         while (length > 0) {
 280                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 281                 int this_length = min(cacheline_end - gpu_offset, length);
 282                 int swizzled_gpu_offset = gpu_offset ^ 64;
 283
 284                 if (is_read) {
 285                         memcpy(cpu_vaddr + cpu_offset,
 286                                gpu_vaddr + swizzled_gpu_offset,
 287                                this_length);
 288                 } else {
 289                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 290                                cpu_vaddr + cpu_offset,
 291                                this_length);
 292                 }
 293                 cpu_offset += this_length;
 294                 gpu_offset += this_length;
 295                 length -= this_length;
 296         }
 297
 298         kunmap(cpu_page);
 299         kunmap(gpu_page);
 300 }
 301
 302 /**
 303  * This is the fast shmem pread path, which attempts to copy_from_user directly
 304  * from the backing pages of the object to the user's address space.  On a
 305  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 306  */
 307 static int
 308 i915_gem_shmem_pread_fast(struct drm_device *dev,
 309                           struct drm_i915_gem_object *obj,
 310                           struct drm_i915_gem_pread *args,
 311                           struct drm_file *file)
 312 {
 313         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 314         ssize_t remain;
 315         loff_t offset;
 316         char __user *user_data;
 317         int page_offset, page_length;
 318
 319         user_data = (char __user *) (uintptr_t) args->data_ptr;
 320         remain = args->size;
 321
 322         offset = args->offset;
 323
 324         while (remain > 0) {
 325                 struct page *page;
 326                 char *vaddr;
 327                 int ret;
 328
 329                 /* Operation in this page
 330                  *
 331                  * page_offset = offset within page
 332                  * page_length = bytes to copy for this page
 333                  */
 334                 page_offset = offset & (PAGE_SIZE-1);
 335                 page_length = remain;
 336                 if ((page_offset + remain) > PAGE_SIZE)
 337                         page_length = PAGE_SIZE - page_offset;
 338
 339                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 340                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 341                 if (IS_ERR(page))
 342                         return PTR_ERR(page);
 343
 344                 vaddr = kmap_atomic(page);
 345                 ret = __copy_to_user_inatomic(user_data,
 346                                               vaddr + page_offset,
 347                                               page_length);
 348                 kunmap_atomic(vaddr);
 349
 350                 mark_page_accessed(page);
 351                 page_cache_release(page);
 352                 if (ret)
 353                         return -EFAULT;
 354
 355                 remain -= page_length;
 356                 user_data += page_length;
 357                 offset += page_length;
 358         }
 359
 360         return 0;
 361 }
 362
 363 /**
 364  * This is the fallback shmem pread path, which allocates temporary storage
 365  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 366  * can copy out of the object's backing pages while holding the struct mutex
 367  * and not take page faults.
 368  */
 369 static int
 370 i915_gem_shmem_pread_slow(struct drm_device *dev,
 371                           struct drm_i915_gem_object *obj,
 372                           struct drm_i915_gem_pread *args,
 373                           struct drm_file *file)
 374 {
 375         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 376         struct mm_struct *mm = current->mm;
 377         struct page **user_pages;
 378         ssize_t remain;
 379         loff_t offset, pinned_pages, i;
 380         loff_t first_data_page, last_data_page, num_pages;
 381         int shmem_page_offset;
 382         int data_page_index, data_page_offset;
 383         int page_length;
 384         int ret;
 385         uint64_t data_ptr = args->data_ptr;
 386         int do_bit17_swizzling;
 387
 388         remain = args->size;
 389
 390         /* Pin the user pages containing the data.  We can't fault while
 391          * holding the struct mutex, yet we want to hold it while
 392          * dereferencing the user data.
 393          */
 394         first_data_page = data_ptr / PAGE_SIZE;
 395         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 396         num_pages = last_data_page - first_data_page + 1;
 397
 398         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 399         if (user_pages == NULL)
 400                 return -ENOMEM;
 401
 402         mutex_unlock(&dev->struct_mutex);
 403         down_read(&mm->mmap_sem);
 404         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 405                                       num_pages, 1, 0, user_pages, NULL);
 406         up_read(&mm->mmap_sem);
 407         mutex_lock(&dev->struct_mutex);
 408         if (pinned_pages < num_pages) {
 409                 ret = -EFAULT;
 410                 goto out;
 411         }
 412
 413         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 414                                                         args->offset,
 415                                                         args->size);
 416         if (ret)
 417                 goto out;
 418
 419         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 420
 421         offset = args->offset;
 422
 423         while (remain > 0) {
 424                 struct page *page;
 425
 426                 /* Operation in this page
 427                  *
 428                  * shmem_page_offset = offset within page in shmem file
 429                  * data_page_index = page number in get_user_pages return
 430                  * data_page_offset = offset with data_page_index page.
 431                  * page_length = bytes to copy for this page
 432                  */
 433                 shmem_page_offset = offset & ~PAGE_MASK;
 434                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 435                 data_page_offset = data_ptr & ~PAGE_MASK;
 436
 437                 page_length = remain;
 438                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 439                         page_length = PAGE_SIZE - shmem_page_offset;
 440                 if ((data_page_offset + page_length) > PAGE_SIZE)
 441                         page_length = PAGE_SIZE - data_page_offset;
 442
 443                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 444                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 445                 if (IS_ERR(page))
 446                         return PTR_ERR(page);
 447
 448                 if (do_bit17_swizzling) {
 449                         slow_shmem_bit17_copy(page,
 450                                               shmem_page_offset,
 451                                               user_pages[data_page_index],
 452                                               data_page_offset,
 453                                               page_length,
 454                                               1);
 455                 } else {
 456                         slow_shmem_copy(user_pages[data_page_index],
 457                                         data_page_offset,
 458                                         page,
 459                                         shmem_page_offset,
 460                                         page_length);
 461                 }
 462
 463                 mark_page_accessed(page);
 464                 page_cache_release(page);
 465
 466                 remain -= page_length;
 467                 data_ptr += page_length;
 468                 offset += page_length;
 469         }
 470
 471 out:
 472         for (i = 0; i < pinned_pages; i++) {
 473                 SetPageDirty(user_pages[i]);
 474                 mark_page_accessed(user_pages[i]);
 475                 page_cache_release(user_pages[i]);
 476         }
 477         drm_free_large(user_pages);
 478
 479         return ret;
 480 }
 481
 482 /**
 483  * Reads data from the object referenced by handle.
 484  *
 485  * On error, the contents of *data are undefined.
 486  */
 487 int
 488 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 489                      struct drm_file *file)
 490 {
 491         struct drm_i915_gem_pread *args = data;
 492         struct drm_i915_gem_object *obj;
 493         int ret = 0;
 494
 495         if (args->size == 0)
 496                 return 0;
 497
 498         if (!access_ok(VERIFY_WRITE,
 499                        (char __user *)(uintptr_t)args->data_ptr,
 500                        args->size))
 501                 return -EFAULT;
 502
 503         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
 504                                        args->size);
 505         if (ret)
 506                 return -EFAULT;
 507
 508         ret = i915_mutex_lock_interruptible(dev);
 509         if (ret)
 510                 return ret;
 511
 512         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 513         if (obj == NULL) {
 514                 ret = -ENOENT;
 515                 goto unlock;
 516         }
 517
 518         /* Bounds check source.  */
 519         if (args->offset > obj->base.size ||
 520             args->size > obj->base.size - args->offset) {
 521                 ret = -EINVAL;
 522                 goto out;
 523         }
 524
 525         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 526                                                         args->offset,
 527                                                         args->size);
 528         if (ret)
 529                 goto out;
 530
 531         ret = -EFAULT;
 532         if (!i915_gem_object_needs_bit17_swizzle(obj))
 533                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
 534         if (ret == -EFAULT)
 535                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
 536
 537 out:
 538         drm_gem_object_unreference(&obj->base);
 539 unlock:
 540         mutex_unlock(&dev->struct_mutex);
 541         return ret;
 542 }
 543
 544 /* This is the fast write path which cannot handle
 545  * page faults in the source data
 546  */
 547
 548 static inline int
 549 fast_user_write(struct io_mapping *mapping,
 550                 loff_t page_base, int page_offset,
 551                 char __user *user_data,
 552                 int length)
 553 {
 554         char *vaddr_atomic;
 555         unsigned long unwritten;
 556
 557         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 558         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 559                                                       user_data, length);
 560         io_mapping_unmap_atomic(vaddr_atomic);
 561         return unwritten;
 562 }
 563
 564 /* Here's the write path which can sleep for
 565  * page faults
 566  */
 567
 568 static inline void
 569 slow_kernel_write(struct io_mapping *mapping,
 570                   loff_t gtt_base, int gtt_offset,
 571                   struct page *user_page, int user_offset,
 572                   int length)
 573 {
 574         char __iomem *dst_vaddr;
 575         char *src_vaddr;
 576
 577         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 578         src_vaddr = kmap(user_page);
 579
 580         memcpy_toio(dst_vaddr + gtt_offset,
 581                     src_vaddr + user_offset,
 582                     length);
 583
 584         kunmap(user_page);
 585         io_mapping_unmap(dst_vaddr);
 586 }
 587
 588 /**
 589  * This is the fast pwrite path, where we copy the data directly from the
 590  * user into the GTT, uncached.
 591  */
 592 static int
 593 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 594                          struct drm_i915_gem_object *obj,
 595                          struct drm_i915_gem_pwrite *args,
 596                          struct drm_file *file)
 597 {
 598         drm_i915_private_t *dev_priv = dev->dev_private;
 599         ssize_t remain;
 600         loff_t offset, page_base;
 601         char __user *user_data;
 602         int page_offset, page_length;
 603
 604         user_data = (char __user *) (uintptr_t) args->data_ptr;
 605         remain = args->size;
 606
 607         offset = obj->gtt_offset + args->offset;
 608
 609         while (remain > 0) {
 610                 /* Operation in this page
 611                  *
 612                  * page_base = page offset within aperture
 613                  * page_offset = offset within page
 614                  * page_length = bytes to copy for this page
 615                  */
 616                 page_base = (offset & ~(PAGE_SIZE-1));
 617                 page_offset = offset & (PAGE_SIZE-1);
 618                 page_length = remain;
 619                 if ((page_offset + remain) > PAGE_SIZE)
 620                         page_length = PAGE_SIZE - page_offset;
 621
 622                 /* If we get a fault while copying data, then (presumably) our
 623                  * source page isn't available.  Return the error and we'll
 624                  * retry in the slow path.
 625                  */
 626                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 627                                     page_offset, user_data, page_length))
 628
 629                         return -EFAULT;
 630
 631                 remain -= page_length;
 632                 user_data += page_length;
 633                 offset += page_length;
 634         }
 635
 636         return 0;
 637 }
 638
 639 /**
 640  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 641  * the memory and maps it using kmap_atomic for copying.
 642  *
 643  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 644  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 645  */
 646 static int
 647 i915_gem_gtt_pwrite_slow(struct drm_device *dev,
 648                          struct drm_i915_gem_object *obj,
 649                          struct drm_i915_gem_pwrite *args,
 650                          struct drm_file *file)
 651 {
 652         drm_i915_private_t *dev_priv = dev->dev_private;
 653         ssize_t remain;
 654         loff_t gtt_page_base, offset;
 655         loff_t first_data_page, last_data_page, num_pages;
 656         loff_t pinned_pages, i;
 657         struct page **user_pages;
 658         struct mm_struct *mm = current->mm;
 659         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 660         int ret;
 661         uint64_t data_ptr = args->data_ptr;
 662
 663         remain = args->size;
 664
 665         /* Pin the user pages containing the data.  We can't fault while
 666          * holding the struct mutex, and all of the pwrite implementations
 667          * want to hold it while dereferencing the user data.
 668          */
 669         first_data_page = data_ptr / PAGE_SIZE;
 670         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 671         num_pages = last_data_page - first_data_page + 1;
 672
 673         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 674         if (user_pages == NULL)
 675                 return -ENOMEM;
 676
 677         mutex_unlock(&dev->struct_mutex);
 678         down_read(&mm->mmap_sem);
 679         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 680                                       num_pages, 0, 0, user_pages, NULL);
 681         up_read(&mm->mmap_sem);
 682         mutex_lock(&dev->struct_mutex);
 683         if (pinned_pages < num_pages) {
 684                 ret = -EFAULT;
 685                 goto out_unpin_pages;
 686         }
 687
 688         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 689         if (ret)
 690                 goto out_unpin_pages;
 691
 692         ret = i915_gem_object_put_fence(obj);
 693         if (ret)
 694                 goto out_unpin_pages;
 695
 696         offset = obj->gtt_offset + args->offset;
 697
 698         while (remain > 0) {
 699                 /* Operation in this page
 700                  *
 701                  * gtt_page_base = page offset within aperture
 702                  * gtt_page_offset = offset within page in aperture
 703                  * data_page_index = page number in get_user_pages return
 704                  * data_page_offset = offset with data_page_index page.
 705                  * page_length = bytes to copy for this page
 706                  */
 707                 gtt_page_base = offset & PAGE_MASK;
 708                 gtt_page_offset = offset & ~PAGE_MASK;
 709                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 710                 data_page_offset = data_ptr & ~PAGE_MASK;
 711
 712                 page_length = remain;
 713                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 714                         page_length = PAGE_SIZE - gtt_page_offset;
 715                 if ((data_page_offset + page_length) > PAGE_SIZE)
 716                         page_length = PAGE_SIZE - data_page_offset;
 717
 718                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 719                                   gtt_page_base, gtt_page_offset,
 720                                   user_pages[data_page_index],
 721                                   data_page_offset,
 722                                   page_length);
 723
 724                 remain -= page_length;
 725                 offset += page_length;
 726                 data_ptr += page_length;
 727         }
 728
 729 out_unpin_pages:
 730         for (i = 0; i < pinned_pages; i++)
 731                 page_cache_release(user_pages[i]);
 732         drm_free_large(user_pages);
 733
 734         return ret;
 735 }
 736
 737 /**
 738  * This is the fast shmem pwrite path, which attempts to directly
 739  * copy_from_user into the kmapped pages backing the object.
 740  */
 741 static int
 742 i915_gem_shmem_pwrite_fast(struct drm_device *dev,
 743                            struct drm_i915_gem_object *obj,
 744                            struct drm_i915_gem_pwrite *args,
 745                            struct drm_file *file)
 746 {
 747         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 748         ssize_t remain;
 749         loff_t offset;
 750         char __user *user_data;
 751         int page_offset, page_length;
 752
 753         user_data = (char __user *) (uintptr_t) args->data_ptr;
 754         remain = args->size;
 755
 756         offset = args->offset;
 757         obj->dirty = 1;
 758
 759         while (remain > 0) {
 760                 struct page *page;
 761                 char *vaddr;
 762                 int ret;
 763
 764                 /* Operation in this page
 765                  *
 766                  * page_offset = offset within page
 767                  * page_length = bytes to copy for this page
 768                  */
 769                 page_offset = offset & (PAGE_SIZE-1);
 770                 page_length = remain;
 771                 if ((page_offset + remain) > PAGE_SIZE)
 772                         page_length = PAGE_SIZE - page_offset;
 773
 774                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 775                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 776                 if (IS_ERR(page))
 777                         return PTR_ERR(page);
 778
 779                 vaddr = kmap_atomic(page, KM_USER0);
 780                 ret = __copy_from_user_inatomic(vaddr + page_offset,
 781                                                 user_data,
 782                                                 page_length);
 783                 kunmap_atomic(vaddr, KM_USER0);
 784
 785                 set_page_dirty(page);
 786                 mark_page_accessed(page);
 787                 page_cache_release(page);
 788
 789                 /* If we get a fault while copying data, then (presumably) our
 790                  * source page isn't available.  Return the error and we'll
 791                  * retry in the slow path.
 792                  */
 793                 if (ret)
 794                         return -EFAULT;
 795
 796                 remain -= page_length;
 797                 user_data += page_length;
 798                 offset += page_length;
 799         }
 800
 801         return 0;
 802 }
 803
 804 /**
 805  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 806  * the memory and maps it using kmap_atomic for copying.
 807  *
 808  * This avoids taking mmap_sem for faulting on the user's address while the
 809  * struct_mutex is held.
 810  */
 811 static int
 812 i915_gem_shmem_pwrite_slow(struct drm_device *dev,
 813                            struct drm_i915_gem_object *obj,
 814                            struct drm_i915_gem_pwrite *args,
 815                            struct drm_file *file)
 816 {
 817         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 818         struct mm_struct *mm = current->mm;
 819         struct page **user_pages;
 820         ssize_t remain;
 821         loff_t offset, pinned_pages, i;
 822         loff_t first_data_page, last_data_page, num_pages;
 823         int shmem_page_offset;
 824         int data_page_index,  data_page_offset;
 825         int page_length;
 826         int ret;
 827         uint64_t data_ptr = args->data_ptr;
 828         int do_bit17_swizzling;
 829
 830         remain = args->size;
 831
 832         /* Pin the user pages containing the data.  We can't fault while
 833          * holding the struct mutex, and all of the pwrite implementations
 834          * want to hold it while dereferencing the user data.
 835          */
 836         first_data_page = data_ptr / PAGE_SIZE;
 837         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 838         num_pages = last_data_page - first_data_page + 1;
 839
 840         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 841         if (user_pages == NULL)
 842                 return -ENOMEM;
 843
 844         mutex_unlock(&dev->struct_mutex);
 845         down_read(&mm->mmap_sem);
 846         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 847                                       num_pages, 0, 0, user_pages, NULL);
 848         up_read(&mm->mmap_sem);
 849         mutex_lock(&dev->struct_mutex);
 850         if (pinned_pages < num_pages) {
 851                 ret = -EFAULT;
 852                 goto out;
 853         }
 854
 855         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 856         if (ret)
 857                 goto out;
 858
 859         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 860
 861         offset = args->offset;
 862         obj->dirty = 1;
 863
 864         while (remain > 0) {
 865                 struct page *page;
 866
 867                 /* Operation in this page
 868                  *
 869                  * shmem_page_offset = offset within page in shmem file
 870                  * data_page_index = page number in get_user_pages return
 871                  * data_page_offset = offset with data_page_index page.
 872                  * page_length = bytes to copy for this page
 873                  */
 874                 shmem_page_offset = offset & ~PAGE_MASK;
 875                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 876                 data_page_offset = data_ptr & ~PAGE_MASK;
 877
 878                 page_length = remain;
 879                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 880                         page_length = PAGE_SIZE - shmem_page_offset;
 881                 if ((data_page_offset + page_length) > PAGE_SIZE)
 882                         page_length = PAGE_SIZE - data_page_offset;
 883
 884                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 885                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 886                 if (IS_ERR(page)) {
 887                         ret = PTR_ERR(page);
 888                         goto out;
 889                 }
 890
 891                 if (do_bit17_swizzling) {
 892                         slow_shmem_bit17_copy(page,
 893                                               shmem_page_offset,
 894                                               user_pages[data_page_index],
 895                                               data_page_offset,
 896                                               page_length,
 897                                               0);
 898                 } else {
 899                         slow_shmem_copy(page,
 900                                         shmem_page_offset,
 901                                         user_pages[data_page_index],
 902                                         data_page_offset,
 903                                         page_length);
 904                 }
 905
 906                 set_page_dirty(page);
 907                 mark_page_accessed(page);
 908                 page_cache_release(page);
 909
 910                 remain -= page_length;
 911                 data_ptr += page_length;
 912                 offset += page_length;
 913         }
 914
 915 out:
 916         for (i = 0; i < pinned_pages; i++)
 917                 page_cache_release(user_pages[i]);
 918         drm_free_large(user_pages);
 919
 920         return ret;
 921 }
 922
 923 /**
 924  * Writes data to the object referenced by handle.
 925  *
 926  * On error, the contents of the buffer that were to be modified are undefined.
 927  */
 928 int
 929 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 930                       struct drm_file *file)
 931 {
 932         struct drm_i915_gem_pwrite *args = data;
 933         struct drm_i915_gem_object *obj;
 934         int ret;
 935
 936         if (args->size == 0)
 937                 return 0;
 938
 939         if (!access_ok(VERIFY_READ,
 940                        (char __user *)(uintptr_t)args->data_ptr,
 941                        args->size))
 942                 return -EFAULT;
 943
 944         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
 945                                       args->size);
 946         if (ret)
 947                 return -EFAULT;
 948
 949         ret = i915_mutex_lock_interruptible(dev);
 950         if (ret)
 951                 return ret;
 952
 953         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 954         if (obj == NULL) {
 955                 ret = -ENOENT;
 956                 goto unlock;
 957         }
 958
 959         /* Bounds check destination. */
 960         if (args->offset > obj->base.size ||
 961             args->size > obj->base.size - args->offset) {
 962                 ret = -EINVAL;
 963                 goto out;
 964         }
 965
 966         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 967          * it would end up going through the fenced access, and we'll get
 968          * different detiling behavior between reading and writing.
 969          * pread/pwrite currently are reading and writing from the CPU
 970          * perspective, requiring manual detiling by the client.
 971          */
 972         if (obj->phys_obj)
 973                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
 974         else if (obj->gtt_space &&
 975                  obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 976                 ret = i915_gem_object_pin(obj, 0, true);
 977                 if (ret)
 978                         goto out;
 979
 980                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
 981                 if (ret)
 982                         goto out_unpin;
 983
 984                 ret = i915_gem_object_put_fence(obj);
 985                 if (ret)
 986                         goto out_unpin;
 987
 988                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
 989                 if (ret == -EFAULT)
 990                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
 991
 992 out_unpin:
 993                 i915_gem_object_unpin(obj);
 994         } else {
 995                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 996                 if (ret)
 997                         goto out;
 998
 999                 ret = -EFAULT;
1000                 if (!i915_gem_object_needs_bit17_swizzle(obj))
1001                         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1002                 if (ret == -EFAULT)
1003                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1004         }
1005
1006 out:
1007         drm_gem_object_unreference(&obj->base);
1008 unlock:
1009         mutex_unlock(&dev->struct_mutex);
1010         return ret;
1011 }
1012
1013 /**
1014  * Called when user space prepares to use an object with the CPU, either
1015  * through the mmap ioctl's mapping or a GTT mapping.
1016  */
1017 int
1018 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1019                           struct drm_file *file)
1020 {
1021         struct drm_i915_gem_set_domain *args = data;
1022         struct drm_i915_gem_object *obj;
1023         uint32_t read_domains = args->read_domains;
1024         uint32_t write_domain = args->write_domain;
1025         int ret;
1026
1027         if (!(dev->driver->driver_features & DRIVER_GEM))
1028                 return -ENODEV;
1029
1030         /* Only handle setting domains to types used by the CPU. */
1031         if (write_domain & I915_GEM_GPU_DOMAINS)
1032                 return -EINVAL;
1033
1034         if (read_domains & I915_GEM_GPU_DOMAINS)
1035                 return -EINVAL;
1036
1037         /* Having something in the write domain implies it's in the read
1038          * domain, and only that read domain.  Enforce that in the request.
1039          */
1040         if (write_domain != 0 && read_domains != write_domain)
1041                 return -EINVAL;
1042
1043         ret = i915_mutex_lock_interruptible(dev);
1044         if (ret)
1045                 return ret;
1046
1047         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1048         if (obj == NULL) {
1049                 ret = -ENOENT;
1050                 goto unlock;
1051         }
1052
1053         if (read_domains & I915_GEM_DOMAIN_GTT) {
1054                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1055
1056                 /* Silently promote "you're not bound, there was nothing to do"
1057                  * to success, since the client was just asking us to
1058                  * make sure everything was done.
1059                  */
1060                 if (ret == -EINVAL)
1061                         ret = 0;
1062         } else {
1063                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1064         }
1065
1066         drm_gem_object_unreference(&obj->base);
1067 unlock:
1068         mutex_unlock(&dev->struct_mutex);
1069         return ret;
1070 }
1071
1072 /**
1073  * Called when user space has done writes to this buffer
1074  */
1075 int
1076 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1077                          struct drm_file *file)
1078 {
1079         struct drm_i915_gem_sw_finish *args = data;
1080         struct drm_i915_gem_object *obj;
1081         int ret = 0;
1082
1083         if (!(dev->driver->driver_features & DRIVER_GEM))
1084                 return -ENODEV;
1085
1086         ret = i915_mutex_lock_interruptible(dev);
1087         if (ret)
1088                 return ret;
1089
1090         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1091         if (obj == NULL) {
1092                 ret = -ENOENT;
1093                 goto unlock;
1094         }
1095
1096         /* Pinned buffers may be scanout, so flush the cache */
1097         if (obj->pin_count)
1098                 i915_gem_object_flush_cpu_write_domain(obj);
1099
1100         drm_gem_object_unreference(&obj->base);
1101 unlock:
1102         mutex_unlock(&dev->struct_mutex);
1103         return ret;
1104 }
1105
1106 /**
1107  * Maps the contents of an object, returning the address it is mapped
1108  * into.
1109  *
1110  * While the mapping holds a reference on the contents of the object, it doesn't
1111  * imply a ref on the object itself.
1112  */
1113 int
1114 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1115                     struct drm_file *file)
1116 {
1117         struct drm_i915_private *dev_priv = dev->dev_private;
1118         struct drm_i915_gem_mmap *args = data;
1119         struct drm_gem_object *obj;
1120         loff_t offset;
1121         unsigned long addr;
1122
1123         if (!(dev->driver->driver_features & DRIVER_GEM))
1124                 return -ENODEV;
1125
1126         obj = drm_gem_object_lookup(dev, file, args->handle);
1127         if (obj == NULL)
1128                 return -ENOENT;
1129
1130         if (obj->size > dev_priv->mm.gtt_mappable_end) {
1131                 drm_gem_object_unreference_unlocked(obj);
1132                 return -E2BIG;
1133         }
1134
1135         offset = args->offset;
1136
1137         down_write(&current->mm->mmap_sem);
1138         addr = do_mmap(obj->filp, 0, args->size,
1139                        PROT_READ | PROT_WRITE, MAP_SHARED,
1140                        args->offset);
1141         up_write(&current->mm->mmap_sem);
1142         drm_gem_object_unreference_unlocked(obj);
1143         if (IS_ERR((void *)addr))
1144                 return addr;
1145
1146         args->addr_ptr = (uint64_t) addr;
1147
1148         return 0;
1149 }
1150
1151 /**
1152  * i915_gem_fault - fault a page into the GTT
1153  * vma: VMA in question
1154  * vmf: fault info
1155  *
1156  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1157  * from userspace.  The fault handler takes care of binding the object to
1158  * the GTT (if needed), allocating and programming a fence register (again,
1159  * only if needed based on whether the old reg is still valid or the object
1160  * is tiled) and inserting a new PTE into the faulting process.
1161  *
1162  * Note that the faulting process may involve evicting existing objects
1163  * from the GTT and/or fence registers to make room.  So performance may
1164  * suffer if the GTT working set is large or there are few fence registers
1165  * left.
1166  */
1167 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1168 {
1169         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1170         struct drm_device *dev = obj->base.dev;
1171         drm_i915_private_t *dev_priv = dev->dev_private;
1172         pgoff_t page_offset;
1173         unsigned long pfn;
1174         int ret = 0;
1175         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1176
1177         /* We don't use vmf->pgoff since that has the fake offset */
1178         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1179                 PAGE_SHIFT;
1180
1181         /* Now bind it into the GTT if needed */
1182         mutex_lock(&dev->struct_mutex);
1183
1184         if (!obj->map_and_fenceable) {
1185                 ret = i915_gem_object_unbind(obj);
1186                 if (ret)
1187                         goto unlock;
1188         }
1189         if (!obj->gtt_space) {
1190                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1191                 if (ret)
1192                         goto unlock;
1193         }
1194
1195         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1196         if (ret)
1197                 goto unlock;
1198
1199         if (obj->tiling_mode == I915_TILING_NONE)
1200                 ret = i915_gem_object_put_fence(obj);
1201         else
1202                 ret = i915_gem_object_get_fence(obj, NULL, true);
1203         if (ret)
1204                 goto unlock;
1205
1206         if (i915_gem_object_is_inactive(obj))
1207                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1208
1209         obj->fault_mappable = true;
1210
1211         pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1212                 page_offset;
1213
1214         /* Finally, remap it using the new GTT offset */
1215         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1216 unlock:
1217         mutex_unlock(&dev->struct_mutex);
1218
1219         switch (ret) {
1220         case -EAGAIN:
1221                 set_need_resched();
1222         case 0:
1223         case -ERESTARTSYS:
1224                 return VM_FAULT_NOPAGE;
1225         case -ENOMEM:
1226                 return VM_FAULT_OOM;
1227         default:
1228                 return VM_FAULT_SIGBUS;
1229         }
1230 }
1231
1232 /**
1233  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1234  * @obj: obj in question
1235  *
1236  * GEM memory mapping works by handing back to userspace a fake mmap offset
1237  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1238  * up the object based on the offset and sets up the various memory mapping
1239  * structures.
1240  *
1241  * This routine allocates and attaches a fake offset for @obj.
1242  */
1243 static int
1244 i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj)
1245 {
1246         struct drm_device *dev = obj->base.dev;
1247         struct drm_gem_mm *mm = dev->mm_private;
1248         struct drm_map_list *list;
1249         struct drm_local_map *map;
1250         int ret = 0;
1251
1252         /* Set the object up for mmap'ing */
1253         list = &obj->base.map_list;
1254         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1255         if (!list->map)
1256                 return -ENOMEM;
1257
1258         map = list->map;
1259         map->type = _DRM_GEM;
1260         map->size = obj->base.size;
1261         map->handle = obj;
1262
1263         /* Get a DRM GEM mmap offset allocated... */
1264         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1265                                                     obj->base.size / PAGE_SIZE,
1266                                                     0, 0);
1267         if (!list->file_offset_node) {
1268                 DRM_ERROR("failed to allocate offset for bo %d\n",
1269                           obj->base.name);
1270                 ret = -ENOSPC;
1271                 goto out_free_list;
1272         }
1273
1274         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1275                                                   obj->base.size / PAGE_SIZE,
1276                                                   0);
1277         if (!list->file_offset_node) {
1278                 ret = -ENOMEM;
1279                 goto out_free_list;
1280         }
1281
1282         list->hash.key = list->file_offset_node->start;
1283         ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1284         if (ret) {
1285                 DRM_ERROR("failed to add to map hash\n");
1286                 goto out_free_mm;
1287         }
1288
1289         return 0;
1290
1291 out_free_mm:
1292         drm_mm_put_block(list->file_offset_node);
1293 out_free_list:
1294         kfree(list->map);
1295         list->map = NULL;
1296
1297         return ret;
1298 }
1299
1300 /**
1301  * i915_gem_release_mmap - remove physical page mappings
1302  * @obj: obj in question
1303  *
1304  * Preserve the reservation of the mmapping with the DRM core code, but
1305  * relinquish ownership of the pages back to the system.
1306  *
1307  * It is vital that we remove the page mapping if we have mapped a tiled
1308  * object through the GTT and then lose the fence register due to
1309  * resource pressure. Similarly if the object has been moved out of the
1310  * aperture, than pages mapped into userspace must be revoked. Removing the
1311  * mapping will then trigger a page fault on the next user access, allowing
1312  * fixup by i915_gem_fault().
1313  */
1314 void
1315 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1316 {
1317         if (!obj->fault_mappable)
1318                 return;
1319
1320         unmap_mapping_range(obj->base.dev->dev_mapping,
1321                             (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1322                             obj->base.size, 1);
1323
1324         obj->fault_mappable = false;
1325 }
1326
1327 static void
1328 i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj)
1329 {
1330         struct drm_device *dev = obj->base.dev;
1331         struct drm_gem_mm *mm = dev->mm_private;
1332         struct drm_map_list *list = &obj->base.map_list;
1333
1334         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1335         drm_mm_put_block(list->file_offset_node);
1336         kfree(list->map);
1337         list->map = NULL;
1338 }
1339
1340 static uint32_t
1341 i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)
1342 {
1343         struct drm_device *dev = obj->base.dev;
1344         uint32_t size;
1345
1346         if (INTEL_INFO(dev)->gen >= 4 ||
1347             obj->tiling_mode == I915_TILING_NONE)
1348                 return obj->base.size;
1349
1350         /* Previous chips need a power-of-two fence region when tiling */
1351         if (INTEL_INFO(dev)->gen == 3)
1352                 size = 1024*1024;
1353         else
1354                 size = 512*1024;
1355
1356         while (size < obj->base.size)
1357                 size <<= 1;
1358
1359         return size;
1360 }
1361
1362 /**
1363  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1364  * @obj: object to check
1365  *
1366  * Return the required GTT alignment for an object, taking into account
1367  * potential fence register mapping.
1368  */
1369 static uint32_t
1370 i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)
1371 {
1372         struct drm_device *dev = obj->base.dev;
1373
1374         /*
1375          * Minimum alignment is 4k (GTT page size), but might be greater
1376          * if a fence register is needed for the object.
1377          */
1378         if (INTEL_INFO(dev)->gen >= 4 ||
1379             obj->tiling_mode == I915_TILING_NONE)
1380                 return 4096;
1381
1382         /*
1383          * Previous chips need to be aligned to the size of the smallest
1384          * fence register that can contain the object.
1385          */
1386         return i915_gem_get_gtt_size(obj);
1387 }
1388
1389 /**
1390  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1391  *                                       unfenced object
1392  * @obj: object to check
1393  *
1394  * Return the required GTT alignment for an object, only taking into account
1395  * unfenced tiled surface requirements.
1396  */
1397 static uint32_t
1398 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
1399 {
1400         struct drm_device *dev = obj->base.dev;
1401         int tile_height;
1402
1403         /*
1404          * Minimum alignment is 4k (GTT page size) for sane hw.
1405          */
1406         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1407             obj->tiling_mode == I915_TILING_NONE)
1408                 return 4096;
1409
1410         /*
1411          * Older chips need unfenced tiled buffers to be aligned to the left
1412          * edge of an even tile row (where tile rows are counted as if the bo is
1413          * placed in a fenced gtt region).
1414          */
1415         if (IS_GEN2(dev) ||
1416             (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
1417                 tile_height = 32;
1418         else
1419                 tile_height = 8;
1420
1421         return tile_height * obj->stride * 2;
1422 }
1423
1424 /**
1425  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1426  * @dev: DRM device
1427  * @data: GTT mapping ioctl data
1428  * @file: GEM object info
1429  *
1430  * Simply returns the fake offset to userspace so it can mmap it.
1431  * The mmap call will end up in drm_gem_mmap(), which will set things
1432  * up so we can get faults in the handler above.
1433  *
1434  * The fault handler will take care of binding the object into the GTT
1435  * (since it may have been evicted to make room for something), allocating
1436  * a fence register, and mapping the appropriate aperture address into
1437  * userspace.
1438  */
1439 int
1440 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1441                         struct drm_file *file)
1442 {
1443         struct drm_i915_private *dev_priv = dev->dev_private;
1444         struct drm_i915_gem_mmap_gtt *args = data;
1445         struct drm_i915_gem_object *obj;
1446         int ret;
1447
1448         if (!(dev->driver->driver_features & DRIVER_GEM))
1449                 return -ENODEV;
1450
1451         ret = i915_mutex_lock_interruptible(dev);
1452         if (ret)
1453                 return ret;
1454
1455         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1456         if (obj == NULL) {
1457                 ret = -ENOENT;
1458                 goto unlock;
1459         }
1460
1461         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1462                 ret = -E2BIG;
1463                 goto unlock;
1464         }
1465
1466         if (obj->madv != I915_MADV_WILLNEED) {
1467                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1468                 ret = -EINVAL;
1469                 goto out;
1470         }
1471
1472         if (!obj->base.map_list.map) {
1473                 ret = i915_gem_create_mmap_offset(obj);
1474                 if (ret)
1475                         goto out;
1476         }
1477
1478         args->offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1479
1480 out:
1481         drm_gem_object_unreference(&obj->base);
1482 unlock:
1483         mutex_unlock(&dev->struct_mutex);
1484         return ret;
1485 }
1486
1487 static int
1488 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1489                               gfp_t gfpmask)
1490 {
1491         int page_count, i;
1492         struct address_space *mapping;
1493         struct inode *inode;
1494         struct page *page;
1495
1496         /* Get the list of pages out of our struct file.  They'll be pinned
1497          * at this point until we release them.
1498          */
1499         page_count = obj->base.size / PAGE_SIZE;
1500         BUG_ON(obj->pages != NULL);
1501         obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1502         if (obj->pages == NULL)
1503                 return -ENOMEM;
1504
1505         inode = obj->base.filp->f_path.dentry->d_inode;
1506         mapping = inode->i_mapping;
1507         for (i = 0; i < page_count; i++) {
1508                 page = read_cache_page_gfp(mapping, i,
1509                                            GFP_HIGHUSER |
1510                                            __GFP_COLD |
1511                                            __GFP_RECLAIMABLE |
1512                                            gfpmask);
1513                 if (IS_ERR(page))
1514                         goto err_pages;
1515
1516                 obj->pages[i] = page;
1517         }
1518
1519         if (obj->tiling_mode != I915_TILING_NONE)
1520                 i915_gem_object_do_bit_17_swizzle(obj);
1521
1522         return 0;
1523
1524 err_pages:
1525         while (i--)
1526                 page_cache_release(obj->pages[i]);
1527
1528         drm_free_large(obj->pages);
1529         obj->pages = NULL;
1530         return PTR_ERR(page);
1531 }
1532
1533 static void
1534 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1535 {
1536         int page_count = obj->base.size / PAGE_SIZE;
1537         int i;
1538
1539         BUG_ON(obj->madv == __I915_MADV_PURGED);
1540
1541         if (obj->tiling_mode != I915_TILING_NONE)
1542                 i915_gem_object_save_bit_17_swizzle(obj);
1543
1544         if (obj->madv == I915_MADV_DONTNEED)
1545                 obj->dirty = 0;
1546
1547         for (i = 0; i < page_count; i++) {
1548                 if (obj->dirty)
1549                         set_page_dirty(obj->pages[i]);
1550
1551                 if (obj->madv == I915_MADV_WILLNEED)
1552                         mark_page_accessed(obj->pages[i]);
1553
1554                 page_cache_release(obj->pages[i]);
1555         }
1556         obj->dirty = 0;
1557
1558         drm_free_large(obj->pages);
1559         obj->pages = NULL;
1560 }
1561
1562 void
1563 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1564                                struct intel_ring_buffer *ring)
1565 {
1566         struct drm_device *dev = obj->base.dev;
1567         struct drm_i915_private *dev_priv = dev->dev_private;
1568         uint32_t seqno = i915_gem_next_request_seqno(dev, ring);
1569
1570         BUG_ON(ring == NULL);
1571         obj->ring = ring;
1572
1573         /* Add a reference if we're newly entering the active list. */
1574         if (!obj->active) {
1575                 drm_gem_object_reference(&obj->base);
1576                 obj->active = 1;
1577         }
1578
1579         /* Move from whatever list we were on to the tail of execution. */
1580         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1581         list_move_tail(&obj->ring_list, &ring->active_list);
1582
1583         obj->last_rendering_seqno = seqno;
1584         if (obj->fenced_gpu_access) {
1585                 struct drm_i915_fence_reg *reg;
1586
1587                 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1588
1589                 obj->last_fenced_seqno = seqno;
1590                 obj->last_fenced_ring = ring;
1591
1592                 reg = &dev_priv->fence_regs[obj->fence_reg];
1593                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
1594         }
1595 }
1596
1597 static void
1598 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1599 {
1600         list_del_init(&obj->ring_list);
1601         obj->last_rendering_seqno = 0;
1602 }
1603
1604 static void
1605 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1606 {
1607         struct drm_device *dev = obj->base.dev;
1608         drm_i915_private_t *dev_priv = dev->dev_private;
1609
1610         BUG_ON(!obj->active);
1611         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1612
1613         i915_gem_object_move_off_active(obj);
1614 }
1615
1616 static void
1617 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1618 {
1619         struct drm_device *dev = obj->base.dev;
1620         struct drm_i915_private *dev_priv = dev->dev_private;
1621
1622         if (obj->pin_count != 0)
1623                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1624         else
1625                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1626
1627         BUG_ON(!list_empty(&obj->gpu_write_list));
1628         BUG_ON(!obj->active);
1629         obj->ring = NULL;
1630
1631         i915_gem_object_move_off_active(obj);
1632         obj->fenced_gpu_access = false;
1633
1634         obj->active = 0;
1635         obj->pending_gpu_write = false;
1636         drm_gem_object_unreference(&obj->base);
1637
1638         WARN_ON(i915_verify_lists(dev));
1639 }
1640
1641 /* Immediately discard the backing storage */
1642 static void
1643 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1644 {
1645         struct inode *inode;
1646
1647         /* Our goal here is to return as much of the memory as
1648          * is possible back to the system as we are called from OOM.
1649          * To do this we must instruct the shmfs to drop all of its
1650          * backing pages, *now*. Here we mirror the actions taken
1651          * when by shmem_delete_inode() to release the backing store.
1652          */
1653         inode = obj->base.filp->f_path.dentry->d_inode;
1654         truncate_inode_pages(inode->i_mapping, 0);
1655         if (inode->i_op->truncate_range)
1656                 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1657
1658         obj->madv = __I915_MADV_PURGED;
1659 }
1660
1661 static inline int
1662 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1663 {
1664         return obj->madv == I915_MADV_DONTNEED;
1665 }
1666
1667 static void
1668 i915_gem_process_flushing_list(struct drm_device *dev,
1669                                uint32_t flush_domains,
1670                                struct intel_ring_buffer *ring)
1671 {
1672         struct drm_i915_gem_object *obj, *next;
1673
1674         list_for_each_entry_safe(obj, next,
1675                                  &ring->gpu_write_list,
1676                                  gpu_write_list) {
1677                 if (obj->base.write_domain & flush_domains) {
1678                         uint32_t old_write_domain = obj->base.write_domain;
1679
1680                         obj->base.write_domain = 0;
1681                         list_del_init(&obj->gpu_write_list);
1682                         i915_gem_object_move_to_active(obj, ring);
1683
1684                         trace_i915_gem_object_change_domain(obj,
1685                                                             obj->base.read_domains,
1686                                                             old_write_domain);
1687                 }
1688         }
1689 }
1690
1691 int
1692 i915_add_request(struct drm_device *dev,
1693                  struct drm_file *file,
1694                  struct drm_i915_gem_request *request,
1695                  struct intel_ring_buffer *ring)
1696 {
1697         drm_i915_private_t *dev_priv = dev->dev_private;
1698         struct drm_i915_file_private *file_priv = NULL;
1699         uint32_t seqno;
1700         int was_empty;
1701         int ret;
1702
1703         BUG_ON(request == NULL);
1704
1705         if (file != NULL)
1706                 file_priv = file->driver_priv;
1707
1708         ret = ring->add_request(ring, &seqno);
1709         if (ret)
1710             return ret;
1711
1712         ring->outstanding_lazy_request = false;
1713
1714         request->seqno = seqno;
1715         request->ring = ring;
1716         request->emitted_jiffies = jiffies;
1717         was_empty = list_empty(&ring->request_list);
1718         list_add_tail(&request->list, &ring->request_list);
1719
1720         if (file_priv) {
1721                 spin_lock(&file_priv->mm.lock);
1722                 request->file_priv = file_priv;
1723                 list_add_tail(&request->client_list,
1724                               &file_priv->mm.request_list);
1725                 spin_unlock(&file_priv->mm.lock);
1726         }
1727
1728         if (!dev_priv->mm.suspended) {
1729                 mod_timer(&dev_priv->hangcheck_timer,
1730                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1731                 if (was_empty)
1732                         queue_delayed_work(dev_priv->wq,
1733                                            &dev_priv->mm.retire_work, HZ);
1734         }
1735         return 0;
1736 }
1737
1738 static inline void
1739 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1740 {
1741         struct drm_i915_file_private *file_priv = request->file_priv;
1742
1743         if (!file_priv)
1744                 return;
1745
1746         spin_lock(&file_priv->mm.lock);
1747         list_del(&request->client_list);
1748         request->file_priv = NULL;
1749         spin_unlock(&file_priv->mm.lock);
1750 }
1751
1752 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1753                                       struct intel_ring_buffer *ring)
1754 {
1755         while (!list_empty(&ring->request_list)) {
1756                 struct drm_i915_gem_request *request;
1757
1758                 request = list_first_entry(&ring->request_list,
1759                                            struct drm_i915_gem_request,
1760                                            list);
1761
1762                 list_del(&request->list);
1763                 i915_gem_request_remove_from_client(request);
1764                 kfree(request);
1765         }
1766
1767         while (!list_empty(&ring->active_list)) {
1768                 struct drm_i915_gem_object *obj;
1769
1770                 obj = list_first_entry(&ring->active_list,
1771                                        struct drm_i915_gem_object,
1772                                        ring_list);
1773
1774                 obj->base.write_domain = 0;
1775                 list_del_init(&obj->gpu_write_list);
1776                 i915_gem_object_move_to_inactive(obj);
1777         }
1778 }
1779
1780 static void i915_gem_reset_fences(struct drm_device *dev)
1781 {
1782         struct drm_i915_private *dev_priv = dev->dev_private;
1783         int i;
1784
1785         for (i = 0; i < 16; i++) {
1786                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1787                 struct drm_i915_gem_object *obj = reg->obj;
1788
1789                 if (!obj)
1790                         continue;
1791
1792                 if (obj->tiling_mode)
1793                         i915_gem_release_mmap(obj);
1794
1795                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1796                 reg->obj->fenced_gpu_access = false;
1797                 reg->obj->last_fenced_seqno = 0;
1798                 reg->obj->last_fenced_ring = NULL;
1799                 i915_gem_clear_fence_reg(dev, reg);
1800         }
1801 }
1802
1803 void i915_gem_reset(struct drm_device *dev)
1804 {
1805         struct drm_i915_private *dev_priv = dev->dev_private;
1806         struct drm_i915_gem_object *obj;
1807
1808         i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring);
1809         i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring);
1810         i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring);
1811
1812         /* Remove anything from the flushing lists. The GPU cache is likely
1813          * to be lost on reset along with the data, so simply move the
1814          * lost bo to the inactive list.
1815          */
1816         while (!list_empty(&dev_priv->mm.flushing_list)) {
1817                 obj= list_first_entry(&dev_priv->mm.flushing_list,
1818                                       struct drm_i915_gem_object,
1819                                       mm_list);
1820
1821                 obj->base.write_domain = 0;
1822                 list_del_init(&obj->gpu_write_list);
1823                 i915_gem_object_move_to_inactive(obj);
1824         }
1825
1826         /* Move everything out of the GPU domains to ensure we do any
1827          * necessary invalidation upon reuse.
1828          */
1829         list_for_each_entry(obj,
1830                             &dev_priv->mm.inactive_list,
1831                             mm_list)
1832         {
1833                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1834         }
1835
1836         /* The fence registers are invalidated so clear them out */
1837         i915_gem_reset_fences(dev);
1838 }
1839
1840 /**
1841  * This function clears the request list as sequence numbers are passed.
1842  */
1843 static void
1844 i915_gem_retire_requests_ring(struct drm_device *dev,
1845                               struct intel_ring_buffer *ring)
1846 {
1847         drm_i915_private_t *dev_priv = dev->dev_private;
1848         uint32_t seqno;
1849
1850         if (!ring->status_page.page_addr ||
1851             list_empty(&ring->request_list))
1852                 return;
1853
1854         WARN_ON(i915_verify_lists(dev));
1855
1856         seqno = ring->get_seqno(ring);
1857         while (!list_empty(&ring->request_list)) {
1858                 struct drm_i915_gem_request *request;
1859
1860                 request = list_first_entry(&ring->request_list,
1861                                            struct drm_i915_gem_request,
1862                                            list);
1863
1864                 if (!i915_seqno_passed(seqno, request->seqno))
1865                         break;
1866
1867                 trace_i915_gem_request_retire(dev, request->seqno);
1868
1869                 list_del(&request->list);
1870                 i915_gem_request_remove_from_client(request);
1871                 kfree(request);
1872         }
1873
1874         /* Move any buffers on the active list that are no longer referenced
1875          * by the ringbuffer to the flushing/inactive lists as appropriate.
1876          */
1877         while (!list_empty(&ring->active_list)) {
1878                 struct drm_i915_gem_object *obj;
1879
1880                 obj= list_first_entry(&ring->active_list,
1881                                       struct drm_i915_gem_object,
1882                                       ring_list);
1883
1884                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1885                         break;
1886
1887                 if (obj->base.write_domain != 0)
1888                         i915_gem_object_move_to_flushing(obj);
1889                 else
1890                         i915_gem_object_move_to_inactive(obj);
1891         }
1892
1893         if (unlikely (dev_priv->trace_irq_seqno &&
1894                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1895                 ring->user_irq_put(ring);
1896                 dev_priv->trace_irq_seqno = 0;
1897         }
1898
1899         WARN_ON(i915_verify_lists(dev));
1900 }
1901
1902 void
1903 i915_gem_retire_requests(struct drm_device *dev)
1904 {
1905         drm_i915_private_t *dev_priv = dev->dev_private;
1906
1907         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1908             struct drm_i915_gem_object *obj, *next;
1909
1910             /* We must be careful that during unbind() we do not
1911              * accidentally infinitely recurse into retire requests.
1912              * Currently:
1913              *   retire -> free -> unbind -> wait -> retire_ring
1914              */
1915             list_for_each_entry_safe(obj, next,
1916                                      &dev_priv->mm.deferred_free_list,
1917                                      mm_list)
1918                     i915_gem_free_object_tail(obj);
1919         }
1920
1921         i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1922         i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1923         i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring);
1924 }
1925
1926 static void
1927 i915_gem_retire_work_handler(struct work_struct *work)
1928 {
1929         drm_i915_private_t *dev_priv;
1930         struct drm_device *dev;
1931
1932         dev_priv = container_of(work, drm_i915_private_t,
1933                                 mm.retire_work.work);
1934         dev = dev_priv->dev;
1935
1936         /* Come back later if the device is busy... */
1937         if (!mutex_trylock(&dev->struct_mutex)) {
1938                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1939                 return;
1940         }
1941
1942         i915_gem_retire_requests(dev);
1943
1944         if (!dev_priv->mm.suspended &&
1945                 (!list_empty(&dev_priv->render_ring.request_list) ||
1946                  !list_empty(&dev_priv->bsd_ring.request_list) ||
1947                  !list_empty(&dev_priv->blt_ring.request_list)))
1948                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1949         mutex_unlock(&dev->struct_mutex);
1950 }
1951
1952 int
1953 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1954                      bool interruptible, struct intel_ring_buffer *ring)
1955 {
1956         drm_i915_private_t *dev_priv = dev->dev_private;
1957         u32 ier;
1958         int ret = 0;
1959
1960         BUG_ON(seqno == 0);
1961
1962         if (atomic_read(&dev_priv->mm.wedged))
1963                 return -EAGAIN;
1964
1965         if (seqno == ring->outstanding_lazy_request) {
1966                 struct drm_i915_gem_request *request;
1967
1968                 request = kzalloc(sizeof(*request), GFP_KERNEL);
1969                 if (request == NULL)
1970                         return -ENOMEM;
1971
1972                 ret = i915_add_request(dev, NULL, request, ring);
1973                 if (ret) {
1974                         kfree(request);
1975                         return ret;
1976                 }
1977
1978                 seqno = request->seqno;
1979         }
1980
1981         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
1982                 if (HAS_PCH_SPLIT(dev))
1983                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1984                 else
1985                         ier = I915_READ(IER);
1986                 if (!ier) {
1987                         DRM_ERROR("something (likely vbetool) disabled "
1988                                   "interrupts, re-enabling\n");
1989                         i915_driver_irq_preinstall(dev);
1990                         i915_driver_irq_postinstall(dev);
1991                 }
1992
1993                 trace_i915_gem_request_wait_begin(dev, seqno);
1994
1995                 ring->waiting_seqno = seqno;
1996                 ring->user_irq_get(ring);
1997                 if (interruptible)
1998                         ret = wait_event_interruptible(ring->irq_queue,
1999                                 i915_seqno_passed(ring->get_seqno(ring), seqno)
2000                                 || atomic_read(&dev_priv->mm.wedged));
2001                 else
2002                         wait_event(ring->irq_queue,
2003                                 i915_seqno_passed(ring->get_seqno(ring), seqno)
2004                                 || atomic_read(&dev_priv->mm.wedged));
2005
2006                 ring->user_irq_put(ring);
2007                 ring->waiting_seqno = 0;
2008
2009                 trace_i915_gem_request_wait_end(dev, seqno);
2010         }
2011         if (atomic_read(&dev_priv->mm.wedged))
2012                 ret = -EAGAIN;
2013
2014         if (ret && ret != -ERESTARTSYS)
2015                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2016                           __func__, ret, seqno, ring->get_seqno(ring),
2017                           dev_priv->next_seqno);
2018
2019         /* Directly dispatch request retiring.  While we have the work queue
2020          * to handle this, the waiter on a request often wants an associated
2021          * buffer to have made it to the inactive list, and we would need
2022          * a separate wait queue to handle that.
2023          */
2024         if (ret == 0)
2025                 i915_gem_retire_requests_ring(dev, ring);
2026
2027         return ret;
2028 }
2029
2030 /**
2031  * Waits for a sequence number to be signaled, and cleans up the
2032  * request and object lists appropriately for that event.
2033  */
2034 static int
2035 i915_wait_request(struct drm_device *dev, uint32_t seqno,
2036                   struct intel_ring_buffer *ring)
2037 {
2038         return i915_do_wait_request(dev, seqno, 1, ring);
2039 }
2040
2041 /**
2042  * Ensures that all rendering to the object has completed and the object is
2043  * safe to unbind from the GTT or access from the CPU.
2044  */
2045 int
2046 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2047                                bool interruptible)
2048 {
2049         struct drm_device *dev = obj->base.dev;
2050         int ret;
2051
2052         /* This function only exists to support waiting for existing rendering,
2053          * not for emitting required flushes.
2054          */
2055         BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2056
2057         /* If there is rendering queued on the buffer being evicted, wait for
2058          * it.
2059          */
2060         if (obj->active) {
2061                 ret = i915_do_wait_request(dev,
2062                                            obj->last_rendering_seqno,
2063                                            interruptible,
2064                                            obj->ring);
2065                 if (ret)
2066                         return ret;
2067         }
2068
2069         return 0;
2070 }
2071
2072 /**
2073  * Unbinds an object from the GTT aperture.
2074  */
2075 int
2076 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2077 {
2078         int ret = 0;
2079
2080         if (obj->gtt_space == NULL)
2081                 return 0;
2082
2083         if (obj->pin_count != 0) {
2084                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2085                 return -EINVAL;
2086         }
2087
2088         /* blow away mappings if mapped through GTT */
2089         i915_gem_release_mmap(obj);
2090
2091         /* Move the object to the CPU domain to ensure that
2092          * any possible CPU writes while it's not in the GTT
2093          * are flushed when we go to remap it. This will
2094          * also ensure that all pending GPU writes are finished
2095          * before we unbind.
2096          */
2097         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2098         if (ret == -ERESTARTSYS)
2099                 return ret;
2100         /* Continue on if we fail due to EIO, the GPU is hung so we
2101          * should be safe and we need to cleanup or else we might
2102          * cause memory corruption through use-after-free.
2103          */
2104         if (ret) {
2105                 i915_gem_clflush_object(obj);
2106                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2107         }
2108
2109         /* release the fence reg _after_ flushing */
2110         ret = i915_gem_object_put_fence(obj);
2111         if (ret == -ERESTARTSYS)
2112                 return ret;
2113
2114         i915_gem_gtt_unbind_object(obj);
2115         i915_gem_object_put_pages_gtt(obj);
2116
2117         list_del_init(&obj->gtt_list);
2118         list_del_init(&obj->mm_list);
2119         /* Avoid an unnecessary call to unbind on rebind. */
2120         obj->map_and_fenceable = true;
2121
2122         drm_mm_put_block(obj->gtt_space);
2123         obj->gtt_space = NULL;
2124         obj->gtt_offset = 0;
2125
2126         if (i915_gem_object_is_purgeable(obj))
2127                 i915_gem_object_truncate(obj);
2128
2129         trace_i915_gem_object_unbind(obj);
2130
2131         return ret;
2132 }
2133
2134 void
2135 i915_gem_flush_ring(struct drm_device *dev,
2136                     struct intel_ring_buffer *ring,
2137                     uint32_t invalidate_domains,
2138                     uint32_t flush_domains)
2139 {
2140         ring->flush(ring, invalidate_domains, flush_domains);
2141         i915_gem_process_flushing_list(dev, flush_domains, ring);
2142 }
2143
2144 static int i915_ring_idle(struct drm_device *dev,
2145                           struct intel_ring_buffer *ring)
2146 {
2147         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2148                 return 0;
2149
2150         i915_gem_flush_ring(dev, ring,
2151                             I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2152         return i915_wait_request(dev,
2153                                  i915_gem_next_request_seqno(dev, ring),
2154                                  ring);
2155 }
2156
2157 int
2158 i915_gpu_idle(struct drm_device *dev)
2159 {
2160         drm_i915_private_t *dev_priv = dev->dev_private;
2161         bool lists_empty;
2162         int ret;
2163
2164         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2165                        list_empty(&dev_priv->mm.active_list));
2166         if (lists_empty)
2167                 return 0;
2168
2169         /* Flush everything onto the inactive list. */
2170         ret = i915_ring_idle(dev, &dev_priv->render_ring);
2171         if (ret)
2172                 return ret;
2173
2174         ret = i915_ring_idle(dev, &dev_priv->bsd_ring);
2175         if (ret)
2176                 return ret;
2177
2178         ret = i915_ring_idle(dev, &dev_priv->blt_ring);
2179         if (ret)
2180                 return ret;
2181
2182         return 0;
2183 }
2184
2185 static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2186                                        struct intel_ring_buffer *pipelined)
2187 {
2188         struct drm_device *dev = obj->base.dev;
2189         drm_i915_private_t *dev_priv = dev->dev_private;
2190         u32 size = obj->gtt_space->size;
2191         int regnum = obj->fence_reg;
2192         uint64_t val;
2193
2194         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2195                          0xfffff000) << 32;
2196         val |= obj->gtt_offset & 0xfffff000;
2197         val |= (uint64_t)((obj->stride / 128) - 1) <<
2198                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2199
2200         if (obj->tiling_mode == I915_TILING_Y)
2201                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2202         val |= I965_FENCE_REG_VALID;
2203
2204         if (pipelined) {
2205                 int ret = intel_ring_begin(pipelined, 6);
2206                 if (ret)
2207                         return ret;
2208
2209                 intel_ring_emit(pipelined, MI_NOOP);
2210                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2211                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2212                 intel_ring_emit(pipelined, (u32)val);
2213                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2214                 intel_ring_emit(pipelined, (u32)(val >> 32));
2215                 intel_ring_advance(pipelined);
2216         } else
2217                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2218
2219         return 0;
2220 }
2221
2222 static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
2223                                 struct intel_ring_buffer *pipelined)
2224 {
2225         struct drm_device *dev = obj->base.dev;
2226         drm_i915_private_t *dev_priv = dev->dev_private;
2227         u32 size = obj->gtt_space->size;
2228         int regnum = obj->fence_reg;
2229         uint64_t val;
2230
2231         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2232                     0xfffff000) << 32;
2233         val |= obj->gtt_offset & 0xfffff000;
2234         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2235         if (obj->tiling_mode == I915_TILING_Y)
2236                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2237         val |= I965_FENCE_REG_VALID;
2238
2239         if (pipelined) {
2240                 int ret = intel_ring_begin(pipelined, 6);
2241                 if (ret)
2242                         return ret;
2243
2244                 intel_ring_emit(pipelined, MI_NOOP);
2245                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2246                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2247                 intel_ring_emit(pipelined, (u32)val);
2248                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2249                 intel_ring_emit(pipelined, (u32)(val >> 32));
2250                 intel_ring_advance(pipelined);
2251         } else
2252                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2253
2254         return 0;
2255 }
2256
2257 static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
2258                                 struct intel_ring_buffer *pipelined)
2259 {
2260         struct drm_device *dev = obj->base.dev;
2261         drm_i915_private_t *dev_priv = dev->dev_private;
2262         u32 size = obj->gtt_space->size;
2263         u32 fence_reg, val, pitch_val;
2264         int tile_width;
2265
2266         if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2267                  (size & -size) != size ||
2268                  (obj->gtt_offset & (size - 1)),
2269                  "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2270                  obj->gtt_offset, obj->map_and_fenceable, size))
2271                 return -EINVAL;
2272
2273         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2274                 tile_width = 128;
2275         else
2276                 tile_width = 512;
2277
2278         /* Note: pitch better be a power of two tile widths */
2279         pitch_val = obj->stride / tile_width;
2280         pitch_val = ffs(pitch_val) - 1;
2281
2282         val = obj->gtt_offset;
2283         if (obj->tiling_mode == I915_TILING_Y)
2284                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2285         val |= I915_FENCE_SIZE_BITS(size);
2286         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2287         val |= I830_FENCE_REG_VALID;
2288
2289         fence_reg = obj->fence_reg;
2290         if (fence_reg < 8)
2291                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2292         else
2293                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2294
2295         if (pipelined) {
2296                 int ret = intel_ring_begin(pipelined, 4);
2297                 if (ret)
2298                         return ret;
2299
2300                 intel_ring_emit(pipelined, MI_NOOP);
2301                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2302                 intel_ring_emit(pipelined, fence_reg);
2303                 intel_ring_emit(pipelined, val);
2304                 intel_ring_advance(pipelined);
2305         } else
2306                 I915_WRITE(fence_reg, val);
2307
2308         return 0;
2309 }
2310
2311 static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
2312                                 struct intel_ring_buffer *pipelined)
2313 {
2314         struct drm_device *dev = obj->base.dev;
2315         drm_i915_private_t *dev_priv = dev->dev_private;
2316         u32 size = obj->gtt_space->size;
2317         int regnum = obj->fence_reg;
2318         uint32_t val;
2319         uint32_t pitch_val;
2320
2321         if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2322                  (size & -size) != size ||
2323                  (obj->gtt_offset & (size - 1)),
2324                  "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2325                  obj->gtt_offset, size))
2326                 return -EINVAL;
2327
2328         pitch_val = obj->stride / 128;
2329         pitch_val = ffs(pitch_val) - 1;
2330
2331         val = obj->gtt_offset;
2332         if (obj->tiling_mode == I915_TILING_Y)
2333                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2334         val |= I830_FENCE_SIZE_BITS(size);
2335         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2336         val |= I830_FENCE_REG_VALID;
2337
2338         if (pipelined) {
2339                 int ret = intel_ring_begin(pipelined, 4);
2340                 if (ret)
2341                         return ret;
2342
2343                 intel_ring_emit(pipelined, MI_NOOP);
2344                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2345                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2346                 intel_ring_emit(pipelined, val);
2347                 intel_ring_advance(pipelined);
2348         } else
2349                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2350
2351         return 0;
2352 }
2353
2354 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2355 {
2356         return i915_seqno_passed(ring->get_seqno(ring), seqno);
2357 }
2358
2359 static int
2360 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2361                             struct intel_ring_buffer *pipelined,
2362                             bool interruptible)
2363 {
2364         int ret;
2365
2366         if (obj->fenced_gpu_access) {
2367                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS)
2368                         i915_gem_flush_ring(obj->base.dev,
2369                                             obj->last_fenced_ring,
2370                                             0, obj->base.write_domain);
2371
2372                 obj->fenced_gpu_access = false;
2373         }
2374
2375         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2376                 if (!ring_passed_seqno(obj->last_fenced_ring,
2377                                        obj->last_fenced_seqno)) {
2378                         ret = i915_do_wait_request(obj->base.dev,
2379                                                    obj->last_fenced_seqno,
2380                                                    interruptible,
2381                                                    obj->last_fenced_ring);
2382                         if (ret)
2383                                 return ret;
2384                 }
2385
2386                 obj->last_fenced_seqno = 0;
2387                 obj->last_fenced_ring = NULL;
2388         }
2389
2390         return 0;
2391 }
2392
2393 int
2394 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2395 {
2396         int ret;
2397
2398         if (obj->tiling_mode)
2399                 i915_gem_release_mmap(obj);
2400
2401         ret = i915_gem_object_flush_fence(obj, NULL, true);
2402         if (ret)
2403                 return ret;
2404
2405         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2406                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2407                 i915_gem_clear_fence_reg(obj->base.dev,
2408                                          &dev_priv->fence_regs[obj->fence_reg]);
2409
2410                 obj->fence_reg = I915_FENCE_REG_NONE;
2411         }
2412
2413         return 0;
2414 }
2415
2416 static struct drm_i915_fence_reg *
2417 i915_find_fence_reg(struct drm_device *dev,
2418                     struct intel_ring_buffer *pipelined)
2419 {
2420         struct drm_i915_private *dev_priv = dev->dev_private;
2421         struct drm_i915_fence_reg *reg, *first, *avail;
2422         int i;
2423
2424         /* First try to find a free reg */
2425         avail = NULL;
2426         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2427                 reg = &dev_priv->fence_regs[i];
2428                 if (!reg->obj)
2429                         return reg;
2430
2431                 if (!reg->obj->pin_count)
2432                         avail = reg;
2433         }
2434
2435         if (avail == NULL)
2436                 return NULL;
2437
2438         /* None available, try to steal one or wait for a user to finish */
2439         avail = first = NULL;
2440         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2441                 if (reg->obj->pin_count)
2442                         continue;
2443
2444                 if (first == NULL)
2445                         first = reg;
2446
2447                 if (!pipelined ||
2448                     !reg->obj->last_fenced_ring ||
2449                     reg->obj->last_fenced_ring == pipelined) {
2450                         avail = reg;
2451                         break;
2452                 }
2453         }
2454
2455         if (avail == NULL)
2456                 avail = first;
2457
2458         return avail;
2459 }
2460
2461 /**
2462  * i915_gem_object_get_fence - set up a fence reg for an object
2463  * @obj: object to map through a fence reg
2464  * @pipelined: ring on which to queue the change, or NULL for CPU access
2465  * @interruptible: must we wait uninterruptibly for the register to retire?
2466  *
2467  * When mapping objects through the GTT, userspace wants to be able to write
2468  * to them without having to worry about swizzling if the object is tiled.
2469  *
2470  * This function walks the fence regs looking for a free one for @obj,
2471  * stealing one if it can't find any.
2472  *
2473  * It then sets up the reg based on the object's properties: address, pitch
2474  * and tiling format.
2475  */
2476 int
2477 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2478                           struct intel_ring_buffer *pipelined,
2479                           bool interruptible)
2480 {
2481         struct drm_device *dev = obj->base.dev;
2482         struct drm_i915_private *dev_priv = dev->dev_private;
2483         struct drm_i915_fence_reg *reg;
2484         int ret;
2485
2486         /* Just update our place in the LRU if our fence is getting reused. */
2487         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2488                 reg = &dev_priv->fence_regs[obj->fence_reg];
2489                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2490
2491                 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2492                         pipelined = NULL;
2493
2494                 if (!pipelined) {
2495                         if (reg->setup_seqno) {
2496                                 if (!ring_passed_seqno(obj->last_fenced_ring,
2497                                                        reg->setup_seqno)) {
2498                                         ret = i915_do_wait_request(obj->base.dev,
2499                                                                    reg->setup_seqno,
2500                                                                    interruptible,
2501                                                                    obj->last_fenced_ring);
2502                                         if (ret)
2503                                                 return ret;
2504                                 }
2505
2506                                 reg->setup_seqno = 0;
2507                         }
2508                 } else if (obj->last_fenced_ring &&
2509                            obj->last_fenced_ring != pipelined) {
2510                         ret = i915_gem_object_flush_fence(obj,
2511                                                           pipelined,
2512                                                           interruptible);
2513                         if (ret)
2514                                 return ret;
2515                 } else if (obj->tiling_changed) {
2516                         if (obj->fenced_gpu_access) {
2517                                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS)
2518                                         i915_gem_flush_ring(obj->base.dev, obj->ring,
2519                                                             0, obj->base.write_domain);
2520
2521                                 obj->fenced_gpu_access = false;
2522                         }
2523                 }
2524
2525                 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2526                         pipelined = NULL;
2527                 BUG_ON(!pipelined && reg->setup_seqno);
2528
2529                 if (obj->tiling_changed) {
2530                         if (pipelined) {
2531                                 reg->setup_seqno =
2532                                         i915_gem_next_request_seqno(dev, pipelined);
2533                                 obj->last_fenced_seqno = reg->setup_seqno;
2534                                 obj->last_fenced_ring = pipelined;
2535                         }
2536                         goto update;
2537                 }
2538
2539                 return 0;
2540         }
2541
2542         reg = i915_find_fence_reg(dev, pipelined);
2543         if (reg == NULL)
2544                 return -ENOSPC;
2545
2546         ret = i915_gem_object_flush_fence(obj, pipelined, interruptible);
2547         if (ret)
2548                 return ret;
2549
2550         if (reg->obj) {
2551                 struct drm_i915_gem_object *old = reg->obj;
2552
2553                 drm_gem_object_reference(&old->base);
2554
2555                 if (old->tiling_mode)
2556                         i915_gem_release_mmap(old);
2557
2558                 /* XXX The pipelined change over appears to be incoherent. */
2559                 ret = i915_gem_object_flush_fence(old,
2560                                                   NULL, //pipelined,
2561                                                   interruptible);
2562                 if (ret) {
2563                         drm_gem_object_unreference(&old->base);
2564                         return ret;
2565                 }
2566
2567                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
2568                         pipelined = NULL;
2569
2570                 old->fence_reg = I915_FENCE_REG_NONE;
2571                 old->last_fenced_ring = pipelined;
2572                 old->last_fenced_seqno =
2573                         pipelined ? i915_gem_next_request_seqno(dev, pipelined) : 0;
2574
2575                 drm_gem_object_unreference(&old->base);
2576         } else if (obj->last_fenced_seqno == 0)
2577                 pipelined = NULL;
2578
2579         reg->obj = obj;
2580         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2581         obj->fence_reg = reg - dev_priv->fence_regs;
2582         obj->last_fenced_ring = pipelined;
2583
2584         reg->setup_seqno =
2585                 pipelined ? i915_gem_next_request_seqno(dev, pipelined) : 0;
2586         obj->last_fenced_seqno = reg->setup_seqno;
2587
2588 update:
2589         obj->tiling_changed = false;
2590         switch (INTEL_INFO(dev)->gen) {
2591         case 6:
2592                 ret = sandybridge_write_fence_reg(obj, pipelined);
2593                 break;
2594         case 5:
2595         case 4:
2596                 ret = i965_write_fence_reg(obj, pipelined);
2597                 break;
2598         case 3:
2599                 ret = i915_write_fence_reg(obj, pipelined);
2600                 break;
2601         case 2:
2602                 ret = i830_write_fence_reg(obj, pipelined);
2603                 break;
2604         }
2605
2606         trace_i915_gem_object_get_fence(obj,
2607                                         obj->fence_reg,
2608                                         obj->tiling_mode);
2609         return ret;
2610 }
2611
2612 /**
2613  * i915_gem_clear_fence_reg - clear out fence register info
2614  * @obj: object to clear
2615  *
2616  * Zeroes out the fence register itself and clears out the associated
2617  * data structures in dev_priv and obj.
2618  */
2619 static void
2620 i915_gem_clear_fence_reg(struct drm_device *dev,
2621                          struct drm_i915_fence_reg *reg)
2622 {
2623         drm_i915_private_t *dev_priv = dev->dev_private;
2624         uint32_t fence_reg = reg - dev_priv->fence_regs;
2625
2626         switch (INTEL_INFO(dev)->gen) {
2627         case 6:
2628                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
2629                 break;
2630         case 5:
2631         case 4:
2632                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
2633                 break;
2634         case 3:
2635                 if (fence_reg >= 8)
2636                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2637                 else
2638         case 2:
2639                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2640
2641                 I915_WRITE(fence_reg, 0);
2642                 break;
2643         }
2644
2645         list_del_init(&reg->lru_list);
2646         reg->obj = NULL;
2647         reg->setup_seqno = 0;
2648 }
2649
2650 /**
2651  * Finds free space in the GTT aperture and binds the object there.
2652  */
2653 static int
2654 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2655                             unsigned alignment,
2656                             bool map_and_fenceable)
2657 {
2658         struct drm_device *dev = obj->base.dev;
2659         drm_i915_private_t *dev_priv = dev->dev_private;
2660         struct drm_mm_node *free_space;
2661         gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2662         u32 size, fence_size, fence_alignment, unfenced_alignment;
2663         bool mappable, fenceable;
2664         int ret;
2665
2666         if (obj->madv != I915_MADV_WILLNEED) {
2667                 DRM_ERROR("Attempting to bind a purgeable object\n");
2668                 return -EINVAL;
2669         }
2670
2671         fence_size = i915_gem_get_gtt_size(obj);
2672         fence_alignment = i915_gem_get_gtt_alignment(obj);
2673         unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj);
2674
2675         if (alignment == 0)
2676                 alignment = map_and_fenceable ? fence_alignment :
2677                                                 unfenced_alignment;
2678         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2679                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2680                 return -EINVAL;
2681         }
2682
2683         size = map_and_fenceable ? fence_size : obj->base.size;
2684
2685         /* If the object is bigger than the entire aperture, reject it early
2686          * before evicting everything in a vain attempt to find space.
2687          */
2688         if (obj->base.size >
2689             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2690                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2691                 return -E2BIG;
2692         }
2693
2694  search_free:
2695         if (map_and_fenceable)
2696                 free_space =
2697                         drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2698                                                     size, alignment, 0,
2699                                                     dev_priv->mm.gtt_mappable_end,
2700                                                     0);
2701         else
2702                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2703                                                 size, alignment, 0);
2704
2705         if (free_space != NULL) {
2706                 if (map_and_fenceable)
2707                         obj->gtt_space =
2708                                 drm_mm_get_block_range_generic(free_space,
2709                                                                size, alignment, 0,
2710                                                                dev_priv->mm.gtt_mappable_end,
2711                                                                0);
2712                 else
2713                         obj->gtt_space =
2714                                 drm_mm_get_block(free_space, size, alignment);
2715         }
2716         if (obj->gtt_space == NULL) {
2717                 /* If the gtt is empty and we're still having trouble
2718                  * fitting our object in, we're out of memory.
2719                  */
2720                 ret = i915_gem_evict_something(dev, size, alignment,
2721                                                map_and_fenceable);
2722                 if (ret)
2723                         return ret;
2724
2725                 goto search_free;
2726         }
2727
2728         ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2729         if (ret) {
2730                 drm_mm_put_block(obj->gtt_space);
2731                 obj->gtt_space = NULL;
2732
2733                 if (ret == -ENOMEM) {
2734                         /* first try to clear up some space from the GTT */
2735                         ret = i915_gem_evict_something(dev, size,
2736                                                        alignment,
2737                                                        map_and_fenceable);
2738                         if (ret) {
2739                                 /* now try to shrink everyone else */
2740                                 if (gfpmask) {
2741                                         gfpmask = 0;
2742                                         goto search_free;
2743                                 }
2744
2745                                 return ret;
2746                         }
2747
2748                         goto search_free;
2749                 }
2750
2751                 return ret;
2752         }
2753
2754         ret = i915_gem_gtt_bind_object(obj);
2755         if (ret) {
2756                 i915_gem_object_put_pages_gtt(obj);
2757                 drm_mm_put_block(obj->gtt_space);
2758                 obj->gtt_space = NULL;
2759
2760                 ret = i915_gem_evict_something(dev, size,
2761                                                alignment, map_and_fenceable);
2762                 if (ret)
2763                         return ret;
2764
2765                 goto search_free;
2766         }
2767
2768         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2769         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2770
2771         /* Assert that the object is not currently in any GPU domain. As it
2772          * wasn't in the GTT, there shouldn't be any way it could have been in
2773          * a GPU cache
2774          */
2775         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2776         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2777
2778         obj->gtt_offset = obj->gtt_space->start;
2779
2780         fenceable =
2781                 obj->gtt_space->size == fence_size &&
2782                 (obj->gtt_space->start & (fence_alignment -1)) == 0;
2783
2784         mappable =
2785                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2786
2787         obj->map_and_fenceable = mappable && fenceable;
2788
2789         trace_i915_gem_object_bind(obj, obj->gtt_offset, map_and_fenceable);
2790         return 0;
2791 }
2792
2793 void
2794 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2795 {
2796         /* If we don't have a page list set up, then we're not pinned
2797          * to GPU, and we can ignore the cache flush because it'll happen
2798          * again at bind time.
2799          */
2800         if (obj->pages == NULL)
2801                 return;
2802
2803         trace_i915_gem_object_clflush(obj);
2804
2805         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2806 }
2807
2808 /** Flushes any GPU write domain for the object if it's dirty. */
2809 static void
2810 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2811 {
2812         struct drm_device *dev = obj->base.dev;
2813
2814         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2815                 return;
2816
2817         /* Queue the GPU write cache flushing we need. */
2818         i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain);
2819         BUG_ON(obj->base.write_domain);
2820 }
2821
2822 /** Flushes the GTT write domain for the object if it's dirty. */
2823 static void
2824 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2825 {
2826         uint32_t old_write_domain;
2827
2828         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2829                 return;
2830
2831         /* No actual flushing is required for the GTT write domain.   Writes
2832          * to it immediately go to main memory as far as we know, so there's
2833          * no chipset flush.  It also doesn't land in render cache.
2834          */
2835         i915_gem_release_mmap(obj);
2836
2837         old_write_domain = obj->base.write_domain;
2838         obj->base.write_domain = 0;
2839
2840         trace_i915_gem_object_change_domain(obj,
2841                                             obj->base.read_domains,
2842                                             old_write_domain);
2843 }
2844
2845 /** Flushes the CPU write domain for the object if it's dirty. */
2846 static void
2847 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2848 {
2849         uint32_t old_write_domain;
2850
2851         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2852                 return;
2853
2854         i915_gem_clflush_object(obj);
2855         intel_gtt_chipset_flush();
2856         old_write_domain = obj->base.write_domain;
2857         obj->base.write_domain = 0;
2858
2859         trace_i915_gem_object_change_domain(obj,
2860                                             obj->base.read_domains,
2861                                             old_write_domain);
2862 }
2863
2864 /**
2865  * Moves a single object to the GTT read, and possibly write domain.
2866  *
2867  * This function returns when the move is complete, including waiting on
2868  * flushes to occur.
2869  */
2870 int
2871 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2872 {
2873         uint32_t old_write_domain, old_read_domains;
2874         int ret;
2875
2876         /* Not valid to be called on unbound objects. */
2877         if (obj->gtt_space == NULL)
2878                 return -EINVAL;
2879
2880         i915_gem_object_flush_gpu_write_domain(obj);
2881         if (obj->pending_gpu_write || write) {
2882                 ret = i915_gem_object_wait_rendering(obj, true);
2883                 if (ret)
2884                         return ret;
2885         }
2886
2887         i915_gem_object_flush_cpu_write_domain(obj);
2888
2889         old_write_domain = obj->base.write_domain;
2890         old_read_domains = obj->base.read_domains;
2891
2892         /* It should now be out of any other write domains, and we can update
2893          * the domain values for our changes.
2894          */
2895         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2896         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2897         if (write) {
2898                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2899                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2900                 obj->dirty = 1;
2901         }
2902
2903         trace_i915_gem_object_change_domain(obj,
2904                                             old_read_domains,
2905                                             old_write_domain);
2906
2907         return 0;
2908 }
2909
2910 /*
2911  * Prepare buffer for display plane. Use uninterruptible for possible flush
2912  * wait, as in modesetting process we're not supposed to be interrupted.
2913  */
2914 int
2915 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
2916                                      struct intel_ring_buffer *pipelined)
2917 {
2918         uint32_t old_read_domains;
2919         int ret;
2920
2921         /* Not valid to be called on unbound objects. */
2922         if (obj->gtt_space == NULL)
2923                 return -EINVAL;
2924
2925         i915_gem_object_flush_gpu_write_domain(obj);
2926
2927         /* Currently, we are always called from an non-interruptible context. */
2928         if (!pipelined) {
2929                 ret = i915_gem_object_wait_rendering(obj, false);
2930                 if (ret)
2931                         return ret;
2932         }
2933
2934         i915_gem_object_flush_cpu_write_domain(obj);
2935
2936         old_read_domains = obj->base.read_domains;
2937         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2938
2939         trace_i915_gem_object_change_domain(obj,
2940                                             old_read_domains,
2941                                             obj->base.write_domain);
2942
2943         return 0;
2944 }
2945
2946 int
2947 i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
2948                           bool interruptible)
2949 {
2950         if (!obj->active)
2951                 return 0;
2952
2953         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS)
2954                 i915_gem_flush_ring(obj->base.dev, obj->ring,
2955                                     0, obj->base.write_domain);
2956
2957         return i915_gem_object_wait_rendering(obj, interruptible);
2958 }
2959
2960 /**
2961  * Moves a single object to the CPU read, and possibly write domain.
2962  *
2963  * This function returns when the move is complete, including waiting on
2964  * flushes to occur.
2965  */
2966 static int
2967 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2968 {
2969         uint32_t old_write_domain, old_read_domains;
2970         int ret;
2971
2972         i915_gem_object_flush_gpu_write_domain(obj);
2973         ret = i915_gem_object_wait_rendering(obj, true);
2974         if (ret)
2975                 return ret;
2976
2977         i915_gem_object_flush_gtt_write_domain(obj);
2978
2979         /* If we have a partially-valid cache of the object in the CPU,
2980          * finish invalidating it and free the per-page flags.
2981          */
2982         i915_gem_object_set_to_full_cpu_read_domain(obj);
2983
2984         old_write_domain = obj->base.write_domain;
2985         old_read_domains = obj->base.read_domains;
2986
2987         /* Flush the CPU cache if it's still invalid. */
2988         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2989                 i915_gem_clflush_object(obj);
2990
2991                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2992         }
2993
2994         /* It should now be out of any other write domains, and we can update
2995          * the domain values for our changes.
2996          */
2997         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2998
2999         /* If we're writing through the CPU, then the GPU read domains will
3000          * need to be invalidated at next use.
3001          */
3002         if (write) {
3003                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3004                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3005         }
3006
3007         trace_i915_gem_object_change_domain(obj,
3008                                             old_read_domains,
3009                                             old_write_domain);
3010
3011         return 0;
3012 }
3013
3014 /**
3015  * Moves the object from a partially CPU read to a full one.
3016  *
3017  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3018  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3019  */
3020 static void
3021 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
3022 {
3023         if (!obj->page_cpu_valid)
3024                 return;
3025
3026         /* If we're partially in the CPU read domain, finish moving it in.
3027          */
3028         if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
3029                 int i;
3030
3031                 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
3032                         if (obj->page_cpu_valid[i])
3033                                 continue;
3034                         drm_clflush_pages(obj->pages + i, 1);
3035                 }
3036         }
3037
3038         /* Free the page_cpu_valid mappings which are now stale, whether
3039          * or not we've got I915_GEM_DOMAIN_CPU.
3040          */
3041         kfree(obj->page_cpu_valid);
3042         obj->page_cpu_valid = NULL;
3043 }
3044
3045 /**
3046  * Set the CPU read domain on a range of the object.
3047  *
3048  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3049  * not entirely valid.  The page_cpu_valid member of the object flags which
3050  * pages have been flushed, and will be respected by
3051  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3052  * of the whole object.
3053  *
3054  * This function returns when the move is complete, including waiting on
3055  * flushes to occur.
3056  */
3057 static int
3058 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3059                                           uint64_t offset, uint64_t size)
3060 {
3061         uint32_t old_read_domains;
3062         int i, ret;
3063
3064         if (offset == 0 && size == obj->base.size)
3065                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3066
3067         i915_gem_object_flush_gpu_write_domain(obj);
3068         ret = i915_gem_object_wait_rendering(obj, true);
3069         if (ret)
3070                 return ret;
3071
3072         i915_gem_object_flush_gtt_write_domain(obj);
3073
3074         /* If we're already fully in the CPU read domain, we're done. */
3075         if (obj->page_cpu_valid == NULL &&
3076             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3077                 return 0;
3078
3079         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3080          * newly adding I915_GEM_DOMAIN_CPU
3081          */
3082         if (obj->page_cpu_valid == NULL) {
3083                 obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
3084                                               GFP_KERNEL);
3085                 if (obj->page_cpu_valid == NULL)
3086                         return -ENOMEM;
3087         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3088                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3089
3090         /* Flush the cache on any pages that are still invalid from the CPU's
3091          * perspective.
3092          */
3093         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3094              i++) {
3095                 if (obj->page_cpu_valid[i])
3096                         continue;
3097
3098                 drm_clflush_pages(obj->pages + i, 1);
3099
3100                 obj->page_cpu_valid[i] = 1;
3101         }
3102
3103         /* It should now be out of any other write domains, and we can update
3104          * the domain values for our changes.
3105          */
3106         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3107
3108         old_read_domains = obj->base.read_domains;
3109         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3110
3111         trace_i915_gem_object_change_domain(obj,
3112                                             old_read_domains,
3113                                             obj->base.write_domain);
3114
3115         return 0;
3116 }
3117
3118 /* Throttle our rendering by waiting until the ring has completed our requests
3119  * emitted over 20 msec ago.
3120  *
3121  * Note that if we were to use the current jiffies each time around the loop,
3122  * we wouldn't escape the function with any frames outstanding if the time to
3123  * render a frame was over 20ms.
3124  *
3125  * This should get us reasonable parallelism between CPU and GPU but also
3126  * relatively low latency when blocking on a particular request to finish.
3127  */
3128 static int
3129 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3130 {
3131         struct drm_i915_private *dev_priv = dev->dev_private;
3132         struct drm_i915_file_private *file_priv = file->driver_priv;
3133         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3134         struct drm_i915_gem_request *request;
3135         struct intel_ring_buffer *ring = NULL;
3136         u32 seqno = 0;
3137         int ret;
3138
3139         spin_lock(&file_priv->mm.lock);
3140         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3141                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3142                         break;
3143
3144                 ring = request->ring;
3145                 seqno = request->seqno;
3146         }
3147         spin_unlock(&file_priv->mm.lock);
3148
3149         if (seqno == 0)
3150                 return 0;
3151
3152         ret = 0;
3153         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3154                 /* And wait for the seqno passing without holding any locks and
3155                  * causing extra latency for others. This is safe as the irq
3156                  * generation is designed to be run atomically and so is
3157                  * lockless.
3158                  */
3159                 ring->user_irq_get(ring);
3160                 ret = wait_event_interruptible(ring->irq_queue,
3161                                                i915_seqno_passed(ring->get_seqno(ring), seqno)
3162                                                || atomic_read(&dev_priv->mm.wedged));
3163                 ring->user_irq_put(ring);
3164
3165                 if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3166                         ret = -EIO;
3167         }
3168
3169         if (ret == 0)
3170                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3171
3172         return ret;
3173 }
3174
3175 int
3176 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3177                     uint32_t alignment,
3178                     bool map_and_fenceable)
3179 {
3180         struct drm_device *dev = obj->base.dev;
3181         struct drm_i915_private *dev_priv = dev->dev_private;
3182         int ret;
3183
3184         BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3185         WARN_ON(i915_verify_lists(dev));
3186
3187         if (obj->gtt_space != NULL) {
3188                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3189                     (map_and_fenceable && !obj->map_and_fenceable)) {
3190                         WARN(obj->pin_count,
3191                              "bo is already pinned with incorrect alignment:"
3192                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3193                              " obj->map_and_fenceable=%d\n",
3194                              obj->gtt_offset, alignment,
3195                              map_and_fenceable,
3196                              obj->map_and_fenceable);
3197                         ret = i915_gem_object_unbind(obj);
3198                         if (ret)
3199                                 return ret;
3200                 }
3201         }
3202
3203         if (obj->gtt_space == NULL) {
3204                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3205                                                   map_and_fenceable);
3206                 if (ret)
3207                         return ret;
3208         }
3209
3210         if (obj->pin_count++ == 0) {
3211                 if (!obj->active)
3212                         list_move_tail(&obj->mm_list,
3213                                        &dev_priv->mm.pinned_list);
3214         }
3215         obj->pin_mappable |= map_and_fenceable;
3216
3217         WARN_ON(i915_verify_lists(dev));
3218         return 0;
3219 }
3220
3221 void
3222 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3223 {
3224         struct drm_device *dev = obj->base.dev;
3225         drm_i915_private_t *dev_priv = dev->dev_private;
3226
3227         WARN_ON(i915_verify_lists(dev));
3228         BUG_ON(obj->pin_count == 0);
3229         BUG_ON(obj->gtt_space == NULL);
3230
3231         if (--obj->pin_count == 0) {
3232                 if (!obj->active)
3233                         list_move_tail(&obj->mm_list,
3234                                        &dev_priv->mm.inactive_list);
3235                 obj->pin_mappable = false;
3236         }
3237         WARN_ON(i915_verify_lists(dev));
3238 }
3239
3240 int
3241 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3242                    struct drm_file *file)
3243 {
3244         struct drm_i915_gem_pin *args = data;
3245         struct drm_i915_gem_object *obj;
3246         int ret;
3247
3248         ret = i915_mutex_lock_interruptible(dev);
3249         if (ret)
3250                 return ret;
3251
3252         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3253         if (obj == NULL) {
3254                 ret = -ENOENT;
3255                 goto unlock;
3256         }
3257
3258         if (obj->madv != I915_MADV_WILLNEED) {
3259                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3260                 ret = -EINVAL;
3261                 goto out;
3262         }
3263
3264         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3265                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3266                           args->handle);
3267                 ret = -EINVAL;
3268                 goto out;
3269         }
3270
3271         obj->user_pin_count++;
3272         obj->pin_filp = file;
3273         if (obj->user_pin_count == 1) {
3274                 ret = i915_gem_object_pin(obj, args->alignment, true);
3275                 if (ret)
3276                         goto out;
3277         }
3278
3279         /* XXX - flush the CPU caches for pinned objects
3280          * as the X server doesn't manage domains yet
3281          */
3282         i915_gem_object_flush_cpu_write_domain(obj);
3283         args->offset = obj->gtt_offset;
3284 out:
3285         drm_gem_object_unreference(&obj->base);
3286 unlock:
3287         mutex_unlock(&dev->struct_mutex);
3288         return ret;
3289 }
3290
3291 int
3292 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3293                      struct drm_file *file)
3294 {
3295         struct drm_i915_gem_pin *args = data;
3296         struct drm_i915_gem_object *obj;
3297         int ret;
3298
3299         ret = i915_mutex_lock_interruptible(dev);
3300         if (ret)
3301                 return ret;
3302
3303         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3304         if (obj == NULL) {
3305                 ret = -ENOENT;
3306                 goto unlock;
3307         }
3308
3309         if (obj->pin_filp != file) {
3310                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3311                           args->handle);
3312                 ret = -EINVAL;
3313                 goto out;
3314         }
3315         obj->user_pin_count--;
3316         if (obj->user_pin_count == 0) {
3317                 obj->pin_filp = NULL;
3318                 i915_gem_object_unpin(obj);
3319         }
3320
3321 out:
3322         drm_gem_object_unreference(&obj->base);
3323 unlock:
3324         mutex_unlock(&dev->struct_mutex);
3325         return ret;
3326 }
3327
3328 int
3329 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3330                     struct drm_file *file)
3331 {
3332         struct drm_i915_gem_busy *args = data;
3333         struct drm_i915_gem_object *obj;
3334         int ret;
3335
3336         ret = i915_mutex_lock_interruptible(dev);
3337         if (ret)
3338                 return ret;
3339
3340         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3341         if (obj == NULL) {
3342                 ret = -ENOENT;
3343                 goto unlock;
3344         }
3345
3346         /* Count all active objects as busy, even if they are currently not used
3347          * by the gpu. Users of this interface expect objects to eventually
3348          * become non-busy without any further actions, therefore emit any
3349          * necessary flushes here.
3350          */
3351         args->busy = obj->active;
3352         if (args->busy) {
3353                 /* Unconditionally flush objects, even when the gpu still uses this
3354                  * object. Userspace calling this function indicates that it wants to
3355                  * use this buffer rather sooner than later, so issuing the required
3356                  * flush earlier is beneficial.
3357                  */
3358                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS)
3359                         i915_gem_flush_ring(dev, obj->ring,
3360                                             0, obj->base.write_domain);
3361
3362                 /* Update the active list for the hardware's current position.
3363                  * Otherwise this only updates on a delayed timer or when irqs
3364                  * are actually unmasked, and our working set ends up being
3365                  * larger than required.
3366                  */
3367                 i915_gem_retire_requests_ring(dev, obj->ring);
3368
3369                 args->busy = obj->active;
3370         }
3371
3372         drm_gem_object_unreference(&obj->base);
3373 unlock:
3374         mutex_unlock(&dev->struct_mutex);
3375         return ret;
3376 }
3377
3378 int
3379 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3380                         struct drm_file *file_priv)
3381 {
3382     return i915_gem_ring_throttle(dev, file_priv);
3383 }
3384
3385 int
3386 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3387                        struct drm_file *file_priv)
3388 {
3389         struct drm_i915_gem_madvise *args = data;
3390         struct drm_i915_gem_object *obj;
3391         int ret;
3392
3393         switch (args->madv) {
3394         case I915_MADV_DONTNEED:
3395         case I915_MADV_WILLNEED:
3396             break;
3397         default:
3398             return -EINVAL;
3399         }
3400
3401         ret = i915_mutex_lock_interruptible(dev);
3402         if (ret)
3403                 return ret;
3404
3405         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3406         if (obj == NULL) {
3407                 ret = -ENOENT;
3408                 goto unlock;
3409         }
3410
3411         if (obj->pin_count) {
3412                 ret = -EINVAL;
3413                 goto out;
3414         }
3415
3416         if (obj->madv != __I915_MADV_PURGED)
3417                 obj->madv = args->madv;
3418
3419         /* if the object is no longer bound, discard its backing storage */
3420         if (i915_gem_object_is_purgeable(obj) &&
3421             obj->gtt_space == NULL)
3422                 i915_gem_object_truncate(obj);
3423
3424         args->retained = obj->madv != __I915_MADV_PURGED;
3425
3426 out:
3427         drm_gem_object_unreference(&obj->base);
3428 unlock:
3429         mutex_unlock(&dev->struct_mutex);
3430         return ret;
3431 }
3432
3433 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3434                                                   size_t size)
3435 {
3436         struct drm_i915_private *dev_priv = dev->dev_private;
3437         struct drm_i915_gem_object *obj;
3438
3439         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3440         if (obj == NULL)
3441                 return NULL;
3442
3443         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3444                 kfree(obj);
3445                 return NULL;
3446         }
3447
3448         i915_gem_info_add_obj(dev_priv, size);
3449
3450         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3451         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3452
3453         obj->agp_type = AGP_USER_MEMORY;
3454         obj->base.driver_private = NULL;
3455         obj->fence_reg = I915_FENCE_REG_NONE;
3456         INIT_LIST_HEAD(&obj->mm_list);
3457         INIT_LIST_HEAD(&obj->gtt_list);
3458         INIT_LIST_HEAD(&obj->ring_list);
3459         INIT_LIST_HEAD(&obj->exec_list);
3460         INIT_LIST_HEAD(&obj->gpu_write_list);
3461         obj->madv = I915_MADV_WILLNEED;
3462         /* Avoid an unnecessary call to unbind on the first bind. */
3463         obj->map_and_fenceable = true;
3464
3465         return obj;
3466 }
3467
3468 int i915_gem_init_object(struct drm_gem_object *obj)
3469 {
3470         BUG();
3471
3472         return 0;
3473 }
3474
3475 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3476 {
3477         struct drm_device *dev = obj->base.dev;
3478         drm_i915_private_t *dev_priv = dev->dev_private;
3479         int ret;
3480
3481         ret = i915_gem_object_unbind(obj);
3482         if (ret == -ERESTARTSYS) {
3483                 list_move(&obj->mm_list,
3484                           &dev_priv->mm.deferred_free_list);
3485                 return;
3486         }
3487
3488         if (obj->base.map_list.map)
3489                 i915_gem_free_mmap_offset(obj);
3490
3491         drm_gem_object_release(&obj->base);
3492         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3493
3494         kfree(obj->page_cpu_valid);
3495         kfree(obj->bit_17);
3496         kfree(obj);
3497 }
3498
3499 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3500 {
3501         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3502         struct drm_device *dev = obj->base.dev;
3503
3504         trace_i915_gem_object_destroy(obj);
3505
3506         while (obj->pin_count > 0)
3507                 i915_gem_object_unpin(obj);
3508
3509         if (obj->phys_obj)
3510                 i915_gem_detach_phys_object(dev, obj);
3511
3512         i915_gem_free_object_tail(obj);
3513 }
3514
3515 int
3516 i915_gem_idle(struct drm_device *dev)
3517 {
3518         drm_i915_private_t *dev_priv = dev->dev_private;
3519         int ret;
3520
3521         mutex_lock(&dev->struct_mutex);
3522
3523         if (dev_priv->mm.suspended) {
3524                 mutex_unlock(&dev->struct_mutex);
3525                 return 0;
3526         }
3527
3528         ret = i915_gpu_idle(dev);
3529         if (ret) {
3530                 mutex_unlock(&dev->struct_mutex);
3531                 return ret;
3532         }
3533
3534         /* Under UMS, be paranoid and evict. */
3535         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
3536                 ret = i915_gem_evict_inactive(dev, false);
3537                 if (ret) {
3538                         mutex_unlock(&dev->struct_mutex);
3539                         return ret;
3540                 }
3541         }
3542
3543         i915_gem_reset_fences(dev);
3544
3545         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3546          * We need to replace this with a semaphore, or something.
3547          * And not confound mm.suspended!
3548          */
3549         dev_priv->mm.suspended = 1;
3550         del_timer_sync(&dev_priv->hangcheck_timer);
3551
3552         i915_kernel_lost_context(dev);
3553         i915_gem_cleanup_ringbuffer(dev);
3554
3555         mutex_unlock(&dev->struct_mutex);
3556
3557         /* Cancel the retire work handler, which should be idle now. */
3558         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3559
3560         return 0;
3561 }
3562
3563 int
3564 i915_gem_init_ringbuffer(struct drm_device *dev)
3565 {
3566         drm_i915_private_t *dev_priv = dev->dev_private;
3567         int ret;
3568
3569         ret = intel_init_render_ring_buffer(dev);
3570         if (ret)
3571                 return ret;
3572
3573         if (HAS_BSD(dev)) {
3574                 ret = intel_init_bsd_ring_buffer(dev);
3575                 if (ret)
3576                         goto cleanup_render_ring;
3577         }
3578
3579         if (HAS_BLT(dev)) {
3580                 ret = intel_init_blt_ring_buffer(dev);
3581                 if (ret)
3582                         goto cleanup_bsd_ring;
3583         }
3584
3585         dev_priv->next_seqno = 1;
3586
3587         return 0;
3588
3589 cleanup_bsd_ring:
3590         intel_cleanup_ring_buffer(&dev_priv->bsd_ring);
3591 cleanup_render_ring:
3592         intel_cleanup_ring_buffer(&dev_priv->render_ring);
3593         return ret;
3594 }
3595
3596 void
3597 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3598 {
3599         drm_i915_private_t *dev_priv = dev->dev_private;
3600
3601         intel_cleanup_ring_buffer(&dev_priv->render_ring);
3602         intel_cleanup_ring_buffer(&dev_priv->bsd_ring);
3603         intel_cleanup_ring_buffer(&dev_priv->blt_ring);
3604 }
3605
3606 int
3607 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3608                        struct drm_file *file_priv)
3609 {
3610         drm_i915_private_t *dev_priv = dev->dev_private;
3611         int ret;
3612
3613         if (drm_core_check_feature(dev, DRIVER_MODESET))
3614                 return 0;
3615
3616         if (atomic_read(&dev_priv->mm.wedged)) {
3617                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3618                 atomic_set(&dev_priv->mm.wedged, 0);
3619         }
3620
3621         mutex_lock(&dev->struct_mutex);
3622         dev_priv->mm.suspended = 0;
3623
3624         ret = i915_gem_init_ringbuffer(dev);
3625         if (ret != 0) {
3626                 mutex_unlock(&dev->struct_mutex);
3627                 return ret;
3628         }
3629
3630         BUG_ON(!list_empty(&dev_priv->mm.active_list));
3631         BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
3632         BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list));
3633         BUG_ON(!list_empty(&dev_priv->blt_ring.active_list));
3634         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3635         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3636         BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
3637         BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list));
3638         BUG_ON(!list_empty(&dev_priv->blt_ring.request_list));
3639         mutex_unlock(&dev->struct_mutex);
3640
3641         ret = drm_irq_install(dev);
3642         if (ret)
3643                 goto cleanup_ringbuffer;
3644
3645         return 0;
3646
3647 cleanup_ringbuffer:
3648         mutex_lock(&dev->struct_mutex);
3649         i915_gem_cleanup_ringbuffer(dev);
3650         dev_priv->mm.suspended = 1;
3651         mutex_unlock(&dev->struct_mutex);
3652
3653         return ret;
3654 }
3655
3656 int
3657 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3658                        struct drm_file *file_priv)
3659 {
3660         if (drm_core_check_feature(dev, DRIVER_MODESET))
3661                 return 0;
3662
3663         drm_irq_uninstall(dev);
3664         return i915_gem_idle(dev);
3665 }
3666
3667 void
3668 i915_gem_lastclose(struct drm_device *dev)
3669 {
3670         int ret;
3671
3672         if (drm_core_check_feature(dev, DRIVER_MODESET))
3673                 return;
3674
3675         ret = i915_gem_idle(dev);
3676         if (ret)
3677                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3678 }
3679
3680 static void
3681 init_ring_lists(struct intel_ring_buffer *ring)
3682 {
3683         INIT_LIST_HEAD(&ring->active_list);
3684         INIT_LIST_HEAD(&ring->request_list);
3685         INIT_LIST_HEAD(&ring->gpu_write_list);
3686 }
3687
3688 void
3689 i915_gem_load(struct drm_device *dev)
3690 {
3691         int i;
3692         drm_i915_private_t *dev_priv = dev->dev_private;
3693
3694         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3695         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3696         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3697         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3698         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3699         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3700         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3701         init_ring_lists(&dev_priv->render_ring);
3702         init_ring_lists(&dev_priv->bsd_ring);
3703         init_ring_lists(&dev_priv->blt_ring);
3704         for (i = 0; i < 16; i++)
3705                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3706         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3707                           i915_gem_retire_work_handler);
3708         init_completion(&dev_priv->error_completion);
3709
3710         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3711         if (IS_GEN3(dev)) {
3712                 u32 tmp = I915_READ(MI_ARB_STATE);
3713                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
3714                         /* arb state is a masked write, so set bit + bit in mask */
3715                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3716                         I915_WRITE(MI_ARB_STATE, tmp);
3717                 }
3718         }
3719
3720         /* Old X drivers will take 0-2 for front, back, depth buffers */
3721         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3722                 dev_priv->fence_reg_start = 3;
3723
3724         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3725                 dev_priv->num_fence_regs = 16;
3726         else
3727                 dev_priv->num_fence_regs = 8;
3728
3729         /* Initialize fence registers to zero */
3730         switch (INTEL_INFO(dev)->gen) {
3731         case 6:
3732                 for (i = 0; i < 16; i++)
3733                         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
3734                 break;
3735         case 5:
3736         case 4:
3737                 for (i = 0; i < 16; i++)
3738                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
3739                 break;
3740         case 3:
3741                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3742                         for (i = 0; i < 8; i++)
3743                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
3744         case 2:
3745                 for (i = 0; i < 8; i++)
3746                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
3747                 break;
3748         }
3749         i915_gem_detect_bit_6_swizzle(dev);
3750         init_waitqueue_head(&dev_priv->pending_flip_queue);
3751
3752         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3753         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3754         register_shrinker(&dev_priv->mm.inactive_shrinker);
3755 }
3756
3757 /*
3758  * Create a physically contiguous memory object for this object
3759  * e.g. for cursor + overlay regs
3760  */
3761 static int i915_gem_init_phys_object(struct drm_device *dev,
3762                                      int id, int size, int align)
3763 {
3764         drm_i915_private_t *dev_priv = dev->dev_private;
3765         struct drm_i915_gem_phys_object *phys_obj;
3766         int ret;
3767
3768         if (dev_priv->mm.phys_objs[id - 1] || !size)
3769                 return 0;
3770
3771         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3772         if (!phys_obj)
3773                 return -ENOMEM;
3774
3775         phys_obj->id = id;
3776
3777         phys_obj->handle = drm_pci_alloc(dev, size, align);
3778         if (!phys_obj->handle) {
3779                 ret = -ENOMEM;
3780                 goto kfree_obj;
3781         }
3782 #ifdef CONFIG_X86
3783         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3784 #endif
3785
3786         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3787
3788         return 0;
3789 kfree_obj:
3790         kfree(phys_obj);
3791         return ret;
3792 }
3793
3794 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3795 {
3796         drm_i915_private_t *dev_priv = dev->dev_private;
3797         struct drm_i915_gem_phys_object *phys_obj;
3798
3799         if (!dev_priv->mm.phys_objs[id - 1])
3800                 return;
3801
3802         phys_obj = dev_priv->mm.phys_objs[id - 1];
3803         if (phys_obj->cur_obj) {
3804                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3805         }
3806
3807 #ifdef CONFIG_X86
3808         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3809 #endif
3810         drm_pci_free(dev, phys_obj->handle);
3811         kfree(phys_obj);
3812         dev_priv->mm.phys_objs[id - 1] = NULL;
3813 }
3814
3815 void i915_gem_free_all_phys_object(struct drm_device *dev)
3816 {
3817         int i;
3818
3819         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3820                 i915_gem_free_phys_object(dev, i);
3821 }
3822
3823 void i915_gem_detach_phys_object(struct drm_device *dev,
3824                                  struct drm_i915_gem_object *obj)
3825 {
3826         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3827         char *vaddr;
3828         int i;
3829         int page_count;
3830
3831         if (!obj->phys_obj)
3832                 return;
3833         vaddr = obj->phys_obj->handle->vaddr;
3834
3835         page_count = obj->base.size / PAGE_SIZE;
3836         for (i = 0; i < page_count; i++) {
3837                 struct page *page = read_cache_page_gfp(mapping, i,
3838                                                         GFP_HIGHUSER | __GFP_RECLAIMABLE);
3839                 if (!IS_ERR(page)) {
3840                         char *dst = kmap_atomic(page);
3841                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
3842                         kunmap_atomic(dst);
3843
3844                         drm_clflush_pages(&page, 1);
3845
3846                         set_page_dirty(page);
3847                         mark_page_accessed(page);
3848                         page_cache_release(page);
3849                 }
3850         }
3851         intel_gtt_chipset_flush();
3852
3853         obj->phys_obj->cur_obj = NULL;
3854         obj->phys_obj = NULL;
3855 }
3856
3857 int
3858 i915_gem_attach_phys_object(struct drm_device *dev,
3859                             struct drm_i915_gem_object *obj,
3860                             int id,
3861                             int align)
3862 {
3863         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3864         drm_i915_private_t *dev_priv = dev->dev_private;
3865         int ret = 0;
3866         int page_count;
3867         int i;
3868
3869         if (id > I915_MAX_PHYS_OBJECT)
3870                 return -EINVAL;
3871
3872         if (obj->phys_obj) {
3873                 if (obj->phys_obj->id == id)
3874                         return 0;
3875                 i915_gem_detach_phys_object(dev, obj);
3876         }
3877
3878         /* create a new object */
3879         if (!dev_priv->mm.phys_objs[id - 1]) {
3880                 ret = i915_gem_init_phys_object(dev, id,
3881                                                 obj->base.size, align);
3882                 if (ret) {
3883                         DRM_ERROR("failed to init phys object %d size: %zu\n",
3884                                   id, obj->base.size);
3885                         return ret;
3886                 }
3887         }
3888
3889         /* bind to the object */
3890         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3891         obj->phys_obj->cur_obj = obj;
3892
3893         page_count = obj->base.size / PAGE_SIZE;
3894
3895         for (i = 0; i < page_count; i++) {
3896                 struct page *page;
3897                 char *dst, *src;
3898
3899                 page = read_cache_page_gfp(mapping, i,
3900                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
3901                 if (IS_ERR(page))
3902                         return PTR_ERR(page);
3903
3904                 src = kmap_atomic(page);
3905                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3906                 memcpy(dst, src, PAGE_SIZE);
3907                 kunmap_atomic(src);
3908
3909                 mark_page_accessed(page);
3910                 page_cache_release(page);
3911         }
3912
3913         return 0;
3914 }
3915
3916 static int
3917 i915_gem_phys_pwrite(struct drm_device *dev,
3918                      struct drm_i915_gem_object *obj,
3919                      struct drm_i915_gem_pwrite *args,
3920                      struct drm_file *file_priv)
3921 {
3922         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
3923         char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
3924
3925         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
3926                 unsigned long unwritten;
3927
3928                 /* The physical object once assigned is fixed for the lifetime
3929                  * of the obj, so we can safely drop the lock and continue
3930                  * to access vaddr.
3931                  */
3932                 mutex_unlock(&dev->struct_mutex);
3933                 unwritten = copy_from_user(vaddr, user_data, args->size);
3934                 mutex_lock(&dev->struct_mutex);
3935                 if (unwritten)
3936                         return -EFAULT;
3937         }
3938
3939         intel_gtt_chipset_flush();
3940         return 0;
3941 }
3942
3943 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
3944 {
3945         struct drm_i915_file_private *file_priv = file->driver_priv;
3946
3947         /* Clean up our request list when the client is going away, so that
3948          * later retire_requests won't dereference our soon-to-be-gone
3949          * file_priv.
3950          */
3951         spin_lock(&file_priv->mm.lock);
3952         while (!list_empty(&file_priv->mm.request_list)) {
3953                 struct drm_i915_gem_request *request;
3954
3955                 request = list_first_entry(&file_priv->mm.request_list,
3956                                            struct drm_i915_gem_request,
3957                                            client_list);
3958                 list_del(&request->client_list);
3959                 request->file_priv = NULL;
3960         }
3961         spin_unlock(&file_priv->mm.lock);
3962 }
3963
3964 static int
3965 i915_gpu_is_active(struct drm_device *dev)
3966 {
3967         drm_i915_private_t *dev_priv = dev->dev_private;
3968         int lists_empty;
3969
3970         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
3971                       list_empty(&dev_priv->mm.active_list);
3972
3973         return !lists_empty;
3974 }
3975
3976 static int
3977 i915_gem_inactive_shrink(struct shrinker *shrinker,
3978                          int nr_to_scan,
3979                          gfp_t gfp_mask)
3980 {
3981         struct drm_i915_private *dev_priv =
3982                 container_of(shrinker,
3983                              struct drm_i915_private,
3984                              mm.inactive_shrinker);
3985         struct drm_device *dev = dev_priv->dev;
3986         struct drm_i915_gem_object *obj, *next;
3987         int cnt;
3988
3989         if (!mutex_trylock(&dev->struct_mutex))
3990                 return 0;
3991
3992         /* "fast-path" to count number of available objects */
3993         if (nr_to_scan == 0) {
3994                 cnt = 0;
3995                 list_for_each_entry(obj,
3996                                     &dev_priv->mm.inactive_list,
3997                                     mm_list)
3998                         cnt++;
3999                 mutex_unlock(&dev->struct_mutex);
4000                 return cnt / 100 * sysctl_vfs_cache_pressure;
4001         }
4002
4003 rescan:
4004         /* first scan for clean buffers */
4005         i915_gem_retire_requests(dev);
4006
4007         list_for_each_entry_safe(obj, next,
4008                                  &dev_priv->mm.inactive_list,
4009                                  mm_list) {
4010                 if (i915_gem_object_is_purgeable(obj)) {
4011                         if (i915_gem_object_unbind(obj) == 0 &&
4012                             --nr_to_scan == 0)
4013                                 break;
4014                 }
4015         }
4016
4017         /* second pass, evict/count anything still on the inactive list */
4018         cnt = 0;
4019         list_for_each_entry_safe(obj, next,
4020                                  &dev_priv->mm.inactive_list,
4021                                  mm_list) {
4022                 if (nr_to_scan &&
4023                     i915_gem_object_unbind(obj) == 0)
4024                         nr_to_scan--;
4025                 else
4026                         cnt++;
4027         }
4028
4029         if (nr_to_scan && i915_gpu_is_active(dev)) {
4030                 /*
4031                  * We are desperate for pages, so as a last resort, wait
4032                  * for the GPU to finish and discard whatever we can.
4033                  * This has a dramatic impact to reduce the number of
4034                  * OOM-killer events whilst running the GPU aggressively.
4035                  */
4036                 if (i915_gpu_idle(dev) == 0)
4037                         goto rescan;
4038         }
4039         mutex_unlock(&dev->struct_mutex);
4040         return cnt / 100 * sysctl_vfs_cache_pressure;
4041 }