drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include "drm_crtc_helper.h"
  39
  40 static int i915_modeset = -1;
  41 module_param_named(modeset, i915_modeset, int, 0400);
  42
  43 unsigned int i915_fbpercrtc = 0;
  44 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  45
  46 unsigned int i915_powersave = 1;
  47 module_param_named(powersave, i915_powersave, int, 0600);
  48
  49 unsigned int i915_lvds_downclock = 0;
  50 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  51
  52 static struct drm_driver driver;
  53 extern int intel_agp_enabled;
  54
  55 #define INTEL_VGA_DEVICE(id, info) {            \
  56         .class = PCI_CLASS_DISPLAY_VGA << 8,    \
  57         .class_mask = 0xffff00,                 \
  58         .vendor = 0x8086,                       \
  59         .device = id,                           \
  60         .subvendor = PCI_ANY_ID,                \
  61         .subdevice = PCI_ANY_ID,                \
  62         .driver_data = (unsigned long) info }
  63
  64 static const struct intel_device_info intel_i830_info = {
  65         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
  66         .has_overlay = 1, .overlay_needs_physical = 1,
  67 };
  68
  69 static const struct intel_device_info intel_845g_info = {
  70         .gen = 2,
  71         .has_overlay = 1, .overlay_needs_physical = 1,
  72 };
  73
  74 static const struct intel_device_info intel_i85x_info = {
  75         .gen = 2, .is_i85x = 1, .is_mobile = 1,
  76         .cursor_needs_physical = 1,
  77         .has_overlay = 1, .overlay_needs_physical = 1,
  78 };
  79
  80 static const struct intel_device_info intel_i865g_info = {
  81         .gen = 2,
  82         .has_overlay = 1, .overlay_needs_physical = 1,
  83 };
  84
  85 static const struct intel_device_info intel_i915g_info = {
  86         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
  87         .has_overlay = 1, .overlay_needs_physical = 1,
  88 };
  89 static const struct intel_device_info intel_i915gm_info = {
  90         .gen = 3, .is_mobile = 1,
  91         .cursor_needs_physical = 1,
  92         .has_overlay = 1, .overlay_needs_physical = 1,
  93         .supports_tv = 1,
  94 };
  95 static const struct intel_device_info intel_i945g_info = {
  96         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
  97         .has_overlay = 1, .overlay_needs_physical = 1,
  98 };
  99 static const struct intel_device_info intel_i945gm_info = {
 100         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 101         .has_hotplug = 1, .cursor_needs_physical = 1,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .supports_tv = 1,
 104 };
 105
 106 static const struct intel_device_info intel_i965g_info = {
 107         .gen = 4, .is_broadwater = 1,
 108         .has_hotplug = 1,
 109         .has_overlay = 1,
 110 };
 111
 112 static const struct intel_device_info intel_i965gm_info = {
 113         .gen = 4, .is_crestline = 1,
 114         .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
 115         .has_overlay = 1,
 116         .supports_tv = 1,
 117 };
 118
 119 static const struct intel_device_info intel_g33_info = {
 120         .gen = 3, .is_g33 = 1,
 121         .need_gfx_hws = 1, .has_hotplug = 1,
 122         .has_overlay = 1,
 123 };
 124
 125 static const struct intel_device_info intel_g45_info = {
 126         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 127         .has_pipe_cxsr = 1, .has_hotplug = 1,
 128         .has_bsd_ring = 1,
 129 };
 130
 131 static const struct intel_device_info intel_gm45_info = {
 132         .gen = 4, .is_g4x = 1,
 133         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
 134         .has_pipe_cxsr = 1, .has_hotplug = 1,
 135         .supports_tv = 1,
 136         .has_bsd_ring = 1,
 137 };
 138
 139 static const struct intel_device_info intel_pineview_info = {
 140         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 141         .need_gfx_hws = 1, .has_hotplug = 1,
 142         .has_overlay = 1,
 143 };
 144
 145 static const struct intel_device_info intel_ironlake_d_info = {
 146         .gen = 5,
 147         .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
 148         .has_bsd_ring = 1,
 149 };
 150
 151 static const struct intel_device_info intel_ironlake_m_info = {
 152         .gen = 5, .is_mobile = 1,
 153         .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
 154         .has_bsd_ring = 1,
 155 };
 156
 157 static const struct intel_device_info intel_sandybridge_d_info = {
 158         .gen = 6,
 159         .need_gfx_hws = 1, .has_hotplug = 1,
 160         .has_bsd_ring = 1,
 161         .has_blt_ring = 1,
 162 };
 163
 164 static const struct intel_device_info intel_sandybridge_m_info = {
 165         .gen = 6, .is_mobile = 1,
 166         .need_gfx_hws = 1, .has_hotplug = 1,
 167         .has_bsd_ring = 1,
 168         .has_blt_ring = 1,
 169 };
 170
 171 static const struct pci_device_id pciidlist[] = {               /* aka */
 172         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 173         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 174         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 175         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 176         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 177         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 178         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 179         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 180         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 181         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 182         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 183         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 184         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 185         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 186         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 187         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 188         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 189         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 190         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 191         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 192         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 193         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 194         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 195         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 196         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 197         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 198         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 199         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 200         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 201         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 202         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 203         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 204         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 205         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 206         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 207         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 208         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 209         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 210         {0, 0, 0}
 211 };
 212
 213 #if defined(CONFIG_DRM_I915_KMS)
 214 MODULE_DEVICE_TABLE(pci, pciidlist);
 215 #endif
 216
 217 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 218 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 219
 220 void intel_detect_pch (struct drm_device *dev)
 221 {
 222         struct drm_i915_private *dev_priv = dev->dev_private;
 223         struct pci_dev *pch;
 224
 225         /*
 226          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 227          * make graphics device passthrough work easy for VMM, that only
 228          * need to expose ISA bridge to let driver know the real hardware
 229          * underneath. This is a requirement from virtualization team.
 230          */
 231         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 232         if (pch) {
 233                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 234                         int id;
 235                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 236
 237                         if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 238                                 dev_priv->pch_type = PCH_CPT;
 239                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 240                         }
 241                 }
 242                 pci_dev_put(pch);
 243         }
 244 }
 245
 246 static int i915_drm_freeze(struct drm_device *dev)
 247 {
 248         struct drm_i915_private *dev_priv = dev->dev_private;
 249
 250         pci_save_state(dev->pdev);
 251
 252         /* If KMS is active, we do the leavevt stuff here */
 253         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 254                 int error = i915_gem_idle(dev);
 255                 if (error) {
 256                         dev_err(&dev->pdev->dev,
 257                                 "GEM idle failed, resume might fail\n");
 258                         return error;
 259                 }
 260                 drm_irq_uninstall(dev);
 261         }
 262
 263         i915_save_state(dev);
 264
 265         intel_opregion_fini(dev);
 266
 267         /* Modeset on resume, not lid events */
 268         dev_priv->modeset_on_lid = 0;
 269
 270         return 0;
 271 }
 272
 273 int i915_suspend(struct drm_device *dev, pm_message_t state)
 274 {
 275         int error;
 276
 277         if (!dev || !dev->dev_private) {
 278                 DRM_ERROR("dev: %p\n", dev);
 279                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 280                 return -ENODEV;
 281         }
 282
 283         if (state.event == PM_EVENT_PRETHAW)
 284                 return 0;
 285
 286         drm_kms_helper_poll_disable(dev);
 287
 288         error = i915_drm_freeze(dev);
 289         if (error)
 290                 return error;
 291
 292         if (state.event == PM_EVENT_SUSPEND) {
 293                 /* Shut down the device */
 294                 pci_disable_device(dev->pdev);
 295                 pci_set_power_state(dev->pdev, PCI_D3hot);
 296         }
 297
 298         return 0;
 299 }
 300
 301 static int i915_drm_thaw(struct drm_device *dev)
 302 {
 303         struct drm_i915_private *dev_priv = dev->dev_private;
 304         int error = 0;
 305
 306         i915_restore_state(dev);
 307         intel_opregion_setup(dev);
 308
 309         /* KMS EnterVT equivalent */
 310         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 311                 mutex_lock(&dev->struct_mutex);
 312                 dev_priv->mm.suspended = 0;
 313
 314                 error = i915_gem_init_ringbuffer(dev);
 315                 mutex_unlock(&dev->struct_mutex);
 316
 317                 drm_irq_install(dev);
 318
 319                 /* Resume the modeset for every activated CRTC */
 320                 drm_helper_resume_force_mode(dev);
 321         }
 322
 323         intel_opregion_init(dev);
 324
 325         dev_priv->modeset_on_lid = 0;
 326
 327         return error;
 328 }
 329
 330 int i915_resume(struct drm_device *dev)
 331 {
 332         int ret;
 333
 334         if (pci_enable_device(dev->pdev))
 335                 return -EIO;
 336
 337         pci_set_master(dev->pdev);
 338
 339         ret = i915_drm_thaw(dev);
 340         if (ret)
 341                 return ret;
 342
 343         drm_kms_helper_poll_enable(dev);
 344         return 0;
 345 }
 346
 347 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 348 {
 349         struct drm_i915_private *dev_priv = dev->dev_private;
 350
 351         if (IS_I85X(dev))
 352                 return -ENODEV;
 353
 354         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 355         POSTING_READ(D_STATE);
 356
 357         if (IS_I830(dev) || IS_845G(dev)) {
 358                 I915_WRITE(DEBUG_RESET_I830,
 359                            DEBUG_RESET_DISPLAY |
 360                            DEBUG_RESET_RENDER |
 361                            DEBUG_RESET_FULL);
 362                 POSTING_READ(DEBUG_RESET_I830);
 363                 msleep(1);
 364
 365                 I915_WRITE(DEBUG_RESET_I830, 0);
 366                 POSTING_READ(DEBUG_RESET_I830);
 367         }
 368
 369         msleep(1);
 370
 371         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 372         POSTING_READ(D_STATE);
 373
 374         return 0;
 375 }
 376
 377 static int i965_reset_complete(struct drm_device *dev)
 378 {
 379         u8 gdrst;
 380         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 381         return gdrst & 0x1;
 382 }
 383
 384 static int i965_do_reset(struct drm_device *dev, u8 flags)
 385 {
 386         u8 gdrst;
 387
 388         /*
 389          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 390          * well as the reset bit (GR/bit 0).  Setting the GR bit
 391          * triggers the reset; when done, the hardware will clear it.
 392          */
 393         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 394         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 395
 396         return wait_for(i965_reset_complete(dev), 500);
 397 }
 398
 399 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 400 {
 401         struct drm_i915_private *dev_priv = dev->dev_private;
 402         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 403         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 404         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 405 }
 406
 407 /**
 408  * i965_reset - reset chip after a hang
 409  * @dev: drm device to reset
 410  * @flags: reset domains
 411  *
 412  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 413  * reset or otherwise an error code.
 414  *
 415  * Procedure is fairly simple:
 416  *   - reset the chip using the reset reg
 417  *   - re-init context state
 418  *   - re-init hardware status page
 419  *   - re-init ring buffer
 420  *   - re-init interrupt state
 421  *   - re-init display
 422  */
 423 int i915_reset(struct drm_device *dev, u8 flags)
 424 {
 425         drm_i915_private_t *dev_priv = dev->dev_private;
 426         /*
 427          * We really should only reset the display subsystem if we actually
 428          * need to
 429          */
 430         bool need_display = true;
 431         int ret;
 432
 433         mutex_lock(&dev->struct_mutex);
 434
 435         i915_gem_reset(dev);
 436
 437         ret = -ENODEV;
 438         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 439                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 440         } else switch (INTEL_INFO(dev)->gen) {
 441         case 5:
 442                 ret = ironlake_do_reset(dev, flags);
 443                 break;
 444         case 4:
 445                 ret = i965_do_reset(dev, flags);
 446                 break;
 447         case 2:
 448                 ret = i8xx_do_reset(dev, flags);
 449                 break;
 450         }
 451         dev_priv->last_gpu_reset = get_seconds();
 452         if (ret) {
 453                 DRM_ERROR("Failed to reset chip.\n");
 454                 mutex_unlock(&dev->struct_mutex);
 455                 return ret;
 456         }
 457
 458         /* Ok, now get things going again... */
 459
 460         /*
 461          * Everything depends on having the GTT running, so we need to start
 462          * there.  Fortunately we don't need to do this unless we reset the
 463          * chip at a PCI level.
 464          *
 465          * Next we need to restore the context, but we don't use those
 466          * yet either...
 467          *
 468          * Ring buffer needs to be re-initialized in the KMS case, or if X
 469          * was running at the time of the reset (i.e. we weren't VT
 470          * switched away).
 471          */
 472         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 473                         !dev_priv->mm.suspended) {
 474                 struct intel_ring_buffer *ring = &dev_priv->render_ring;
 475                 dev_priv->mm.suspended = 0;
 476                 ring->init(ring);
 477                 mutex_unlock(&dev->struct_mutex);
 478                 drm_irq_uninstall(dev);
 479                 drm_irq_install(dev);
 480                 mutex_lock(&dev->struct_mutex);
 481         }
 482
 483         mutex_unlock(&dev->struct_mutex);
 484
 485         /*
 486          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 487          * need to retrain the display link and cannot just restore the register
 488          * values.
 489          */
 490         if (need_display) {
 491                 mutex_lock(&dev->mode_config.mutex);
 492                 drm_helper_resume_force_mode(dev);
 493                 mutex_unlock(&dev->mode_config.mutex);
 494         }
 495
 496         return 0;
 497 }
 498
 499
 500 static int __devinit
 501 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 502 {
 503         return drm_get_pci_dev(pdev, ent, &driver);
 504 }
 505
 506 static void
 507 i915_pci_remove(struct pci_dev *pdev)
 508 {
 509         struct drm_device *dev = pci_get_drvdata(pdev);
 510
 511         drm_put_dev(dev);
 512 }
 513
 514 static int i915_pm_suspend(struct device *dev)
 515 {
 516         struct pci_dev *pdev = to_pci_dev(dev);
 517         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 518         int error;
 519
 520         if (!drm_dev || !drm_dev->dev_private) {
 521                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 522                 return -ENODEV;
 523         }
 524
 525         error = i915_drm_freeze(drm_dev);
 526         if (error)
 527                 return error;
 528
 529         pci_disable_device(pdev);
 530         pci_set_power_state(pdev, PCI_D3hot);
 531
 532         return 0;
 533 }
 534
 535 static int i915_pm_resume(struct device *dev)
 536 {
 537         struct pci_dev *pdev = to_pci_dev(dev);
 538         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 539
 540         return i915_resume(drm_dev);
 541 }
 542
 543 static int i915_pm_freeze(struct device *dev)
 544 {
 545         struct pci_dev *pdev = to_pci_dev(dev);
 546         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 547
 548         if (!drm_dev || !drm_dev->dev_private) {
 549                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 550                 return -ENODEV;
 551         }
 552
 553         return i915_drm_freeze(drm_dev);
 554 }
 555
 556 static int i915_pm_thaw(struct device *dev)
 557 {
 558         struct pci_dev *pdev = to_pci_dev(dev);
 559         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 560
 561         return i915_drm_thaw(drm_dev);
 562 }
 563
 564 static int i915_pm_poweroff(struct device *dev)
 565 {
 566         struct pci_dev *pdev = to_pci_dev(dev);
 567         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 568
 569         return i915_drm_freeze(drm_dev);
 570 }
 571
 572 static const struct dev_pm_ops i915_pm_ops = {
 573      .suspend = i915_pm_suspend,
 574      .resume = i915_pm_resume,
 575      .freeze = i915_pm_freeze,
 576      .thaw = i915_pm_thaw,
 577      .poweroff = i915_pm_poweroff,
 578      .restore = i915_pm_resume,
 579 };
 580
 581 static struct vm_operations_struct i915_gem_vm_ops = {
 582         .fault = i915_gem_fault,
 583         .open = drm_gem_vm_open,
 584         .close = drm_gem_vm_close,
 585 };
 586
 587 static struct drm_driver driver = {
 588         /* don't use mtrr's here, the Xserver or user space app should
 589          * deal with them for intel hardware.
 590          */
 591         .driver_features =
 592             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 593             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 594         .load = i915_driver_load,
 595         .unload = i915_driver_unload,
 596         .open = i915_driver_open,
 597         .lastclose = i915_driver_lastclose,
 598         .preclose = i915_driver_preclose,
 599         .postclose = i915_driver_postclose,
 600
 601         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 602         .suspend = i915_suspend,
 603         .resume = i915_resume,
 604
 605         .device_is_agp = i915_driver_device_is_agp,
 606         .enable_vblank = i915_enable_vblank,
 607         .disable_vblank = i915_disable_vblank,
 608         .irq_preinstall = i915_driver_irq_preinstall,
 609         .irq_postinstall = i915_driver_irq_postinstall,
 610         .irq_uninstall = i915_driver_irq_uninstall,
 611         .irq_handler = i915_driver_irq_handler,
 612         .reclaim_buffers = drm_core_reclaim_buffers,
 613         .master_create = i915_master_create,
 614         .master_destroy = i915_master_destroy,
 615 #if defined(CONFIG_DEBUG_FS)
 616         .debugfs_init = i915_debugfs_init,
 617         .debugfs_cleanup = i915_debugfs_cleanup,
 618 #endif
 619         .gem_init_object = i915_gem_init_object,
 620         .gem_free_object = i915_gem_free_object,
 621         .gem_vm_ops = &i915_gem_vm_ops,
 622         .ioctls = i915_ioctls,
 623         .fops = {
 624                  .owner = THIS_MODULE,
 625                  .open = drm_open,
 626                  .release = drm_release,
 627                  .unlocked_ioctl = drm_ioctl,
 628                  .mmap = drm_gem_mmap,
 629                  .poll = drm_poll,
 630                  .fasync = drm_fasync,
 631                  .read = drm_read,
 632 #ifdef CONFIG_COMPAT
 633                  .compat_ioctl = i915_compat_ioctl,
 634 #endif
 635                  .llseek = noop_llseek,
 636         },
 637
 638         .pci_driver = {
 639                  .name = DRIVER_NAME,
 640                  .id_table = pciidlist,
 641                  .probe = i915_pci_probe,
 642                  .remove = i915_pci_remove,
 643                  .driver.pm = &i915_pm_ops,
 644         },
 645
 646         .name = DRIVER_NAME,
 647         .desc = DRIVER_DESC,
 648         .date = DRIVER_DATE,
 649         .major = DRIVER_MAJOR,
 650         .minor = DRIVER_MINOR,
 651         .patchlevel = DRIVER_PATCHLEVEL,
 652 };
 653
 654 static int __init i915_init(void)
 655 {
 656         if (!intel_agp_enabled) {
 657                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 658                 return -ENODEV;
 659         }
 660
 661         driver.num_ioctls = i915_max_ioctl;
 662
 663         /*
 664          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 665          * explicitly disabled with the module pararmeter.
 666          *
 667          * Otherwise, just follow the parameter (defaulting to off).
 668          *
 669          * Allow optional vga_text_mode_force boot option to override
 670          * the default behavior.
 671          */
 672 #if defined(CONFIG_DRM_I915_KMS)
 673         if (i915_modeset != 0)
 674                 driver.driver_features |= DRIVER_MODESET;
 675 #endif
 676         if (i915_modeset == 1)
 677                 driver.driver_features |= DRIVER_MODESET;
 678
 679 #ifdef CONFIG_VGA_CONSOLE
 680         if (vgacon_text_force() && i915_modeset == -1)
 681                 driver.driver_features &= ~DRIVER_MODESET;
 682 #endif
 683
 684         if (!(driver.driver_features & DRIVER_MODESET)) {
 685                 driver.suspend = i915_suspend;
 686                 driver.resume = i915_resume;
 687         }
 688
 689         return drm_init(&driver);
 690 }
 691
 692 static void __exit i915_exit(void)
 693 {
 694         drm_exit(&driver);
 695 }
 696
 697 module_init(i915_init);
 698 module_exit(i915_exit);
 699
 700 MODULE_AUTHOR(DRIVER_AUTHOR);
 701 MODULE_DESCRIPTION(DRIVER_DESC);
 702 MODULE_LICENSE("GPL and additional rights");