drm exynos: use drm_fb_helper_set_par directly
[linux-2.6.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29
30 #include <linux/device.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "intel_drv.h"
36
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include "drm_crtc_helper.h"
40
41 static int i915_modeset __read_mostly = -1;
42 module_param_named(modeset, i915_modeset, int, 0400);
43 MODULE_PARM_DESC(modeset,
44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45                 "1=on, -1=force vga console preference [default])");
46
47 unsigned int i915_fbpercrtc __always_unused = 0;
48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
49
50 int i915_panel_ignore_lid __read_mostly = 0;
51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid,
53                 "Override lid status (0=autodetect [default], 1=lid open, "
54                 "-1=lid closed)");
55
56 unsigned int i915_powersave __read_mostly = 1;
57 module_param_named(powersave, i915_powersave, int, 0600);
58 MODULE_PARM_DESC(powersave,
59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
60
61 int i915_semaphores __read_mostly = -1;
62 module_param_named(semaphores, i915_semaphores, int, 0600);
63 MODULE_PARM_DESC(semaphores,
64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
65
66 int i915_enable_rc6 __read_mostly = -1;
67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
68 MODULE_PARM_DESC(i915_enable_rc6,
69                 "Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
70
71 int i915_enable_fbc __read_mostly = -1;
72 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
73 MODULE_PARM_DESC(i915_enable_fbc,
74                 "Enable frame buffer compression for power savings "
75                 "(default: -1 (use per-chip default))");
76
77 unsigned int i915_lvds_downclock __read_mostly = 0;
78 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
79 MODULE_PARM_DESC(lvds_downclock,
80                 "Use panel (LVDS/eDP) downclocking for power savings "
81                 "(default: false)");
82
83 int i915_panel_use_ssc __read_mostly = -1;
84 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
85 MODULE_PARM_DESC(lvds_use_ssc,
86                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
87                 "(default: auto from VBT)");
88
89 int i915_vbt_sdvo_panel_type __read_mostly = -1;
90 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
91 MODULE_PARM_DESC(vbt_sdvo_panel_type,
92                 "Override selection of SDVO panel mode in the VBT "
93                 "(default: auto)");
94
95 static bool i915_try_reset __read_mostly = true;
96 module_param_named(reset, i915_try_reset, bool, 0600);
97 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
98
99 bool i915_enable_hangcheck __read_mostly = true;
100 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
101 MODULE_PARM_DESC(enable_hangcheck,
102                 "Periodically check GPU activity for detecting hangs. "
103                 "WARNING: Disabling this can cause system wide hangs. "
104                 "(default: true)");
105
106 static struct drm_driver driver;
107 extern int intel_agp_enabled;
108
109 #define INTEL_VGA_DEVICE(id, info) {            \
110         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
111         .class_mask = 0xff0000,                 \
112         .vendor = 0x8086,                       \
113         .device = id,                           \
114         .subvendor = PCI_ANY_ID,                \
115         .subdevice = PCI_ANY_ID,                \
116         .driver_data = (unsigned long) info }
117
118 static const struct intel_device_info intel_i830_info = {
119         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
120         .has_overlay = 1, .overlay_needs_physical = 1,
121 };
122
123 static const struct intel_device_info intel_845g_info = {
124         .gen = 2,
125         .has_overlay = 1, .overlay_needs_physical = 1,
126 };
127
128 static const struct intel_device_info intel_i85x_info = {
129         .gen = 2, .is_i85x = 1, .is_mobile = 1,
130         .cursor_needs_physical = 1,
131         .has_overlay = 1, .overlay_needs_physical = 1,
132 };
133
134 static const struct intel_device_info intel_i865g_info = {
135         .gen = 2,
136         .has_overlay = 1, .overlay_needs_physical = 1,
137 };
138
139 static const struct intel_device_info intel_i915g_info = {
140         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
141         .has_overlay = 1, .overlay_needs_physical = 1,
142 };
143 static const struct intel_device_info intel_i915gm_info = {
144         .gen = 3, .is_mobile = 1,
145         .cursor_needs_physical = 1,
146         .has_overlay = 1, .overlay_needs_physical = 1,
147         .supports_tv = 1,
148 };
149 static const struct intel_device_info intel_i945g_info = {
150         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
151         .has_overlay = 1, .overlay_needs_physical = 1,
152 };
153 static const struct intel_device_info intel_i945gm_info = {
154         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
155         .has_hotplug = 1, .cursor_needs_physical = 1,
156         .has_overlay = 1, .overlay_needs_physical = 1,
157         .supports_tv = 1,
158 };
159
160 static const struct intel_device_info intel_i965g_info = {
161         .gen = 4, .is_broadwater = 1,
162         .has_hotplug = 1,
163         .has_overlay = 1,
164 };
165
166 static const struct intel_device_info intel_i965gm_info = {
167         .gen = 4, .is_crestline = 1,
168         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
169         .has_overlay = 1,
170         .supports_tv = 1,
171 };
172
173 static const struct intel_device_info intel_g33_info = {
174         .gen = 3, .is_g33 = 1,
175         .need_gfx_hws = 1, .has_hotplug = 1,
176         .has_overlay = 1,
177 };
178
179 static const struct intel_device_info intel_g45_info = {
180         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
181         .has_pipe_cxsr = 1, .has_hotplug = 1,
182         .has_bsd_ring = 1,
183 };
184
185 static const struct intel_device_info intel_gm45_info = {
186         .gen = 4, .is_g4x = 1,
187         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
188         .has_pipe_cxsr = 1, .has_hotplug = 1,
189         .supports_tv = 1,
190         .has_bsd_ring = 1,
191 };
192
193 static const struct intel_device_info intel_pineview_info = {
194         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
195         .need_gfx_hws = 1, .has_hotplug = 1,
196         .has_overlay = 1,
197 };
198
199 static const struct intel_device_info intel_ironlake_d_info = {
200         .gen = 5,
201         .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
202         .has_bsd_ring = 1,
203 };
204
205 static const struct intel_device_info intel_ironlake_m_info = {
206         .gen = 5, .is_mobile = 1,
207         .need_gfx_hws = 1, .has_hotplug = 1,
208         .has_fbc = 1,
209         .has_bsd_ring = 1,
210 };
211
212 static const struct intel_device_info intel_sandybridge_d_info = {
213         .gen = 6,
214         .need_gfx_hws = 1, .has_hotplug = 1,
215         .has_bsd_ring = 1,
216         .has_blt_ring = 1,
217 };
218
219 static const struct intel_device_info intel_sandybridge_m_info = {
220         .gen = 6, .is_mobile = 1,
221         .need_gfx_hws = 1, .has_hotplug = 1,
222         .has_fbc = 1,
223         .has_bsd_ring = 1,
224         .has_blt_ring = 1,
225 };
226
227 static const struct intel_device_info intel_ivybridge_d_info = {
228         .is_ivybridge = 1, .gen = 7,
229         .need_gfx_hws = 1, .has_hotplug = 1,
230         .has_bsd_ring = 1,
231         .has_blt_ring = 1,
232 };
233
234 static const struct intel_device_info intel_ivybridge_m_info = {
235         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
236         .need_gfx_hws = 1, .has_hotplug = 1,
237         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
238         .has_bsd_ring = 1,
239         .has_blt_ring = 1,
240 };
241
242 static const struct pci_device_id pciidlist[] = {               /* aka */
243         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
244         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
245         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
246         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
247         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
248         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
249         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
250         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
251         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
252         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
253         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
254         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
255         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
256         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
257         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
258         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
259         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
260         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
261         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
262         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
263         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
264         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
265         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
266         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
267         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
268         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
269         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
270         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
271         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
272         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
273         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
274         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
275         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
276         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
277         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
278         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
279         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
280         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
281         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
282         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
283         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
284         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
285         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
286         {0, 0, 0}
287 };
288
289 #if defined(CONFIG_DRM_I915_KMS)
290 MODULE_DEVICE_TABLE(pci, pciidlist);
291 #endif
292
293 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
294 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
295 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
296 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
297
298 void intel_detect_pch(struct drm_device *dev)
299 {
300         struct drm_i915_private *dev_priv = dev->dev_private;
301         struct pci_dev *pch;
302
303         /*
304          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
305          * make graphics device passthrough work easy for VMM, that only
306          * need to expose ISA bridge to let driver know the real hardware
307          * underneath. This is a requirement from virtualization team.
308          */
309         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
310         if (pch) {
311                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
312                         int id;
313                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
314
315                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
316                                 dev_priv->pch_type = PCH_IBX;
317                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
318                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
319                                 dev_priv->pch_type = PCH_CPT;
320                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
321                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
322                                 /* PantherPoint is CPT compatible */
323                                 dev_priv->pch_type = PCH_CPT;
324                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
325                         }
326                 }
327                 pci_dev_put(pch);
328         }
329 }
330
331 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
332 {
333         int count;
334
335         count = 0;
336         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
337                 udelay(10);
338
339         I915_WRITE_NOTRACE(FORCEWAKE, 1);
340         POSTING_READ(FORCEWAKE);
341
342         count = 0;
343         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
344                 udelay(10);
345 }
346
347 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
348 {
349         int count;
350
351         count = 0;
352         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
353                 udelay(10);
354
355         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
356         POSTING_READ(FORCEWAKE_MT);
357
358         count = 0;
359         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
360                 udelay(10);
361 }
362
363 /*
364  * Generally this is called implicitly by the register read function. However,
365  * if some sequence requires the GT to not power down then this function should
366  * be called at the beginning of the sequence followed by a call to
367  * gen6_gt_force_wake_put() at the end of the sequence.
368  */
369 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
370 {
371         unsigned long irqflags;
372
373         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
374         if (dev_priv->forcewake_count++ == 0)
375                 dev_priv->display.force_wake_get(dev_priv);
376         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
377 }
378
379 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
380 {
381         I915_WRITE_NOTRACE(FORCEWAKE, 0);
382         POSTING_READ(FORCEWAKE);
383 }
384
385 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
386 {
387         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
388         POSTING_READ(FORCEWAKE_MT);
389 }
390
391 /*
392  * see gen6_gt_force_wake_get()
393  */
394 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
395 {
396         unsigned long irqflags;
397
398         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
399         if (--dev_priv->forcewake_count == 0)
400                 dev_priv->display.force_wake_put(dev_priv);
401         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
402 }
403
404 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
405 {
406         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
407                 int loop = 500;
408                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
409                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
410                         udelay(10);
411                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
412                 }
413                 WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES);
414                 dev_priv->gt_fifo_count = fifo;
415         }
416         dev_priv->gt_fifo_count--;
417 }
418
419 static int i915_drm_freeze(struct drm_device *dev)
420 {
421         struct drm_i915_private *dev_priv = dev->dev_private;
422
423         drm_kms_helper_poll_disable(dev);
424
425         pci_save_state(dev->pdev);
426
427         /* If KMS is active, we do the leavevt stuff here */
428         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
429                 int error = i915_gem_idle(dev);
430                 if (error) {
431                         dev_err(&dev->pdev->dev,
432                                 "GEM idle failed, resume might fail\n");
433                         return error;
434                 }
435                 drm_irq_uninstall(dev);
436         }
437
438         i915_save_state(dev);
439
440         intel_opregion_fini(dev);
441
442         /* Modeset on resume, not lid events */
443         dev_priv->modeset_on_lid = 0;
444
445         return 0;
446 }
447
448 int i915_suspend(struct drm_device *dev, pm_message_t state)
449 {
450         int error;
451
452         if (!dev || !dev->dev_private) {
453                 DRM_ERROR("dev: %p\n", dev);
454                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
455                 return -ENODEV;
456         }
457
458         if (state.event == PM_EVENT_PRETHAW)
459                 return 0;
460
461
462         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
463                 return 0;
464
465         error = i915_drm_freeze(dev);
466         if (error)
467                 return error;
468
469         if (state.event == PM_EVENT_SUSPEND) {
470                 /* Shut down the device */
471                 pci_disable_device(dev->pdev);
472                 pci_set_power_state(dev->pdev, PCI_D3hot);
473         }
474
475         return 0;
476 }
477
478 static int i915_drm_thaw(struct drm_device *dev)
479 {
480         struct drm_i915_private *dev_priv = dev->dev_private;
481         int error = 0;
482
483         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
484                 mutex_lock(&dev->struct_mutex);
485                 i915_gem_restore_gtt_mappings(dev);
486                 mutex_unlock(&dev->struct_mutex);
487         }
488
489         i915_restore_state(dev);
490         intel_opregion_setup(dev);
491
492         /* KMS EnterVT equivalent */
493         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
494                 mutex_lock(&dev->struct_mutex);
495                 dev_priv->mm.suspended = 0;
496
497                 error = i915_gem_init_ringbuffer(dev);
498                 mutex_unlock(&dev->struct_mutex);
499
500                 if (HAS_PCH_SPLIT(dev))
501                         ironlake_init_pch_refclk(dev);
502
503                 drm_mode_config_reset(dev);
504                 drm_irq_install(dev);
505
506                 /* Resume the modeset for every activated CRTC */
507                 drm_helper_resume_force_mode(dev);
508
509                 if (IS_IRONLAKE_M(dev))
510                         ironlake_enable_rc6(dev);
511         }
512
513         intel_opregion_init(dev);
514
515         dev_priv->modeset_on_lid = 0;
516
517         return error;
518 }
519
520 int i915_resume(struct drm_device *dev)
521 {
522         int ret;
523
524         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
525                 return 0;
526
527         if (pci_enable_device(dev->pdev))
528                 return -EIO;
529
530         pci_set_master(dev->pdev);
531
532         ret = i915_drm_thaw(dev);
533         if (ret)
534                 return ret;
535
536         drm_kms_helper_poll_enable(dev);
537         return 0;
538 }
539
540 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
541 {
542         struct drm_i915_private *dev_priv = dev->dev_private;
543
544         if (IS_I85X(dev))
545                 return -ENODEV;
546
547         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
548         POSTING_READ(D_STATE);
549
550         if (IS_I830(dev) || IS_845G(dev)) {
551                 I915_WRITE(DEBUG_RESET_I830,
552                            DEBUG_RESET_DISPLAY |
553                            DEBUG_RESET_RENDER |
554                            DEBUG_RESET_FULL);
555                 POSTING_READ(DEBUG_RESET_I830);
556                 msleep(1);
557
558                 I915_WRITE(DEBUG_RESET_I830, 0);
559                 POSTING_READ(DEBUG_RESET_I830);
560         }
561
562         msleep(1);
563
564         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
565         POSTING_READ(D_STATE);
566
567         return 0;
568 }
569
570 static int i965_reset_complete(struct drm_device *dev)
571 {
572         u8 gdrst;
573         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
574         return gdrst & 0x1;
575 }
576
577 static int i965_do_reset(struct drm_device *dev, u8 flags)
578 {
579         u8 gdrst;
580
581         /*
582          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
583          * well as the reset bit (GR/bit 0).  Setting the GR bit
584          * triggers the reset; when done, the hardware will clear it.
585          */
586         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
587         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
588
589         return wait_for(i965_reset_complete(dev), 500);
590 }
591
592 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
593 {
594         struct drm_i915_private *dev_priv = dev->dev_private;
595         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
596         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
597         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
598 }
599
600 static int gen6_do_reset(struct drm_device *dev, u8 flags)
601 {
602         struct drm_i915_private *dev_priv = dev->dev_private;
603         int     ret;
604         unsigned long irqflags;
605
606         /* Hold gt_lock across reset to prevent any register access
607          * with forcewake not set correctly
608          */
609         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
610
611         /* Reset the chip */
612
613         /* GEN6_GDRST is not in the gt power well, no need to check
614          * for fifo space for the write or forcewake the chip for
615          * the read
616          */
617         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
618
619         /* Spin waiting for the device to ack the reset request */
620         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
621
622         /* If reset with a user forcewake, try to restore, otherwise turn it off */
623         if (dev_priv->forcewake_count)
624                 dev_priv->display.force_wake_get(dev_priv);
625         else
626                 dev_priv->display.force_wake_put(dev_priv);
627
628         /* Restore fifo count */
629         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
630
631         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
632         return ret;
633 }
634
635 /**
636  * i965_reset - reset chip after a hang
637  * @dev: drm device to reset
638  * @flags: reset domains
639  *
640  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
641  * reset or otherwise an error code.
642  *
643  * Procedure is fairly simple:
644  *   - reset the chip using the reset reg
645  *   - re-init context state
646  *   - re-init hardware status page
647  *   - re-init ring buffer
648  *   - re-init interrupt state
649  *   - re-init display
650  */
651 int i915_reset(struct drm_device *dev, u8 flags)
652 {
653         drm_i915_private_t *dev_priv = dev->dev_private;
654         /*
655          * We really should only reset the display subsystem if we actually
656          * need to
657          */
658         bool need_display = true;
659         int ret;
660
661         if (!i915_try_reset)
662                 return 0;
663
664         if (!mutex_trylock(&dev->struct_mutex))
665                 return -EBUSY;
666
667         i915_gem_reset(dev);
668
669         ret = -ENODEV;
670         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
671                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
672         } else switch (INTEL_INFO(dev)->gen) {
673         case 7:
674         case 6:
675                 ret = gen6_do_reset(dev, flags);
676                 break;
677         case 5:
678                 ret = ironlake_do_reset(dev, flags);
679                 break;
680         case 4:
681                 ret = i965_do_reset(dev, flags);
682                 break;
683         case 2:
684                 ret = i8xx_do_reset(dev, flags);
685                 break;
686         }
687         dev_priv->last_gpu_reset = get_seconds();
688         if (ret) {
689                 DRM_ERROR("Failed to reset chip.\n");
690                 mutex_unlock(&dev->struct_mutex);
691                 return ret;
692         }
693
694         /* Ok, now get things going again... */
695
696         /*
697          * Everything depends on having the GTT running, so we need to start
698          * there.  Fortunately we don't need to do this unless we reset the
699          * chip at a PCI level.
700          *
701          * Next we need to restore the context, but we don't use those
702          * yet either...
703          *
704          * Ring buffer needs to be re-initialized in the KMS case, or if X
705          * was running at the time of the reset (i.e. we weren't VT
706          * switched away).
707          */
708         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
709                         !dev_priv->mm.suspended) {
710                 dev_priv->mm.suspended = 0;
711
712                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
713                 if (HAS_BSD(dev))
714                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
715                 if (HAS_BLT(dev))
716                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
717
718                 mutex_unlock(&dev->struct_mutex);
719                 drm_irq_uninstall(dev);
720                 drm_mode_config_reset(dev);
721                 drm_irq_install(dev);
722                 mutex_lock(&dev->struct_mutex);
723         }
724
725         mutex_unlock(&dev->struct_mutex);
726
727         /*
728          * Perform a full modeset as on later generations, e.g. Ironlake, we may
729          * need to retrain the display link and cannot just restore the register
730          * values.
731          */
732         if (need_display) {
733                 mutex_lock(&dev->mode_config.mutex);
734                 drm_helper_resume_force_mode(dev);
735                 mutex_unlock(&dev->mode_config.mutex);
736         }
737
738         return 0;
739 }
740
741
742 static int __devinit
743 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
744 {
745         /* Only bind to function 0 of the device. Early generations
746          * used function 1 as a placeholder for multi-head. This causes
747          * us confusion instead, especially on the systems where both
748          * functions have the same PCI-ID!
749          */
750         if (PCI_FUNC(pdev->devfn))
751                 return -ENODEV;
752
753         return drm_get_pci_dev(pdev, ent, &driver);
754 }
755
756 static void
757 i915_pci_remove(struct pci_dev *pdev)
758 {
759         struct drm_device *dev = pci_get_drvdata(pdev);
760
761         drm_put_dev(dev);
762 }
763
764 static int i915_pm_suspend(struct device *dev)
765 {
766         struct pci_dev *pdev = to_pci_dev(dev);
767         struct drm_device *drm_dev = pci_get_drvdata(pdev);
768         int error;
769
770         if (!drm_dev || !drm_dev->dev_private) {
771                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
772                 return -ENODEV;
773         }
774
775         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
776                 return 0;
777
778         error = i915_drm_freeze(drm_dev);
779         if (error)
780                 return error;
781
782         pci_disable_device(pdev);
783         pci_set_power_state(pdev, PCI_D3hot);
784
785         return 0;
786 }
787
788 static int i915_pm_resume(struct device *dev)
789 {
790         struct pci_dev *pdev = to_pci_dev(dev);
791         struct drm_device *drm_dev = pci_get_drvdata(pdev);
792
793         return i915_resume(drm_dev);
794 }
795
796 static int i915_pm_freeze(struct device *dev)
797 {
798         struct pci_dev *pdev = to_pci_dev(dev);
799         struct drm_device *drm_dev = pci_get_drvdata(pdev);
800
801         if (!drm_dev || !drm_dev->dev_private) {
802                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
803                 return -ENODEV;
804         }
805
806         return i915_drm_freeze(drm_dev);
807 }
808
809 static int i915_pm_thaw(struct device *dev)
810 {
811         struct pci_dev *pdev = to_pci_dev(dev);
812         struct drm_device *drm_dev = pci_get_drvdata(pdev);
813
814         return i915_drm_thaw(drm_dev);
815 }
816
817 static int i915_pm_poweroff(struct device *dev)
818 {
819         struct pci_dev *pdev = to_pci_dev(dev);
820         struct drm_device *drm_dev = pci_get_drvdata(pdev);
821
822         return i915_drm_freeze(drm_dev);
823 }
824
825 static const struct dev_pm_ops i915_pm_ops = {
826         .suspend = i915_pm_suspend,
827         .resume = i915_pm_resume,
828         .freeze = i915_pm_freeze,
829         .thaw = i915_pm_thaw,
830         .poweroff = i915_pm_poweroff,
831         .restore = i915_pm_resume,
832 };
833
834 static struct vm_operations_struct i915_gem_vm_ops = {
835         .fault = i915_gem_fault,
836         .open = drm_gem_vm_open,
837         .close = drm_gem_vm_close,
838 };
839
840 static const struct file_operations i915_driver_fops = {
841         .owner = THIS_MODULE,
842         .open = drm_open,
843         .release = drm_release,
844         .unlocked_ioctl = drm_ioctl,
845         .mmap = drm_gem_mmap,
846         .poll = drm_poll,
847         .fasync = drm_fasync,
848         .read = drm_read,
849 #ifdef CONFIG_COMPAT
850         .compat_ioctl = i915_compat_ioctl,
851 #endif
852         .llseek = noop_llseek,
853 };
854
855 static struct drm_driver driver = {
856         /* Don't use MTRRs here; the Xserver or userspace app should
857          * deal with them for Intel hardware.
858          */
859         .driver_features =
860             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
861             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
862         .load = i915_driver_load,
863         .unload = i915_driver_unload,
864         .open = i915_driver_open,
865         .lastclose = i915_driver_lastclose,
866         .preclose = i915_driver_preclose,
867         .postclose = i915_driver_postclose,
868
869         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
870         .suspend = i915_suspend,
871         .resume = i915_resume,
872
873         .device_is_agp = i915_driver_device_is_agp,
874         .reclaim_buffers = drm_core_reclaim_buffers,
875         .master_create = i915_master_create,
876         .master_destroy = i915_master_destroy,
877 #if defined(CONFIG_DEBUG_FS)
878         .debugfs_init = i915_debugfs_init,
879         .debugfs_cleanup = i915_debugfs_cleanup,
880 #endif
881         .gem_init_object = i915_gem_init_object,
882         .gem_free_object = i915_gem_free_object,
883         .gem_vm_ops = &i915_gem_vm_ops,
884         .dumb_create = i915_gem_dumb_create,
885         .dumb_map_offset = i915_gem_mmap_gtt,
886         .dumb_destroy = i915_gem_dumb_destroy,
887         .ioctls = i915_ioctls,
888         .fops = &i915_driver_fops,
889         .name = DRIVER_NAME,
890         .desc = DRIVER_DESC,
891         .date = DRIVER_DATE,
892         .major = DRIVER_MAJOR,
893         .minor = DRIVER_MINOR,
894         .patchlevel = DRIVER_PATCHLEVEL,
895 };
896
897 static struct pci_driver i915_pci_driver = {
898         .name = DRIVER_NAME,
899         .id_table = pciidlist,
900         .probe = i915_pci_probe,
901         .remove = i915_pci_remove,
902         .driver.pm = &i915_pm_ops,
903 };
904
905 static int __init i915_init(void)
906 {
907         if (!intel_agp_enabled) {
908                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
909                 return -ENODEV;
910         }
911
912         driver.num_ioctls = i915_max_ioctl;
913
914         /*
915          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
916          * explicitly disabled with the module pararmeter.
917          *
918          * Otherwise, just follow the parameter (defaulting to off).
919          *
920          * Allow optional vga_text_mode_force boot option to override
921          * the default behavior.
922          */
923 #if defined(CONFIG_DRM_I915_KMS)
924         if (i915_modeset != 0)
925                 driver.driver_features |= DRIVER_MODESET;
926 #endif
927         if (i915_modeset == 1)
928                 driver.driver_features |= DRIVER_MODESET;
929
930 #ifdef CONFIG_VGA_CONSOLE
931         if (vgacon_text_force() && i915_modeset == -1)
932                 driver.driver_features &= ~DRIVER_MODESET;
933 #endif
934
935         if (!(driver.driver_features & DRIVER_MODESET))
936                 driver.get_vblank_timestamp = NULL;
937
938         return drm_pci_init(&driver, &i915_pci_driver);
939 }
940
941 static void __exit i915_exit(void)
942 {
943         drm_pci_exit(&driver, &i915_pci_driver);
944 }
945
946 module_init(i915_init);
947 module_exit(i915_exit);
948
949 MODULE_AUTHOR(DRIVER_AUTHOR);
950 MODULE_DESCRIPTION(DRIVER_DESC);
951 MODULE_LICENSE("GPL and additional rights");
952
953 #define __i915_read(x, y) \
954 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
955         u##x val = 0; \
956         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
957                 unsigned long irqflags; \
958                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
959                 if (dev_priv->forcewake_count == 0) \
960                         dev_priv->display.force_wake_get(dev_priv); \
961                 val = read##y(dev_priv->regs + reg); \
962                 if (dev_priv->forcewake_count == 0) \
963                         dev_priv->display.force_wake_put(dev_priv); \
964                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
965         } else { \
966                 val = read##y(dev_priv->regs + reg); \
967         } \
968         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
969         return val; \
970 }
971
972 __i915_read(8, b)
973 __i915_read(16, w)
974 __i915_read(32, l)
975 __i915_read(64, q)
976 #undef __i915_read
977
978 #define __i915_write(x, y) \
979 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
980         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
981         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
982                 __gen6_gt_wait_for_fifo(dev_priv); \
983         } \
984         write##y(val, dev_priv->regs + reg); \
985 }
986 __i915_write(8, b)
987 __i915_write(16, w)
988 __i915_write(32, l)
989 __i915_write(64, q)
990 #undef __i915_write