dmaengine: kill struct dma_client and supporting infrastructure
[linux-2.6.git] / drivers / dma / iop-adma.c
1 /*
2  * offload engine driver for the Intel Xscale series of i/o processors
3  * Copyright © 2006, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17  *
18  */
19
20 /*
21  * This driver supports the asynchrounous DMA copy and RAID engines available
22  * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
23  */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/spinlock.h>
30 #include <linux/interrupt.h>
31 #include <linux/platform_device.h>
32 #include <linux/memory.h>
33 #include <linux/ioport.h>
34
35 #include <mach/adma.h>
36
37 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
38 #define to_iop_adma_device(dev) \
39         container_of(dev, struct iop_adma_device, common)
40 #define tx_to_iop_adma_slot(tx) \
41         container_of(tx, struct iop_adma_desc_slot, async_tx)
42
43 /**
44  * iop_adma_free_slots - flags descriptor slots for reuse
45  * @slot: Slot to free
46  * Caller must hold &iop_chan->lock while calling this function
47  */
48 static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
49 {
50         int stride = slot->slots_per_op;
51
52         while (stride--) {
53                 slot->slots_per_op = 0;
54                 slot = list_entry(slot->slot_node.next,
55                                 struct iop_adma_desc_slot,
56                                 slot_node);
57         }
58 }
59
60 static dma_cookie_t
61 iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
62         struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
63 {
64         BUG_ON(desc->async_tx.cookie < 0);
65         if (desc->async_tx.cookie > 0) {
66                 cookie = desc->async_tx.cookie;
67                 desc->async_tx.cookie = 0;
68
69                 /* call the callback (must not sleep or submit new
70                  * operations to this channel)
71                  */
72                 if (desc->async_tx.callback)
73                         desc->async_tx.callback(
74                                 desc->async_tx.callback_param);
75
76                 /* unmap dma addresses
77                  * (unmap_single vs unmap_page?)
78                  */
79                 if (desc->group_head && desc->unmap_len) {
80                         struct iop_adma_desc_slot *unmap = desc->group_head;
81                         struct device *dev =
82                                 &iop_chan->device->pdev->dev;
83                         u32 len = unmap->unmap_len;
84                         enum dma_ctrl_flags flags = desc->async_tx.flags;
85                         u32 src_cnt;
86                         dma_addr_t addr;
87                         dma_addr_t dest;
88
89                         src_cnt = unmap->unmap_src_cnt;
90                         dest = iop_desc_get_dest_addr(unmap, iop_chan);
91                         if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
92                                 enum dma_data_direction dir;
93
94                                 if (src_cnt > 1) /* is xor? */
95                                         dir = DMA_BIDIRECTIONAL;
96                                 else
97                                         dir = DMA_FROM_DEVICE;
98
99                                 dma_unmap_page(dev, dest, len, dir);
100                         }
101
102                         if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
103                                 while (src_cnt--) {
104                                         addr = iop_desc_get_src_addr(unmap,
105                                                                      iop_chan,
106                                                                      src_cnt);
107                                         if (addr == dest)
108                                                 continue;
109                                         dma_unmap_page(dev, addr, len,
110                                                        DMA_TO_DEVICE);
111                                 }
112                         }
113                         desc->group_head = NULL;
114                 }
115         }
116
117         /* run dependent operations */
118         dma_run_dependencies(&desc->async_tx);
119
120         return cookie;
121 }
122
123 static int
124 iop_adma_clean_slot(struct iop_adma_desc_slot *desc,
125         struct iop_adma_chan *iop_chan)
126 {
127         /* the client is allowed to attach dependent operations
128          * until 'ack' is set
129          */
130         if (!async_tx_test_ack(&desc->async_tx))
131                 return 0;
132
133         /* leave the last descriptor in the chain
134          * so we can append to it
135          */
136         if (desc->chain_node.next == &iop_chan->chain)
137                 return 1;
138
139         dev_dbg(iop_chan->device->common.dev,
140                 "\tfree slot: %d slots_per_op: %d\n",
141                 desc->idx, desc->slots_per_op);
142
143         list_del(&desc->chain_node);
144         iop_adma_free_slots(desc);
145
146         return 0;
147 }
148
149 static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
150 {
151         struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL;
152         dma_cookie_t cookie = 0;
153         u32 current_desc = iop_chan_get_current_descriptor(iop_chan);
154         int busy = iop_chan_is_busy(iop_chan);
155         int seen_current = 0, slot_cnt = 0, slots_per_op = 0;
156
157         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
158         /* free completed slots from the chain starting with
159          * the oldest descriptor
160          */
161         list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
162                                         chain_node) {
163                 pr_debug("\tcookie: %d slot: %d busy: %d "
164                         "this_desc: %#x next_desc: %#x ack: %d\n",
165                         iter->async_tx.cookie, iter->idx, busy,
166                         iter->async_tx.phys, iop_desc_get_next_desc(iter),
167                         async_tx_test_ack(&iter->async_tx));
168                 prefetch(_iter);
169                 prefetch(&_iter->async_tx);
170
171                 /* do not advance past the current descriptor loaded into the
172                  * hardware channel, subsequent descriptors are either in
173                  * process or have not been submitted
174                  */
175                 if (seen_current)
176                         break;
177
178                 /* stop the search if we reach the current descriptor and the
179                  * channel is busy, or if it appears that the current descriptor
180                  * needs to be re-read (i.e. has been appended to)
181                  */
182                 if (iter->async_tx.phys == current_desc) {
183                         BUG_ON(seen_current++);
184                         if (busy || iop_desc_get_next_desc(iter))
185                                 break;
186                 }
187
188                 /* detect the start of a group transaction */
189                 if (!slot_cnt && !slots_per_op) {
190                         slot_cnt = iter->slot_cnt;
191                         slots_per_op = iter->slots_per_op;
192                         if (slot_cnt <= slots_per_op) {
193                                 slot_cnt = 0;
194                                 slots_per_op = 0;
195                         }
196                 }
197
198                 if (slot_cnt) {
199                         pr_debug("\tgroup++\n");
200                         if (!grp_start)
201                                 grp_start = iter;
202                         slot_cnt -= slots_per_op;
203                 }
204
205                 /* all the members of a group are complete */
206                 if (slots_per_op != 0 && slot_cnt == 0) {
207                         struct iop_adma_desc_slot *grp_iter, *_grp_iter;
208                         int end_of_chain = 0;
209                         pr_debug("\tgroup end\n");
210
211                         /* collect the total results */
212                         if (grp_start->xor_check_result) {
213                                 u32 zero_sum_result = 0;
214                                 slot_cnt = grp_start->slot_cnt;
215                                 grp_iter = grp_start;
216
217                                 list_for_each_entry_from(grp_iter,
218                                         &iop_chan->chain, chain_node) {
219                                         zero_sum_result |=
220                                             iop_desc_get_zero_result(grp_iter);
221                                             pr_debug("\titer%d result: %d\n",
222                                             grp_iter->idx, zero_sum_result);
223                                         slot_cnt -= slots_per_op;
224                                         if (slot_cnt == 0)
225                                                 break;
226                                 }
227                                 pr_debug("\tgrp_start->xor_check_result: %p\n",
228                                         grp_start->xor_check_result);
229                                 *grp_start->xor_check_result = zero_sum_result;
230                         }
231
232                         /* clean up the group */
233                         slot_cnt = grp_start->slot_cnt;
234                         grp_iter = grp_start;
235                         list_for_each_entry_safe_from(grp_iter, _grp_iter,
236                                 &iop_chan->chain, chain_node) {
237                                 cookie = iop_adma_run_tx_complete_actions(
238                                         grp_iter, iop_chan, cookie);
239
240                                 slot_cnt -= slots_per_op;
241                                 end_of_chain = iop_adma_clean_slot(grp_iter,
242                                         iop_chan);
243
244                                 if (slot_cnt == 0 || end_of_chain)
245                                         break;
246                         }
247
248                         /* the group should be complete at this point */
249                         BUG_ON(slot_cnt);
250
251                         slots_per_op = 0;
252                         grp_start = NULL;
253                         if (end_of_chain)
254                                 break;
255                         else
256                                 continue;
257                 } else if (slots_per_op) /* wait for group completion */
258                         continue;
259
260                 /* write back zero sum results (single descriptor case) */
261                 if (iter->xor_check_result && iter->async_tx.cookie)
262                         *iter->xor_check_result =
263                                 iop_desc_get_zero_result(iter);
264
265                 cookie = iop_adma_run_tx_complete_actions(
266                                         iter, iop_chan, cookie);
267
268                 if (iop_adma_clean_slot(iter, iop_chan))
269                         break;
270         }
271
272         BUG_ON(!seen_current);
273
274         if (cookie > 0) {
275                 iop_chan->completed_cookie = cookie;
276                 pr_debug("\tcompleted cookie %d\n", cookie);
277         }
278 }
279
280 static void
281 iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
282 {
283         spin_lock_bh(&iop_chan->lock);
284         __iop_adma_slot_cleanup(iop_chan);
285         spin_unlock_bh(&iop_chan->lock);
286 }
287
288 static void iop_adma_tasklet(unsigned long data)
289 {
290         struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data;
291
292         spin_lock(&iop_chan->lock);
293         __iop_adma_slot_cleanup(iop_chan);
294         spin_unlock(&iop_chan->lock);
295 }
296
297 static struct iop_adma_desc_slot *
298 iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
299                         int slots_per_op)
300 {
301         struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL;
302         LIST_HEAD(chain);
303         int slots_found, retry = 0;
304
305         /* start search from the last allocated descrtiptor
306          * if a contiguous allocation can not be found start searching
307          * from the beginning of the list
308          */
309 retry:
310         slots_found = 0;
311         if (retry == 0)
312                 iter = iop_chan->last_used;
313         else
314                 iter = list_entry(&iop_chan->all_slots,
315                         struct iop_adma_desc_slot,
316                         slot_node);
317
318         list_for_each_entry_safe_continue(
319                 iter, _iter, &iop_chan->all_slots, slot_node) {
320                 prefetch(_iter);
321                 prefetch(&_iter->async_tx);
322                 if (iter->slots_per_op) {
323                         /* give up after finding the first busy slot
324                          * on the second pass through the list
325                          */
326                         if (retry)
327                                 break;
328
329                         slots_found = 0;
330                         continue;
331                 }
332
333                 /* start the allocation if the slot is correctly aligned */
334                 if (!slots_found++) {
335                         if (iop_desc_is_aligned(iter, slots_per_op))
336                                 alloc_start = iter;
337                         else {
338                                 slots_found = 0;
339                                 continue;
340                         }
341                 }
342
343                 if (slots_found == num_slots) {
344                         struct iop_adma_desc_slot *alloc_tail = NULL;
345                         struct iop_adma_desc_slot *last_used = NULL;
346                         iter = alloc_start;
347                         while (num_slots) {
348                                 int i;
349                                 dev_dbg(iop_chan->device->common.dev,
350                                         "allocated slot: %d "
351                                         "(desc %p phys: %#x) slots_per_op %d\n",
352                                         iter->idx, iter->hw_desc,
353                                         iter->async_tx.phys, slots_per_op);
354
355                                 /* pre-ack all but the last descriptor */
356                                 if (num_slots != slots_per_op)
357                                         async_tx_ack(&iter->async_tx);
358
359                                 list_add_tail(&iter->chain_node, &chain);
360                                 alloc_tail = iter;
361                                 iter->async_tx.cookie = 0;
362                                 iter->slot_cnt = num_slots;
363                                 iter->xor_check_result = NULL;
364                                 for (i = 0; i < slots_per_op; i++) {
365                                         iter->slots_per_op = slots_per_op - i;
366                                         last_used = iter;
367                                         iter = list_entry(iter->slot_node.next,
368                                                 struct iop_adma_desc_slot,
369                                                 slot_node);
370                                 }
371                                 num_slots -= slots_per_op;
372                         }
373                         alloc_tail->group_head = alloc_start;
374                         alloc_tail->async_tx.cookie = -EBUSY;
375                         list_splice(&chain, &alloc_tail->async_tx.tx_list);
376                         iop_chan->last_used = last_used;
377                         iop_desc_clear_next_desc(alloc_start);
378                         iop_desc_clear_next_desc(alloc_tail);
379                         return alloc_tail;
380                 }
381         }
382         if (!retry++)
383                 goto retry;
384
385         /* perform direct reclaim if the allocation fails */
386         __iop_adma_slot_cleanup(iop_chan);
387
388         return NULL;
389 }
390
391 static dma_cookie_t
392 iop_desc_assign_cookie(struct iop_adma_chan *iop_chan,
393         struct iop_adma_desc_slot *desc)
394 {
395         dma_cookie_t cookie = iop_chan->common.cookie;
396         cookie++;
397         if (cookie < 0)
398                 cookie = 1;
399         iop_chan->common.cookie = desc->async_tx.cookie = cookie;
400         return cookie;
401 }
402
403 static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
404 {
405         dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
406                 iop_chan->pending);
407
408         if (iop_chan->pending >= IOP_ADMA_THRESHOLD) {
409                 iop_chan->pending = 0;
410                 iop_chan_append(iop_chan);
411         }
412 }
413
414 static dma_cookie_t
415 iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
416 {
417         struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx);
418         struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
419         struct iop_adma_desc_slot *grp_start, *old_chain_tail;
420         int slot_cnt;
421         int slots_per_op;
422         dma_cookie_t cookie;
423         dma_addr_t next_dma;
424
425         grp_start = sw_desc->group_head;
426         slot_cnt = grp_start->slot_cnt;
427         slots_per_op = grp_start->slots_per_op;
428
429         spin_lock_bh(&iop_chan->lock);
430         cookie = iop_desc_assign_cookie(iop_chan, sw_desc);
431
432         old_chain_tail = list_entry(iop_chan->chain.prev,
433                 struct iop_adma_desc_slot, chain_node);
434         list_splice_init(&sw_desc->async_tx.tx_list,
435                          &old_chain_tail->chain_node);
436
437         /* fix up the hardware chain */
438         next_dma = grp_start->async_tx.phys;
439         iop_desc_set_next_desc(old_chain_tail, next_dma);
440         BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */
441
442         /* check for pre-chained descriptors */
443         iop_paranoia(iop_desc_get_next_desc(sw_desc));
444
445         /* increment the pending count by the number of slots
446          * memcpy operations have a 1:1 (slot:operation) relation
447          * other operations are heavier and will pop the threshold
448          * more often.
449          */
450         iop_chan->pending += slot_cnt;
451         iop_adma_check_threshold(iop_chan);
452         spin_unlock_bh(&iop_chan->lock);
453
454         dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n",
455                 __func__, sw_desc->async_tx.cookie, sw_desc->idx);
456
457         return cookie;
458 }
459
460 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan);
461 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan);
462
463 /**
464  * iop_adma_alloc_chan_resources -  returns the number of allocated descriptors
465  * @chan - allocate descriptor resources for this channel
466  * @client - current client requesting the channel be ready for requests
467  *
468  * Note: We keep the slots for 1 operation on iop_chan->chain at all times.  To
469  * avoid deadlock, via async_xor, num_descs_in_pool must at a minimum be
470  * greater than 2x the number slots needed to satisfy a device->max_xor
471  * request.
472  * */
473 static int iop_adma_alloc_chan_resources(struct dma_chan *chan)
474 {
475         char *hw_desc;
476         int idx;
477         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
478         struct iop_adma_desc_slot *slot = NULL;
479         int init = iop_chan->slots_allocated ? 0 : 1;
480         struct iop_adma_platform_data *plat_data =
481                 iop_chan->device->pdev->dev.platform_data;
482         int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE;
483
484         /* Allocate descriptor slots */
485         do {
486                 idx = iop_chan->slots_allocated;
487                 if (idx == num_descs_in_pool)
488                         break;
489
490                 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
491                 if (!slot) {
492                         printk(KERN_INFO "IOP ADMA Channel only initialized"
493                                 " %d descriptor slots", idx);
494                         break;
495                 }
496                 hw_desc = (char *) iop_chan->device->dma_desc_pool_virt;
497                 slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
498
499                 dma_async_tx_descriptor_init(&slot->async_tx, chan);
500                 slot->async_tx.tx_submit = iop_adma_tx_submit;
501                 INIT_LIST_HEAD(&slot->chain_node);
502                 INIT_LIST_HEAD(&slot->slot_node);
503                 INIT_LIST_HEAD(&slot->async_tx.tx_list);
504                 hw_desc = (char *) iop_chan->device->dma_desc_pool;
505                 slot->async_tx.phys =
506                         (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
507                 slot->idx = idx;
508
509                 spin_lock_bh(&iop_chan->lock);
510                 iop_chan->slots_allocated++;
511                 list_add_tail(&slot->slot_node, &iop_chan->all_slots);
512                 spin_unlock_bh(&iop_chan->lock);
513         } while (iop_chan->slots_allocated < num_descs_in_pool);
514
515         if (idx && !iop_chan->last_used)
516                 iop_chan->last_used = list_entry(iop_chan->all_slots.next,
517                                         struct iop_adma_desc_slot,
518                                         slot_node);
519
520         dev_dbg(iop_chan->device->common.dev,
521                 "allocated %d descriptor slots last_used: %p\n",
522                 iop_chan->slots_allocated, iop_chan->last_used);
523
524         /* initialize the channel and the chain with a null operation */
525         if (init) {
526                 if (dma_has_cap(DMA_MEMCPY,
527                         iop_chan->device->common.cap_mask))
528                         iop_chan_start_null_memcpy(iop_chan);
529                 else if (dma_has_cap(DMA_XOR,
530                         iop_chan->device->common.cap_mask))
531                         iop_chan_start_null_xor(iop_chan);
532                 else
533                         BUG();
534         }
535
536         return (idx > 0) ? idx : -ENOMEM;
537 }
538
539 static struct dma_async_tx_descriptor *
540 iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
541 {
542         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
543         struct iop_adma_desc_slot *sw_desc, *grp_start;
544         int slot_cnt, slots_per_op;
545
546         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
547
548         spin_lock_bh(&iop_chan->lock);
549         slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan);
550         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
551         if (sw_desc) {
552                 grp_start = sw_desc->group_head;
553                 iop_desc_init_interrupt(grp_start, iop_chan);
554                 grp_start->unmap_len = 0;
555                 sw_desc->async_tx.flags = flags;
556         }
557         spin_unlock_bh(&iop_chan->lock);
558
559         return sw_desc ? &sw_desc->async_tx : NULL;
560 }
561
562 static struct dma_async_tx_descriptor *
563 iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
564                          dma_addr_t dma_src, size_t len, unsigned long flags)
565 {
566         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
567         struct iop_adma_desc_slot *sw_desc, *grp_start;
568         int slot_cnt, slots_per_op;
569
570         if (unlikely(!len))
571                 return NULL;
572         BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
573
574         dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
575                 __func__, len);
576
577         spin_lock_bh(&iop_chan->lock);
578         slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op);
579         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
580         if (sw_desc) {
581                 grp_start = sw_desc->group_head;
582                 iop_desc_init_memcpy(grp_start, flags);
583                 iop_desc_set_byte_count(grp_start, iop_chan, len);
584                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
585                 iop_desc_set_memcpy_src_addr(grp_start, dma_src);
586                 sw_desc->unmap_src_cnt = 1;
587                 sw_desc->unmap_len = len;
588                 sw_desc->async_tx.flags = flags;
589         }
590         spin_unlock_bh(&iop_chan->lock);
591
592         return sw_desc ? &sw_desc->async_tx : NULL;
593 }
594
595 static struct dma_async_tx_descriptor *
596 iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest,
597                          int value, size_t len, unsigned long flags)
598 {
599         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
600         struct iop_adma_desc_slot *sw_desc, *grp_start;
601         int slot_cnt, slots_per_op;
602
603         if (unlikely(!len))
604                 return NULL;
605         BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
606
607         dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
608                 __func__, len);
609
610         spin_lock_bh(&iop_chan->lock);
611         slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op);
612         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
613         if (sw_desc) {
614                 grp_start = sw_desc->group_head;
615                 iop_desc_init_memset(grp_start, flags);
616                 iop_desc_set_byte_count(grp_start, iop_chan, len);
617                 iop_desc_set_block_fill_val(grp_start, value);
618                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
619                 sw_desc->unmap_src_cnt = 1;
620                 sw_desc->unmap_len = len;
621                 sw_desc->async_tx.flags = flags;
622         }
623         spin_unlock_bh(&iop_chan->lock);
624
625         return sw_desc ? &sw_desc->async_tx : NULL;
626 }
627
628 static struct dma_async_tx_descriptor *
629 iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest,
630                       dma_addr_t *dma_src, unsigned int src_cnt, size_t len,
631                       unsigned long flags)
632 {
633         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
634         struct iop_adma_desc_slot *sw_desc, *grp_start;
635         int slot_cnt, slots_per_op;
636
637         if (unlikely(!len))
638                 return NULL;
639         BUG_ON(unlikely(len > IOP_ADMA_XOR_MAX_BYTE_COUNT));
640
641         dev_dbg(iop_chan->device->common.dev,
642                 "%s src_cnt: %d len: %u flags: %lx\n",
643                 __func__, src_cnt, len, flags);
644
645         spin_lock_bh(&iop_chan->lock);
646         slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op);
647         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
648         if (sw_desc) {
649                 grp_start = sw_desc->group_head;
650                 iop_desc_init_xor(grp_start, src_cnt, flags);
651                 iop_desc_set_byte_count(grp_start, iop_chan, len);
652                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
653                 sw_desc->unmap_src_cnt = src_cnt;
654                 sw_desc->unmap_len = len;
655                 sw_desc->async_tx.flags = flags;
656                 while (src_cnt--)
657                         iop_desc_set_xor_src_addr(grp_start, src_cnt,
658                                                   dma_src[src_cnt]);
659         }
660         spin_unlock_bh(&iop_chan->lock);
661
662         return sw_desc ? &sw_desc->async_tx : NULL;
663 }
664
665 static struct dma_async_tx_descriptor *
666 iop_adma_prep_dma_zero_sum(struct dma_chan *chan, dma_addr_t *dma_src,
667                            unsigned int src_cnt, size_t len, u32 *result,
668                            unsigned long flags)
669 {
670         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
671         struct iop_adma_desc_slot *sw_desc, *grp_start;
672         int slot_cnt, slots_per_op;
673
674         if (unlikely(!len))
675                 return NULL;
676
677         dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
678                 __func__, src_cnt, len);
679
680         spin_lock_bh(&iop_chan->lock);
681         slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op);
682         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
683         if (sw_desc) {
684                 grp_start = sw_desc->group_head;
685                 iop_desc_init_zero_sum(grp_start, src_cnt, flags);
686                 iop_desc_set_zero_sum_byte_count(grp_start, len);
687                 grp_start->xor_check_result = result;
688                 pr_debug("\t%s: grp_start->xor_check_result: %p\n",
689                         __func__, grp_start->xor_check_result);
690                 sw_desc->unmap_src_cnt = src_cnt;
691                 sw_desc->unmap_len = len;
692                 sw_desc->async_tx.flags = flags;
693                 while (src_cnt--)
694                         iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
695                                                        dma_src[src_cnt]);
696         }
697         spin_unlock_bh(&iop_chan->lock);
698
699         return sw_desc ? &sw_desc->async_tx : NULL;
700 }
701
702 static void iop_adma_free_chan_resources(struct dma_chan *chan)
703 {
704         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
705         struct iop_adma_desc_slot *iter, *_iter;
706         int in_use_descs = 0;
707
708         iop_adma_slot_cleanup(iop_chan);
709
710         spin_lock_bh(&iop_chan->lock);
711         list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
712                                         chain_node) {
713                 in_use_descs++;
714                 list_del(&iter->chain_node);
715         }
716         list_for_each_entry_safe_reverse(
717                 iter, _iter, &iop_chan->all_slots, slot_node) {
718                 list_del(&iter->slot_node);
719                 kfree(iter);
720                 iop_chan->slots_allocated--;
721         }
722         iop_chan->last_used = NULL;
723
724         dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n",
725                 __func__, iop_chan->slots_allocated);
726         spin_unlock_bh(&iop_chan->lock);
727
728         /* one is ok since we left it on there on purpose */
729         if (in_use_descs > 1)
730                 printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n",
731                         in_use_descs - 1);
732 }
733
734 /**
735  * iop_adma_is_complete - poll the status of an ADMA transaction
736  * @chan: ADMA channel handle
737  * @cookie: ADMA transaction identifier
738  */
739 static enum dma_status iop_adma_is_complete(struct dma_chan *chan,
740                                         dma_cookie_t cookie,
741                                         dma_cookie_t *done,
742                                         dma_cookie_t *used)
743 {
744         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
745         dma_cookie_t last_used;
746         dma_cookie_t last_complete;
747         enum dma_status ret;
748
749         last_used = chan->cookie;
750         last_complete = iop_chan->completed_cookie;
751
752         if (done)
753                 *done = last_complete;
754         if (used)
755                 *used = last_used;
756
757         ret = dma_async_is_complete(cookie, last_complete, last_used);
758         if (ret == DMA_SUCCESS)
759                 return ret;
760
761         iop_adma_slot_cleanup(iop_chan);
762
763         last_used = chan->cookie;
764         last_complete = iop_chan->completed_cookie;
765
766         if (done)
767                 *done = last_complete;
768         if (used)
769                 *used = last_used;
770
771         return dma_async_is_complete(cookie, last_complete, last_used);
772 }
773
774 static irqreturn_t iop_adma_eot_handler(int irq, void *data)
775 {
776         struct iop_adma_chan *chan = data;
777
778         dev_dbg(chan->device->common.dev, "%s\n", __func__);
779
780         tasklet_schedule(&chan->irq_tasklet);
781
782         iop_adma_device_clear_eot_status(chan);
783
784         return IRQ_HANDLED;
785 }
786
787 static irqreturn_t iop_adma_eoc_handler(int irq, void *data)
788 {
789         struct iop_adma_chan *chan = data;
790
791         dev_dbg(chan->device->common.dev, "%s\n", __func__);
792
793         tasklet_schedule(&chan->irq_tasklet);
794
795         iop_adma_device_clear_eoc_status(chan);
796
797         return IRQ_HANDLED;
798 }
799
800 static irqreturn_t iop_adma_err_handler(int irq, void *data)
801 {
802         struct iop_adma_chan *chan = data;
803         unsigned long status = iop_chan_get_status(chan);
804
805         dev_printk(KERN_ERR, chan->device->common.dev,
806                 "error ( %s%s%s%s%s%s%s)\n",
807                 iop_is_err_int_parity(status, chan) ? "int_parity " : "",
808                 iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "",
809                 iop_is_err_int_tabort(status, chan) ? "int_tabort " : "",
810                 iop_is_err_int_mabort(status, chan) ? "int_mabort " : "",
811                 iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "",
812                 iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "",
813                 iop_is_err_split_tx(status, chan) ? "split_tx " : "");
814
815         iop_adma_device_clear_err_status(chan);
816
817         BUG();
818
819         return IRQ_HANDLED;
820 }
821
822 static void iop_adma_issue_pending(struct dma_chan *chan)
823 {
824         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
825
826         if (iop_chan->pending) {
827                 iop_chan->pending = 0;
828                 iop_chan_append(iop_chan);
829         }
830 }
831
832 /*
833  * Perform a transaction to verify the HW works.
834  */
835 #define IOP_ADMA_TEST_SIZE 2000
836
837 static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device)
838 {
839         int i;
840         void *src, *dest;
841         dma_addr_t src_dma, dest_dma;
842         struct dma_chan *dma_chan;
843         dma_cookie_t cookie;
844         struct dma_async_tx_descriptor *tx;
845         int err = 0;
846         struct iop_adma_chan *iop_chan;
847
848         dev_dbg(device->common.dev, "%s\n", __func__);
849
850         src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
851         if (!src)
852                 return -ENOMEM;
853         dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
854         if (!dest) {
855                 kfree(src);
856                 return -ENOMEM;
857         }
858
859         /* Fill in src buffer */
860         for (i = 0; i < IOP_ADMA_TEST_SIZE; i++)
861                 ((u8 *) src)[i] = (u8)i;
862
863         /* Start copy, using first DMA channel */
864         dma_chan = container_of(device->common.channels.next,
865                                 struct dma_chan,
866                                 device_node);
867         if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
868                 err = -ENODEV;
869                 goto out;
870         }
871
872         dest_dma = dma_map_single(dma_chan->device->dev, dest,
873                                 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
874         src_dma = dma_map_single(dma_chan->device->dev, src,
875                                 IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
876         tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
877                                       IOP_ADMA_TEST_SIZE,
878                                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
879
880         cookie = iop_adma_tx_submit(tx);
881         iop_adma_issue_pending(dma_chan);
882         msleep(1);
883
884         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
885                         DMA_SUCCESS) {
886                 dev_printk(KERN_ERR, dma_chan->device->dev,
887                         "Self-test copy timed out, disabling\n");
888                 err = -ENODEV;
889                 goto free_resources;
890         }
891
892         iop_chan = to_iop_adma_chan(dma_chan);
893         dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
894                 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
895         if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) {
896                 dev_printk(KERN_ERR, dma_chan->device->dev,
897                         "Self-test copy failed compare, disabling\n");
898                 err = -ENODEV;
899                 goto free_resources;
900         }
901
902 free_resources:
903         iop_adma_free_chan_resources(dma_chan);
904 out:
905         kfree(src);
906         kfree(dest);
907         return err;
908 }
909
910 #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
911 static int __devinit
912 iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device)
913 {
914         int i, src_idx;
915         struct page *dest;
916         struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST];
917         struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
918         dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
919         dma_addr_t dma_addr, dest_dma;
920         struct dma_async_tx_descriptor *tx;
921         struct dma_chan *dma_chan;
922         dma_cookie_t cookie;
923         u8 cmp_byte = 0;
924         u32 cmp_word;
925         u32 zero_sum_result;
926         int err = 0;
927         struct iop_adma_chan *iop_chan;
928
929         dev_dbg(device->common.dev, "%s\n", __func__);
930
931         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
932                 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
933                 if (!xor_srcs[src_idx])
934                         while (src_idx--) {
935                                 __free_page(xor_srcs[src_idx]);
936                                 return -ENOMEM;
937                         }
938         }
939
940         dest = alloc_page(GFP_KERNEL);
941         if (!dest)
942                 while (src_idx--) {
943                         __free_page(xor_srcs[src_idx]);
944                         return -ENOMEM;
945                 }
946
947         /* Fill in src buffers */
948         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
949                 u8 *ptr = page_address(xor_srcs[src_idx]);
950                 for (i = 0; i < PAGE_SIZE; i++)
951                         ptr[i] = (1 << src_idx);
952         }
953
954         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++)
955                 cmp_byte ^= (u8) (1 << src_idx);
956
957         cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
958                         (cmp_byte << 8) | cmp_byte;
959
960         memset(page_address(dest), 0, PAGE_SIZE);
961
962         dma_chan = container_of(device->common.channels.next,
963                                 struct dma_chan,
964                                 device_node);
965         if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
966                 err = -ENODEV;
967                 goto out;
968         }
969
970         /* test xor */
971         dest_dma = dma_map_page(dma_chan->device->dev, dest, 0,
972                                 PAGE_SIZE, DMA_FROM_DEVICE);
973         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
974                 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
975                                            0, PAGE_SIZE, DMA_TO_DEVICE);
976         tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
977                                    IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE,
978                                    DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
979
980         cookie = iop_adma_tx_submit(tx);
981         iop_adma_issue_pending(dma_chan);
982         msleep(8);
983
984         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
985                 DMA_SUCCESS) {
986                 dev_printk(KERN_ERR, dma_chan->device->dev,
987                         "Self-test xor timed out, disabling\n");
988                 err = -ENODEV;
989                 goto free_resources;
990         }
991
992         iop_chan = to_iop_adma_chan(dma_chan);
993         dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
994                 PAGE_SIZE, DMA_FROM_DEVICE);
995         for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
996                 u32 *ptr = page_address(dest);
997                 if (ptr[i] != cmp_word) {
998                         dev_printk(KERN_ERR, dma_chan->device->dev,
999                                 "Self-test xor failed compare, disabling\n");
1000                         err = -ENODEV;
1001                         goto free_resources;
1002                 }
1003         }
1004         dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma,
1005                 PAGE_SIZE, DMA_TO_DEVICE);
1006
1007         /* skip zero sum if the capability is not present */
1008         if (!dma_has_cap(DMA_ZERO_SUM, dma_chan->device->cap_mask))
1009                 goto free_resources;
1010
1011         /* zero sum the sources with the destintation page */
1012         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1013                 zero_sum_srcs[i] = xor_srcs[i];
1014         zero_sum_srcs[i] = dest;
1015
1016         zero_sum_result = 1;
1017
1018         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1019                 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1020                                            zero_sum_srcs[i], 0, PAGE_SIZE,
1021                                            DMA_TO_DEVICE);
1022         tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
1023                                         IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1024                                         &zero_sum_result,
1025                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1026
1027         cookie = iop_adma_tx_submit(tx);
1028         iop_adma_issue_pending(dma_chan);
1029         msleep(8);
1030
1031         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1032                 dev_printk(KERN_ERR, dma_chan->device->dev,
1033                         "Self-test zero sum timed out, disabling\n");
1034                 err = -ENODEV;
1035                 goto free_resources;
1036         }
1037
1038         if (zero_sum_result != 0) {
1039                 dev_printk(KERN_ERR, dma_chan->device->dev,
1040                         "Self-test zero sum failed compare, disabling\n");
1041                 err = -ENODEV;
1042                 goto free_resources;
1043         }
1044
1045         /* test memset */
1046         dma_addr = dma_map_page(dma_chan->device->dev, dest, 0,
1047                         PAGE_SIZE, DMA_FROM_DEVICE);
1048         tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
1049                                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1050
1051         cookie = iop_adma_tx_submit(tx);
1052         iop_adma_issue_pending(dma_chan);
1053         msleep(8);
1054
1055         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1056                 dev_printk(KERN_ERR, dma_chan->device->dev,
1057                         "Self-test memset timed out, disabling\n");
1058                 err = -ENODEV;
1059                 goto free_resources;
1060         }
1061
1062         for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1063                 u32 *ptr = page_address(dest);
1064                 if (ptr[i]) {
1065                         dev_printk(KERN_ERR, dma_chan->device->dev,
1066                                 "Self-test memset failed compare, disabling\n");
1067                         err = -ENODEV;
1068                         goto free_resources;
1069                 }
1070         }
1071
1072         /* test for non-zero parity sum */
1073         zero_sum_result = 0;
1074         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1075                 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1076                                            zero_sum_srcs[i], 0, PAGE_SIZE,
1077                                            DMA_TO_DEVICE);
1078         tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
1079                                         IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1080                                         &zero_sum_result,
1081                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1082
1083         cookie = iop_adma_tx_submit(tx);
1084         iop_adma_issue_pending(dma_chan);
1085         msleep(8);
1086
1087         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1088                 dev_printk(KERN_ERR, dma_chan->device->dev,
1089                         "Self-test non-zero sum timed out, disabling\n");
1090                 err = -ENODEV;
1091                 goto free_resources;
1092         }
1093
1094         if (zero_sum_result != 1) {
1095                 dev_printk(KERN_ERR, dma_chan->device->dev,
1096                         "Self-test non-zero sum failed compare, disabling\n");
1097                 err = -ENODEV;
1098                 goto free_resources;
1099         }
1100
1101 free_resources:
1102         iop_adma_free_chan_resources(dma_chan);
1103 out:
1104         src_idx = IOP_ADMA_NUM_SRC_TEST;
1105         while (src_idx--)
1106                 __free_page(xor_srcs[src_idx]);
1107         __free_page(dest);
1108         return err;
1109 }
1110
1111 static int __devexit iop_adma_remove(struct platform_device *dev)
1112 {
1113         struct iop_adma_device *device = platform_get_drvdata(dev);
1114         struct dma_chan *chan, *_chan;
1115         struct iop_adma_chan *iop_chan;
1116         int i;
1117         struct iop_adma_platform_data *plat_data = dev->dev.platform_data;
1118
1119         dma_async_device_unregister(&device->common);
1120
1121         for (i = 0; i < 3; i++) {
1122                 unsigned int irq;
1123                 irq = platform_get_irq(dev, i);
1124                 free_irq(irq, device);
1125         }
1126
1127         dma_free_coherent(&dev->dev, plat_data->pool_size,
1128                         device->dma_desc_pool_virt, device->dma_desc_pool);
1129
1130         do {
1131                 struct resource *res;
1132                 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1133                 release_mem_region(res->start, res->end - res->start);
1134         } while (0);
1135
1136         list_for_each_entry_safe(chan, _chan, &device->common.channels,
1137                                 device_node) {
1138                 iop_chan = to_iop_adma_chan(chan);
1139                 list_del(&chan->device_node);
1140                 kfree(iop_chan);
1141         }
1142         kfree(device);
1143
1144         return 0;
1145 }
1146
1147 static int __devinit iop_adma_probe(struct platform_device *pdev)
1148 {
1149         struct resource *res;
1150         int ret = 0, i;
1151         struct iop_adma_device *adev;
1152         struct iop_adma_chan *iop_chan;
1153         struct dma_device *dma_dev;
1154         struct iop_adma_platform_data *plat_data = pdev->dev.platform_data;
1155
1156         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1157         if (!res)
1158                 return -ENODEV;
1159
1160         if (!devm_request_mem_region(&pdev->dev, res->start,
1161                                 res->end - res->start, pdev->name))
1162                 return -EBUSY;
1163
1164         adev = kzalloc(sizeof(*adev), GFP_KERNEL);
1165         if (!adev)
1166                 return -ENOMEM;
1167         dma_dev = &adev->common;
1168
1169         /* allocate coherent memory for hardware descriptors
1170          * note: writecombine gives slightly better performance, but
1171          * requires that we explicitly flush the writes
1172          */
1173         if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1174                                         plat_data->pool_size,
1175                                         &adev->dma_desc_pool,
1176                                         GFP_KERNEL)) == NULL) {
1177                 ret = -ENOMEM;
1178                 goto err_free_adev;
1179         }
1180
1181         dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p\n",
1182                 __func__, adev->dma_desc_pool_virt,
1183                 (void *) adev->dma_desc_pool);
1184
1185         adev->id = plat_data->hw_id;
1186
1187         /* discover transaction capabilites from the platform data */
1188         dma_dev->cap_mask = plat_data->cap_mask;
1189
1190         adev->pdev = pdev;
1191         platform_set_drvdata(pdev, adev);
1192
1193         INIT_LIST_HEAD(&dma_dev->channels);
1194
1195         /* set base routines */
1196         dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1197         dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
1198         dma_dev->device_is_tx_complete = iop_adma_is_complete;
1199         dma_dev->device_issue_pending = iop_adma_issue_pending;
1200         dma_dev->dev = &pdev->dev;
1201
1202         /* set prep routines based on capability */
1203         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1204                 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1205         if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1206                 dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset;
1207         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1208                 dma_dev->max_xor = iop_adma_get_max_xor();
1209                 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1210         }
1211         if (dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask))
1212                 dma_dev->device_prep_dma_zero_sum =
1213                         iop_adma_prep_dma_zero_sum;
1214         if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1215                 dma_dev->device_prep_dma_interrupt =
1216                         iop_adma_prep_dma_interrupt;
1217
1218         iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL);
1219         if (!iop_chan) {
1220                 ret = -ENOMEM;
1221                 goto err_free_dma;
1222         }
1223         iop_chan->device = adev;
1224
1225         iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start,
1226                                         res->end - res->start);
1227         if (!iop_chan->mmr_base) {
1228                 ret = -ENOMEM;
1229                 goto err_free_iop_chan;
1230         }
1231         tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long)
1232                 iop_chan);
1233
1234         /* clear errors before enabling interrupts */
1235         iop_adma_device_clear_err_status(iop_chan);
1236
1237         for (i = 0; i < 3; i++) {
1238                 irq_handler_t handler[] = { iop_adma_eot_handler,
1239                                         iop_adma_eoc_handler,
1240                                         iop_adma_err_handler };
1241                 int irq = platform_get_irq(pdev, i);
1242                 if (irq < 0) {
1243                         ret = -ENXIO;
1244                         goto err_free_iop_chan;
1245                 } else {
1246                         ret = devm_request_irq(&pdev->dev, irq,
1247                                         handler[i], 0, pdev->name, iop_chan);
1248                         if (ret)
1249                                 goto err_free_iop_chan;
1250                 }
1251         }
1252
1253         spin_lock_init(&iop_chan->lock);
1254         INIT_LIST_HEAD(&iop_chan->chain);
1255         INIT_LIST_HEAD(&iop_chan->all_slots);
1256         INIT_RCU_HEAD(&iop_chan->common.rcu);
1257         iop_chan->common.device = dma_dev;
1258         list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1259
1260         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1261                 ret = iop_adma_memcpy_self_test(adev);
1262                 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1263                 if (ret)
1264                         goto err_free_iop_chan;
1265         }
1266
1267         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) ||
1268                 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1269                 ret = iop_adma_xor_zero_sum_self_test(adev);
1270                 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1271                 if (ret)
1272                         goto err_free_iop_chan;
1273         }
1274
1275         dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: "
1276           "( %s%s%s%s%s%s%s%s%s%s)\n",
1277           dma_has_cap(DMA_PQ_XOR, dma_dev->cap_mask) ? "pq_xor " : "",
1278           dma_has_cap(DMA_PQ_UPDATE, dma_dev->cap_mask) ? "pq_update " : "",
1279           dma_has_cap(DMA_PQ_ZERO_SUM, dma_dev->cap_mask) ? "pq_zero_sum " : "",
1280           dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1281           dma_has_cap(DMA_DUAL_XOR, dma_dev->cap_mask) ? "dual_xor " : "",
1282           dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask) ? "xor_zero_sum " : "",
1283           dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)  ? "fill " : "",
1284           dma_has_cap(DMA_MEMCPY_CRC32C, dma_dev->cap_mask) ? "cpy+crc " : "",
1285           dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1286           dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1287
1288         dma_async_device_register(dma_dev);
1289         goto out;
1290
1291  err_free_iop_chan:
1292         kfree(iop_chan);
1293  err_free_dma:
1294         dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1295                         adev->dma_desc_pool_virt, adev->dma_desc_pool);
1296  err_free_adev:
1297         kfree(adev);
1298  out:
1299         return ret;
1300 }
1301
1302 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
1303 {
1304         struct iop_adma_desc_slot *sw_desc, *grp_start;
1305         dma_cookie_t cookie;
1306         int slot_cnt, slots_per_op;
1307
1308         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1309
1310         spin_lock_bh(&iop_chan->lock);
1311         slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op);
1312         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1313         if (sw_desc) {
1314                 grp_start = sw_desc->group_head;
1315
1316                 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1317                 async_tx_ack(&sw_desc->async_tx);
1318                 iop_desc_init_memcpy(grp_start, 0);
1319                 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1320                 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1321                 iop_desc_set_memcpy_src_addr(grp_start, 0);
1322
1323                 cookie = iop_chan->common.cookie;
1324                 cookie++;
1325                 if (cookie <= 1)
1326                         cookie = 2;
1327
1328                 /* initialize the completed cookie to be less than
1329                  * the most recently used cookie
1330                  */
1331                 iop_chan->completed_cookie = cookie - 1;
1332                 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1333
1334                 /* channel should not be busy */
1335                 BUG_ON(iop_chan_is_busy(iop_chan));
1336
1337                 /* clear any prior error-status bits */
1338                 iop_adma_device_clear_err_status(iop_chan);
1339
1340                 /* disable operation */
1341                 iop_chan_disable(iop_chan);
1342
1343                 /* set the descriptor address */
1344                 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1345
1346                 /* 1/ don't add pre-chained descriptors
1347                  * 2/ dummy read to flush next_desc write
1348                  */
1349                 BUG_ON(iop_desc_get_next_desc(sw_desc));
1350
1351                 /* run the descriptor */
1352                 iop_chan_enable(iop_chan);
1353         } else
1354                 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1355                          "failed to allocate null descriptor\n");
1356         spin_unlock_bh(&iop_chan->lock);
1357 }
1358
1359 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
1360 {
1361         struct iop_adma_desc_slot *sw_desc, *grp_start;
1362         dma_cookie_t cookie;
1363         int slot_cnt, slots_per_op;
1364
1365         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1366
1367         spin_lock_bh(&iop_chan->lock);
1368         slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op);
1369         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1370         if (sw_desc) {
1371                 grp_start = sw_desc->group_head;
1372                 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1373                 async_tx_ack(&sw_desc->async_tx);
1374                 iop_desc_init_null_xor(grp_start, 2, 0);
1375                 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1376                 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1377                 iop_desc_set_xor_src_addr(grp_start, 0, 0);
1378                 iop_desc_set_xor_src_addr(grp_start, 1, 0);
1379
1380                 cookie = iop_chan->common.cookie;
1381                 cookie++;
1382                 if (cookie <= 1)
1383                         cookie = 2;
1384
1385                 /* initialize the completed cookie to be less than
1386                  * the most recently used cookie
1387                  */
1388                 iop_chan->completed_cookie = cookie - 1;
1389                 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1390
1391                 /* channel should not be busy */
1392                 BUG_ON(iop_chan_is_busy(iop_chan));
1393
1394                 /* clear any prior error-status bits */
1395                 iop_adma_device_clear_err_status(iop_chan);
1396
1397                 /* disable operation */
1398                 iop_chan_disable(iop_chan);
1399
1400                 /* set the descriptor address */
1401                 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1402
1403                 /* 1/ don't add pre-chained descriptors
1404                  * 2/ dummy read to flush next_desc write
1405                  */
1406                 BUG_ON(iop_desc_get_next_desc(sw_desc));
1407
1408                 /* run the descriptor */
1409                 iop_chan_enable(iop_chan);
1410         } else
1411                 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1412                         "failed to allocate null descriptor\n");
1413         spin_unlock_bh(&iop_chan->lock);
1414 }
1415
1416 MODULE_ALIAS("platform:iop-adma");
1417
1418 static struct platform_driver iop_adma_driver = {
1419         .probe          = iop_adma_probe,
1420         .remove         = iop_adma_remove,
1421         .driver         = {
1422                 .owner  = THIS_MODULE,
1423                 .name   = "iop-adma",
1424         },
1425 };
1426
1427 static int __init iop_adma_init (void)
1428 {
1429         return platform_driver_register(&iop_adma_driver);
1430 }
1431
1432 /* it's currently unsafe to unload this module */
1433 #if 0
1434 static void __exit iop_adma_exit (void)
1435 {
1436         platform_driver_unregister(&iop_adma_driver);
1437         return;
1438 }
1439 module_exit(iop_adma_exit);
1440 #endif
1441
1442 module_init(iop_adma_init);
1443
1444 MODULE_AUTHOR("Intel Corporation");
1445 MODULE_DESCRIPTION("IOP ADMA Engine Driver");
1446 MODULE_LICENSE("GPL");