Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[linux-2.6.git] / drivers / dma / fsldma.c
1 /*
2  * Freescale MPC85xx, MPC83xx DMA Engine support
3  *
4  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
5  *
6  * Author:
7  *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8  *   Ebony Zhu <ebony.zhu@freescale.com>, May 2007
9  *
10  * Description:
11  *   DMA engine driver for Freescale MPC8540 DMA controller, which is
12  *   also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
13  *   The support for MPC8349 DMA contorller is also added.
14  *
15  * This is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License as published by
17  * the Free Software Foundation; either version 2 of the License, or
18  * (at your option) any later version.
19  *
20  */
21
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/interrupt.h>
26 #include <linux/dmaengine.h>
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/dmapool.h>
30 #include <linux/of_platform.h>
31
32 #include "fsldma.h"
33
34 static void dma_init(struct fsl_dma_chan *fsl_chan)
35 {
36         /* Reset the channel */
37         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32);
38
39         switch (fsl_chan->feature & FSL_DMA_IP_MASK) {
40         case FSL_DMA_IP_85XX:
41                 /* Set the channel to below modes:
42                  * EIE - Error interrupt enable
43                  * EOSIE - End of segments interrupt enable (basic mode)
44                  * EOLNIE - End of links interrupt enable
45                  */
46                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE
47                                 | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
48                 break;
49         case FSL_DMA_IP_83XX:
50                 /* Set the channel to below modes:
51                  * EOTIE - End-of-transfer interrupt enable
52                  */
53                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE,
54                                 32);
55                 break;
56         }
57
58 }
59
60 static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val)
61 {
62         DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32);
63 }
64
65 static u32 get_sr(struct fsl_dma_chan *fsl_chan)
66 {
67         return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32);
68 }
69
70 static void set_desc_cnt(struct fsl_dma_chan *fsl_chan,
71                                 struct fsl_dma_ld_hw *hw, u32 count)
72 {
73         hw->count = CPU_TO_DMA(fsl_chan, count, 32);
74 }
75
76 static void set_desc_src(struct fsl_dma_chan *fsl_chan,
77                                 struct fsl_dma_ld_hw *hw, dma_addr_t src)
78 {
79         u64 snoop_bits;
80
81         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
82                 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
83         hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64);
84 }
85
86 static void set_desc_dest(struct fsl_dma_chan *fsl_chan,
87                                 struct fsl_dma_ld_hw *hw, dma_addr_t dest)
88 {
89         u64 snoop_bits;
90
91         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
92                 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
93         hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64);
94 }
95
96 static void set_desc_next(struct fsl_dma_chan *fsl_chan,
97                                 struct fsl_dma_ld_hw *hw, dma_addr_t next)
98 {
99         u64 snoop_bits;
100
101         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
102                 ? FSL_DMA_SNEN : 0;
103         hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64);
104 }
105
106 static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
107 {
108         DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64);
109 }
110
111 static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan)
112 {
113         return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN;
114 }
115
116 static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
117 {
118         DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64);
119 }
120
121 static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan)
122 {
123         return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64);
124 }
125
126 static u32 get_bcr(struct fsl_dma_chan *fsl_chan)
127 {
128         return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32);
129 }
130
131 static int dma_is_idle(struct fsl_dma_chan *fsl_chan)
132 {
133         u32 sr = get_sr(fsl_chan);
134         return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
135 }
136
137 static void dma_start(struct fsl_dma_chan *fsl_chan)
138 {
139         u32 mr_set = 0;;
140
141         if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
142                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32);
143                 mr_set |= FSL_DMA_MR_EMP_EN;
144         } else
145                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
146                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
147                                 & ~FSL_DMA_MR_EMP_EN, 32);
148
149         if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT)
150                 mr_set |= FSL_DMA_MR_EMS_EN;
151         else
152                 mr_set |= FSL_DMA_MR_CS;
153
154         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
155                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
156                         | mr_set, 32);
157 }
158
159 static void dma_halt(struct fsl_dma_chan *fsl_chan)
160 {
161         int i;
162
163         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
164                 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA,
165                 32);
166         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
167                 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS
168                 | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32);
169
170         for (i = 0; i < 100; i++) {
171                 if (dma_is_idle(fsl_chan))
172                         break;
173                 udelay(10);
174         }
175         if (i >= 100 && !dma_is_idle(fsl_chan))
176                 dev_err(fsl_chan->dev, "DMA halt timeout!\n");
177 }
178
179 static void set_ld_eol(struct fsl_dma_chan *fsl_chan,
180                         struct fsl_desc_sw *desc)
181 {
182         u64 snoop_bits;
183
184         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
185                 ? FSL_DMA_SNEN : 0;
186
187         desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
188                 DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
189                         | snoop_bits, 64);
190 }
191
192 static void append_ld_queue(struct fsl_dma_chan *fsl_chan,
193                 struct fsl_desc_sw *new_desc)
194 {
195         struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev);
196
197         if (list_empty(&fsl_chan->ld_queue))
198                 return;
199
200         /* Link to the new descriptor physical address and
201          * Enable End-of-segment interrupt for
202          * the last link descriptor.
203          * (the previous node's next link descriptor)
204          *
205          * For FSL_DMA_IP_83xx, the snoop enable bit need be set.
206          */
207         queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
208                         new_desc->async_tx.phys | FSL_DMA_EOSIE |
209                         (((fsl_chan->feature & FSL_DMA_IP_MASK)
210                                 == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64);
211 }
212
213 /**
214  * fsl_chan_set_src_loop_size - Set source address hold transfer size
215  * @fsl_chan : Freescale DMA channel
216  * @size     : Address loop size, 0 for disable loop
217  *
218  * The set source address hold transfer size. The source
219  * address hold or loop transfer size is when the DMA transfer
220  * data from source address (SA), if the loop size is 4, the DMA will
221  * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
222  * SA + 1 ... and so on.
223  */
224 static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size)
225 {
226         switch (size) {
227         case 0:
228                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
229                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
230                         (~FSL_DMA_MR_SAHE), 32);
231                 break;
232         case 1:
233         case 2:
234         case 4:
235         case 8:
236                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
237                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
238                         FSL_DMA_MR_SAHE | (__ilog2(size) << 14),
239                         32);
240                 break;
241         }
242 }
243
244 /**
245  * fsl_chan_set_dest_loop_size - Set destination address hold transfer size
246  * @fsl_chan : Freescale DMA channel
247  * @size     : Address loop size, 0 for disable loop
248  *
249  * The set destination address hold transfer size. The destination
250  * address hold or loop transfer size is when the DMA transfer
251  * data to destination address (TA), if the loop size is 4, the DMA will
252  * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
253  * TA + 1 ... and so on.
254  */
255 static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size)
256 {
257         switch (size) {
258         case 0:
259                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
260                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
261                         (~FSL_DMA_MR_DAHE), 32);
262                 break;
263         case 1:
264         case 2:
265         case 4:
266         case 8:
267                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
268                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
269                         FSL_DMA_MR_DAHE | (__ilog2(size) << 16),
270                         32);
271                 break;
272         }
273 }
274
275 /**
276  * fsl_chan_toggle_ext_pause - Toggle channel external pause status
277  * @fsl_chan : Freescale DMA channel
278  * @size     : Pause control size, 0 for disable external pause control.
279  *             The maximum is 1024.
280  *
281  * The Freescale DMA channel can be controlled by the external
282  * signal DREQ#. The pause control size is how many bytes are allowed
283  * to transfer before pausing the channel, after which a new assertion
284  * of DREQ# resumes channel operation.
285  */
286 static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int size)
287 {
288         if (size > 1024)
289                 return;
290
291         if (size) {
292                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
293                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
294                                 | ((__ilog2(size) << 24) & 0x0f000000),
295                         32);
296                 fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
297         } else
298                 fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
299 }
300
301 /**
302  * fsl_chan_toggle_ext_start - Toggle channel external start status
303  * @fsl_chan : Freescale DMA channel
304  * @enable   : 0 is disabled, 1 is enabled.
305  *
306  * If enable the external start, the channel can be started by an
307  * external DMA start pin. So the dma_start() does not start the
308  * transfer immediately. The DMA channel will wait for the
309  * control pin asserted.
310  */
311 static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable)
312 {
313         if (enable)
314                 fsl_chan->feature |= FSL_DMA_CHAN_START_EXT;
315         else
316                 fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT;
317 }
318
319 static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
320 {
321         struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan);
322         struct fsl_desc_sw *desc;
323         unsigned long flags;
324         dma_cookie_t cookie;
325
326         /* cookie increment and adding to ld_queue must be atomic */
327         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
328
329         cookie = fsl_chan->common.cookie;
330         list_for_each_entry(desc, &tx->tx_list, node) {
331                 cookie++;
332                 if (cookie < 0)
333                         cookie = 1;
334
335                 desc->async_tx.cookie = cookie;
336         }
337
338         fsl_chan->common.cookie = cookie;
339         append_ld_queue(fsl_chan, tx_to_fsl_desc(tx));
340         list_splice_init(&tx->tx_list, fsl_chan->ld_queue.prev);
341
342         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
343
344         return cookie;
345 }
346
347 /**
348  * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
349  * @fsl_chan : Freescale DMA channel
350  *
351  * Return - The descriptor allocated. NULL for failed.
352  */
353 static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
354                                         struct fsl_dma_chan *fsl_chan)
355 {
356         dma_addr_t pdesc;
357         struct fsl_desc_sw *desc_sw;
358
359         desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc);
360         if (desc_sw) {
361                 memset(desc_sw, 0, sizeof(struct fsl_desc_sw));
362                 dma_async_tx_descriptor_init(&desc_sw->async_tx,
363                                                 &fsl_chan->common);
364                 desc_sw->async_tx.tx_submit = fsl_dma_tx_submit;
365                 desc_sw->async_tx.phys = pdesc;
366         }
367
368         return desc_sw;
369 }
370
371
372 /**
373  * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
374  * @fsl_chan : Freescale DMA channel
375  *
376  * This function will create a dma pool for descriptor allocation.
377  *
378  * Return - The number of descriptors allocated.
379  */
380 static int fsl_dma_alloc_chan_resources(struct dma_chan *chan)
381 {
382         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
383
384         /* Has this channel already been allocated? */
385         if (fsl_chan->desc_pool)
386                 return 1;
387
388         /* We need the descriptor to be aligned to 32bytes
389          * for meeting FSL DMA specification requirement.
390          */
391         fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
392                         fsl_chan->dev, sizeof(struct fsl_desc_sw),
393                         32, 0);
394         if (!fsl_chan->desc_pool) {
395                 dev_err(fsl_chan->dev, "No memory for channel %d "
396                         "descriptor dma pool.\n", fsl_chan->id);
397                 return 0;
398         }
399
400         return 1;
401 }
402
403 /**
404  * fsl_dma_free_chan_resources - Free all resources of the channel.
405  * @fsl_chan : Freescale DMA channel
406  */
407 static void fsl_dma_free_chan_resources(struct dma_chan *chan)
408 {
409         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
410         struct fsl_desc_sw *desc, *_desc;
411         unsigned long flags;
412
413         dev_dbg(fsl_chan->dev, "Free all channel resources.\n");
414         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
415         list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
416 #ifdef FSL_DMA_LD_DEBUG
417                 dev_dbg(fsl_chan->dev,
418                                 "LD %p will be released.\n", desc);
419 #endif
420                 list_del(&desc->node);
421                 /* free link descriptor */
422                 dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
423         }
424         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
425         dma_pool_destroy(fsl_chan->desc_pool);
426
427         fsl_chan->desc_pool = NULL;
428 }
429
430 static struct dma_async_tx_descriptor *
431 fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags)
432 {
433         struct fsl_dma_chan *fsl_chan;
434         struct fsl_desc_sw *new;
435
436         if (!chan)
437                 return NULL;
438
439         fsl_chan = to_fsl_chan(chan);
440
441         new = fsl_dma_alloc_descriptor(fsl_chan);
442         if (!new) {
443                 dev_err(fsl_chan->dev, "No free memory for link descriptor\n");
444                 return NULL;
445         }
446
447         new->async_tx.cookie = -EBUSY;
448         new->async_tx.flags = flags;
449
450         /* Insert the link descriptor to the LD ring */
451         list_add_tail(&new->node, &new->async_tx.tx_list);
452
453         /* Set End-of-link to the last link descriptor of new list*/
454         set_ld_eol(fsl_chan, new);
455
456         return &new->async_tx;
457 }
458
459 static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
460         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
461         size_t len, unsigned long flags)
462 {
463         struct fsl_dma_chan *fsl_chan;
464         struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
465         struct list_head *list;
466         size_t copy;
467
468         if (!chan)
469                 return NULL;
470
471         if (!len)
472                 return NULL;
473
474         fsl_chan = to_fsl_chan(chan);
475
476         do {
477
478                 /* Allocate the link descriptor from DMA pool */
479                 new = fsl_dma_alloc_descriptor(fsl_chan);
480                 if (!new) {
481                         dev_err(fsl_chan->dev,
482                                         "No free memory for link descriptor\n");
483                         goto fail;
484                 }
485 #ifdef FSL_DMA_LD_DEBUG
486                 dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new);
487 #endif
488
489                 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
490
491                 set_desc_cnt(fsl_chan, &new->hw, copy);
492                 set_desc_src(fsl_chan, &new->hw, dma_src);
493                 set_desc_dest(fsl_chan, &new->hw, dma_dest);
494
495                 if (!first)
496                         first = new;
497                 else
498                         set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys);
499
500                 new->async_tx.cookie = 0;
501                 async_tx_ack(&new->async_tx);
502
503                 prev = new;
504                 len -= copy;
505                 dma_src += copy;
506                 dma_dest += copy;
507
508                 /* Insert the link descriptor to the LD ring */
509                 list_add_tail(&new->node, &first->async_tx.tx_list);
510         } while (len);
511
512         new->async_tx.flags = flags; /* client is in control of this ack */
513         new->async_tx.cookie = -EBUSY;
514
515         /* Set End-of-link to the last link descriptor of new list*/
516         set_ld_eol(fsl_chan, new);
517
518         return &first->async_tx;
519
520 fail:
521         if (!first)
522                 return NULL;
523
524         list = &first->async_tx.tx_list;
525         list_for_each_entry_safe_reverse(new, prev, list, node) {
526                 list_del(&new->node);
527                 dma_pool_free(fsl_chan->desc_pool, new, new->async_tx.phys);
528         }
529
530         return NULL;
531 }
532
533 /**
534  * fsl_dma_update_completed_cookie - Update the completed cookie.
535  * @fsl_chan : Freescale DMA channel
536  */
537 static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan)
538 {
539         struct fsl_desc_sw *cur_desc, *desc;
540         dma_addr_t ld_phy;
541
542         ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK;
543
544         if (ld_phy) {
545                 cur_desc = NULL;
546                 list_for_each_entry(desc, &fsl_chan->ld_queue, node)
547                         if (desc->async_tx.phys == ld_phy) {
548                                 cur_desc = desc;
549                                 break;
550                         }
551
552                 if (cur_desc && cur_desc->async_tx.cookie) {
553                         if (dma_is_idle(fsl_chan))
554                                 fsl_chan->completed_cookie =
555                                         cur_desc->async_tx.cookie;
556                         else
557                                 fsl_chan->completed_cookie =
558                                         cur_desc->async_tx.cookie - 1;
559                 }
560         }
561 }
562
563 /**
564  * fsl_chan_ld_cleanup - Clean up link descriptors
565  * @fsl_chan : Freescale DMA channel
566  *
567  * This function clean up the ld_queue of DMA channel.
568  * If 'in_intr' is set, the function will move the link descriptor to
569  * the recycle list. Otherwise, free it directly.
570  */
571 static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan)
572 {
573         struct fsl_desc_sw *desc, *_desc;
574         unsigned long flags;
575
576         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
577
578         dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n",
579                         fsl_chan->completed_cookie);
580         list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
581                 dma_async_tx_callback callback;
582                 void *callback_param;
583
584                 if (dma_async_is_complete(desc->async_tx.cookie,
585                             fsl_chan->completed_cookie, fsl_chan->common.cookie)
586                                 == DMA_IN_PROGRESS)
587                         break;
588
589                 callback = desc->async_tx.callback;
590                 callback_param = desc->async_tx.callback_param;
591
592                 /* Remove from ld_queue list */
593                 list_del(&desc->node);
594
595                 dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n",
596                                 desc);
597                 dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
598
599                 /* Run the link descriptor callback function */
600                 if (callback) {
601                         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
602                         dev_dbg(fsl_chan->dev, "link descriptor %p callback\n",
603                                         desc);
604                         callback(callback_param);
605                         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
606                 }
607         }
608         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
609 }
610
611 /**
612  * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue.
613  * @fsl_chan : Freescale DMA channel
614  */
615 static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan)
616 {
617         struct list_head *ld_node;
618         dma_addr_t next_dest_addr;
619         unsigned long flags;
620
621         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
622
623         if (!dma_is_idle(fsl_chan))
624                 goto out_unlock;
625
626         dma_halt(fsl_chan);
627
628         /* If there are some link descriptors
629          * not transfered in queue. We need to start it.
630          */
631
632         /* Find the first un-transfer desciptor */
633         for (ld_node = fsl_chan->ld_queue.next;
634                 (ld_node != &fsl_chan->ld_queue)
635                         && (dma_async_is_complete(
636                                 to_fsl_desc(ld_node)->async_tx.cookie,
637                                 fsl_chan->completed_cookie,
638                                 fsl_chan->common.cookie) == DMA_SUCCESS);
639                 ld_node = ld_node->next);
640
641         if (ld_node != &fsl_chan->ld_queue) {
642                 /* Get the ld start address from ld_queue */
643                 next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys;
644                 dev_dbg(fsl_chan->dev, "xfer LDs staring from 0x%llx\n",
645                                 (unsigned long long)next_dest_addr);
646                 set_cdar(fsl_chan, next_dest_addr);
647                 dma_start(fsl_chan);
648         } else {
649                 set_cdar(fsl_chan, 0);
650                 set_ndar(fsl_chan, 0);
651         }
652
653 out_unlock:
654         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
655 }
656
657 /**
658  * fsl_dma_memcpy_issue_pending - Issue the DMA start command
659  * @fsl_chan : Freescale DMA channel
660  */
661 static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan)
662 {
663         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
664
665 #ifdef FSL_DMA_LD_DEBUG
666         struct fsl_desc_sw *ld;
667         unsigned long flags;
668
669         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
670         if (list_empty(&fsl_chan->ld_queue)) {
671                 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
672                 return;
673         }
674
675         dev_dbg(fsl_chan->dev, "--memcpy issue--\n");
676         list_for_each_entry(ld, &fsl_chan->ld_queue, node) {
677                 int i;
678                 dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n",
679                                 fsl_chan->id, ld->async_tx.phys);
680                 for (i = 0; i < 8; i++)
681                         dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n",
682                                         i, *(((u32 *)&ld->hw) + i));
683         }
684         dev_dbg(fsl_chan->dev, "----------------\n");
685         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
686 #endif
687
688         fsl_chan_xfer_ld_queue(fsl_chan);
689 }
690
691 /**
692  * fsl_dma_is_complete - Determine the DMA status
693  * @fsl_chan : Freescale DMA channel
694  */
695 static enum dma_status fsl_dma_is_complete(struct dma_chan *chan,
696                                         dma_cookie_t cookie,
697                                         dma_cookie_t *done,
698                                         dma_cookie_t *used)
699 {
700         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
701         dma_cookie_t last_used;
702         dma_cookie_t last_complete;
703
704         fsl_chan_ld_cleanup(fsl_chan);
705
706         last_used = chan->cookie;
707         last_complete = fsl_chan->completed_cookie;
708
709         if (done)
710                 *done = last_complete;
711
712         if (used)
713                 *used = last_used;
714
715         return dma_async_is_complete(cookie, last_complete, last_used);
716 }
717
718 static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data)
719 {
720         struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
721         u32 stat;
722         int update_cookie = 0;
723         int xfer_ld_q = 0;
724
725         stat = get_sr(fsl_chan);
726         dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n",
727                                                 fsl_chan->id, stat);
728         set_sr(fsl_chan, stat);         /* Clear the event register */
729
730         stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
731         if (!stat)
732                 return IRQ_NONE;
733
734         if (stat & FSL_DMA_SR_TE)
735                 dev_err(fsl_chan->dev, "Transfer Error!\n");
736
737         /* Programming Error
738          * The DMA_INTERRUPT async_tx is a NULL transfer, which will
739          * triger a PE interrupt.
740          */
741         if (stat & FSL_DMA_SR_PE) {
742                 dev_dbg(fsl_chan->dev, "event: Programming Error INT\n");
743                 if (get_bcr(fsl_chan) == 0) {
744                         /* BCR register is 0, this is a DMA_INTERRUPT async_tx.
745                          * Now, update the completed cookie, and continue the
746                          * next uncompleted transfer.
747                          */
748                         update_cookie = 1;
749                         xfer_ld_q = 1;
750                 }
751                 stat &= ~FSL_DMA_SR_PE;
752         }
753
754         /* If the link descriptor segment transfer finishes,
755          * we will recycle the used descriptor.
756          */
757         if (stat & FSL_DMA_SR_EOSI) {
758                 dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n");
759                 dev_dbg(fsl_chan->dev, "event: clndar 0x%llx, nlndar 0x%llx\n",
760                         (unsigned long long)get_cdar(fsl_chan),
761                         (unsigned long long)get_ndar(fsl_chan));
762                 stat &= ~FSL_DMA_SR_EOSI;
763                 update_cookie = 1;
764         }
765
766         /* For MPC8349, EOCDI event need to update cookie
767          * and start the next transfer if it exist.
768          */
769         if (stat & FSL_DMA_SR_EOCDI) {
770                 dev_dbg(fsl_chan->dev, "event: End-of-Chain link INT\n");
771                 stat &= ~FSL_DMA_SR_EOCDI;
772                 update_cookie = 1;
773                 xfer_ld_q = 1;
774         }
775
776         /* If it current transfer is the end-of-transfer,
777          * we should clear the Channel Start bit for
778          * prepare next transfer.
779          */
780         if (stat & FSL_DMA_SR_EOLNI) {
781                 dev_dbg(fsl_chan->dev, "event: End-of-link INT\n");
782                 stat &= ~FSL_DMA_SR_EOLNI;
783                 xfer_ld_q = 1;
784         }
785
786         if (update_cookie)
787                 fsl_dma_update_completed_cookie(fsl_chan);
788         if (xfer_ld_q)
789                 fsl_chan_xfer_ld_queue(fsl_chan);
790         if (stat)
791                 dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n",
792                                         stat);
793
794         dev_dbg(fsl_chan->dev, "event: Exit\n");
795         tasklet_schedule(&fsl_chan->tasklet);
796         return IRQ_HANDLED;
797 }
798
799 static irqreturn_t fsl_dma_do_interrupt(int irq, void *data)
800 {
801         struct fsl_dma_device *fdev = (struct fsl_dma_device *)data;
802         u32 gsr;
803         int ch_nr;
804
805         gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base)
806                         : in_le32(fdev->reg_base);
807         ch_nr = (32 - ffs(gsr)) / 8;
808
809         return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq,
810                         fdev->chan[ch_nr]) : IRQ_NONE;
811 }
812
813 static void dma_do_tasklet(unsigned long data)
814 {
815         struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
816         fsl_chan_ld_cleanup(fsl_chan);
817 }
818
819 static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev,
820         struct device_node *node, u32 feature, const char *compatible)
821 {
822         struct fsl_dma_chan *new_fsl_chan;
823         int err;
824
825         /* alloc channel */
826         new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL);
827         if (!new_fsl_chan) {
828                 dev_err(fdev->dev, "No free memory for allocating "
829                                 "dma channels!\n");
830                 return -ENOMEM;
831         }
832
833         /* get dma channel register base */
834         err = of_address_to_resource(node, 0, &new_fsl_chan->reg);
835         if (err) {
836                 dev_err(fdev->dev, "Can't get %s property 'reg'\n",
837                                 node->full_name);
838                 goto err_no_reg;
839         }
840
841         new_fsl_chan->feature = feature;
842
843         if (!fdev->feature)
844                 fdev->feature = new_fsl_chan->feature;
845
846         /* If the DMA device's feature is different than its channels',
847          * report the bug.
848          */
849         WARN_ON(fdev->feature != new_fsl_chan->feature);
850
851         new_fsl_chan->dev = fdev->dev;
852         new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start,
853                         new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1);
854
855         new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7;
856         if (new_fsl_chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
857                 dev_err(fdev->dev, "There is no %d channel!\n",
858                                 new_fsl_chan->id);
859                 err = -EINVAL;
860                 goto err_no_chan;
861         }
862         fdev->chan[new_fsl_chan->id] = new_fsl_chan;
863         tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet,
864                         (unsigned long)new_fsl_chan);
865
866         /* Init the channel */
867         dma_init(new_fsl_chan);
868
869         /* Clear cdar registers */
870         set_cdar(new_fsl_chan, 0);
871
872         switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) {
873         case FSL_DMA_IP_85XX:
874                 new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start;
875                 new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
876         case FSL_DMA_IP_83XX:
877                 new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size;
878                 new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size;
879         }
880
881         spin_lock_init(&new_fsl_chan->desc_lock);
882         INIT_LIST_HEAD(&new_fsl_chan->ld_queue);
883
884         new_fsl_chan->common.device = &fdev->common;
885
886         /* Add the channel to DMA device channel list */
887         list_add_tail(&new_fsl_chan->common.device_node,
888                         &fdev->common.channels);
889         fdev->common.chancnt++;
890
891         new_fsl_chan->irq = irq_of_parse_and_map(node, 0);
892         if (new_fsl_chan->irq != NO_IRQ) {
893                 err = request_irq(new_fsl_chan->irq,
894                                         &fsl_dma_chan_do_interrupt, IRQF_SHARED,
895                                         "fsldma-channel", new_fsl_chan);
896                 if (err) {
897                         dev_err(fdev->dev, "DMA channel %s request_irq error "
898                                 "with return %d\n", node->full_name, err);
899                         goto err_no_irq;
900                 }
901         }
902
903         dev_info(fdev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id,
904                  compatible,
905                  new_fsl_chan->irq != NO_IRQ ? new_fsl_chan->irq : fdev->irq);
906
907         return 0;
908
909 err_no_irq:
910         list_del(&new_fsl_chan->common.device_node);
911 err_no_chan:
912         iounmap(new_fsl_chan->reg_base);
913 err_no_reg:
914         kfree(new_fsl_chan);
915         return err;
916 }
917
918 static void fsl_dma_chan_remove(struct fsl_dma_chan *fchan)
919 {
920         if (fchan->irq != NO_IRQ)
921                 free_irq(fchan->irq, fchan);
922         list_del(&fchan->common.device_node);
923         iounmap(fchan->reg_base);
924         kfree(fchan);
925 }
926
927 static int __devinit of_fsl_dma_probe(struct of_device *dev,
928                         const struct of_device_id *match)
929 {
930         int err;
931         struct fsl_dma_device *fdev;
932         struct device_node *child;
933
934         fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL);
935         if (!fdev) {
936                 dev_err(&dev->dev, "No enough memory for 'priv'\n");
937                 return -ENOMEM;
938         }
939         fdev->dev = &dev->dev;
940         INIT_LIST_HEAD(&fdev->common.channels);
941
942         /* get DMA controller register base */
943         err = of_address_to_resource(dev->node, 0, &fdev->reg);
944         if (err) {
945                 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
946                                 dev->node->full_name);
947                 goto err_no_reg;
948         }
949
950         dev_info(&dev->dev, "Probe the Freescale DMA driver for %s "
951                         "controller at 0x%llx...\n",
952                         match->compatible, (unsigned long long)fdev->reg.start);
953         fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end
954                                                 - fdev->reg.start + 1);
955
956         dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
957         dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
958         fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
959         fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
960         fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
961         fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
962         fdev->common.device_is_tx_complete = fsl_dma_is_complete;
963         fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
964         fdev->common.dev = &dev->dev;
965
966         fdev->irq = irq_of_parse_and_map(dev->node, 0);
967         if (fdev->irq != NO_IRQ) {
968                 err = request_irq(fdev->irq, &fsl_dma_do_interrupt, IRQF_SHARED,
969                                         "fsldma-device", fdev);
970                 if (err) {
971                         dev_err(&dev->dev, "DMA device request_irq error "
972                                 "with return %d\n", err);
973                         goto err;
974                 }
975         }
976
977         dev_set_drvdata(&(dev->dev), fdev);
978
979         /* We cannot use of_platform_bus_probe() because there is no
980          * of_platform_bus_remove.  Instead, we manually instantiate every DMA
981          * channel object.
982          */
983         for_each_child_of_node(dev->node, child) {
984                 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel"))
985                         fsl_dma_chan_probe(fdev, child,
986                                 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
987                                 "fsl,eloplus-dma-channel");
988                 if (of_device_is_compatible(child, "fsl,elo-dma-channel"))
989                         fsl_dma_chan_probe(fdev, child,
990                                 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
991                                 "fsl,elo-dma-channel");
992         }
993
994         dma_async_device_register(&fdev->common);
995         return 0;
996
997 err:
998         iounmap(fdev->reg_base);
999 err_no_reg:
1000         kfree(fdev);
1001         return err;
1002 }
1003
1004 static int of_fsl_dma_remove(struct of_device *of_dev)
1005 {
1006         struct fsl_dma_device *fdev;
1007         unsigned int i;
1008
1009         fdev = dev_get_drvdata(&of_dev->dev);
1010
1011         dma_async_device_unregister(&fdev->common);
1012
1013         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++)
1014                 if (fdev->chan[i])
1015                         fsl_dma_chan_remove(fdev->chan[i]);
1016
1017         if (fdev->irq != NO_IRQ)
1018                 free_irq(fdev->irq, fdev);
1019
1020         iounmap(fdev->reg_base);
1021
1022         kfree(fdev);
1023         dev_set_drvdata(&of_dev->dev, NULL);
1024
1025         return 0;
1026 }
1027
1028 static struct of_device_id of_fsl_dma_ids[] = {
1029         { .compatible = "fsl,eloplus-dma", },
1030         { .compatible = "fsl,elo-dma", },
1031         {}
1032 };
1033
1034 static struct of_platform_driver of_fsl_dma_driver = {
1035         .name = "fsl-elo-dma",
1036         .match_table = of_fsl_dma_ids,
1037         .probe = of_fsl_dma_probe,
1038         .remove = of_fsl_dma_remove,
1039 };
1040
1041 static __init int of_fsl_dma_init(void)
1042 {
1043         int ret;
1044
1045         pr_info("Freescale Elo / Elo Plus DMA driver\n");
1046
1047         ret = of_register_platform_driver(&of_fsl_dma_driver);
1048         if (ret)
1049                 pr_err("fsldma: failed to register platform driver\n");
1050
1051         return ret;
1052 }
1053
1054 static void __exit of_fsl_dma_exit(void)
1055 {
1056         of_unregister_platform_driver(&of_fsl_dma_driver);
1057 }
1058
1059 subsys_initcall(of_fsl_dma_init);
1060 module_exit(of_fsl_dma_exit);
1061
1062 MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver");
1063 MODULE_LICENSE("GPL");