drivers/crypto/omap-sham.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP SHA1/MD5 HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as published
  11  * by the Free Software Foundation.
  12  *
  13  * Some ideas are from old omap-sha1-md5.c driver.
  14  */
  15
  16 #define pr_fmt(fmt) "%s: " fmt, __func__
  17
  18 #include <linux/err.h>
  19 #include <linux/device.h>
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/kernel.h>
  25 #include <linux/clk.h>
  26 #include <linux/irq.h>
  27 #include <linux/io.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/crypto.h>
  33 #include <linux/cryptohash.h>
  34 #include <crypto/scatterwalk.h>
  35 #include <crypto/algapi.h>
  36 #include <crypto/sha.h>
  37 #include <crypto/hash.h>
  38 #include <crypto/internal/hash.h>
  39
  40 #include <plat/cpu.h>
  41 #include <plat/dma.h>
  42 #include <mach/irqs.h>
  43
  44 #define SHA_REG_DIGEST(x)               (0x00 + ((x) * 0x04))
  45 #define SHA_REG_DIN(x)                  (0x1C + ((x) * 0x04))
  46
  47 #define SHA1_MD5_BLOCK_SIZE             SHA1_BLOCK_SIZE
  48 #define MD5_DIGEST_SIZE                 16
  49
  50 #define SHA_REG_DIGCNT                  0x14
  51
  52 #define SHA_REG_CTRL                    0x18
  53 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  54 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  55 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  56 #define SHA_REG_CTRL_ALGO               (1 << 2)
  57 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  58 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  59
  60 #define SHA_REG_REV                     0x5C
  61 #define SHA_REG_REV_MAJOR               0xF0
  62 #define SHA_REG_REV_MINOR               0x0F
  63
  64 #define SHA_REG_MASK                    0x60
  65 #define SHA_REG_MASK_DMA_EN             (1 << 3)
  66 #define SHA_REG_MASK_IT_EN              (1 << 2)
  67 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
  68 #define SHA_REG_AUTOIDLE                (1 << 0)
  69
  70 #define SHA_REG_SYSSTATUS               0x64
  71 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  72
  73 #define DEFAULT_TIMEOUT_INTERVAL        HZ
  74
  75 /* mostly device flags */
  76 #define FLAGS_BUSY              0
  77 #define FLAGS_FINAL             1
  78 #define FLAGS_DMA_ACTIVE        2
  79 #define FLAGS_OUTPUT_READY      3
  80 #define FLAGS_INIT              4
  81 #define FLAGS_CPU               5
  82 /* context flags */
  83 #define FLAGS_FINUP             16
  84 #define FLAGS_SG                17
  85 #define FLAGS_SHA1              18
  86 #define FLAGS_HMAC              19
  87 #define FLAGS_ERROR             20
  88
  89 #define OP_UPDATE       1
  90 #define OP_FINAL        2
  91
  92 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
  93 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
  94
  95 #define BUFLEN          PAGE_SIZE
  96
  97 struct omap_sham_dev;
  98
  99 struct omap_sham_reqctx {
 100         struct omap_sham_dev    *dd;
 101         unsigned long           flags;
 102         unsigned long           op;
 103
 104         u8                      digest[SHA1_DIGEST_SIZE] OMAP_ALIGNED;
 105         size_t                  digcnt;
 106         size_t                  bufcnt;
 107         size_t                  buflen;
 108         dma_addr_t              dma_addr;
 109
 110         /* walk state */
 111         struct scatterlist      *sg;
 112         unsigned int            offset; /* offset in current sg */
 113         unsigned int            total;  /* total request */
 114
 115         u8                      buffer[0] OMAP_ALIGNED;
 116 };
 117
 118 struct omap_sham_hmac_ctx {
 119         struct crypto_shash     *shash;
 120         u8                      ipad[SHA1_MD5_BLOCK_SIZE];
 121         u8                      opad[SHA1_MD5_BLOCK_SIZE];
 122 };
 123
 124 struct omap_sham_ctx {
 125         struct omap_sham_dev    *dd;
 126
 127         unsigned long           flags;
 128
 129         /* fallback stuff */
 130         struct crypto_shash     *fallback;
 131
 132         struct omap_sham_hmac_ctx base[0];
 133 };
 134
 135 #define OMAP_SHAM_QUEUE_LENGTH  1
 136
 137 struct omap_sham_dev {
 138         struct list_head        list;
 139         unsigned long           phys_base;
 140         struct device           *dev;
 141         void __iomem            *io_base;
 142         int                     irq;
 143         struct clk              *iclk;
 144         spinlock_t              lock;
 145         int                     err;
 146         int                     dma;
 147         int                     dma_lch;
 148         struct tasklet_struct   done_task;
 149         struct tasklet_struct   queue_task;
 150
 151         unsigned long           flags;
 152         struct crypto_queue     queue;
 153         struct ahash_request    *req;
 154 };
 155
 156 struct omap_sham_drv {
 157         struct list_head        dev_list;
 158         spinlock_t              lock;
 159         unsigned long           flags;
 160 };
 161
 162 static struct omap_sham_drv sham = {
 163         .dev_list = LIST_HEAD_INIT(sham.dev_list),
 164         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 165 };
 166
 167 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 168 {
 169         return __raw_readl(dd->io_base + offset);
 170 }
 171
 172 static inline void omap_sham_write(struct omap_sham_dev *dd,
 173                                         u32 offset, u32 value)
 174 {
 175         __raw_writel(value, dd->io_base + offset);
 176 }
 177
 178 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 179                                         u32 value, u32 mask)
 180 {
 181         u32 val;
 182
 183         val = omap_sham_read(dd, address);
 184         val &= ~mask;
 185         val |= value;
 186         omap_sham_write(dd, address, val);
 187 }
 188
 189 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 190 {
 191         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 192
 193         while (!(omap_sham_read(dd, offset) & bit)) {
 194                 if (time_is_before_jiffies(timeout))
 195                         return -ETIMEDOUT;
 196         }
 197
 198         return 0;
 199 }
 200
 201 static void omap_sham_copy_hash(struct ahash_request *req, int out)
 202 {
 203         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 204         u32 *hash = (u32 *)ctx->digest;
 205         int i;
 206
 207         /* MD5 is almost unused. So copy sha1 size to reduce code */
 208         for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++) {
 209                 if (out)
 210                         hash[i] = omap_sham_read(ctx->dd,
 211                                                 SHA_REG_DIGEST(i));
 212                 else
 213                         omap_sham_write(ctx->dd,
 214                                         SHA_REG_DIGEST(i), hash[i]);
 215         }
 216 }
 217
 218 static void omap_sham_copy_ready_hash(struct ahash_request *req)
 219 {
 220         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 221         u32 *in = (u32 *)ctx->digest;
 222         u32 *hash = (u32 *)req->result;
 223         int i;
 224
 225         if (!hash)
 226                 return;
 227
 228         if (likely(ctx->flags & BIT(FLAGS_SHA1))) {
 229                 /* SHA1 results are in big endian */
 230                 for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++)
 231                         hash[i] = be32_to_cpu(in[i]);
 232         } else {
 233                 /* MD5 results are in little endian */
 234                 for (i = 0; i < MD5_DIGEST_SIZE / sizeof(u32); i++)
 235                         hash[i] = le32_to_cpu(in[i]);
 236         }
 237 }
 238
 239 static int omap_sham_hw_init(struct omap_sham_dev *dd)
 240 {
 241         clk_enable(dd->iclk);
 242
 243         if (!(dd->flags & BIT(FLAGS_INIT))) {
 244                 omap_sham_write_mask(dd, SHA_REG_MASK,
 245                         SHA_REG_MASK_SOFTRESET, SHA_REG_MASK_SOFTRESET);
 246
 247                 if (omap_sham_wait(dd, SHA_REG_SYSSTATUS,
 248                                         SHA_REG_SYSSTATUS_RESETDONE))
 249                         return -ETIMEDOUT;
 250
 251                 dd->flags |= BIT(FLAGS_INIT);
 252                 dd->err = 0;
 253         }
 254
 255         return 0;
 256 }
 257
 258 static void omap_sham_write_ctrl(struct omap_sham_dev *dd, size_t length,
 259                                  int final, int dma)
 260 {
 261         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 262         u32 val = length << 5, mask;
 263
 264         if (likely(ctx->digcnt))
 265                 omap_sham_write(dd, SHA_REG_DIGCNT, ctx->digcnt);
 266
 267         omap_sham_write_mask(dd, SHA_REG_MASK,
 268                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 269                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 270         /*
 271          * Setting ALGO_CONST only for the first iteration
 272          * and CLOSE_HASH only for the last one.
 273          */
 274         if (ctx->flags & BIT(FLAGS_SHA1))
 275                 val |= SHA_REG_CTRL_ALGO;
 276         if (!ctx->digcnt)
 277                 val |= SHA_REG_CTRL_ALGO_CONST;
 278         if (final)
 279                 val |= SHA_REG_CTRL_CLOSE_HASH;
 280
 281         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 282                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 283
 284         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 285 }
 286
 287 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
 288                               size_t length, int final)
 289 {
 290         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 291         int count, len32;
 292         const u32 *buffer = (const u32 *)buf;
 293
 294         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 295                                                 ctx->digcnt, length, final);
 296
 297         omap_sham_write_ctrl(dd, length, final, 0);
 298
 299         /* should be non-zero before next lines to disable clocks later */
 300         ctx->digcnt += length;
 301
 302         if (omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY))
 303                 return -ETIMEDOUT;
 304
 305         if (final)
 306                 ctx->flags |= BIT(FLAGS_FINAL); /* catch last interrupt */
 307
 308         len32 = DIV_ROUND_UP(length, sizeof(u32));
 309
 310         for (count = 0; count < len32; count++)
 311                 omap_sham_write(dd, SHA_REG_DIN(count), buffer[count]);
 312
 313         return -EINPROGRESS;
 314 }
 315
 316 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
 317                               size_t length, int final)
 318 {
 319         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 320         int len32;
 321
 322         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 323                                                 ctx->digcnt, length, final);
 324
 325         len32 = DIV_ROUND_UP(length, sizeof(u32));
 326
 327         omap_set_dma_transfer_params(dd->dma_lch, OMAP_DMA_DATA_TYPE_S32, len32,
 328                         1, OMAP_DMA_SYNC_PACKET, dd->dma,
 329                                 OMAP_DMA_DST_SYNC_PREFETCH);
 330
 331         omap_set_dma_src_params(dd->dma_lch, 0, OMAP_DMA_AMODE_POST_INC,
 332                                 dma_addr, 0, 0);
 333
 334         omap_sham_write_ctrl(dd, length, final, 1);
 335
 336         ctx->digcnt += length;
 337
 338         if (final)
 339                 ctx->flags |= BIT(FLAGS_FINAL); /* catch last interrupt */
 340
 341         dd->flags |= BIT(FLAGS_DMA_ACTIVE);
 342
 343         omap_start_dma(dd->dma_lch);
 344
 345         return -EINPROGRESS;
 346 }
 347
 348 static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
 349                                 const u8 *data, size_t length)
 350 {
 351         size_t count = min(length, ctx->buflen - ctx->bufcnt);
 352
 353         count = min(count, ctx->total);
 354         if (count <= 0)
 355                 return 0;
 356         memcpy(ctx->buffer + ctx->bufcnt, data, count);
 357         ctx->bufcnt += count;
 358
 359         return count;
 360 }
 361
 362 static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
 363 {
 364         size_t count;
 365
 366         while (ctx->sg) {
 367                 count = omap_sham_append_buffer(ctx,
 368                                 sg_virt(ctx->sg) + ctx->offset,
 369                                 ctx->sg->length - ctx->offset);
 370                 if (!count)
 371                         break;
 372                 ctx->offset += count;
 373                 ctx->total -= count;
 374                 if (ctx->offset == ctx->sg->length) {
 375                         ctx->sg = sg_next(ctx->sg);
 376                         if (ctx->sg)
 377                                 ctx->offset = 0;
 378                         else
 379                                 ctx->total = 0;
 380                 }
 381         }
 382
 383         return 0;
 384 }
 385
 386 static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
 387                                         struct omap_sham_reqctx *ctx,
 388                                         size_t length, int final)
 389 {
 390         ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
 391                                        DMA_TO_DEVICE);
 392         if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
 393                 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
 394                 return -EINVAL;
 395         }
 396
 397         ctx->flags &= ~BIT(FLAGS_SG);
 398
 399         /* next call does not fail... so no unmap in the case of error */
 400         return omap_sham_xmit_dma(dd, ctx->dma_addr, length, final);
 401 }
 402
 403 static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
 404 {
 405         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 406         unsigned int final;
 407         size_t count;
 408
 409         omap_sham_append_sg(ctx);
 410
 411         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 412
 413         dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
 414                                          ctx->bufcnt, ctx->digcnt, final);
 415
 416         if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
 417                 count = ctx->bufcnt;
 418                 ctx->bufcnt = 0;
 419                 return omap_sham_xmit_dma_map(dd, ctx, count, final);
 420         }
 421
 422         return 0;
 423 }
 424
 425 /* Start address alignment */
 426 #define SG_AA(sg)       (IS_ALIGNED(sg->offset, sizeof(u32)))
 427 /* SHA1 block size alignment */
 428 #define SG_SA(sg)       (IS_ALIGNED(sg->length, SHA1_MD5_BLOCK_SIZE))
 429
 430 static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
 431 {
 432         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 433         unsigned int length, final, tail;
 434         struct scatterlist *sg;
 435
 436         if (!ctx->total)
 437                 return 0;
 438
 439         if (ctx->bufcnt || ctx->offset)
 440                 return omap_sham_update_dma_slow(dd);
 441
 442         dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
 443                         ctx->digcnt, ctx->bufcnt, ctx->total);
 444
 445         sg = ctx->sg;
 446
 447         if (!SG_AA(sg))
 448                 return omap_sham_update_dma_slow(dd);
 449
 450         if (!sg_is_last(sg) && !SG_SA(sg))
 451                 /* size is not SHA1_BLOCK_SIZE aligned */
 452                 return omap_sham_update_dma_slow(dd);
 453
 454         length = min(ctx->total, sg->length);
 455
 456         if (sg_is_last(sg)) {
 457                 if (!(ctx->flags & BIT(FLAGS_FINUP))) {
 458                         /* not last sg must be SHA1_MD5_BLOCK_SIZE aligned */
 459                         tail = length & (SHA1_MD5_BLOCK_SIZE - 1);
 460                         /* without finup() we need one block to close hash */
 461                         if (!tail)
 462                                 tail = SHA1_MD5_BLOCK_SIZE;
 463                         length -= tail;
 464                 }
 465         }
 466
 467         if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
 468                 dev_err(dd->dev, "dma_map_sg  error\n");
 469                 return -EINVAL;
 470         }
 471
 472         ctx->flags |= BIT(FLAGS_SG);
 473
 474         ctx->total -= length;
 475         ctx->offset = length; /* offset where to start slow */
 476
 477         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 478
 479         /* next call does not fail... so no unmap in the case of error */
 480         return omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final);
 481 }
 482
 483 static int omap_sham_update_cpu(struct omap_sham_dev *dd)
 484 {
 485         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 486         int bufcnt;
 487
 488         omap_sham_append_sg(ctx);
 489         bufcnt = ctx->bufcnt;
 490         ctx->bufcnt = 0;
 491
 492         return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, 1);
 493 }
 494
 495 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 496 {
 497         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 498
 499         omap_stop_dma(dd->dma_lch);
 500         if (ctx->flags & BIT(FLAGS_SG)) {
 501                 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
 502                 if (ctx->sg->length == ctx->offset) {
 503                         ctx->sg = sg_next(ctx->sg);
 504                         if (ctx->sg)
 505                                 ctx->offset = 0;
 506                 }
 507         } else {
 508                 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
 509                                  DMA_TO_DEVICE);
 510         }
 511
 512         return 0;
 513 }
 514
 515 static int omap_sham_init(struct ahash_request *req)
 516 {
 517         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 518         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 519         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 520         struct omap_sham_dev *dd = NULL, *tmp;
 521
 522         spin_lock_bh(&sham.lock);
 523         if (!tctx->dd) {
 524                 list_for_each_entry(tmp, &sham.dev_list, list) {
 525                         dd = tmp;
 526                         break;
 527                 }
 528                 tctx->dd = dd;
 529         } else {
 530                 dd = tctx->dd;
 531         }
 532         spin_unlock_bh(&sham.lock);
 533
 534         ctx->dd = dd;
 535
 536         ctx->flags = 0;
 537
 538         dev_dbg(dd->dev, "init: digest size: %d\n",
 539                 crypto_ahash_digestsize(tfm));
 540
 541         if (crypto_ahash_digestsize(tfm) == SHA1_DIGEST_SIZE)
 542                 ctx->flags |= BIT(FLAGS_SHA1);
 543
 544         ctx->bufcnt = 0;
 545         ctx->digcnt = 0;
 546         ctx->buflen = BUFLEN;
 547
 548         if (tctx->flags & BIT(FLAGS_HMAC)) {
 549                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 550
 551                 memcpy(ctx->buffer, bctx->ipad, SHA1_MD5_BLOCK_SIZE);
 552                 ctx->bufcnt = SHA1_MD5_BLOCK_SIZE;
 553                 ctx->flags |= BIT(FLAGS_HMAC);
 554         }
 555
 556         return 0;
 557
 558 }
 559
 560 static int omap_sham_update_req(struct omap_sham_dev *dd)
 561 {
 562         struct ahash_request *req = dd->req;
 563         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 564         int err;
 565
 566         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
 567                  ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
 568
 569         if (ctx->flags & BIT(FLAGS_CPU))
 570                 err = omap_sham_update_cpu(dd);
 571         else
 572                 err = omap_sham_update_dma_start(dd);
 573
 574         /* wait for dma completion before can take more data */
 575         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
 576
 577         return err;
 578 }
 579
 580 static int omap_sham_final_req(struct omap_sham_dev *dd)
 581 {
 582         struct ahash_request *req = dd->req;
 583         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 584         int err = 0, use_dma = 1;
 585
 586         if (ctx->bufcnt <= 64)
 587                 /* faster to handle last block with cpu */
 588                 use_dma = 0;
 589
 590         if (use_dma)
 591                 err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
 592         else
 593                 err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
 594
 595         ctx->bufcnt = 0;
 596
 597         dev_dbg(dd->dev, "final_req: err: %d\n", err);
 598
 599         return err;
 600 }
 601
 602 static int omap_sham_finish_hmac(struct ahash_request *req)
 603 {
 604         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
 605         struct omap_sham_hmac_ctx *bctx = tctx->base;
 606         int bs = crypto_shash_blocksize(bctx->shash);
 607         int ds = crypto_shash_digestsize(bctx->shash);
 608         struct {
 609                 struct shash_desc shash;
 610                 char ctx[crypto_shash_descsize(bctx->shash)];
 611         } desc;
 612
 613         desc.shash.tfm = bctx->shash;
 614         desc.shash.flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
 615
 616         return crypto_shash_init(&desc.shash) ?:
 617                crypto_shash_update(&desc.shash, bctx->opad, bs) ?:
 618                crypto_shash_finup(&desc.shash, req->result, ds, req->result);
 619 }
 620
 621 static int omap_sham_finish(struct ahash_request *req)
 622 {
 623         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 624         struct omap_sham_dev *dd = ctx->dd;
 625         int err = 0;
 626
 627         if (ctx->digcnt) {
 628                 omap_sham_copy_ready_hash(req);
 629                 if (ctx->flags & BIT(FLAGS_HMAC))
 630                         err = omap_sham_finish_hmac(req);
 631         }
 632
 633         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
 634
 635         return err;
 636 }
 637
 638 static void omap_sham_finish_req(struct ahash_request *req, int err)
 639 {
 640         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 641         struct omap_sham_dev *dd = ctx->dd;
 642
 643         if (!err) {
 644                 omap_sham_copy_hash(req, 1);
 645                 if (ctx->flags & BIT(FLAGS_FINAL))
 646                         err = omap_sham_finish(req);
 647         } else {
 648                 ctx->flags |= BIT(FLAGS_ERROR);
 649         }
 650
 651         clk_disable(dd->iclk);
 652         dd->flags &= ~BIT(FLAGS_BUSY);
 653
 654         if (req->base.complete)
 655                 req->base.complete(&req->base, err);
 656 }
 657
 658 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
 659                                   struct ahash_request *req)
 660 {
 661         struct crypto_async_request *async_req, *backlog;
 662         struct omap_sham_reqctx *ctx;
 663         unsigned long flags;
 664         int err = 0, ret = 0;
 665
 666         spin_lock_irqsave(&dd->lock, flags);
 667         if (req)
 668                 ret = ahash_enqueue_request(&dd->queue, req);
 669         if (dd->flags & BIT(FLAGS_BUSY)) {
 670                 spin_unlock_irqrestore(&dd->lock, flags);
 671                 return ret;
 672         }
 673         backlog = crypto_get_backlog(&dd->queue);
 674         async_req = crypto_dequeue_request(&dd->queue);
 675         if (async_req)
 676                 dd->flags |= BIT(FLAGS_BUSY);
 677         spin_unlock_irqrestore(&dd->lock, flags);
 678
 679         if (!async_req)
 680                 return ret;
 681
 682         if (backlog)
 683                 backlog->complete(backlog, -EINPROGRESS);
 684
 685         req = ahash_request_cast(async_req);
 686         dd->req = req;
 687         ctx = ahash_request_ctx(req);
 688
 689         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
 690                                                 ctx->op, req->nbytes);
 691
 692         err = omap_sham_hw_init(dd);
 693         if (err)
 694                 goto err1;
 695
 696         omap_set_dma_dest_params(dd->dma_lch, 0,
 697                         OMAP_DMA_AMODE_CONSTANT,
 698                         dd->phys_base + SHA_REG_DIN(0), 0, 16);
 699
 700         omap_set_dma_dest_burst_mode(dd->dma_lch,
 701                         OMAP_DMA_DATA_BURST_16);
 702
 703         omap_set_dma_src_burst_mode(dd->dma_lch,
 704                         OMAP_DMA_DATA_BURST_4);
 705
 706         if (ctx->digcnt)
 707                 /* request has changed - restore hash */
 708                 omap_sham_copy_hash(req, 0);
 709
 710         if (ctx->op == OP_UPDATE) {
 711                 err = omap_sham_update_req(dd);
 712                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
 713                         /* no final() after finup() */
 714                         err = omap_sham_final_req(dd);
 715         } else if (ctx->op == OP_FINAL) {
 716                 err = omap_sham_final_req(dd);
 717         }
 718 err1:
 719         if (err != -EINPROGRESS) {
 720                 /* done_task will not finish it, so do it here */
 721                 omap_sham_finish_req(req, err);
 722                 tasklet_schedule(&dd->queue_task);
 723         }
 724
 725         dev_dbg(dd->dev, "exit, err: %d\n", err);
 726
 727         return ret;
 728 }
 729
 730 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
 731 {
 732         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 733         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
 734         struct omap_sham_dev *dd = tctx->dd;
 735
 736         ctx->op = op;
 737
 738         return omap_sham_handle_queue(dd, req);
 739 }
 740
 741 static int omap_sham_update(struct ahash_request *req)
 742 {
 743         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 744
 745         if (!req->nbytes)
 746                 return 0;
 747
 748         ctx->total = req->nbytes;
 749         ctx->sg = req->src;
 750         ctx->offset = 0;
 751
 752         if (ctx->flags & BIT(FLAGS_FINUP)) {
 753                 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) {
 754                         /*
 755                         * OMAP HW accel works only with buffers >= 9
 756                         * will switch to bypass in final()
 757                         * final has the same request and data
 758                         */
 759                         omap_sham_append_sg(ctx);
 760                         return 0;
 761                 } else if (ctx->bufcnt + ctx->total <= SHA1_MD5_BLOCK_SIZE) {
 762                         /*
 763                         * faster to use CPU for short transfers
 764                         */
 765                         ctx->flags |= BIT(FLAGS_CPU);
 766                 }
 767         } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
 768                 omap_sham_append_sg(ctx);
 769                 return 0;
 770         }
 771
 772         return omap_sham_enqueue(req, OP_UPDATE);
 773 }
 774
 775 static int omap_sham_shash_digest(struct crypto_shash *shash, u32 flags,
 776                                   const u8 *data, unsigned int len, u8 *out)
 777 {
 778         struct {
 779                 struct shash_desc shash;
 780                 char ctx[crypto_shash_descsize(shash)];
 781         } desc;
 782
 783         desc.shash.tfm = shash;
 784         desc.shash.flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 785
 786         return crypto_shash_digest(&desc.shash, data, len, out);
 787 }
 788
 789 static int omap_sham_final_shash(struct ahash_request *req)
 790 {
 791         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
 792         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 793
 794         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
 795                                       ctx->buffer, ctx->bufcnt, req->result);
 796 }
 797
 798 static int omap_sham_final(struct ahash_request *req)
 799 {
 800         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 801
 802         ctx->flags |= BIT(FLAGS_FINUP);
 803
 804         if (ctx->flags & BIT(FLAGS_ERROR))
 805                 return 0; /* uncompleted hash is not needed */
 806
 807         /* OMAP HW accel works only with buffers >= 9 */
 808         /* HMAC is always >= 9 because ipad == block size */
 809         if ((ctx->digcnt + ctx->bufcnt) < 9)
 810                 return omap_sham_final_shash(req);
 811         else if (ctx->bufcnt)
 812                 return omap_sham_enqueue(req, OP_FINAL);
 813
 814         /* copy ready hash (+ finalize hmac) */
 815         return omap_sham_finish(req);
 816 }
 817
 818 static int omap_sham_finup(struct ahash_request *req)
 819 {
 820         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 821         int err1, err2;
 822
 823         ctx->flags |= BIT(FLAGS_FINUP);
 824
 825         err1 = omap_sham_update(req);
 826         if (err1 == -EINPROGRESS || err1 == -EBUSY)
 827                 return err1;
 828         /*
 829          * final() has to be always called to cleanup resources
 830          * even if udpate() failed, except EINPROGRESS
 831          */
 832         err2 = omap_sham_final(req);
 833
 834         return err1 ?: err2;
 835 }
 836
 837 static int omap_sham_digest(struct ahash_request *req)
 838 {
 839         return omap_sham_init(req) ?: omap_sham_finup(req);
 840 }
 841
 842 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
 843                       unsigned int keylen)
 844 {
 845         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 846         struct omap_sham_hmac_ctx *bctx = tctx->base;
 847         int bs = crypto_shash_blocksize(bctx->shash);
 848         int ds = crypto_shash_digestsize(bctx->shash);
 849         int err, i;
 850         err = crypto_shash_setkey(tctx->fallback, key, keylen);
 851         if (err)
 852                 return err;
 853
 854         if (keylen > bs) {
 855                 err = omap_sham_shash_digest(bctx->shash,
 856                                 crypto_shash_get_flags(bctx->shash),
 857                                 key, keylen, bctx->ipad);
 858                 if (err)
 859                         return err;
 860                 keylen = ds;
 861         } else {
 862                 memcpy(bctx->ipad, key, keylen);
 863         }
 864
 865         memset(bctx->ipad + keylen, 0, bs - keylen);
 866         memcpy(bctx->opad, bctx->ipad, bs);
 867
 868         for (i = 0; i < bs; i++) {
 869                 bctx->ipad[i] ^= 0x36;
 870                 bctx->opad[i] ^= 0x5c;
 871         }
 872
 873         return err;
 874 }
 875
 876 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
 877 {
 878         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
 879         const char *alg_name = crypto_tfm_alg_name(tfm);
 880
 881         /* Allocate a fallback and abort if it failed. */
 882         tctx->fallback = crypto_alloc_shash(alg_name, 0,
 883                                             CRYPTO_ALG_NEED_FALLBACK);
 884         if (IS_ERR(tctx->fallback)) {
 885                 pr_err("omap-sham: fallback driver '%s' "
 886                                 "could not be loaded.\n", alg_name);
 887                 return PTR_ERR(tctx->fallback);
 888         }
 889
 890         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
 891                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
 892
 893         if (alg_base) {
 894                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 895                 tctx->flags |= BIT(FLAGS_HMAC);
 896                 bctx->shash = crypto_alloc_shash(alg_base, 0,
 897                                                 CRYPTO_ALG_NEED_FALLBACK);
 898                 if (IS_ERR(bctx->shash)) {
 899                         pr_err("omap-sham: base driver '%s' "
 900                                         "could not be loaded.\n", alg_base);
 901                         crypto_free_shash(tctx->fallback);
 902                         return PTR_ERR(bctx->shash);
 903                 }
 904
 905         }
 906
 907         return 0;
 908 }
 909
 910 static int omap_sham_cra_init(struct crypto_tfm *tfm)
 911 {
 912         return omap_sham_cra_init_alg(tfm, NULL);
 913 }
 914
 915 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
 916 {
 917         return omap_sham_cra_init_alg(tfm, "sha1");
 918 }
 919
 920 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
 921 {
 922         return omap_sham_cra_init_alg(tfm, "md5");
 923 }
 924
 925 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
 926 {
 927         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
 928
 929         crypto_free_shash(tctx->fallback);
 930         tctx->fallback = NULL;
 931
 932         if (tctx->flags & BIT(FLAGS_HMAC)) {
 933                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 934                 crypto_free_shash(bctx->shash);
 935         }
 936 }
 937
 938 static struct ahash_alg algs[] = {
 939 {
 940         .init           = omap_sham_init,
 941         .update         = omap_sham_update,
 942         .final          = omap_sham_final,
 943         .finup          = omap_sham_finup,
 944         .digest         = omap_sham_digest,
 945         .halg.digestsize        = SHA1_DIGEST_SIZE,
 946         .halg.base      = {
 947                 .cra_name               = "sha1",
 948                 .cra_driver_name        = "omap-sha1",
 949                 .cra_priority           = 100,
 950                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
 951                                                 CRYPTO_ALG_ASYNC |
 952                                                 CRYPTO_ALG_NEED_FALLBACK,
 953                 .cra_blocksize          = SHA1_BLOCK_SIZE,
 954                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
 955                 .cra_alignmask          = 0,
 956                 .cra_module             = THIS_MODULE,
 957                 .cra_init               = omap_sham_cra_init,
 958                 .cra_exit               = omap_sham_cra_exit,
 959         }
 960 },
 961 {
 962         .init           = omap_sham_init,
 963         .update         = omap_sham_update,
 964         .final          = omap_sham_final,
 965         .finup          = omap_sham_finup,
 966         .digest         = omap_sham_digest,
 967         .halg.digestsize        = MD5_DIGEST_SIZE,
 968         .halg.base      = {
 969                 .cra_name               = "md5",
 970                 .cra_driver_name        = "omap-md5",
 971                 .cra_priority           = 100,
 972                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
 973                                                 CRYPTO_ALG_ASYNC |
 974                                                 CRYPTO_ALG_NEED_FALLBACK,
 975                 .cra_blocksize          = SHA1_BLOCK_SIZE,
 976                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
 977                 .cra_alignmask          = OMAP_ALIGN_MASK,
 978                 .cra_module             = THIS_MODULE,
 979                 .cra_init               = omap_sham_cra_init,
 980                 .cra_exit               = omap_sham_cra_exit,
 981         }
 982 },
 983 {
 984         .init           = omap_sham_init,
 985         .update         = omap_sham_update,
 986         .final          = omap_sham_final,
 987         .finup          = omap_sham_finup,
 988         .digest         = omap_sham_digest,
 989         .setkey         = omap_sham_setkey,
 990         .halg.digestsize        = SHA1_DIGEST_SIZE,
 991         .halg.base      = {
 992                 .cra_name               = "hmac(sha1)",
 993                 .cra_driver_name        = "omap-hmac-sha1",
 994                 .cra_priority           = 100,
 995                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
 996                                                 CRYPTO_ALG_ASYNC |
 997                                                 CRYPTO_ALG_NEED_FALLBACK,
 998                 .cra_blocksize          = SHA1_BLOCK_SIZE,
 999                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1000                                         sizeof(struct omap_sham_hmac_ctx),
1001                 .cra_alignmask          = OMAP_ALIGN_MASK,
1002                 .cra_module             = THIS_MODULE,
1003                 .cra_init               = omap_sham_cra_sha1_init,
1004                 .cra_exit               = omap_sham_cra_exit,
1005         }
1006 },
1007 {
1008         .init           = omap_sham_init,
1009         .update         = omap_sham_update,
1010         .final          = omap_sham_final,
1011         .finup          = omap_sham_finup,
1012         .digest         = omap_sham_digest,
1013         .setkey         = omap_sham_setkey,
1014         .halg.digestsize        = MD5_DIGEST_SIZE,
1015         .halg.base      = {
1016                 .cra_name               = "hmac(md5)",
1017                 .cra_driver_name        = "omap-hmac-md5",
1018                 .cra_priority           = 100,
1019                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1020                                                 CRYPTO_ALG_ASYNC |
1021                                                 CRYPTO_ALG_NEED_FALLBACK,
1022                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1023                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1024                                         sizeof(struct omap_sham_hmac_ctx),
1025                 .cra_alignmask          = OMAP_ALIGN_MASK,
1026                 .cra_module             = THIS_MODULE,
1027                 .cra_init               = omap_sham_cra_md5_init,
1028                 .cra_exit               = omap_sham_cra_exit,
1029         }
1030 }
1031 };
1032
1033 static void omap_sham_done_task(unsigned long data)
1034 {
1035         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1036         struct ahash_request *req = dd->req;
1037         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1038         int ready = 0, err = 0;
1039
1040         if (ctx->flags & BIT(FLAGS_OUTPUT_READY)) {
1041                 ctx->flags &= ~BIT(FLAGS_OUTPUT_READY);
1042                 ready = 1;
1043         }
1044
1045         if (dd->flags & BIT(FLAGS_DMA_ACTIVE)) {
1046                 dd->flags &= ~BIT(FLAGS_DMA_ACTIVE);
1047                 omap_sham_update_dma_stop(dd);
1048                 if (!dd->err)
1049                         err = omap_sham_update_dma_start(dd);
1050         }
1051
1052         err = dd->err ? : err;
1053
1054         if (err != -EINPROGRESS && (ready || err)) {
1055                 dev_dbg(dd->dev, "update done: err: %d\n", err);
1056                 /* finish curent request */
1057                 omap_sham_finish_req(req, err);
1058                 /* start new request */
1059                 omap_sham_handle_queue(dd, NULL);
1060         }
1061 }
1062
1063 static void omap_sham_queue_task(unsigned long data)
1064 {
1065         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1066
1067         omap_sham_handle_queue(dd, NULL);
1068 }
1069
1070 static irqreturn_t omap_sham_irq(int irq, void *dev_id)
1071 {
1072         struct omap_sham_dev *dd = dev_id;
1073         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
1074
1075         if (!ctx) {
1076                 dev_err(dd->dev, "unknown interrupt.\n");
1077                 return IRQ_HANDLED;
1078         }
1079
1080         if (unlikely(ctx->flags & BIT(FLAGS_FINAL)))
1081                 /* final -> allow device to go to power-saving mode */
1082                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1083
1084         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1085                                  SHA_REG_CTRL_OUTPUT_READY);
1086         omap_sham_read(dd, SHA_REG_CTRL);
1087
1088         ctx->flags |= BIT(FLAGS_OUTPUT_READY);
1089         dd->err = 0;
1090         tasklet_schedule(&dd->done_task);
1091
1092         return IRQ_HANDLED;
1093 }
1094
1095 static void omap_sham_dma_callback(int lch, u16 ch_status, void *data)
1096 {
1097         struct omap_sham_dev *dd = data;
1098
1099         if (ch_status != OMAP_DMA_BLOCK_IRQ) {
1100                 pr_err("omap-sham DMA error status: 0x%hx\n", ch_status);
1101                 dd->err = -EIO;
1102                 dd->flags &= ~BIT(FLAGS_INIT); /* request to re-initialize */
1103         }
1104
1105         tasklet_schedule(&dd->done_task);
1106 }
1107
1108 static int omap_sham_dma_init(struct omap_sham_dev *dd)
1109 {
1110         int err;
1111
1112         dd->dma_lch = -1;
1113
1114         err = omap_request_dma(dd->dma, dev_name(dd->dev),
1115                         omap_sham_dma_callback, dd, &dd->dma_lch);
1116         if (err) {
1117                 dev_err(dd->dev, "Unable to request DMA channel\n");
1118                 return err;
1119         }
1120
1121         return 0;
1122 }
1123
1124 static void omap_sham_dma_cleanup(struct omap_sham_dev *dd)
1125 {
1126         if (dd->dma_lch >= 0) {
1127                 omap_free_dma(dd->dma_lch);
1128                 dd->dma_lch = -1;
1129         }
1130 }
1131
1132 static int __devinit omap_sham_probe(struct platform_device *pdev)
1133 {
1134         struct omap_sham_dev *dd;
1135         struct device *dev = &pdev->dev;
1136         struct resource *res;
1137         int err, i, j;
1138
1139         dd = kzalloc(sizeof(struct omap_sham_dev), GFP_KERNEL);
1140         if (dd == NULL) {
1141                 dev_err(dev, "unable to alloc data struct.\n");
1142                 err = -ENOMEM;
1143                 goto data_err;
1144         }
1145         dd->dev = dev;
1146         platform_set_drvdata(pdev, dd);
1147
1148         INIT_LIST_HEAD(&dd->list);
1149         spin_lock_init(&dd->lock);
1150         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
1151         tasklet_init(&dd->queue_task, omap_sham_queue_task, (unsigned long)dd);
1152         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
1153
1154         dd->irq = -1;
1155
1156         /* Get the base address */
1157         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1158         if (!res) {
1159                 dev_err(dev, "no MEM resource info\n");
1160                 err = -ENODEV;
1161                 goto res_err;
1162         }
1163         dd->phys_base = res->start;
1164
1165         /* Get the DMA */
1166         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1167         if (!res) {
1168                 dev_err(dev, "no DMA resource info\n");
1169                 err = -ENODEV;
1170                 goto res_err;
1171         }
1172         dd->dma = res->start;
1173
1174         /* Get the IRQ */
1175         dd->irq = platform_get_irq(pdev,  0);
1176         if (dd->irq < 0) {
1177                 dev_err(dev, "no IRQ resource info\n");
1178                 err = dd->irq;
1179                 goto res_err;
1180         }
1181
1182         err = request_irq(dd->irq, omap_sham_irq,
1183                         IRQF_TRIGGER_LOW, dev_name(dev), dd);
1184         if (err) {
1185                 dev_err(dev, "unable to request irq.\n");
1186                 goto res_err;
1187         }
1188
1189         err = omap_sham_dma_init(dd);
1190         if (err)
1191                 goto dma_err;
1192
1193         /* Initializing the clock */
1194         dd->iclk = clk_get(dev, "ick");
1195         if (IS_ERR(dd->iclk)) {
1196                 dev_err(dev, "clock intialization failed.\n");
1197                 err = PTR_ERR(dd->iclk);
1198                 goto clk_err;
1199         }
1200
1201         dd->io_base = ioremap(dd->phys_base, SZ_4K);
1202         if (!dd->io_base) {
1203                 dev_err(dev, "can't ioremap\n");
1204                 err = -ENOMEM;
1205                 goto io_err;
1206         }
1207
1208         clk_enable(dd->iclk);
1209         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
1210                 (omap_sham_read(dd, SHA_REG_REV) & SHA_REG_REV_MAJOR) >> 4,
1211                 omap_sham_read(dd, SHA_REG_REV) & SHA_REG_REV_MINOR);
1212         clk_disable(dd->iclk);
1213
1214         spin_lock(&sham.lock);
1215         list_add_tail(&dd->list, &sham.dev_list);
1216         spin_unlock(&sham.lock);
1217
1218         for (i = 0; i < ARRAY_SIZE(algs); i++) {
1219                 err = crypto_register_ahash(&algs[i]);
1220                 if (err)
1221                         goto err_algs;
1222         }
1223
1224         return 0;
1225
1226 err_algs:
1227         for (j = 0; j < i; j++)
1228                 crypto_unregister_ahash(&algs[j]);
1229         iounmap(dd->io_base);
1230 io_err:
1231         clk_put(dd->iclk);
1232 clk_err:
1233         omap_sham_dma_cleanup(dd);
1234 dma_err:
1235         if (dd->irq >= 0)
1236                 free_irq(dd->irq, dd);
1237 res_err:
1238         kfree(dd);
1239         dd = NULL;
1240 data_err:
1241         dev_err(dev, "initialization failed.\n");
1242
1243         return err;
1244 }
1245
1246 static int __devexit omap_sham_remove(struct platform_device *pdev)
1247 {
1248         static struct omap_sham_dev *dd;
1249         int i;
1250
1251         dd = platform_get_drvdata(pdev);
1252         if (!dd)
1253                 return -ENODEV;
1254         spin_lock(&sham.lock);
1255         list_del(&dd->list);
1256         spin_unlock(&sham.lock);
1257         for (i = 0; i < ARRAY_SIZE(algs); i++)
1258                 crypto_unregister_ahash(&algs[i]);
1259         tasklet_kill(&dd->done_task);
1260         tasklet_kill(&dd->queue_task);
1261         iounmap(dd->io_base);
1262         clk_put(dd->iclk);
1263         omap_sham_dma_cleanup(dd);
1264         if (dd->irq >= 0)
1265                 free_irq(dd->irq, dd);
1266         kfree(dd);
1267         dd = NULL;
1268
1269         return 0;
1270 }
1271
1272 static struct platform_driver omap_sham_driver = {
1273         .probe  = omap_sham_probe,
1274         .remove = omap_sham_remove,
1275         .driver = {
1276                 .name   = "omap-sham",
1277                 .owner  = THIS_MODULE,
1278         },
1279 };
1280
1281 static int __init omap_sham_mod_init(void)
1282 {
1283         pr_info("loading %s driver\n", "omap-sham");
1284
1285         if (!cpu_class_is_omap2() ||
1286                 (omap_type() != OMAP2_DEVICE_TYPE_SEC &&
1287                         omap_type() != OMAP2_DEVICE_TYPE_EMU)) {
1288                 pr_err("Unsupported cpu\n");
1289                 return -ENODEV;
1290         }
1291
1292         return platform_driver_register(&omap_sham_driver);
1293 }
1294
1295 static void __exit omap_sham_mod_exit(void)
1296 {
1297         platform_driver_unregister(&omap_sham_driver);
1298 }
1299
1300 module_init(omap_sham_mod_init);
1301 module_exit(omap_sham_mod_exit);
1302
1303 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
1304 MODULE_LICENSE("GPL v2");
1305 MODULE_AUTHOR("Dmitry Kasatkin");