WAN: Use u32 type instead of u_int32_t in LMC driver.
[linux-2.6.git] / drivers / char / synclinkmp.c
1 /*
2  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
3  *
4  * Device driver for Microgate SyncLink Multiport
5  * high speed multiprotocol serial adapter.
6  *
7  * written by Paul Fulghum for Microgate Corporation
8  * paulkf@microgate.com
9  *
10  * Microgate and SyncLink are trademarks of Microgate Corporation
11  *
12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13  * This code is released under the GNU General Public License (GPL)
14  *
15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25  * OF THE POSSIBILITY OF SUCH DAMAGE.
26  */
27
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29 #if defined(__i386__)
30 #  define BREAKPOINT() asm("   int $3");
31 #else
32 #  define BREAKPOINT() { }
33 #endif
34
35 #define MAX_DEVICES 12
36
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
52 #include <linux/mm.h>
53 #include <linux/slab.h>
54 #include <linux/netdevice.h>
55 #include <linux/vmalloc.h>
56 #include <linux/init.h>
57 #include <linux/delay.h>
58 #include <linux/ioctl.h>
59
60 #include <asm/system.h>
61 #include <asm/io.h>
62 #include <asm/irq.h>
63 #include <asm/dma.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
70
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
73 #else
74 #define SYNCLINK_GENERIC_HDLC 0
75 #endif
76
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82 #include <asm/uaccess.h>
83
84 static MGSL_PARAMS default_params = {
85         MGSL_MODE_HDLC,                 /* unsigned long mode */
86         0,                              /* unsigned char loopback; */
87         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
88         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
89         0,                              /* unsigned long clock_speed; */
90         0xff,                           /* unsigned char addr_filter; */
91         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
92         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
93         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
94         9600,                           /* unsigned long data_rate; */
95         8,                              /* unsigned char data_bits; */
96         1,                              /* unsigned char stop_bits; */
97         ASYNC_PARITY_NONE               /* unsigned char parity; */
98 };
99
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE      1024
102 #define SCA_MEM_SIZE    0x40000
103 #define SCA_BASE_SIZE   512
104 #define SCA_REG_SIZE    16
105 #define SCA_MAX_PORTS   4
106 #define SCAMAXDESC      128
107
108 #define BUFFERLISTSIZE  4096
109
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
112 {
113         u16     next;           /* lower l6 bits of next descriptor addr */
114         u16     buf_ptr;        /* lower 16 bits of buffer addr */
115         u8      buf_base;       /* upper 8 bits of buffer addr */
116         u8      pad1;
117         u16     length;         /* length of buffer */
118         u8      status;         /* status of buffer */
119         u8      pad2;
120 } SCADESC, *PSCADESC;
121
122 typedef struct _SCADESC_EX
123 {
124         /* device driver bookkeeping section */
125         char    *virt_addr;     /* virtual address of data buffer */
126         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX, *PSCADESC_EX;
128
129 /* The queue of BH actions to be performed */
130
131 #define BH_RECEIVE  1
132 #define BH_TRANSMIT 2
133 #define BH_STATUS   4
134
135 #define IO_PIN_SHUTDOWN_LIMIT 100
136
137 struct  _input_signal_events {
138         int     ri_up;
139         int     ri_down;
140         int     dsr_up;
141         int     dsr_down;
142         int     dcd_up;
143         int     dcd_down;
144         int     cts_up;
145         int     cts_down;
146 };
147
148 /*
149  * Device instance data structure
150  */
151 typedef struct _synclinkmp_info {
152         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
153         int                     magic;
154         struct tty_port         port;
155         int                     line;
156         unsigned short          close_delay;
157         unsigned short          closing_wait;   /* time to wait before closing */
158
159         struct mgsl_icount      icount;
160
161         int                     timeout;
162         int                     x_char;         /* xon/xoff character */
163         u16                     read_status_mask1;  /* break detection (SR1 indications) */
164         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
165         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
166         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
167         unsigned char           *tx_buf;
168         int                     tx_put;
169         int                     tx_get;
170         int                     tx_count;
171
172         wait_queue_head_t       status_event_wait_q;
173         wait_queue_head_t       event_wait_q;
174         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
175         struct _synclinkmp_info *next_device;   /* device list link */
176         struct timer_list       status_timer;   /* input signal status check timer */
177
178         spinlock_t lock;                /* spinlock for synchronizing with ISR */
179         struct work_struct task;                        /* task structure for scheduling bh */
180
181         u32 max_frame_size;                     /* as set by device config */
182
183         u32 pending_bh;
184
185         bool bh_running;                                /* Protection from multiple */
186         int isr_overflow;
187         bool bh_requested;
188
189         int dcd_chkcount;                       /* check counts to prevent */
190         int cts_chkcount;                       /* too many IRQs if a signal */
191         int dsr_chkcount;                       /* is floating */
192         int ri_chkcount;
193
194         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
195         unsigned long buffer_list_phys;
196
197         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
198         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
199         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200         unsigned int current_rx_buf;
201
202         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
203         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
204         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205         unsigned int last_tx_buf;
206
207         unsigned char *tmp_rx_buf;
208         unsigned int tmp_rx_buf_count;
209
210         bool rx_enabled;
211         bool rx_overflow;
212
213         bool tx_enabled;
214         bool tx_active;
215         u32 idle_mode;
216
217         unsigned char ie0_value;
218         unsigned char ie1_value;
219         unsigned char ie2_value;
220         unsigned char ctrlreg_value;
221         unsigned char old_signals;
222
223         char device_name[25];                   /* device instance name */
224
225         int port_count;
226         int adapter_num;
227         int port_num;
228
229         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230
231         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
232
233         unsigned int irq_level;                 /* interrupt level */
234         unsigned long irq_flags;
235         bool irq_requested;                     /* true if IRQ requested */
236
237         MGSL_PARAMS params;                     /* communications parameters */
238
239         unsigned char serial_signals;           /* current serial signal states */
240
241         bool irq_occurred;                      /* for diagnostics use */
242         unsigned int init_error;                /* Initialization startup error */
243
244         u32 last_mem_alloc;
245         unsigned char* memory_base;             /* shared memory address (PCI only) */
246         u32 phys_memory_base;
247         int shared_mem_requested;
248
249         unsigned char* sca_base;                /* HD64570 SCA Memory address */
250         u32 phys_sca_base;
251         u32 sca_offset;
252         bool sca_base_requested;
253
254         unsigned char* lcr_base;                /* local config registers (PCI only) */
255         u32 phys_lcr_base;
256         u32 lcr_offset;
257         int lcr_mem_requested;
258
259         unsigned char* statctrl_base;           /* status/control register memory */
260         u32 phys_statctrl_base;
261         u32 statctrl_offset;
262         bool sca_statctrl_requested;
263
264         u32 misc_ctrl_value;
265         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
266         char char_buf[MAX_ASYNC_BUFFER_SIZE];
267         bool drop_rts_on_tx_done;
268
269         struct  _input_signal_events    input_signal_events;
270
271         /* SPPP/Cisco HDLC device parts */
272         int netcount;
273         spinlock_t netlock;
274
275 #if SYNCLINK_GENERIC_HDLC
276         struct net_device *netdev;
277 #endif
278
279 } SLMP_INFO;
280
281 #define MGSL_MAGIC 0x5401
282
283 /*
284  * define serial signal status change macros
285  */
286 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
287 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
288 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
289 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
290
291 /* Common Register macros */
292 #define LPR     0x00
293 #define PABR0   0x02
294 #define PABR1   0x03
295 #define WCRL    0x04
296 #define WCRM    0x05
297 #define WCRH    0x06
298 #define DPCR    0x08
299 #define DMER    0x09
300 #define ISR0    0x10
301 #define ISR1    0x11
302 #define ISR2    0x12
303 #define IER0    0x14
304 #define IER1    0x15
305 #define IER2    0x16
306 #define ITCR    0x18
307 #define INTVR   0x1a
308 #define IMVR    0x1c
309
310 /* MSCI Register macros */
311 #define TRB     0x20
312 #define TRBL    0x20
313 #define TRBH    0x21
314 #define SR0     0x22
315 #define SR1     0x23
316 #define SR2     0x24
317 #define SR3     0x25
318 #define FST     0x26
319 #define IE0     0x28
320 #define IE1     0x29
321 #define IE2     0x2a
322 #define FIE     0x2b
323 #define CMD     0x2c
324 #define MD0     0x2e
325 #define MD1     0x2f
326 #define MD2     0x30
327 #define CTL     0x31
328 #define SA0     0x32
329 #define SA1     0x33
330 #define IDL     0x34
331 #define TMC     0x35
332 #define RXS     0x36
333 #define TXS     0x37
334 #define TRC0    0x38
335 #define TRC1    0x39
336 #define RRC     0x3a
337 #define CST0    0x3c
338 #define CST1    0x3d
339
340 /* Timer Register Macros */
341 #define TCNT    0x60
342 #define TCNTL   0x60
343 #define TCNTH   0x61
344 #define TCONR   0x62
345 #define TCONRL  0x62
346 #define TCONRH  0x63
347 #define TMCS    0x64
348 #define TEPR    0x65
349
350 /* DMA Controller Register macros */
351 #define DARL    0x80
352 #define DARH    0x81
353 #define DARB    0x82
354 #define BAR     0x80
355 #define BARL    0x80
356 #define BARH    0x81
357 #define BARB    0x82
358 #define SAR     0x84
359 #define SARL    0x84
360 #define SARH    0x85
361 #define SARB    0x86
362 #define CPB     0x86
363 #define CDA     0x88
364 #define CDAL    0x88
365 #define CDAH    0x89
366 #define EDA     0x8a
367 #define EDAL    0x8a
368 #define EDAH    0x8b
369 #define BFL     0x8c
370 #define BFLL    0x8c
371 #define BFLH    0x8d
372 #define BCR     0x8e
373 #define BCRL    0x8e
374 #define BCRH    0x8f
375 #define DSR     0x90
376 #define DMR     0x91
377 #define FCT     0x93
378 #define DIR     0x94
379 #define DCMD    0x95
380
381 /* combine with timer or DMA register address */
382 #define TIMER0  0x00
383 #define TIMER1  0x08
384 #define TIMER2  0x10
385 #define TIMER3  0x18
386 #define RXDMA   0x00
387 #define TXDMA   0x20
388
389 /* SCA Command Codes */
390 #define NOOP            0x00
391 #define TXRESET         0x01
392 #define TXENABLE        0x02
393 #define TXDISABLE       0x03
394 #define TXCRCINIT       0x04
395 #define TXCRCEXCL       0x05
396 #define TXEOM           0x06
397 #define TXABORT         0x07
398 #define MPON            0x08
399 #define TXBUFCLR        0x09
400 #define RXRESET         0x11
401 #define RXENABLE        0x12
402 #define RXDISABLE       0x13
403 #define RXCRCINIT       0x14
404 #define RXREJECT        0x15
405 #define SEARCHMP        0x16
406 #define RXCRCEXCL       0x17
407 #define RXCRCCALC       0x18
408 #define CHRESET         0x21
409 #define HUNT            0x31
410
411 /* DMA command codes */
412 #define SWABORT         0x01
413 #define FEICLEAR        0x02
414
415 /* IE0 */
416 #define TXINTE          BIT7
417 #define RXINTE          BIT6
418 #define TXRDYE          BIT1
419 #define RXRDYE          BIT0
420
421 /* IE1 & SR1 */
422 #define UDRN    BIT7
423 #define IDLE    BIT6
424 #define SYNCD   BIT4
425 #define FLGD    BIT4
426 #define CCTS    BIT3
427 #define CDCD    BIT2
428 #define BRKD    BIT1
429 #define ABTD    BIT1
430 #define GAPD    BIT1
431 #define BRKE    BIT0
432 #define IDLD    BIT0
433
434 /* IE2 & SR2 */
435 #define EOM     BIT7
436 #define PMP     BIT6
437 #define SHRT    BIT6
438 #define PE      BIT5
439 #define ABT     BIT5
440 #define FRME    BIT4
441 #define RBIT    BIT4
442 #define OVRN    BIT3
443 #define CRCE    BIT2
444
445
446 /*
447  * Global linked list of SyncLink devices
448  */
449 static SLMP_INFO *synclinkmp_device_list = NULL;
450 static int synclinkmp_adapter_count = -1;
451 static int synclinkmp_device_count = 0;
452
453 /*
454  * Set this param to non-zero to load eax with the
455  * .text section address and breakpoint on module load.
456  * This is useful for use with gdb and add-symbol-file command.
457  */
458 static int break_on_load = 0;
459
460 /*
461  * Driver major number, defaults to zero to get auto
462  * assigned major number. May be forced as module parameter.
463  */
464 static int ttymajor = 0;
465
466 /*
467  * Array of user specified options for ISA adapters.
468  */
469 static int debug_level = 0;
470 static int maxframe[MAX_DEVICES] = {0,};
471
472 module_param(break_on_load, bool, 0);
473 module_param(ttymajor, int, 0);
474 module_param(debug_level, int, 0);
475 module_param_array(maxframe, int, NULL, 0);
476
477 static char *driver_name = "SyncLink MultiPort driver";
478 static char *driver_version = "$Revision: 4.38 $";
479
480 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
481 static void synclinkmp_remove_one(struct pci_dev *dev);
482
483 static struct pci_device_id synclinkmp_pci_tbl[] = {
484         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
485         { 0, }, /* terminate list */
486 };
487 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
488
489 MODULE_LICENSE("GPL");
490
491 static struct pci_driver synclinkmp_pci_driver = {
492         .name           = "synclinkmp",
493         .id_table       = synclinkmp_pci_tbl,
494         .probe          = synclinkmp_init_one,
495         .remove         = __devexit_p(synclinkmp_remove_one),
496 };
497
498
499 static struct tty_driver *serial_driver;
500
501 /* number of characters left in xmit buffer before we ask for more */
502 #define WAKEUP_CHARS 256
503
504
505 /* tty callbacks */
506
507 static int  open(struct tty_struct *tty, struct file * filp);
508 static void close(struct tty_struct *tty, struct file * filp);
509 static void hangup(struct tty_struct *tty);
510 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
511
512 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
513 static int put_char(struct tty_struct *tty, unsigned char ch);
514 static void send_xchar(struct tty_struct *tty, char ch);
515 static void wait_until_sent(struct tty_struct *tty, int timeout);
516 static int  write_room(struct tty_struct *tty);
517 static void flush_chars(struct tty_struct *tty);
518 static void flush_buffer(struct tty_struct *tty);
519 static void tx_hold(struct tty_struct *tty);
520 static void tx_release(struct tty_struct *tty);
521
522 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
523 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
524 static int  chars_in_buffer(struct tty_struct *tty);
525 static void throttle(struct tty_struct * tty);
526 static void unthrottle(struct tty_struct * tty);
527 static void set_break(struct tty_struct *tty, int break_state);
528
529 #if SYNCLINK_GENERIC_HDLC
530 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
531 static void hdlcdev_tx_done(SLMP_INFO *info);
532 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
533 static int  hdlcdev_init(SLMP_INFO *info);
534 static void hdlcdev_exit(SLMP_INFO *info);
535 #endif
536
537 /* ioctl handlers */
538
539 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
540 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
541 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
542 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
543 static int  set_txidle(SLMP_INFO *info, int idle_mode);
544 static int  tx_enable(SLMP_INFO *info, int enable);
545 static int  tx_abort(SLMP_INFO *info);
546 static int  rx_enable(SLMP_INFO *info, int enable);
547 static int  modem_input_wait(SLMP_INFO *info,int arg);
548 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
549 static int  tiocmget(struct tty_struct *tty, struct file *file);
550 static int  tiocmset(struct tty_struct *tty, struct file *file,
551                      unsigned int set, unsigned int clear);
552 static void set_break(struct tty_struct *tty, int break_state);
553
554 static void add_device(SLMP_INFO *info);
555 static void device_init(int adapter_num, struct pci_dev *pdev);
556 static int  claim_resources(SLMP_INFO *info);
557 static void release_resources(SLMP_INFO *info);
558
559 static int  startup(SLMP_INFO *info);
560 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
561 static void shutdown(SLMP_INFO *info);
562 static void program_hw(SLMP_INFO *info);
563 static void change_params(SLMP_INFO *info);
564
565 static bool init_adapter(SLMP_INFO *info);
566 static bool register_test(SLMP_INFO *info);
567 static bool irq_test(SLMP_INFO *info);
568 static bool loopback_test(SLMP_INFO *info);
569 static int  adapter_test(SLMP_INFO *info);
570 static bool memory_test(SLMP_INFO *info);
571
572 static void reset_adapter(SLMP_INFO *info);
573 static void reset_port(SLMP_INFO *info);
574 static void async_mode(SLMP_INFO *info);
575 static void hdlc_mode(SLMP_INFO *info);
576
577 static void rx_stop(SLMP_INFO *info);
578 static void rx_start(SLMP_INFO *info);
579 static void rx_reset_buffers(SLMP_INFO *info);
580 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
581 static bool rx_get_frame(SLMP_INFO *info);
582
583 static void tx_start(SLMP_INFO *info);
584 static void tx_stop(SLMP_INFO *info);
585 static void tx_load_fifo(SLMP_INFO *info);
586 static void tx_set_idle(SLMP_INFO *info);
587 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
588
589 static void get_signals(SLMP_INFO *info);
590 static void set_signals(SLMP_INFO *info);
591 static void enable_loopback(SLMP_INFO *info, int enable);
592 static void set_rate(SLMP_INFO *info, u32 data_rate);
593
594 static int  bh_action(SLMP_INFO *info);
595 static void bh_handler(struct work_struct *work);
596 static void bh_receive(SLMP_INFO *info);
597 static void bh_transmit(SLMP_INFO *info);
598 static void bh_status(SLMP_INFO *info);
599 static void isr_timer(SLMP_INFO *info);
600 static void isr_rxint(SLMP_INFO *info);
601 static void isr_rxrdy(SLMP_INFO *info);
602 static void isr_txint(SLMP_INFO *info);
603 static void isr_txrdy(SLMP_INFO *info);
604 static void isr_rxdmaok(SLMP_INFO *info);
605 static void isr_rxdmaerror(SLMP_INFO *info);
606 static void isr_txdmaok(SLMP_INFO *info);
607 static void isr_txdmaerror(SLMP_INFO *info);
608 static void isr_io_pin(SLMP_INFO *info, u16 status);
609
610 static int  alloc_dma_bufs(SLMP_INFO *info);
611 static void free_dma_bufs(SLMP_INFO *info);
612 static int  alloc_buf_list(SLMP_INFO *info);
613 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
614 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
615 static void free_tmp_rx_buf(SLMP_INFO *info);
616
617 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
618 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
619 static void tx_timeout(unsigned long context);
620 static void status_timeout(unsigned long context);
621
622 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
623 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
624 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
625 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
626 static unsigned char read_status_reg(SLMP_INFO * info);
627 static void write_control_reg(SLMP_INFO * info);
628
629
630 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
631 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
632 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
633
634 static u32 misc_ctrl_value = 0x007e4040;
635 static u32 lcr1_brdr_value = 0x00800028;
636
637 static u32 read_ahead_count = 8;
638
639 /* DPCR, DMA Priority Control
640  *
641  * 07..05  Not used, must be 0
642  * 04      BRC, bus release condition: 0=all transfers complete
643  *              1=release after 1 xfer on all channels
644  * 03      CCC, channel change condition: 0=every cycle
645  *              1=after each channel completes all xfers
646  * 02..00  PR<2..0>, priority 100=round robin
647  *
648  * 00000100 = 0x00
649  */
650 static unsigned char dma_priority = 0x04;
651
652 // Number of bytes that can be written to shared RAM
653 // in a single write operation
654 static u32 sca_pci_load_interval = 64;
655
656 /*
657  * 1st function defined in .text section. Calling this function in
658  * init_module() followed by a breakpoint allows a remote debugger
659  * (gdb) to get the .text address for the add-symbol-file command.
660  * This allows remote debugging of dynamically loadable modules.
661  */
662 static void* synclinkmp_get_text_ptr(void);
663 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
664
665 static inline int sanity_check(SLMP_INFO *info,
666                                char *name, const char *routine)
667 {
668 #ifdef SANITY_CHECK
669         static const char *badmagic =
670                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
671         static const char *badinfo =
672                 "Warning: null synclinkmp_struct for (%s) in %s\n";
673
674         if (!info) {
675                 printk(badinfo, name, routine);
676                 return 1;
677         }
678         if (info->magic != MGSL_MAGIC) {
679                 printk(badmagic, name, routine);
680                 return 1;
681         }
682 #else
683         if (!info)
684                 return 1;
685 #endif
686         return 0;
687 }
688
689 /**
690  * line discipline callback wrappers
691  *
692  * The wrappers maintain line discipline references
693  * while calling into the line discipline.
694  *
695  * ldisc_receive_buf  - pass receive data to line discipline
696  */
697
698 static void ldisc_receive_buf(struct tty_struct *tty,
699                               const __u8 *data, char *flags, int count)
700 {
701         struct tty_ldisc *ld;
702         if (!tty)
703                 return;
704         ld = tty_ldisc_ref(tty);
705         if (ld) {
706                 if (ld->ops->receive_buf)
707                         ld->ops->receive_buf(tty, data, flags, count);
708                 tty_ldisc_deref(ld);
709         }
710 }
711
712 /* tty callbacks */
713
714 /* Called when a port is opened.  Init and enable port.
715  */
716 static int open(struct tty_struct *tty, struct file *filp)
717 {
718         SLMP_INFO *info;
719         int retval, line;
720         unsigned long flags;
721
722         line = tty->index;
723         if ((line < 0) || (line >= synclinkmp_device_count)) {
724                 printk("%s(%d): open with invalid line #%d.\n",
725                         __FILE__,__LINE__,line);
726                 return -ENODEV;
727         }
728
729         info = synclinkmp_device_list;
730         while(info && info->line != line)
731                 info = info->next_device;
732         if (sanity_check(info, tty->name, "open"))
733                 return -ENODEV;
734         if ( info->init_error ) {
735                 printk("%s(%d):%s device is not allocated, init error=%d\n",
736                         __FILE__,__LINE__,info->device_name,info->init_error);
737                 return -ENODEV;
738         }
739
740         tty->driver_data = info;
741         info->port.tty = tty;
742
743         if (debug_level >= DEBUG_LEVEL_INFO)
744                 printk("%s(%d):%s open(), old ref count = %d\n",
745                          __FILE__,__LINE__,tty->driver->name, info->port.count);
746
747         /* If port is closing, signal caller to try again */
748         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
749                 if (info->port.flags & ASYNC_CLOSING)
750                         interruptible_sleep_on(&info->port.close_wait);
751                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
752                         -EAGAIN : -ERESTARTSYS);
753                 goto cleanup;
754         }
755
756         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
757
758         spin_lock_irqsave(&info->netlock, flags);
759         if (info->netcount) {
760                 retval = -EBUSY;
761                 spin_unlock_irqrestore(&info->netlock, flags);
762                 goto cleanup;
763         }
764         info->port.count++;
765         spin_unlock_irqrestore(&info->netlock, flags);
766
767         if (info->port.count == 1) {
768                 /* 1st open on this device, init hardware */
769                 retval = startup(info);
770                 if (retval < 0)
771                         goto cleanup;
772         }
773
774         retval = block_til_ready(tty, filp, info);
775         if (retval) {
776                 if (debug_level >= DEBUG_LEVEL_INFO)
777                         printk("%s(%d):%s block_til_ready() returned %d\n",
778                                  __FILE__,__LINE__, info->device_name, retval);
779                 goto cleanup;
780         }
781
782         if (debug_level >= DEBUG_LEVEL_INFO)
783                 printk("%s(%d):%s open() success\n",
784                          __FILE__,__LINE__, info->device_name);
785         retval = 0;
786
787 cleanup:
788         if (retval) {
789                 if (tty->count == 1)
790                         info->port.tty = NULL; /* tty layer will release tty struct */
791                 if(info->port.count)
792                         info->port.count--;
793         }
794
795         return retval;
796 }
797
798 /* Called when port is closed. Wait for remaining data to be
799  * sent. Disable port and free resources.
800  */
801 static void close(struct tty_struct *tty, struct file *filp)
802 {
803         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
804
805         if (sanity_check(info, tty->name, "close"))
806                 return;
807
808         if (debug_level >= DEBUG_LEVEL_INFO)
809                 printk("%s(%d):%s close() entry, count=%d\n",
810                          __FILE__,__LINE__, info->device_name, info->port.count);
811
812         if (!info->port.count)
813                 return;
814
815         if (tty_hung_up_p(filp))
816                 goto cleanup;
817
818         if ((tty->count == 1) && (info->port.count != 1)) {
819                 /*
820                  * tty->count is 1 and the tty structure will be freed.
821                  * info->port.count should be one in this case.
822                  * if it's not, correct it so that the port is shutdown.
823                  */
824                 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
825                        "info->port.count is %d\n",
826                          __FILE__,__LINE__, info->device_name, info->port.count);
827                 info->port.count = 1;
828         }
829
830         info->port.count--;
831
832         /* if at least one open remaining, leave hardware active */
833         if (info->port.count)
834                 goto cleanup;
835
836         info->port.flags |= ASYNC_CLOSING;
837
838         /* set tty->closing to notify line discipline to
839          * only process XON/XOFF characters. Only the N_TTY
840          * discipline appears to use this (ppp does not).
841          */
842         tty->closing = 1;
843
844         /* wait for transmit data to clear all layers */
845
846         if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
847                 if (debug_level >= DEBUG_LEVEL_INFO)
848                         printk("%s(%d):%s close() calling tty_wait_until_sent\n",
849                                  __FILE__,__LINE__, info->device_name );
850                 tty_wait_until_sent(tty, info->port.closing_wait);
851         }
852
853         if (info->port.flags & ASYNC_INITIALIZED)
854                 wait_until_sent(tty, info->timeout);
855
856         flush_buffer(tty);
857
858         tty_ldisc_flush(tty);
859
860         shutdown(info);
861
862         tty->closing = 0;
863         info->port.tty = NULL;
864
865         if (info->port.blocked_open) {
866                 if (info->port.close_delay) {
867                         msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
868                 }
869                 wake_up_interruptible(&info->port.open_wait);
870         }
871
872         info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
873
874         wake_up_interruptible(&info->port.close_wait);
875
876 cleanup:
877         if (debug_level >= DEBUG_LEVEL_INFO)
878                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
879                         tty->driver->name, info->port.count);
880 }
881
882 /* Called by tty_hangup() when a hangup is signaled.
883  * This is the same as closing all open descriptors for the port.
884  */
885 static void hangup(struct tty_struct *tty)
886 {
887         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
888
889         if (debug_level >= DEBUG_LEVEL_INFO)
890                 printk("%s(%d):%s hangup()\n",
891                          __FILE__,__LINE__, info->device_name );
892
893         if (sanity_check(info, tty->name, "hangup"))
894                 return;
895
896         flush_buffer(tty);
897         shutdown(info);
898
899         info->port.count = 0;
900         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
901         info->port.tty = NULL;
902
903         wake_up_interruptible(&info->port.open_wait);
904 }
905
906 /* Set new termios settings
907  */
908 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
909 {
910         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
911         unsigned long flags;
912
913         if (debug_level >= DEBUG_LEVEL_INFO)
914                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
915                         tty->driver->name );
916
917         change_params(info);
918
919         /* Handle transition to B0 status */
920         if (old_termios->c_cflag & CBAUD &&
921             !(tty->termios->c_cflag & CBAUD)) {
922                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
923                 spin_lock_irqsave(&info->lock,flags);
924                 set_signals(info);
925                 spin_unlock_irqrestore(&info->lock,flags);
926         }
927
928         /* Handle transition away from B0 status */
929         if (!(old_termios->c_cflag & CBAUD) &&
930             tty->termios->c_cflag & CBAUD) {
931                 info->serial_signals |= SerialSignal_DTR;
932                 if (!(tty->termios->c_cflag & CRTSCTS) ||
933                     !test_bit(TTY_THROTTLED, &tty->flags)) {
934                         info->serial_signals |= SerialSignal_RTS;
935                 }
936                 spin_lock_irqsave(&info->lock,flags);
937                 set_signals(info);
938                 spin_unlock_irqrestore(&info->lock,flags);
939         }
940
941         /* Handle turning off CRTSCTS */
942         if (old_termios->c_cflag & CRTSCTS &&
943             !(tty->termios->c_cflag & CRTSCTS)) {
944                 tty->hw_stopped = 0;
945                 tx_release(tty);
946         }
947 }
948
949 /* Send a block of data
950  *
951  * Arguments:
952  *
953  *      tty             pointer to tty information structure
954  *      buf             pointer to buffer containing send data
955  *      count           size of send data in bytes
956  *
957  * Return Value:        number of characters written
958  */
959 static int write(struct tty_struct *tty,
960                  const unsigned char *buf, int count)
961 {
962         int     c, ret = 0;
963         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
964         unsigned long flags;
965
966         if (debug_level >= DEBUG_LEVEL_INFO)
967                 printk("%s(%d):%s write() count=%d\n",
968                        __FILE__,__LINE__,info->device_name,count);
969
970         if (sanity_check(info, tty->name, "write"))
971                 goto cleanup;
972
973         if (!info->tx_buf)
974                 goto cleanup;
975
976         if (info->params.mode == MGSL_MODE_HDLC) {
977                 if (count > info->max_frame_size) {
978                         ret = -EIO;
979                         goto cleanup;
980                 }
981                 if (info->tx_active)
982                         goto cleanup;
983                 if (info->tx_count) {
984                         /* send accumulated data from send_char() calls */
985                         /* as frame and wait before accepting more data. */
986                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
987                         goto start;
988                 }
989                 ret = info->tx_count = count;
990                 tx_load_dma_buffer(info, buf, count);
991                 goto start;
992         }
993
994         for (;;) {
995                 c = min_t(int, count,
996                         min(info->max_frame_size - info->tx_count - 1,
997                             info->max_frame_size - info->tx_put));
998                 if (c <= 0)
999                         break;
1000                         
1001                 memcpy(info->tx_buf + info->tx_put, buf, c);
1002
1003                 spin_lock_irqsave(&info->lock,flags);
1004                 info->tx_put += c;
1005                 if (info->tx_put >= info->max_frame_size)
1006                         info->tx_put -= info->max_frame_size;
1007                 info->tx_count += c;
1008                 spin_unlock_irqrestore(&info->lock,flags);
1009
1010                 buf += c;
1011                 count -= c;
1012                 ret += c;
1013         }
1014
1015         if (info->params.mode == MGSL_MODE_HDLC) {
1016                 if (count) {
1017                         ret = info->tx_count = 0;
1018                         goto cleanup;
1019                 }
1020                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1021         }
1022 start:
1023         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1024                 spin_lock_irqsave(&info->lock,flags);
1025                 if (!info->tx_active)
1026                         tx_start(info);
1027                 spin_unlock_irqrestore(&info->lock,flags);
1028         }
1029
1030 cleanup:
1031         if (debug_level >= DEBUG_LEVEL_INFO)
1032                 printk( "%s(%d):%s write() returning=%d\n",
1033                         __FILE__,__LINE__,info->device_name,ret);
1034         return ret;
1035 }
1036
1037 /* Add a character to the transmit buffer.
1038  */
1039 static int put_char(struct tty_struct *tty, unsigned char ch)
1040 {
1041         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1042         unsigned long flags;
1043         int ret = 0;
1044
1045         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1046                 printk( "%s(%d):%s put_char(%d)\n",
1047                         __FILE__,__LINE__,info->device_name,ch);
1048         }
1049
1050         if (sanity_check(info, tty->name, "put_char"))
1051                 return 0;
1052
1053         if (!info->tx_buf)
1054                 return 0;
1055
1056         spin_lock_irqsave(&info->lock,flags);
1057
1058         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1059              !info->tx_active ) {
1060
1061                 if (info->tx_count < info->max_frame_size - 1) {
1062                         info->tx_buf[info->tx_put++] = ch;
1063                         if (info->tx_put >= info->max_frame_size)
1064                                 info->tx_put -= info->max_frame_size;
1065                         info->tx_count++;
1066                         ret = 1;
1067                 }
1068         }
1069
1070         spin_unlock_irqrestore(&info->lock,flags);
1071         return ret;
1072 }
1073
1074 /* Send a high-priority XON/XOFF character
1075  */
1076 static void send_xchar(struct tty_struct *tty, char ch)
1077 {
1078         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1079         unsigned long flags;
1080
1081         if (debug_level >= DEBUG_LEVEL_INFO)
1082                 printk("%s(%d):%s send_xchar(%d)\n",
1083                          __FILE__,__LINE__, info->device_name, ch );
1084
1085         if (sanity_check(info, tty->name, "send_xchar"))
1086                 return;
1087
1088         info->x_char = ch;
1089         if (ch) {
1090                 /* Make sure transmit interrupts are on */
1091                 spin_lock_irqsave(&info->lock,flags);
1092                 if (!info->tx_enabled)
1093                         tx_start(info);
1094                 spin_unlock_irqrestore(&info->lock,flags);
1095         }
1096 }
1097
1098 /* Wait until the transmitter is empty.
1099  */
1100 static void wait_until_sent(struct tty_struct *tty, int timeout)
1101 {
1102         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1103         unsigned long orig_jiffies, char_time;
1104
1105         if (!info )
1106                 return;
1107
1108         if (debug_level >= DEBUG_LEVEL_INFO)
1109                 printk("%s(%d):%s wait_until_sent() entry\n",
1110                          __FILE__,__LINE__, info->device_name );
1111
1112         if (sanity_check(info, tty->name, "wait_until_sent"))
1113                 return;
1114
1115         lock_kernel();
1116
1117         if (!(info->port.flags & ASYNC_INITIALIZED))
1118                 goto exit;
1119
1120         orig_jiffies = jiffies;
1121
1122         /* Set check interval to 1/5 of estimated time to
1123          * send a character, and make it at least 1. The check
1124          * interval should also be less than the timeout.
1125          * Note: use tight timings here to satisfy the NIST-PCTS.
1126          */
1127
1128         if ( info->params.data_rate ) {
1129                 char_time = info->timeout/(32 * 5);
1130                 if (!char_time)
1131                         char_time++;
1132         } else
1133                 char_time = 1;
1134
1135         if (timeout)
1136                 char_time = min_t(unsigned long, char_time, timeout);
1137
1138         if ( info->params.mode == MGSL_MODE_HDLC ) {
1139                 while (info->tx_active) {
1140                         msleep_interruptible(jiffies_to_msecs(char_time));
1141                         if (signal_pending(current))
1142                                 break;
1143                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1144                                 break;
1145                 }
1146         } else {
1147                 //TODO: determine if there is something similar to USC16C32
1148                 //      TXSTATUS_ALL_SENT status
1149                 while ( info->tx_active && info->tx_enabled) {
1150                         msleep_interruptible(jiffies_to_msecs(char_time));
1151                         if (signal_pending(current))
1152                                 break;
1153                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1154                                 break;
1155                 }
1156         }
1157
1158 exit:
1159         unlock_kernel();
1160         if (debug_level >= DEBUG_LEVEL_INFO)
1161                 printk("%s(%d):%s wait_until_sent() exit\n",
1162                          __FILE__,__LINE__, info->device_name );
1163 }
1164
1165 /* Return the count of free bytes in transmit buffer
1166  */
1167 static int write_room(struct tty_struct *tty)
1168 {
1169         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1170         int ret;
1171
1172         if (sanity_check(info, tty->name, "write_room"))
1173                 return 0;
1174
1175         lock_kernel();
1176         if (info->params.mode == MGSL_MODE_HDLC) {
1177                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1178         } else {
1179                 ret = info->max_frame_size - info->tx_count - 1;
1180                 if (ret < 0)
1181                         ret = 0;
1182         }
1183         unlock_kernel();
1184
1185         if (debug_level >= DEBUG_LEVEL_INFO)
1186                 printk("%s(%d):%s write_room()=%d\n",
1187                        __FILE__, __LINE__, info->device_name, ret);
1188
1189         return ret;
1190 }
1191
1192 /* enable transmitter and send remaining buffered characters
1193  */
1194 static void flush_chars(struct tty_struct *tty)
1195 {
1196         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1197         unsigned long flags;
1198
1199         if ( debug_level >= DEBUG_LEVEL_INFO )
1200                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1201                         __FILE__,__LINE__,info->device_name,info->tx_count);
1202
1203         if (sanity_check(info, tty->name, "flush_chars"))
1204                 return;
1205
1206         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1207             !info->tx_buf)
1208                 return;
1209
1210         if ( debug_level >= DEBUG_LEVEL_INFO )
1211                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1212                         __FILE__,__LINE__,info->device_name );
1213
1214         spin_lock_irqsave(&info->lock,flags);
1215
1216         if (!info->tx_active) {
1217                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1218                         info->tx_count ) {
1219                         /* operating in synchronous (frame oriented) mode */
1220                         /* copy data from circular tx_buf to */
1221                         /* transmit DMA buffer. */
1222                         tx_load_dma_buffer(info,
1223                                  info->tx_buf,info->tx_count);
1224                 }
1225                 tx_start(info);
1226         }
1227
1228         spin_unlock_irqrestore(&info->lock,flags);
1229 }
1230
1231 /* Discard all data in the send buffer
1232  */
1233 static void flush_buffer(struct tty_struct *tty)
1234 {
1235         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1236         unsigned long flags;
1237
1238         if (debug_level >= DEBUG_LEVEL_INFO)
1239                 printk("%s(%d):%s flush_buffer() entry\n",
1240                          __FILE__,__LINE__, info->device_name );
1241
1242         if (sanity_check(info, tty->name, "flush_buffer"))
1243                 return;
1244
1245         spin_lock_irqsave(&info->lock,flags);
1246         info->tx_count = info->tx_put = info->tx_get = 0;
1247         del_timer(&info->tx_timer);
1248         spin_unlock_irqrestore(&info->lock,flags);
1249
1250         tty_wakeup(tty);
1251 }
1252
1253 /* throttle (stop) transmitter
1254  */
1255 static void tx_hold(struct tty_struct *tty)
1256 {
1257         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1258         unsigned long flags;
1259
1260         if (sanity_check(info, tty->name, "tx_hold"))
1261                 return;
1262
1263         if ( debug_level >= DEBUG_LEVEL_INFO )
1264                 printk("%s(%d):%s tx_hold()\n",
1265                         __FILE__,__LINE__,info->device_name);
1266
1267         spin_lock_irqsave(&info->lock,flags);
1268         if (info->tx_enabled)
1269                 tx_stop(info);
1270         spin_unlock_irqrestore(&info->lock,flags);
1271 }
1272
1273 /* release (start) transmitter
1274  */
1275 static void tx_release(struct tty_struct *tty)
1276 {
1277         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1278         unsigned long flags;
1279
1280         if (sanity_check(info, tty->name, "tx_release"))
1281                 return;
1282
1283         if ( debug_level >= DEBUG_LEVEL_INFO )
1284                 printk("%s(%d):%s tx_release()\n",
1285                         __FILE__,__LINE__,info->device_name);
1286
1287         spin_lock_irqsave(&info->lock,flags);
1288         if (!info->tx_enabled)
1289                 tx_start(info);
1290         spin_unlock_irqrestore(&info->lock,flags);
1291 }
1292
1293 /* Service an IOCTL request
1294  *
1295  * Arguments:
1296  *
1297  *      tty     pointer to tty instance data
1298  *      file    pointer to associated file object for device
1299  *      cmd     IOCTL command code
1300  *      arg     command argument/context
1301  *
1302  * Return Value:        0 if success, otherwise error code
1303  */
1304 static int do_ioctl(struct tty_struct *tty, struct file *file,
1305                  unsigned int cmd, unsigned long arg)
1306 {
1307         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1308         int error;
1309         struct mgsl_icount cnow;        /* kernel counter temps */
1310         struct serial_icounter_struct __user *p_cuser;  /* user space */
1311         unsigned long flags;
1312         void __user *argp = (void __user *)arg;
1313
1314         if (debug_level >= DEBUG_LEVEL_INFO)
1315                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1316                         info->device_name, cmd );
1317
1318         if (sanity_check(info, tty->name, "ioctl"))
1319                 return -ENODEV;
1320
1321         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1322             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1323                 if (tty->flags & (1 << TTY_IO_ERROR))
1324                     return -EIO;
1325         }
1326
1327         switch (cmd) {
1328         case MGSL_IOCGPARAMS:
1329                 return get_params(info, argp);
1330         case MGSL_IOCSPARAMS:
1331                 return set_params(info, argp);
1332         case MGSL_IOCGTXIDLE:
1333                 return get_txidle(info, argp);
1334         case MGSL_IOCSTXIDLE:
1335                 return set_txidle(info, (int)arg);
1336         case MGSL_IOCTXENABLE:
1337                 return tx_enable(info, (int)arg);
1338         case MGSL_IOCRXENABLE:
1339                 return rx_enable(info, (int)arg);
1340         case MGSL_IOCTXABORT:
1341                 return tx_abort(info);
1342         case MGSL_IOCGSTATS:
1343                 return get_stats(info, argp);
1344         case MGSL_IOCWAITEVENT:
1345                 return wait_mgsl_event(info, argp);
1346         case MGSL_IOCLOOPTXDONE:
1347                 return 0; // TODO: Not supported, need to document
1348                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1349                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1350                  */
1351         case TIOCMIWAIT:
1352                 return modem_input_wait(info,(int)arg);
1353                 
1354                 /*
1355                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1356                  * Return: write counters to the user passed counter struct
1357                  * NB: both 1->0 and 0->1 transitions are counted except for
1358                  *     RI where only 0->1 is counted.
1359                  */
1360         case TIOCGICOUNT:
1361                 spin_lock_irqsave(&info->lock,flags);
1362                 cnow = info->icount;
1363                 spin_unlock_irqrestore(&info->lock,flags);
1364                 p_cuser = argp;
1365                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1366                 if (error) return error;
1367                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1368                 if (error) return error;
1369                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1370                 if (error) return error;
1371                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1372                 if (error) return error;
1373                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1374                 if (error) return error;
1375                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1376                 if (error) return error;
1377                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1378                 if (error) return error;
1379                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1380                 if (error) return error;
1381                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1382                 if (error) return error;
1383                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1384                 if (error) return error;
1385                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1386                 if (error) return error;
1387                 return 0;
1388         default:
1389                 return -ENOIOCTLCMD;
1390         }
1391         return 0;
1392 }
1393
1394 static int ioctl(struct tty_struct *tty, struct file *file,
1395                  unsigned int cmd, unsigned long arg)
1396 {
1397         int ret;
1398         lock_kernel();
1399         ret = do_ioctl(tty, file, cmd, arg);
1400         unlock_kernel();
1401         return ret;
1402 }
1403
1404 /*
1405  * /proc fs routines....
1406  */
1407
1408 static inline int line_info(char *buf, SLMP_INFO *info)
1409 {
1410         char    stat_buf[30];
1411         int     ret;
1412         unsigned long flags;
1413
1414         ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1415                        "\tIRQ=%d MaxFrameSize=%u\n",
1416                 info->device_name,
1417                 info->phys_sca_base,
1418                 info->phys_memory_base,
1419                 info->phys_statctrl_base,
1420                 info->phys_lcr_base,
1421                 info->irq_level,
1422                 info->max_frame_size );
1423
1424         /* output current serial signal states */
1425         spin_lock_irqsave(&info->lock,flags);
1426         get_signals(info);
1427         spin_unlock_irqrestore(&info->lock,flags);
1428
1429         stat_buf[0] = 0;
1430         stat_buf[1] = 0;
1431         if (info->serial_signals & SerialSignal_RTS)
1432                 strcat(stat_buf, "|RTS");
1433         if (info->serial_signals & SerialSignal_CTS)
1434                 strcat(stat_buf, "|CTS");
1435         if (info->serial_signals & SerialSignal_DTR)
1436                 strcat(stat_buf, "|DTR");
1437         if (info->serial_signals & SerialSignal_DSR)
1438                 strcat(stat_buf, "|DSR");
1439         if (info->serial_signals & SerialSignal_DCD)
1440                 strcat(stat_buf, "|CD");
1441         if (info->serial_signals & SerialSignal_RI)
1442                 strcat(stat_buf, "|RI");
1443
1444         if (info->params.mode == MGSL_MODE_HDLC) {
1445                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1446                               info->icount.txok, info->icount.rxok);
1447                 if (info->icount.txunder)
1448                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1449                 if (info->icount.txabort)
1450                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1451                 if (info->icount.rxshort)
1452                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1453                 if (info->icount.rxlong)
1454                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1455                 if (info->icount.rxover)
1456                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1457                 if (info->icount.rxcrc)
1458                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1459         } else {
1460                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1461                               info->icount.tx, info->icount.rx);
1462                 if (info->icount.frame)
1463                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1464                 if (info->icount.parity)
1465                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1466                 if (info->icount.brk)
1467                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1468                 if (info->icount.overrun)
1469                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1470         }
1471
1472         /* Append serial signal status to end */
1473         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1474
1475         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1476          info->tx_active,info->bh_requested,info->bh_running,
1477          info->pending_bh);
1478
1479         return ret;
1480 }
1481
1482 /* Called to print information about devices
1483  */
1484 static int read_proc(char *page, char **start, off_t off, int count,
1485               int *eof, void *data)
1486 {
1487         int len = 0, l;
1488         off_t   begin = 0;
1489         SLMP_INFO *info;
1490
1491         len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1492
1493         info = synclinkmp_device_list;
1494         while( info ) {
1495                 l = line_info(page + len, info);
1496                 len += l;
1497                 if (len+begin > off+count)
1498                         goto done;
1499                 if (len+begin < off) {
1500                         begin += len;
1501                         len = 0;
1502                 }
1503                 info = info->next_device;
1504         }
1505
1506         *eof = 1;
1507 done:
1508         if (off >= len+begin)
1509                 return 0;
1510         *start = page + (off-begin);
1511         return ((count < begin+len-off) ? count : begin+len-off);
1512 }
1513
1514 /* Return the count of bytes in transmit buffer
1515  */
1516 static int chars_in_buffer(struct tty_struct *tty)
1517 {
1518         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1519
1520         if (sanity_check(info, tty->name, "chars_in_buffer"))
1521                 return 0;
1522
1523         if (debug_level >= DEBUG_LEVEL_INFO)
1524                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1525                        __FILE__, __LINE__, info->device_name, info->tx_count);
1526
1527         return info->tx_count;
1528 }
1529
1530 /* Signal remote device to throttle send data (our receive data)
1531  */
1532 static void throttle(struct tty_struct * tty)
1533 {
1534         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1535         unsigned long flags;
1536
1537         if (debug_level >= DEBUG_LEVEL_INFO)
1538                 printk("%s(%d):%s throttle() entry\n",
1539                          __FILE__,__LINE__, info->device_name );
1540
1541         if (sanity_check(info, tty->name, "throttle"))
1542                 return;
1543
1544         if (I_IXOFF(tty))
1545                 send_xchar(tty, STOP_CHAR(tty));
1546
1547         if (tty->termios->c_cflag & CRTSCTS) {
1548                 spin_lock_irqsave(&info->lock,flags);
1549                 info->serial_signals &= ~SerialSignal_RTS;
1550                 set_signals(info);
1551                 spin_unlock_irqrestore(&info->lock,flags);
1552         }
1553 }
1554
1555 /* Signal remote device to stop throttling send data (our receive data)
1556  */
1557 static void unthrottle(struct tty_struct * tty)
1558 {
1559         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1560         unsigned long flags;
1561
1562         if (debug_level >= DEBUG_LEVEL_INFO)
1563                 printk("%s(%d):%s unthrottle() entry\n",
1564                          __FILE__,__LINE__, info->device_name );
1565
1566         if (sanity_check(info, tty->name, "unthrottle"))
1567                 return;
1568
1569         if (I_IXOFF(tty)) {
1570                 if (info->x_char)
1571                         info->x_char = 0;
1572                 else
1573                         send_xchar(tty, START_CHAR(tty));
1574         }
1575
1576         if (tty->termios->c_cflag & CRTSCTS) {
1577                 spin_lock_irqsave(&info->lock,flags);
1578                 info->serial_signals |= SerialSignal_RTS;
1579                 set_signals(info);
1580                 spin_unlock_irqrestore(&info->lock,flags);
1581         }
1582 }
1583
1584 /* set or clear transmit break condition
1585  * break_state  -1=set break condition, 0=clear
1586  */
1587 static void set_break(struct tty_struct *tty, int break_state)
1588 {
1589         unsigned char RegValue;
1590         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1591         unsigned long flags;
1592
1593         if (debug_level >= DEBUG_LEVEL_INFO)
1594                 printk("%s(%d):%s set_break(%d)\n",
1595                          __FILE__,__LINE__, info->device_name, break_state);
1596
1597         if (sanity_check(info, tty->name, "set_break"))
1598                 return;
1599
1600         spin_lock_irqsave(&info->lock,flags);
1601         RegValue = read_reg(info, CTL);
1602         if (break_state == -1)
1603                 RegValue |= BIT3;
1604         else
1605                 RegValue &= ~BIT3;
1606         write_reg(info, CTL, RegValue);
1607         spin_unlock_irqrestore(&info->lock,flags);
1608 }
1609
1610 #if SYNCLINK_GENERIC_HDLC
1611
1612 /**
1613  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1614  * set encoding and frame check sequence (FCS) options
1615  *
1616  * dev       pointer to network device structure
1617  * encoding  serial encoding setting
1618  * parity    FCS setting
1619  *
1620  * returns 0 if success, otherwise error code
1621  */
1622 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1623                           unsigned short parity)
1624 {
1625         SLMP_INFO *info = dev_to_port(dev);
1626         unsigned char  new_encoding;
1627         unsigned short new_crctype;
1628
1629         /* return error if TTY interface open */
1630         if (info->port.count)
1631                 return -EBUSY;
1632
1633         switch (encoding)
1634         {
1635         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1636         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1637         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1638         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1639         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1640         default: return -EINVAL;
1641         }
1642
1643         switch (parity)
1644         {
1645         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1646         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1647         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1648         default: return -EINVAL;
1649         }
1650
1651         info->params.encoding = new_encoding;
1652         info->params.crc_type = new_crctype;
1653
1654         /* if network interface up, reprogram hardware */
1655         if (info->netcount)
1656                 program_hw(info);
1657
1658         return 0;
1659 }
1660
1661 /**
1662  * called by generic HDLC layer to send frame
1663  *
1664  * skb  socket buffer containing HDLC frame
1665  * dev  pointer to network device structure
1666  *
1667  * returns 0 if success, otherwise error code
1668  */
1669 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1670 {
1671         SLMP_INFO *info = dev_to_port(dev);
1672         unsigned long flags;
1673
1674         if (debug_level >= DEBUG_LEVEL_INFO)
1675                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1676
1677         /* stop sending until this frame completes */
1678         netif_stop_queue(dev);
1679
1680         /* copy data to device buffers */
1681         info->tx_count = skb->len;
1682         tx_load_dma_buffer(info, skb->data, skb->len);
1683
1684         /* update network statistics */
1685         dev->stats.tx_packets++;
1686         dev->stats.tx_bytes += skb->len;
1687
1688         /* done with socket buffer, so free it */
1689         dev_kfree_skb(skb);
1690
1691         /* save start time for transmit timeout detection */
1692         dev->trans_start = jiffies;
1693
1694         /* start hardware transmitter if necessary */
1695         spin_lock_irqsave(&info->lock,flags);
1696         if (!info->tx_active)
1697                 tx_start(info);
1698         spin_unlock_irqrestore(&info->lock,flags);
1699
1700         return 0;
1701 }
1702
1703 /**
1704  * called by network layer when interface enabled
1705  * claim resources and initialize hardware
1706  *
1707  * dev  pointer to network device structure
1708  *
1709  * returns 0 if success, otherwise error code
1710  */
1711 static int hdlcdev_open(struct net_device *dev)
1712 {
1713         SLMP_INFO *info = dev_to_port(dev);
1714         int rc;
1715         unsigned long flags;
1716
1717         if (debug_level >= DEBUG_LEVEL_INFO)
1718                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1719
1720         /* generic HDLC layer open processing */
1721         if ((rc = hdlc_open(dev)))
1722                 return rc;
1723
1724         /* arbitrate between network and tty opens */
1725         spin_lock_irqsave(&info->netlock, flags);
1726         if (info->port.count != 0 || info->netcount != 0) {
1727                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1728                 spin_unlock_irqrestore(&info->netlock, flags);
1729                 return -EBUSY;
1730         }
1731         info->netcount=1;
1732         spin_unlock_irqrestore(&info->netlock, flags);
1733
1734         /* claim resources and init adapter */
1735         if ((rc = startup(info)) != 0) {
1736                 spin_lock_irqsave(&info->netlock, flags);
1737                 info->netcount=0;
1738                 spin_unlock_irqrestore(&info->netlock, flags);
1739                 return rc;
1740         }
1741
1742         /* assert DTR and RTS, apply hardware settings */
1743         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1744         program_hw(info);
1745
1746         /* enable network layer transmit */
1747         dev->trans_start = jiffies;
1748         netif_start_queue(dev);
1749
1750         /* inform generic HDLC layer of current DCD status */
1751         spin_lock_irqsave(&info->lock, flags);
1752         get_signals(info);
1753         spin_unlock_irqrestore(&info->lock, flags);
1754         if (info->serial_signals & SerialSignal_DCD)
1755                 netif_carrier_on(dev);
1756         else
1757                 netif_carrier_off(dev);
1758         return 0;
1759 }
1760
1761 /**
1762  * called by network layer when interface is disabled
1763  * shutdown hardware and release resources
1764  *
1765  * dev  pointer to network device structure
1766  *
1767  * returns 0 if success, otherwise error code
1768  */
1769 static int hdlcdev_close(struct net_device *dev)
1770 {
1771         SLMP_INFO *info = dev_to_port(dev);
1772         unsigned long flags;
1773
1774         if (debug_level >= DEBUG_LEVEL_INFO)
1775                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1776
1777         netif_stop_queue(dev);
1778
1779         /* shutdown adapter and release resources */
1780         shutdown(info);
1781
1782         hdlc_close(dev);
1783
1784         spin_lock_irqsave(&info->netlock, flags);
1785         info->netcount=0;
1786         spin_unlock_irqrestore(&info->netlock, flags);
1787
1788         return 0;
1789 }
1790
1791 /**
1792  * called by network layer to process IOCTL call to network device
1793  *
1794  * dev  pointer to network device structure
1795  * ifr  pointer to network interface request structure
1796  * cmd  IOCTL command code
1797  *
1798  * returns 0 if success, otherwise error code
1799  */
1800 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1801 {
1802         const size_t size = sizeof(sync_serial_settings);
1803         sync_serial_settings new_line;
1804         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1805         SLMP_INFO *info = dev_to_port(dev);
1806         unsigned int flags;
1807
1808         if (debug_level >= DEBUG_LEVEL_INFO)
1809                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1810
1811         /* return error if TTY interface open */
1812         if (info->port.count)
1813                 return -EBUSY;
1814
1815         if (cmd != SIOCWANDEV)
1816                 return hdlc_ioctl(dev, ifr, cmd);
1817
1818         switch(ifr->ifr_settings.type) {
1819         case IF_GET_IFACE: /* return current sync_serial_settings */
1820
1821                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1822                 if (ifr->ifr_settings.size < size) {
1823                         ifr->ifr_settings.size = size; /* data size wanted */
1824                         return -ENOBUFS;
1825                 }
1826
1827                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1828                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1829                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1830                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1831
1832                 switch (flags){
1833                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1834                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1835                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1836                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1837                 default: new_line.clock_type = CLOCK_DEFAULT;
1838                 }
1839
1840                 new_line.clock_rate = info->params.clock_speed;
1841                 new_line.loopback   = info->params.loopback ? 1:0;
1842
1843                 if (copy_to_user(line, &new_line, size))
1844                         return -EFAULT;
1845                 return 0;
1846
1847         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1848
1849                 if(!capable(CAP_NET_ADMIN))
1850                         return -EPERM;
1851                 if (copy_from_user(&new_line, line, size))
1852                         return -EFAULT;
1853
1854                 switch (new_line.clock_type)
1855                 {
1856                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1857                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1858                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1859                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1860                 case CLOCK_DEFAULT:  flags = info->params.flags &
1861                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1862                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1863                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1864                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1865                 default: return -EINVAL;
1866                 }
1867
1868                 if (new_line.loopback != 0 && new_line.loopback != 1)
1869                         return -EINVAL;
1870
1871                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1872                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1873                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1874                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1875                 info->params.flags |= flags;
1876
1877                 info->params.loopback = new_line.loopback;
1878
1879                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1880                         info->params.clock_speed = new_line.clock_rate;
1881                 else
1882                         info->params.clock_speed = 0;
1883
1884                 /* if network interface up, reprogram hardware */
1885                 if (info->netcount)
1886                         program_hw(info);
1887                 return 0;
1888
1889         default:
1890                 return hdlc_ioctl(dev, ifr, cmd);
1891         }
1892 }
1893
1894 /**
1895  * called by network layer when transmit timeout is detected
1896  *
1897  * dev  pointer to network device structure
1898  */
1899 static void hdlcdev_tx_timeout(struct net_device *dev)
1900 {
1901         SLMP_INFO *info = dev_to_port(dev);
1902         unsigned long flags;
1903
1904         if (debug_level >= DEBUG_LEVEL_INFO)
1905                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1906
1907         dev->stats.tx_errors++;
1908         dev->stats.tx_aborted_errors++;
1909
1910         spin_lock_irqsave(&info->lock,flags);
1911         tx_stop(info);
1912         spin_unlock_irqrestore(&info->lock,flags);
1913
1914         netif_wake_queue(dev);
1915 }
1916
1917 /**
1918  * called by device driver when transmit completes
1919  * reenable network layer transmit if stopped
1920  *
1921  * info  pointer to device instance information
1922  */
1923 static void hdlcdev_tx_done(SLMP_INFO *info)
1924 {
1925         if (netif_queue_stopped(info->netdev))
1926                 netif_wake_queue(info->netdev);
1927 }
1928
1929 /**
1930  * called by device driver when frame received
1931  * pass frame to network layer
1932  *
1933  * info  pointer to device instance information
1934  * buf   pointer to buffer contianing frame data
1935  * size  count of data bytes in buf
1936  */
1937 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1938 {
1939         struct sk_buff *skb = dev_alloc_skb(size);
1940         struct net_device *dev = info->netdev;
1941
1942         if (debug_level >= DEBUG_LEVEL_INFO)
1943                 printk("hdlcdev_rx(%s)\n",dev->name);
1944
1945         if (skb == NULL) {
1946                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1947                        dev->name);
1948                 dev->stats.rx_dropped++;
1949                 return;
1950         }
1951
1952         memcpy(skb_put(skb, size), buf, size);
1953
1954         skb->protocol = hdlc_type_trans(skb, dev);
1955
1956         dev->stats.rx_packets++;
1957         dev->stats.rx_bytes += size;
1958
1959         netif_rx(skb);
1960
1961         dev->last_rx = jiffies;
1962 }
1963
1964 /**
1965  * called by device driver when adding device instance
1966  * do generic HDLC initialization
1967  *
1968  * info  pointer to device instance information
1969  *
1970  * returns 0 if success, otherwise error code
1971  */
1972 static int hdlcdev_init(SLMP_INFO *info)
1973 {
1974         int rc;
1975         struct net_device *dev;
1976         hdlc_device *hdlc;
1977
1978         /* allocate and initialize network and HDLC layer objects */
1979
1980         if (!(dev = alloc_hdlcdev(info))) {
1981                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1982                 return -ENOMEM;
1983         }
1984
1985         /* for network layer reporting purposes only */
1986         dev->mem_start = info->phys_sca_base;
1987         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1988         dev->irq       = info->irq_level;
1989
1990         /* network layer callbacks and settings */
1991         dev->do_ioctl       = hdlcdev_ioctl;
1992         dev->open           = hdlcdev_open;
1993         dev->stop           = hdlcdev_close;
1994         dev->tx_timeout     = hdlcdev_tx_timeout;
1995         dev->watchdog_timeo = 10*HZ;
1996         dev->tx_queue_len   = 50;
1997
1998         /* generic HDLC layer callbacks and settings */
1999         hdlc         = dev_to_hdlc(dev);
2000         hdlc->attach = hdlcdev_attach;
2001         hdlc->xmit   = hdlcdev_xmit;
2002
2003         /* register objects with HDLC layer */
2004         if ((rc = register_hdlc_device(dev))) {
2005                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2006                 free_netdev(dev);
2007                 return rc;
2008         }
2009
2010         info->netdev = dev;
2011         return 0;
2012 }
2013
2014 /**
2015  * called by device driver when removing device instance
2016  * do generic HDLC cleanup
2017  *
2018  * info  pointer to device instance information
2019  */
2020 static void hdlcdev_exit(SLMP_INFO *info)
2021 {
2022         unregister_hdlc_device(info->netdev);
2023         free_netdev(info->netdev);
2024         info->netdev = NULL;
2025 }
2026
2027 #endif /* CONFIG_HDLC */
2028
2029
2030 /* Return next bottom half action to perform.
2031  * Return Value:        BH action code or 0 if nothing to do.
2032  */
2033 static int bh_action(SLMP_INFO *info)
2034 {
2035         unsigned long flags;
2036         int rc = 0;
2037
2038         spin_lock_irqsave(&info->lock,flags);
2039
2040         if (info->pending_bh & BH_RECEIVE) {
2041                 info->pending_bh &= ~BH_RECEIVE;
2042                 rc = BH_RECEIVE;
2043         } else if (info->pending_bh & BH_TRANSMIT) {
2044                 info->pending_bh &= ~BH_TRANSMIT;
2045                 rc = BH_TRANSMIT;
2046         } else if (info->pending_bh & BH_STATUS) {
2047                 info->pending_bh &= ~BH_STATUS;
2048                 rc = BH_STATUS;
2049         }
2050
2051         if (!rc) {
2052                 /* Mark BH routine as complete */
2053                 info->bh_running = false;
2054                 info->bh_requested = false;
2055         }
2056
2057         spin_unlock_irqrestore(&info->lock,flags);
2058
2059         return rc;
2060 }
2061
2062 /* Perform bottom half processing of work items queued by ISR.
2063  */
2064 static void bh_handler(struct work_struct *work)
2065 {
2066         SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2067         int action;
2068
2069         if (!info)
2070                 return;
2071
2072         if ( debug_level >= DEBUG_LEVEL_BH )
2073                 printk( "%s(%d):%s bh_handler() entry\n",
2074                         __FILE__,__LINE__,info->device_name);
2075
2076         info->bh_running = true;
2077
2078         while((action = bh_action(info)) != 0) {
2079
2080                 /* Process work item */
2081                 if ( debug_level >= DEBUG_LEVEL_BH )
2082                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2083                                 __FILE__,__LINE__,info->device_name, action);
2084
2085                 switch (action) {
2086
2087                 case BH_RECEIVE:
2088                         bh_receive(info);
2089                         break;
2090                 case BH_TRANSMIT:
2091                         bh_transmit(info);
2092                         break;
2093                 case BH_STATUS:
2094                         bh_status(info);
2095                         break;
2096                 default:
2097                         /* unknown work item ID */
2098                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2099                                 __FILE__,__LINE__,info->device_name,action);
2100                         break;
2101                 }
2102         }
2103
2104         if ( debug_level >= DEBUG_LEVEL_BH )
2105                 printk( "%s(%d):%s bh_handler() exit\n",
2106                         __FILE__,__LINE__,info->device_name);
2107 }
2108
2109 static void bh_receive(SLMP_INFO *info)
2110 {
2111         if ( debug_level >= DEBUG_LEVEL_BH )
2112                 printk( "%s(%d):%s bh_receive()\n",
2113                         __FILE__,__LINE__,info->device_name);
2114
2115         while( rx_get_frame(info) );
2116 }
2117
2118 static void bh_transmit(SLMP_INFO *info)
2119 {
2120         struct tty_struct *tty = info->port.tty;
2121
2122         if ( debug_level >= DEBUG_LEVEL_BH )
2123                 printk( "%s(%d):%s bh_transmit() entry\n",
2124                         __FILE__,__LINE__,info->device_name);
2125
2126         if (tty)
2127                 tty_wakeup(tty);
2128 }
2129
2130 static void bh_status(SLMP_INFO *info)
2131 {
2132         if ( debug_level >= DEBUG_LEVEL_BH )
2133                 printk( "%s(%d):%s bh_status() entry\n",
2134                         __FILE__,__LINE__,info->device_name);
2135
2136         info->ri_chkcount = 0;
2137         info->dsr_chkcount = 0;
2138         info->dcd_chkcount = 0;
2139         info->cts_chkcount = 0;
2140 }
2141
2142 static void isr_timer(SLMP_INFO * info)
2143 {
2144         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2145
2146         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2147         write_reg(info, IER2, 0);
2148
2149         /* TMCS, Timer Control/Status Register
2150          *
2151          * 07      CMF, Compare match flag (read only) 1=match
2152          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2153          * 05      Reserved, must be 0
2154          * 04      TME, Timer Enable
2155          * 03..00  Reserved, must be 0
2156          *
2157          * 0000 0000
2158          */
2159         write_reg(info, (unsigned char)(timer + TMCS), 0);
2160
2161         info->irq_occurred = true;
2162
2163         if ( debug_level >= DEBUG_LEVEL_ISR )
2164                 printk("%s(%d):%s isr_timer()\n",
2165                         __FILE__,__LINE__,info->device_name);
2166 }
2167
2168 static void isr_rxint(SLMP_INFO * info)
2169 {
2170         struct tty_struct *tty = info->port.tty;
2171         struct  mgsl_icount *icount = &info->icount;
2172         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2173         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2174
2175         /* clear status bits */
2176         if (status)
2177                 write_reg(info, SR1, status);
2178
2179         if (status2)
2180                 write_reg(info, SR2, status2);
2181         
2182         if ( debug_level >= DEBUG_LEVEL_ISR )
2183                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2184                         __FILE__,__LINE__,info->device_name,status,status2);
2185
2186         if (info->params.mode == MGSL_MODE_ASYNC) {
2187                 if (status & BRKD) {
2188                         icount->brk++;
2189
2190                         /* process break detection if tty control
2191                          * is not set to ignore it
2192                          */
2193                         if ( tty ) {
2194                                 if (!(status & info->ignore_status_mask1)) {
2195                                         if (info->read_status_mask1 & BRKD) {
2196                                                 tty_insert_flip_char(tty, 0, TTY_BREAK);
2197                                                 if (info->port.flags & ASYNC_SAK)
2198                                                         do_SAK(tty);
2199                                         }
2200                                 }
2201                         }
2202                 }
2203         }
2204         else {
2205                 if (status & (FLGD|IDLD)) {
2206                         if (status & FLGD)
2207                                 info->icount.exithunt++;
2208                         else if (status & IDLD)
2209                                 info->icount.rxidle++;
2210                         wake_up_interruptible(&info->event_wait_q);
2211                 }
2212         }
2213
2214         if (status & CDCD) {
2215                 /* simulate a common modem status change interrupt
2216                  * for our handler
2217                  */
2218                 get_signals( info );
2219                 isr_io_pin(info,
2220                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2221         }
2222 }
2223
2224 /*
2225  * handle async rx data interrupts
2226  */
2227 static void isr_rxrdy(SLMP_INFO * info)
2228 {
2229         u16 status;
2230         unsigned char DataByte;
2231         struct tty_struct *tty = info->port.tty;
2232         struct  mgsl_icount *icount = &info->icount;
2233
2234         if ( debug_level >= DEBUG_LEVEL_ISR )
2235                 printk("%s(%d):%s isr_rxrdy\n",
2236                         __FILE__,__LINE__,info->device_name);
2237
2238         while((status = read_reg(info,CST0)) & BIT0)
2239         {
2240                 int flag = 0;
2241                 bool over = false;
2242                 DataByte = read_reg(info,TRB);
2243
2244                 icount->rx++;
2245
2246                 if ( status & (PE + FRME + OVRN) ) {
2247                         printk("%s(%d):%s rxerr=%04X\n",
2248                                 __FILE__,__LINE__,info->device_name,status);
2249
2250                         /* update error statistics */
2251                         if (status & PE)
2252                                 icount->parity++;
2253                         else if (status & FRME)
2254                                 icount->frame++;
2255                         else if (status & OVRN)
2256                                 icount->overrun++;
2257
2258                         /* discard char if tty control flags say so */
2259                         if (status & info->ignore_status_mask2)
2260                                 continue;
2261
2262                         status &= info->read_status_mask2;
2263
2264                         if ( tty ) {
2265                                 if (status & PE)
2266                                         flag = TTY_PARITY;
2267                                 else if (status & FRME)
2268                                         flag = TTY_FRAME;
2269                                 if (status & OVRN) {
2270                                         /* Overrun is special, since it's
2271                                          * reported immediately, and doesn't
2272                                          * affect the current character
2273                                          */
2274                                         over = true;
2275                                 }
2276                         }
2277                 }       /* end of if (error) */
2278
2279                 if ( tty ) {
2280                         tty_insert_flip_char(tty, DataByte, flag);
2281                         if (over)
2282                                 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2283                 }
2284         }
2285
2286         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2287                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2288                         __FILE__,__LINE__,info->device_name,
2289                         icount->rx,icount->brk,icount->parity,
2290                         icount->frame,icount->overrun);
2291         }
2292
2293         if ( tty )
2294                 tty_flip_buffer_push(tty);
2295 }
2296
2297 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2298 {
2299         if ( debug_level >= DEBUG_LEVEL_ISR )
2300                 printk("%s(%d):%s isr_txeom status=%02x\n",
2301                         __FILE__,__LINE__,info->device_name,status);
2302
2303         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2304         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2305         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2306
2307         if (status & UDRN) {
2308                 write_reg(info, CMD, TXRESET);
2309                 write_reg(info, CMD, TXENABLE);
2310         } else
2311                 write_reg(info, CMD, TXBUFCLR);
2312
2313         /* disable and clear tx interrupts */
2314         info->ie0_value &= ~TXRDYE;
2315         info->ie1_value &= ~(IDLE + UDRN);
2316         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2317         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2318
2319         if ( info->tx_active ) {
2320                 if (info->params.mode != MGSL_MODE_ASYNC) {
2321                         if (status & UDRN)
2322                                 info->icount.txunder++;
2323                         else if (status & IDLE)
2324                                 info->icount.txok++;
2325                 }
2326
2327                 info->tx_active = false;
2328                 info->tx_count = info->tx_put = info->tx_get = 0;
2329
2330                 del_timer(&info->tx_timer);
2331
2332                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2333                         info->serial_signals &= ~SerialSignal_RTS;
2334                         info->drop_rts_on_tx_done = false;
2335                         set_signals(info);
2336                 }
2337
2338 #if SYNCLINK_GENERIC_HDLC
2339                 if (info->netcount)
2340                         hdlcdev_tx_done(info);
2341                 else
2342 #endif
2343                 {
2344                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2345                                 tx_stop(info);
2346                                 return;
2347                         }
2348                         info->pending_bh |= BH_TRANSMIT;
2349                 }
2350         }
2351 }
2352
2353
2354 /*
2355  * handle tx status interrupts
2356  */
2357 static void isr_txint(SLMP_INFO * info)
2358 {
2359         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2360
2361         /* clear status bits */
2362         write_reg(info, SR1, status);
2363
2364         if ( debug_level >= DEBUG_LEVEL_ISR )
2365                 printk("%s(%d):%s isr_txint status=%02x\n",
2366                         __FILE__,__LINE__,info->device_name,status);
2367
2368         if (status & (UDRN + IDLE))
2369                 isr_txeom(info, status);
2370
2371         if (status & CCTS) {
2372                 /* simulate a common modem status change interrupt
2373                  * for our handler
2374                  */
2375                 get_signals( info );
2376                 isr_io_pin(info,
2377                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2378
2379         }
2380 }
2381
2382 /*
2383  * handle async tx data interrupts
2384  */
2385 static void isr_txrdy(SLMP_INFO * info)
2386 {
2387         if ( debug_level >= DEBUG_LEVEL_ISR )
2388                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2389                         __FILE__,__LINE__,info->device_name,info->tx_count);
2390
2391         if (info->params.mode != MGSL_MODE_ASYNC) {
2392                 /* disable TXRDY IRQ, enable IDLE IRQ */
2393                 info->ie0_value &= ~TXRDYE;
2394                 info->ie1_value |= IDLE;
2395                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2396                 return;
2397         }
2398
2399         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2400                 tx_stop(info);
2401                 return;
2402         }
2403
2404         if ( info->tx_count )
2405                 tx_load_fifo( info );
2406         else {
2407                 info->tx_active = false;
2408                 info->ie0_value &= ~TXRDYE;
2409                 write_reg(info, IE0, info->ie0_value);
2410         }
2411
2412         if (info->tx_count < WAKEUP_CHARS)
2413                 info->pending_bh |= BH_TRANSMIT;
2414 }
2415
2416 static void isr_rxdmaok(SLMP_INFO * info)
2417 {
2418         /* BIT7 = EOT (end of transfer)
2419          * BIT6 = EOM (end of message/frame)
2420          */
2421         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2422
2423         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2424         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2425
2426         if ( debug_level >= DEBUG_LEVEL_ISR )
2427                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2428                         __FILE__,__LINE__,info->device_name,status);
2429
2430         info->pending_bh |= BH_RECEIVE;
2431 }
2432
2433 static void isr_rxdmaerror(SLMP_INFO * info)
2434 {
2435         /* BIT5 = BOF (buffer overflow)
2436          * BIT4 = COF (counter overflow)
2437          */
2438         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2439
2440         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2441         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2442
2443         if ( debug_level >= DEBUG_LEVEL_ISR )
2444                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2445                         __FILE__,__LINE__,info->device_name,status);
2446
2447         info->rx_overflow = true;
2448         info->pending_bh |= BH_RECEIVE;
2449 }
2450
2451 static void isr_txdmaok(SLMP_INFO * info)
2452 {
2453         unsigned char status_reg1 = read_reg(info, SR1);
2454
2455         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2456         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2457         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2458
2459         if ( debug_level >= DEBUG_LEVEL_ISR )
2460                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2461                         __FILE__,__LINE__,info->device_name,status_reg1);
2462
2463         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2464         write_reg16(info, TRC0, 0);
2465         info->ie0_value |= TXRDYE;
2466         write_reg(info, IE0, info->ie0_value);
2467 }
2468
2469 static void isr_txdmaerror(SLMP_INFO * info)
2470 {
2471         /* BIT5 = BOF (buffer overflow)
2472          * BIT4 = COF (counter overflow)
2473          */
2474         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2475
2476         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2477         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2478
2479         if ( debug_level >= DEBUG_LEVEL_ISR )
2480                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2481                         __FILE__,__LINE__,info->device_name,status);
2482 }
2483
2484 /* handle input serial signal changes
2485  */
2486 static void isr_io_pin( SLMP_INFO *info, u16 status )
2487 {
2488         struct  mgsl_icount *icount;
2489
2490         if ( debug_level >= DEBUG_LEVEL_ISR )
2491                 printk("%s(%d):isr_io_pin status=%04X\n",
2492                         __FILE__,__LINE__,status);
2493
2494         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2495                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2496                 icount = &info->icount;
2497                 /* update input line counters */
2498                 if (status & MISCSTATUS_RI_LATCHED) {
2499                         icount->rng++;
2500                         if ( status & SerialSignal_RI )
2501                                 info->input_signal_events.ri_up++;
2502                         else
2503                                 info->input_signal_events.ri_down++;
2504                 }
2505                 if (status & MISCSTATUS_DSR_LATCHED) {
2506                         icount->dsr++;
2507                         if ( status & SerialSignal_DSR )
2508                                 info->input_signal_events.dsr_up++;
2509                         else
2510                                 info->input_signal_events.dsr_down++;
2511                 }
2512                 if (status & MISCSTATUS_DCD_LATCHED) {
2513                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2514                                 info->ie1_value &= ~CDCD;
2515                                 write_reg(info, IE1, info->ie1_value);
2516                         }
2517                         icount->dcd++;
2518                         if (status & SerialSignal_DCD) {
2519                                 info->input_signal_events.dcd_up++;
2520                         } else
2521                                 info->input_signal_events.dcd_down++;
2522 #if SYNCLINK_GENERIC_HDLC
2523                         if (info->netcount) {
2524                                 if (status & SerialSignal_DCD)
2525                                         netif_carrier_on(info->netdev);
2526                                 else
2527                                         netif_carrier_off(info->netdev);
2528                         }
2529 #endif
2530                 }
2531                 if (status & MISCSTATUS_CTS_LATCHED)
2532                 {
2533                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2534                                 info->ie1_value &= ~CCTS;
2535                                 write_reg(info, IE1, info->ie1_value);
2536                         }
2537                         icount->cts++;
2538                         if ( status & SerialSignal_CTS )
2539                                 info->input_signal_events.cts_up++;
2540                         else
2541                                 info->input_signal_events.cts_down++;
2542                 }
2543                 wake_up_interruptible(&info->status_event_wait_q);
2544                 wake_up_interruptible(&info->event_wait_q);
2545
2546                 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2547                      (status & MISCSTATUS_DCD_LATCHED) ) {
2548                         if ( debug_level >= DEBUG_LEVEL_ISR )
2549                                 printk("%s CD now %s...", info->device_name,
2550                                        (status & SerialSignal_DCD) ? "on" : "off");
2551                         if (status & SerialSignal_DCD)
2552                                 wake_up_interruptible(&info->port.open_wait);
2553                         else {
2554                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2555                                         printk("doing serial hangup...");
2556                                 if (info->port.tty)
2557                                         tty_hangup(info->port.tty);
2558                         }
2559                 }
2560
2561                 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
2562                      (status & MISCSTATUS_CTS_LATCHED) ) {
2563                         if ( info->port.tty ) {
2564                                 if (info->port.tty->hw_stopped) {
2565                                         if (status & SerialSignal_CTS) {
2566                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2567                                                         printk("CTS tx start...");
2568                                                 info->port.tty->hw_stopped = 0;
2569                                                 tx_start(info);
2570                                                 info->pending_bh |= BH_TRANSMIT;
2571                                                 return;
2572                                         }
2573                                 } else {
2574                                         if (!(status & SerialSignal_CTS)) {
2575                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2576                                                         printk("CTS tx stop...");
2577                                                 info->port.tty->hw_stopped = 1;
2578                                                 tx_stop(info);
2579                                         }
2580                                 }
2581                         }
2582                 }
2583         }
2584
2585         info->pending_bh |= BH_STATUS;
2586 }
2587
2588 /* Interrupt service routine entry point.
2589  *
2590  * Arguments:
2591  *      irq             interrupt number that caused interrupt
2592  *      dev_id          device ID supplied during interrupt registration
2593  *      regs            interrupted processor context
2594  */
2595 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2596 {
2597         SLMP_INFO *info = dev_id;
2598         unsigned char status, status0, status1=0;
2599         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2600         unsigned char timerstatus0, timerstatus1=0;
2601         unsigned char shift;
2602         unsigned int i;
2603         unsigned short tmp;
2604
2605         if ( debug_level >= DEBUG_LEVEL_ISR )
2606                 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2607                         __FILE__, __LINE__, info->irq_level);
2608
2609         spin_lock(&info->lock);
2610
2611         for(;;) {
2612
2613                 /* get status for SCA0 (ports 0-1) */
2614                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2615                 status0 = (unsigned char)tmp;
2616                 dmastatus0 = (unsigned char)(tmp>>8);
2617                 timerstatus0 = read_reg(info, ISR2);
2618
2619                 if ( debug_level >= DEBUG_LEVEL_ISR )
2620                         printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2621                                 __FILE__, __LINE__, info->device_name,
2622                                 status0, dmastatus0, timerstatus0);
2623
2624                 if (info->port_count == 4) {
2625                         /* get status for SCA1 (ports 2-3) */
2626                         tmp = read_reg16(info->port_array[2], ISR0);
2627                         status1 = (unsigned char)tmp;
2628                         dmastatus1 = (unsigned char)(tmp>>8);
2629                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2630
2631                         if ( debug_level >= DEBUG_LEVEL_ISR )
2632                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2633                                         __FILE__,__LINE__,info->device_name,
2634                                         status1,dmastatus1,timerstatus1);
2635                 }
2636
2637                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2638                          !status1 && !dmastatus1 && !timerstatus1)
2639                         break;
2640
2641                 for(i=0; i < info->port_count ; i++) {
2642                         if (info->port_array[i] == NULL)
2643                                 continue;
2644                         if (i < 2) {
2645                                 status = status0;
2646                                 dmastatus = dmastatus0;
2647                         } else {
2648                                 status = status1;
2649                                 dmastatus = dmastatus1;
2650                         }
2651
2652                         shift = i & 1 ? 4 :0;
2653
2654                         if (status & BIT0 << shift)
2655                                 isr_rxrdy(info->port_array[i]);
2656                         if (status & BIT1 << shift)
2657                                 isr_txrdy(info->port_array[i]);
2658                         if (status & BIT2 << shift)
2659                                 isr_rxint(info->port_array[i]);
2660                         if (status & BIT3 << shift)
2661                                 isr_txint(info->port_array[i]);
2662
2663                         if (dmastatus & BIT0 << shift)
2664                                 isr_rxdmaerror(info->port_array[i]);
2665                         if (dmastatus & BIT1 << shift)
2666                                 isr_rxdmaok(info->port_array[i]);
2667                         if (dmastatus & BIT2 << shift)
2668                                 isr_txdmaerror(info->port_array[i]);
2669                         if (dmastatus & BIT3 << shift)
2670                                 isr_txdmaok(info->port_array[i]);
2671                 }
2672
2673                 if (timerstatus0 & (BIT5 | BIT4))
2674                         isr_timer(info->port_array[0]);
2675                 if (timerstatus0 & (BIT7 | BIT6))
2676                         isr_timer(info->port_array[1]);
2677                 if (timerstatus1 & (BIT5 | BIT4))
2678                         isr_timer(info->port_array[2]);
2679                 if (timerstatus1 & (BIT7 | BIT6))
2680                         isr_timer(info->port_array[3]);
2681         }
2682
2683         for(i=0; i < info->port_count ; i++) {
2684                 SLMP_INFO * port = info->port_array[i];
2685
2686                 /* Request bottom half processing if there's something
2687                  * for it to do and the bh is not already running.
2688                  *
2689                  * Note: startup adapter diags require interrupts.
2690                  * do not request bottom half processing if the
2691                  * device is not open in a normal mode.
2692                  */
2693                 if ( port && (port->port.count || port->netcount) &&
2694                      port->pending_bh && !port->bh_running &&
2695                      !port->bh_requested ) {
2696                         if ( debug_level >= DEBUG_LEVEL_ISR )
2697                                 printk("%s(%d):%s queueing bh task.\n",
2698                                         __FILE__,__LINE__,port->device_name);
2699                         schedule_work(&port->task);
2700                         port->bh_requested = true;
2701                 }
2702         }
2703
2704         spin_unlock(&info->lock);
2705
2706         if ( debug_level >= DEBUG_LEVEL_ISR )
2707                 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2708                         __FILE__, __LINE__, info->irq_level);
2709         return IRQ_HANDLED;
2710 }
2711
2712 /* Initialize and start device.
2713  */
2714 static int startup(SLMP_INFO * info)
2715 {
2716         if ( debug_level >= DEBUG_LEVEL_INFO )
2717                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2718
2719         if (info->port.flags & ASYNC_INITIALIZED)
2720                 return 0;
2721
2722         if (!info->tx_buf) {
2723                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2724                 if (!info->tx_buf) {
2725                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2726                                 __FILE__,__LINE__,info->device_name);
2727                         return -ENOMEM;
2728                 }
2729         }
2730
2731         info->pending_bh = 0;
2732
2733         memset(&info->icount, 0, sizeof(info->icount));
2734
2735         /* program hardware for current parameters */
2736         reset_port(info);
2737
2738         change_params(info);
2739
2740         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2741
2742         if (info->port.tty)
2743                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2744
2745         info->port.flags |= ASYNC_INITIALIZED;
2746
2747         return 0;
2748 }
2749
2750 /* Called by close() and hangup() to shutdown hardware
2751  */
2752 static void shutdown(SLMP_INFO * info)
2753 {
2754         unsigned long flags;
2755
2756         if (!(info->port.flags & ASYNC_INITIALIZED))
2757                 return;
2758
2759         if (debug_level >= DEBUG_LEVEL_INFO)
2760                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2761                          __FILE__,__LINE__, info->device_name );
2762
2763         /* clear status wait queue because status changes */
2764         /* can't happen after shutting down the hardware */
2765         wake_up_interruptible(&info->status_event_wait_q);
2766         wake_up_interruptible(&info->event_wait_q);
2767
2768         del_timer(&info->tx_timer);
2769         del_timer(&info->status_timer);
2770
2771         kfree(info->tx_buf);
2772         info->tx_buf = NULL;
2773
2774         spin_lock_irqsave(&info->lock,flags);
2775
2776         reset_port(info);
2777
2778         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2779                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2780                 set_signals(info);
2781         }
2782
2783         spin_unlock_irqrestore(&info->lock,flags);
2784
2785         if (info->port.tty)
2786                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2787
2788         info->port.flags &= ~ASYNC_INITIALIZED;
2789 }
2790
2791 static void program_hw(SLMP_INFO *info)
2792 {
2793         unsigned long flags;
2794
2795         spin_lock_irqsave(&info->lock,flags);
2796
2797         rx_stop(info);
2798         tx_stop(info);
2799
2800         info->tx_count = info->tx_put = info->tx_get = 0;
2801
2802         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2803                 hdlc_mode(info);
2804         else
2805                 async_mode(info);
2806
2807         set_signals(info);
2808
2809         info->dcd_chkcount = 0;
2810         info->cts_chkcount = 0;
2811         info->ri_chkcount = 0;
2812         info->dsr_chkcount = 0;
2813
2814         info->ie1_value |= (CDCD|CCTS);
2815         write_reg(info, IE1, info->ie1_value);
2816
2817         get_signals(info);
2818
2819         if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) )
2820                 rx_start(info);
2821
2822         spin_unlock_irqrestore(&info->lock,flags);
2823 }
2824
2825 /* Reconfigure adapter based on new parameters
2826  */
2827 static void change_params(SLMP_INFO *info)
2828 {
2829         unsigned cflag;
2830         int bits_per_char;
2831
2832         if (!info->port.tty || !info->port.tty->termios)
2833                 return;
2834
2835         if (debug_level >= DEBUG_LEVEL_INFO)
2836                 printk("%s(%d):%s change_params()\n",
2837                          __FILE__,__LINE__, info->device_name );
2838
2839         cflag = info->port.tty->termios->c_cflag;
2840
2841         /* if B0 rate (hangup) specified then negate DTR and RTS */
2842         /* otherwise assert DTR and RTS */
2843         if (cflag & CBAUD)
2844                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2845         else
2846                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2847
2848         /* byte size and parity */
2849
2850         switch (cflag & CSIZE) {
2851               case CS5: info->params.data_bits = 5; break;
2852               case CS6: info->params.data_bits = 6; break;
2853               case CS7: info->params.data_bits = 7; break;
2854               case CS8: info->params.data_bits = 8; break;
2855               /* Never happens, but GCC is too dumb to figure it out */
2856               default:  info->params.data_bits = 7; break;
2857               }
2858
2859         if (cflag & CSTOPB)
2860                 info->params.stop_bits = 2;
2861         else
2862                 info->params.stop_bits = 1;
2863
2864         info->params.parity = ASYNC_PARITY_NONE;
2865         if (cflag & PARENB) {
2866                 if (cflag & PARODD)
2867                         info->params.parity = ASYNC_PARITY_ODD;
2868                 else
2869                         info->params.parity = ASYNC_PARITY_EVEN;
2870 #ifdef CMSPAR
2871                 if (cflag & CMSPAR)
2872                         info->params.parity = ASYNC_PARITY_SPACE;
2873 #endif
2874         }
2875
2876         /* calculate number of jiffies to transmit a full
2877          * FIFO (32 bytes) at specified data rate
2878          */
2879         bits_per_char = info->params.data_bits +
2880                         info->params.stop_bits + 1;
2881
2882         /* if port data rate is set to 460800 or less then
2883          * allow tty settings to override, otherwise keep the
2884          * current data rate.
2885          */
2886         if (info->params.data_rate <= 460800) {
2887                 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2888         }
2889
2890         if ( info->params.data_rate ) {
2891                 info->timeout = (32*HZ*bits_per_char) /
2892                                 info->params.data_rate;
2893         }
2894         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2895
2896         if (cflag & CRTSCTS)
2897                 info->port.flags |= ASYNC_CTS_FLOW;
2898         else
2899                 info->port.flags &= ~ASYNC_CTS_FLOW;
2900
2901         if (cflag & CLOCAL)
2902                 info->port.flags &= ~ASYNC_CHECK_CD;
2903         else
2904                 info->port.flags |= ASYNC_CHECK_CD;
2905
2906         /* process tty input control flags */
2907
2908         info->read_status_mask2 = OVRN;
2909         if (I_INPCK(info->port.tty))
2910                 info->read_status_mask2 |= PE | FRME;
2911         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2912                 info->read_status_mask1 |= BRKD;
2913         if (I_IGNPAR(info->port.tty))
2914                 info->ignore_status_mask2 |= PE | FRME;
2915         if (I_IGNBRK(info->port.tty)) {
2916                 info->ignore_status_mask1 |= BRKD;
2917                 /* If ignoring parity and break indicators, ignore
2918                  * overruns too.  (For real raw support).
2919                  */
2920                 if (I_IGNPAR(info->port.tty))
2921                         info->ignore_status_mask2 |= OVRN;
2922         }
2923
2924         program_hw(info);
2925 }
2926
2927 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2928 {
2929         int err;
2930
2931         if (debug_level >= DEBUG_LEVEL_INFO)
2932                 printk("%s(%d):%s get_params()\n",
2933                          __FILE__,__LINE__, info->device_name);
2934
2935         if (!user_icount) {
2936                 memset(&info->icount, 0, sizeof(info->icount));
2937         } else {
2938                 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2939                 if (err)
2940                         return -EFAULT;
2941         }
2942
2943         return 0;
2944 }
2945
2946 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2947 {
2948         int err;
2949         if (debug_level >= DEBUG_LEVEL_INFO)
2950                 printk("%s(%d):%s get_params()\n",
2951                          __FILE__,__LINE__, info->device_name);
2952
2953         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2954         if (err) {
2955                 if ( debug_level >= DEBUG_LEVEL_INFO )
2956                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2957                                 __FILE__,__LINE__,info->device_name);
2958                 return -EFAULT;
2959         }
2960
2961         return 0;
2962 }
2963
2964 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2965 {
2966         unsigned long flags;
2967         MGSL_PARAMS tmp_params;
2968         int err;
2969
2970         if (debug_level >= DEBUG_LEVEL_INFO)
2971                 printk("%s(%d):%s set_params\n",
2972                         __FILE__,__LINE__,info->device_name );
2973         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2974         if (err) {
2975                 if ( debug_level >= DEBUG_LEVEL_INFO )
2976                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2977                                 __FILE__,__LINE__,info->device_name);
2978                 return -EFAULT;
2979         }
2980
2981         spin_lock_irqsave(&info->lock,flags);
2982         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2983         spin_unlock_irqrestore(&info->lock,flags);
2984
2985         change_params(info);
2986
2987         return 0;
2988 }
2989
2990 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2991 {
2992         int err;
2993
2994         if (debug_level >= DEBUG_LEVEL_INFO)
2995                 printk("%s(%d):%s get_txidle()=%d\n",
2996                          __FILE__,__LINE__, info->device_name, info->idle_mode);
2997
2998         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2999         if (err) {
3000                 if ( debug_level >= DEBUG_LEVEL_INFO )
3001                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3002                                 __FILE__,__LINE__,info->device_name);
3003                 return -EFAULT;
3004         }
3005
3006         return 0;
3007 }
3008
3009 static int set_txidle(SLMP_INFO * info, int idle_mode)
3010 {
3011         unsigned long flags;
3012
3013         if (debug_level >= DEBUG_LEVEL_INFO)
3014                 printk("%s(%d):%s set_txidle(%d)\n",
3015                         __FILE__,__LINE__,info->device_name, idle_mode );
3016
3017         spin_lock_irqsave(&info->lock,flags);
3018         info->idle_mode = idle_mode;
3019         tx_set_idle( info );
3020         spin_unlock_irqrestore(&info->lock,flags);
3021         return 0;
3022 }
3023
3024 static int tx_enable(SLMP_INFO * info, int enable)
3025 {
3026         unsigned long flags;
3027
3028         if (debug_level >= DEBUG_LEVEL_INFO)
3029                 printk("%s(%d):%s tx_enable(%d)\n",
3030                         __FILE__,__LINE__,info->device_name, enable);
3031
3032         spin_lock_irqsave(&info->lock,flags);
3033         if ( enable ) {
3034                 if ( !info->tx_enabled ) {
3035                         tx_start(info);
3036                 }
3037         } else {
3038                 if ( info->tx_enabled )
3039                         tx_stop(info);
3040         }
3041         spin_unlock_irqrestore(&info->lock,flags);
3042         return 0;
3043 }
3044
3045 /* abort send HDLC frame
3046  */
3047 static int tx_abort(SLMP_INFO * info)
3048 {
3049         unsigned long flags;
3050
3051         if (debug_level >= DEBUG_LEVEL_INFO)
3052                 printk("%s(%d):%s tx_abort()\n",
3053                         __FILE__,__LINE__,info->device_name);
3054
3055         spin_lock_irqsave(&info->lock,flags);
3056         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3057                 info->ie1_value &= ~UDRN;
3058                 info->ie1_value |= IDLE;
3059                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3060                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3061
3062                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3063                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3064
3065                 write_reg(info, CMD, TXABORT);
3066         }
3067         spin_unlock_irqrestore(&info->lock,flags);
3068         return 0;
3069 }
3070
3071 static int rx_enable(SLMP_INFO * info, int enable)
3072 {
3073         unsigned long flags;
3074
3075         if (debug_level >= DEBUG_LEVEL_INFO)
3076                 printk("%s(%d):%s rx_enable(%d)\n",
3077                         __FILE__,__LINE__,info->device_name,enable);
3078
3079         spin_lock_irqsave(&info->lock,flags);
3080         if ( enable ) {
3081                 if ( !info->rx_enabled )
3082                         rx_start(info);
3083         } else {
3084                 if ( info->rx_enabled )
3085                         rx_stop(info);
3086         }
3087         spin_unlock_irqrestore(&info->lock,flags);
3088         return 0;
3089 }
3090
3091 /* wait for specified event to occur
3092  */
3093 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3094 {
3095         unsigned long flags;
3096         int s;
3097         int rc=0;
3098         struct mgsl_icount cprev, cnow;
3099         int events;
3100         int mask;
3101         struct  _input_signal_events oldsigs, newsigs;
3102         DECLARE_WAITQUEUE(wait, current);
3103
3104         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3105         if (rc) {
3106                 return  -EFAULT;
3107         }
3108
3109         if (debug_level >= DEBUG_LEVEL_INFO)
3110                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3111                         __FILE__,__LINE__,info->device_name,mask);
3112
3113         spin_lock_irqsave(&info->lock,flags);
3114
3115         /* return immediately if state matches requested events */
3116         get_signals(info);
3117         s = info->serial_signals;
3118
3119         events = mask &
3120                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3121                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3122                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3123                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3124         if (events) {
3125                 spin_unlock_irqrestore(&info->lock,flags);
3126                 goto exit;
3127         }
3128
3129         /* save current irq counts */
3130         cprev = info->icount;
3131         oldsigs = info->input_signal_events;
3132
3133         /* enable hunt and idle irqs if needed */
3134         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3135                 unsigned char oldval = info->ie1_value;
3136                 unsigned char newval = oldval +
3137                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3138                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3139                 if ( oldval != newval ) {
3140                         info->ie1_value = newval;
3141                         write_reg(info, IE1, info->ie1_value);
3142                 }
3143         }
3144
3145         set_current_state(TASK_INTERRUPTIBLE);
3146         add_wait_queue(&info->event_wait_q, &wait);
3147
3148         spin_unlock_irqrestore(&info->lock,flags);
3149
3150         for(;;) {
3151                 schedule();
3152                 if (signal_pending(current)) {
3153                         rc = -ERESTARTSYS;
3154                         break;
3155                 }
3156
3157                 /* get current irq counts */
3158                 spin_lock_irqsave(&info->lock,flags);
3159                 cnow = info->icount;
3160                 newsigs = info->input_signal_events;
3161                 set_current_state(TASK_INTERRUPTIBLE);
3162                 spin_unlock_irqrestore(&info->lock,flags);
3163
3164                 /* if no change, wait aborted for some reason */
3165                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3166                     newsigs.dsr_down == oldsigs.dsr_down &&
3167                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3168                     newsigs.dcd_down == oldsigs.dcd_down &&
3169                     newsigs.cts_up   == oldsigs.cts_up   &&
3170                     newsigs.cts_down == oldsigs.cts_down &&
3171                     newsigs.ri_up    == oldsigs.ri_up    &&
3172                     newsigs.ri_down  == oldsigs.ri_down  &&
3173                     cnow.exithunt    == cprev.exithunt   &&
3174                     cnow.rxidle      == cprev.rxidle) {
3175                         rc = -EIO;
3176                         break;
3177                 }
3178
3179                 events = mask &
3180                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3181                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3182                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3183                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3184                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3185                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3186                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3187                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3188                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3189                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3190                 if (events)
3191                         break;
3192
3193                 cprev = cnow;
3194                 oldsigs = newsigs;
3195         }
3196
3197         remove_wait_queue(&info->event_wait_q, &wait);
3198         set_current_state(TASK_RUNNING);
3199
3200
3201         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3202                 spin_lock_irqsave(&info->lock,flags);
3203                 if (!waitqueue_active(&info->event_wait_q)) {
3204                         /* disable enable exit hunt mode/idle rcvd IRQs */
3205                         info->ie1_value &= ~(FLGD|IDLD);
3206                         write_reg(info, IE1, info->ie1_value);
3207                 }
3208                 spin_unlock_irqrestore(&info->lock,flags);
3209         }
3210 exit:
3211         if ( rc == 0 )
3212                 PUT_USER(rc, events, mask_ptr);
3213
3214         return rc;
3215 }
3216
3217 static int modem_input_wait(SLMP_INFO *info,int arg)
3218 {
3219         unsigned long flags;
3220         int rc;
3221         struct mgsl_icount cprev, cnow;
3222         DECLARE_WAITQUEUE(wait, current);
3223
3224         /* save current irq counts */
3225         spin_lock_irqsave(&info->lock,flags);
3226         cprev = info->icount;
3227         add_wait_queue(&info->status_event_wait_q, &wait);
3228         set_current_state(TASK_INTERRUPTIBLE);
3229         spin_unlock_irqrestore(&info->lock,flags);
3230
3231         for(;;) {
3232                 schedule();
3233                 if (signal_pending(current)) {
3234                         rc = -ERESTARTSYS;
3235                         break;
3236                 }
3237
3238                 /* get new irq counts */
3239                 spin_lock_irqsave(&info->lock,flags);
3240                 cnow = info->icount;
3241                 set_current_state(TASK_INTERRUPTIBLE);
3242                 spin_unlock_irqrestore(&info->lock,flags);
3243
3244                 /* if no change, wait aborted for some reason */
3245                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3246                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3247                         rc = -EIO;
3248                         break;
3249                 }
3250
3251                 /* check for change in caller specified modem input */
3252                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3253                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3254                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3255                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3256                         rc = 0;
3257                         break;
3258                 }
3259
3260                 cprev = cnow;
3261         }
3262         remove_wait_queue(&info->status_event_wait_q, &wait);
3263         set_current_state(TASK_RUNNING);
3264         return rc;
3265 }
3266
3267 /* return the state of the serial control and status signals
3268  */
3269 static int tiocmget(struct tty_struct *tty, struct file *file)
3270 {
3271         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3272         unsigned int result;
3273         unsigned long flags;
3274
3275         spin_lock_irqsave(&info->lock,flags);
3276         get_signals(info);
3277         spin_unlock_irqrestore(&info->lock,flags);
3278
3279         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3280                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3281                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3282                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3283                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3284                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3285
3286         if (debug_level >= DEBUG_LEVEL_INFO)
3287                 printk("%s(%d):%s tiocmget() value=%08X\n",
3288                          __FILE__,__LINE__, info->device_name, result );
3289         return result;
3290 }
3291
3292 /* set modem control signals (DTR/RTS)
3293  */
3294 static int tiocmset(struct tty_struct *tty, struct file *file,
3295                     unsigned int set, unsigned int clear)
3296 {
3297         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3298         unsigned long flags;
3299
3300         if (debug_level >= DEBUG_LEVEL_INFO)
3301                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3302                         __FILE__,__LINE__,info->device_name, set, clear);
3303
3304         if (set & TIOCM_RTS)
3305                 info->serial_signals |= SerialSignal_RTS;
3306         if (set & TIOCM_DTR)
3307                 info->serial_signals |= SerialSignal_DTR;
3308         if (clear & TIOCM_RTS)
3309                 info->serial_signals &= ~SerialSignal_RTS;
3310         if (clear & TIOCM_DTR)
3311                 info->serial_signals &= ~SerialSignal_DTR;
3312
3313         spin_lock_irqsave(&info->lock,flags);
3314         set_signals(info);
3315         spin_unlock_irqrestore(&info->lock,flags);
3316
3317         return 0;
3318 }
3319
3320
3321
3322 /* Block the current process until the specified port is ready to open.
3323  */
3324 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3325                            SLMP_INFO *info)
3326 {
3327         DECLARE_WAITQUEUE(wait, current);
3328         int             retval;
3329         bool            do_clocal = false;
3330         bool            extra_count = false;
3331         unsigned long   flags;
3332
3333         if (debug_level >= DEBUG_LEVEL_INFO)
3334                 printk("%s(%d):%s block_til_ready()\n",
3335                          __FILE__,__LINE__, tty->driver->name );
3336
3337         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3338                 /* nonblock mode is set or port is not enabled */
3339                 /* just verify that callout device is not active */
3340                 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3341                 return 0;
3342         }
3343
3344         if (tty->termios->c_cflag & CLOCAL)
3345                 do_clocal = true;
3346
3347         /* Wait for carrier detect and the line to become
3348          * free (i.e., not in use by the callout).  While we are in
3349          * this loop, info->port.count is dropped by one, so that
3350          * close() knows when to free things.  We restore it upon
3351          * exit, either normal or abnormal.
3352          */
3353
3354         retval = 0;
3355         add_wait_queue(&info->port.open_wait, &wait);
3356
3357         if (debug_level >= DEBUG_LEVEL_INFO)
3358                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3359                          __FILE__,__LINE__, tty->driver->name, info->port.count );
3360
3361         spin_lock_irqsave(&info->lock, flags);
3362         if (!tty_hung_up_p(filp)) {
3363                 extra_count = true;
3364                 info->port.count--;
3365         }
3366         spin_unlock_irqrestore(&info->lock, flags);
3367         info->port.blocked_open++;
3368
3369         while (1) {
3370                 if ((tty->termios->c_cflag & CBAUD)) {
3371                         spin_lock_irqsave(&info->lock,flags);
3372                         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3373                         set_signals(info);
3374                         spin_unlock_irqrestore(&info->lock,flags);
3375                 }
3376
3377                 set_current_state(TASK_INTERRUPTIBLE);
3378
3379                 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)){
3380                         retval = (info->port.flags & ASYNC_HUP_NOTIFY) ?
3381                                         -EAGAIN : -ERESTARTSYS;
3382                         break;
3383                 }
3384
3385                 spin_lock_irqsave(&info->lock,flags);
3386                 get_signals(info);
3387                 spin_unlock_irqrestore(&info->lock,flags);
3388
3389                 if (!(info->port.flags & ASYNC_CLOSING) &&
3390                     (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3391                         break;
3392                 }
3393
3394                 if (signal_pending(current)) {
3395                         retval = -ERESTARTSYS;
3396                         break;
3397                 }
3398
3399                 if (debug_level >= DEBUG_LEVEL_INFO)
3400                         printk("%s(%d):%s block_til_ready() count=%d\n",
3401                                  __FILE__,__LINE__, tty->driver->name, info->port.count );
3402
3403                 schedule();
3404         }
3405
3406         set_current_state(TASK_RUNNING);
3407         remove_wait_queue(&info->port.open_wait, &wait);
3408
3409         if (extra_count)
3410                 info->port.count++;
3411         info->port.blocked_open--;
3412
3413         if (debug_level >= DEBUG_LEVEL_INFO)
3414                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3415                          __FILE__,__LINE__, tty->driver->name, info->port.count );
3416
3417         if (!retval)
3418                 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3419
3420         return retval;
3421 }
3422
3423 static int alloc_dma_bufs(SLMP_INFO *info)
3424 {
3425         unsigned short BuffersPerFrame;
3426         unsigned short BufferCount;
3427
3428         // Force allocation to start at 64K boundary for each port.
3429         // This is necessary because *all* buffer descriptors for a port
3430         // *must* be in the same 64K block. All descriptors on a port
3431         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3432         // into the CBP register.
3433         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3434
3435         /* Calculate the number of DMA buffers necessary to hold the */
3436         /* largest allowable frame size. Note: If the max frame size is */
3437         /* not an even multiple of the DMA buffer size then we need to */
3438         /* round the buffer count per frame up one. */
3439
3440         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3441         if ( info->max_frame_size % SCABUFSIZE )
3442                 BuffersPerFrame++;
3443
3444         /* calculate total number of data buffers (SCABUFSIZE) possible
3445          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3446          * for the descriptor list (BUFFERLISTSIZE).
3447          */
3448         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3449
3450         /* limit number of buffers to maximum amount of descriptors */
3451         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3452                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3453
3454         /* use enough buffers to transmit one max size frame */
3455         info->tx_buf_count = BuffersPerFrame + 1;
3456
3457         /* never use more than half the available buffers for transmit */
3458         if (info->tx_buf_count > (BufferCount/2))
3459                 info->tx_buf_count = BufferCount/2;
3460
3461         if (info->tx_buf_count > SCAMAXDESC)
3462                 info->tx_buf_count = SCAMAXDESC;
3463
3464         /* use remaining buffers for receive */
3465         info->rx_buf_count = BufferCount - info->tx_buf_count;
3466
3467         if (info->rx_buf_count > SCAMAXDESC)
3468                 info->rx_buf_count = SCAMAXDESC;
3469
3470         if ( debug_level >= DEBUG_LEVEL_INFO )
3471                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3472                         __FILE__,__LINE__, info->device_name,
3473                         info->tx_buf_count,info->rx_buf_count);
3474
3475         if ( alloc_buf_list( info ) < 0 ||
3476                 alloc_frame_bufs(info,
3477                                         info->rx_buf_list,
3478                                         info->rx_buf_list_ex,
3479                                         info->rx_buf_count) < 0 ||
3480                 alloc_frame_bufs(info,
3481                                         info->tx_buf_list,
3482                                         info->tx_buf_list_ex,
3483                                         info->tx_buf_count) < 0 ||
3484                 alloc_tmp_rx_buf(info) < 0 ) {
3485                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3486                         __FILE__,__LINE__, info->device_name);
3487                 return -ENOMEM;
3488         }
3489
3490         rx_reset_buffers( info );
3491
3492         return 0;
3493 }
3494
3495 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3496  */
3497 static int alloc_buf_list(SLMP_INFO *info)
3498 {
3499         unsigned int i;
3500
3501         /* build list in adapter shared memory */
3502         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3503         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3504         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3505
3506         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3507
3508         /* Save virtual address pointers to the receive and */
3509         /* transmit buffer lists. (Receive 1st). These pointers will */
3510         /* be used by the processor to access the lists. */
3511         info->rx_buf_list = (SCADESC *)info->buffer_list;
3512
3513         info->tx_buf_list = (SCADESC *)info->buffer_list;
3514         info->tx_buf_list += info->rx_buf_count;
3515
3516         /* Build links for circular buffer entry lists (tx and rx)
3517          *
3518          * Note: links are physical addresses read by the SCA device
3519          * to determine the next buffer entry to use.
3520          */
3521
3522         for ( i = 0; i < info->rx_buf_count; i++ ) {
3523                 /* calculate and store physical address of this buffer entry */
3524                 info->rx_buf_list_ex[i].phys_entry =
3525                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3526
3527                 /* calculate and store physical address of */
3528                 /* next entry in cirular list of entries */
3529                 info->rx_buf_list[i].next = info->buffer_list_phys;
3530                 if ( i < info->rx_buf_count - 1 )
3531                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3532
3533                 info->rx_buf_list[i].length = SCABUFSIZE;
3534         }
3535
3536         for ( i = 0; i < info->tx_buf_count; i++ ) {
3537                 /* calculate and store physical address of this buffer entry */
3538                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3539                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3540
3541                 /* calculate and store physical address of */
3542                 /* next entry in cirular list of entries */
3543
3544                 info->tx_buf_list[i].next = info->buffer_list_phys +
3545                         info->rx_buf_count * sizeof(SCADESC);
3546
3547                 if ( i < info->tx_buf_count - 1 )
3548                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3549         }
3550
3551         return 0;
3552 }
3553
3554 /* Allocate the frame DMA buffers used by the specified buffer list.
3555  */
3556 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3557 {
3558         int i;
3559         unsigned long phys_addr;
3560
3561         for ( i = 0; i < count; i++ ) {
3562                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3563                 phys_addr = info->port_array[0]->last_mem_alloc;
3564                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3565
3566                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3567                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3568         }
3569
3570         return 0;
3571 }
3572
3573 static void free_dma_bufs(SLMP_INFO *info)
3574 {
3575         info->buffer_list = NULL;
3576         info->rx_buf_list = NULL;
3577         info->tx_buf_list = NULL;
3578 }
3579
3580 /* allocate buffer large enough to hold max_frame_size.
3581  * This buffer is used to pass an assembled frame to the line discipline.
3582  */
3583 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3584 {
3585         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3586         if (info->tmp_rx_buf == NULL)
3587                 return -ENOMEM;
3588         return 0;
3589 }
3590
3591 static void free_tmp_rx_buf(SLMP_INFO *info)
3592 {
3593         kfree(info->tmp_rx_buf);
3594         info->tmp_rx_buf = NULL;
3595 }
3596
3597 static int claim_resources(SLMP_INFO *info)
3598 {
3599         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3600                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3601                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3602                 info->init_error = DiagStatus_AddressConflict;
3603                 goto errout;
3604         }
3605         else
3606                 info->shared_mem_requested = true;
3607
3608         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3609                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3610                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3611                 info->init_error = DiagStatus_AddressConflict;
3612                 goto errout;
3613         }
3614         else
3615                 info->lcr_mem_requested = true;
3616
3617         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3618                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3619                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3620                 info->init_error = DiagStatus_AddressConflict;
3621                 goto errout;
3622         }
3623         else
3624                 info->sca_base_requested = true;
3625
3626         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3627                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3628                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3629                 info->init_error = DiagStatus_AddressConflict;
3630                 goto errout;
3631         }
3632         else
3633                 info->sca_statctrl_requested = true;
3634
3635         info->memory_base = ioremap_nocache(info->phys_memory_base,
3636                                                                 SCA_MEM_SIZE);
3637         if (!info->memory_base) {
3638                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3639                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3640                 info->init_error = DiagStatus_CantAssignPciResources;
3641                 goto errout;
3642         }
3643
3644         info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3645         if (!info->lcr_base) {
3646                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3647                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3648                 info->init_error = DiagStatus_CantAssignPciResources;
3649                 goto errout;
3650         }
3651         info->lcr_base += info->lcr_offset;
3652
3653         info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3654         if (!info->sca_base) {
3655                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3656                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3657                 info->init_error = DiagStatus_CantAssignPciResources;
3658                 goto errout;
3659         }
3660         info->sca_base += info->sca_offset;
3661
3662         info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3663                                                                 PAGE_SIZE);
3664         if (!info->statctrl_base) {
3665                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3666                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3667                 info->init_error = DiagStatus_CantAssignPciResources;
3668                 goto errout;
3669         }
3670         info->statctrl_base += info->statctrl_offset;
3671
3672         if ( !memory_test(info) ) {
3673                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3674                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3675                 info->init_error = DiagStatus_MemoryError;
3676                 goto errout;
3677         }
3678
3679         return 0;
3680
3681 errout:
3682         release_resources( info );
3683         return -ENODEV;
3684 }
3685
3686 static void release_resources(SLMP_INFO *info)
3687 {
3688         if ( debug_level >= DEBUG_LEVEL_INFO )
3689                 printk( "%s(%d):%s release_resources() entry\n",
3690                         __FILE__,__LINE__,info->device_name );
3691
3692         if ( info->irq_requested ) {
3693                 free_irq(info->irq_level, info);
3694                 info->irq_requested = false;
3695         }
3696
3697         if ( info->shared_mem_requested ) {
3698                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3699                 info->shared_mem_requested = false;
3700         }
3701         if ( info->lcr_mem_requested ) {
3702                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3703                 info->lcr_mem_requested = false;
3704         }
3705         if ( info->sca_base_requested ) {
3706                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3707                 info->sca_base_requested = false;
3708         }
3709         if ( info->sca_statctrl_requested ) {
3710                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3711                 info->sca_statctrl_requested = false;
3712         }
3713
3714         if (info->memory_base){
3715                 iounmap(info->memory_base);
3716                 info->memory_base = NULL;
3717         }
3718
3719         if (info->sca_base) {
3720                 iounmap(info->sca_base - info->sca_offset);
3721                 info->sca_base=NULL;
3722         }
3723
3724         if (info->statctrl_base) {
3725                 iounmap(info->statctrl_base - info->statctrl_offset);
3726                 info->statctrl_base=NULL;
3727         }
3728
3729         if (info->lcr_base){
3730                 iounmap(info->lcr_base - info->lcr_offset);
3731                 info->lcr_base = NULL;
3732         }
3733
3734         if ( debug_level >= DEBUG_LEVEL_INFO )
3735                 printk( "%s(%d):%s release_resources() exit\n",
3736                         __FILE__,__LINE__,info->device_name );
3737 }
3738
3739 /* Add the specified device instance data structure to the
3740  * global linked list of devices and increment the device count.
3741  */
3742 static void add_device(SLMP_INFO *info)
3743 {
3744         info->next_device = NULL;
3745         info->line = synclinkmp_device_count;
3746         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3747
3748         if (info->line < MAX_DEVICES) {
3749                 if (maxframe[info->line])
3750                         info->max_frame_size = maxframe[info->line];
3751         }
3752
3753         synclinkmp_device_count++;
3754
3755         if ( !synclinkmp_device_list )
3756                 synclinkmp_device_list = info;
3757         else {
3758                 SLMP_INFO *current_dev = synclinkmp_device_list;
3759                 while( current_dev->next_device )
3760                         current_dev = current_dev->next_device;
3761                 current_dev->next_device = info;
3762         }
3763
3764         if ( info->max_frame_size < 4096 )
3765                 info->max_frame_size = 4096;
3766         else if ( info->max_frame_size > 65535 )
3767                 info->max_frame_size = 65535;
3768
3769         printk( "SyncLink MultiPort %s: "
3770                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3771                 info->device_name,
3772                 info->phys_sca_base,
3773                 info->phys_memory_base,
3774                 info->phys_statctrl_base,
3775                 info->phys_lcr_base,
3776                 info->irq_level,
3777                 info->max_frame_size );
3778
3779 #if SYNCLINK_GENERIC_HDLC
3780         hdlcdev_init(info);
3781 #endif
3782 }
3783
3784 /* Allocate and initialize a device instance structure
3785  *
3786  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3787  */
3788 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3789 {
3790         SLMP_INFO *info;
3791
3792         info = kzalloc(sizeof(SLMP_INFO),
3793                  GFP_KERNEL);
3794
3795         if (!info) {
3796                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3797                         __FILE__,__LINE__, adapter_num, port_num);
3798         } else {
3799                 tty_port_init(&info->port);
3800                 info->magic = MGSL_MAGIC;
3801                 INIT_WORK(&info->task, bh_handler);
3802                 info->max_frame_size = 4096;
3803                 info->port.close_delay = 5*HZ/10;
3804                 info->port.closing_wait = 30*HZ;
3805                 init_waitqueue_head(&info->status_event_wait_q);
3806                 init_waitqueue_head(&info->event_wait_q);
3807                 spin_lock_init(&info->netlock);
3808                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3809                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3810                 info->adapter_num = adapter_num;
3811                 info->port_num = port_num;
3812
3813                 /* Copy configuration info to device instance data */
3814                 info->irq_level = pdev->irq;
3815                 info->phys_lcr_base = pci_resource_start(pdev,0);
3816                 info->phys_sca_base = pci_resource_start(pdev,2);
3817                 info->phys_memory_base = pci_resource_start(pdev,3);
3818                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3819
3820                 /* Because veremap only works on page boundaries we must map
3821                  * a larger area than is actually implemented for the LCR
3822                  * memory range. We map a full page starting at the page boundary.
3823                  */
3824                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3825                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3826
3827                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3828                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3829
3830                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3831                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3832
3833                 info->bus_type = MGSL_BUS_TYPE_PCI;
3834                 info->irq_flags = IRQF_SHARED;
3835
3836                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3837                 setup_timer(&info->status_timer, status_timeout,
3838                                 (unsigned long)info);
3839
3840                 /* Store the PCI9050 misc control register value because a flaw
3841                  * in the PCI9050 prevents LCR registers from being read if
3842                  * BIOS assigns an LCR base address with bit 7 set.
3843                  *
3844                  * Only the misc control register is accessed for which only
3845                  * write access is needed, so set an initial value and change
3846                  * bits to the device instance data as we write the value
3847                  * to the actual misc control register.
3848                  */
3849                 info->misc_ctrl_value = 0x087e4546;
3850
3851                 /* initial port state is unknown - if startup errors
3852                  * occur, init_error will be set to indicate the
3853                  * problem. Once the port is fully initialized,
3854                  * this value will be set to 0 to indicate the
3855                  * port is available.
3856                  */
3857                 info->init_error = -1;
3858         }
3859
3860         return info;
3861 }
3862
3863 static void device_init(int adapter_num, struct pci_dev *pdev)
3864 {
3865         SLMP_INFO *port_array[SCA_MAX_PORTS];
3866         int port;
3867
3868         /* allocate device instances for up to SCA_MAX_PORTS devices */
3869         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3870                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3871                 if( port_array[port] == NULL ) {
3872                         for ( --port; port >= 0; --port )
3873                                 kfree(port_array[port]);
3874                         return;
3875                 }
3876         }
3877
3878         /* give copy of port_array to all ports and add to device list  */
3879         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3880                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3881                 add_device( port_array[port] );
3882                 spin_lock_init(&port_array[port]->lock);
3883         }
3884
3885         /* Allocate and claim adapter resources */
3886         if ( !claim_resources(port_array[0]) ) {
3887
3888                 alloc_dma_bufs(port_array[0]);
3889
3890                 /* copy resource information from first port to others */
3891                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3892                         port_array[port]->lock  = port_array[0]->lock;
3893                         port_array[port]->irq_level     = port_array[0]->irq_level;
3894                         port_array[port]->memory_base   = port_array[0]->memory_base;
3895                         port_array[port]->sca_base      = port_array[0]->sca_base;
3896                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3897                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3898                         alloc_dma_bufs(port_array[port]);
3899                 }
3900
3901                 if ( request_irq(port_array[0]->irq_level,
3902                                         synclinkmp_interrupt,
3903                                         port_array[0]->irq_flags,
3904                                         port_array[0]->device_name,
3905                                         port_array[0]) < 0 ) {
3906                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3907                                 __FILE__,__LINE__,
3908                                 port_array[0]->device_name,
3909                                 port_array[0]->irq_level );
3910                 }
3911                 else {
3912                         port_array[0]->irq_requested = true;
3913                         adapter_test(port_array[0]);
3914                 }
3915         }
3916 }
3917
3918 static const struct tty_operations ops = {
3919         .open = open,
3920         .close = close,
3921         .write = write,
3922         .put_char = put_char,
3923         .flush_chars = flush_chars,
3924         .write_room = write_room,
3925         .chars_in_buffer = chars_in_buffer,
3926         .flush_buffer = flush_buffer,
3927         .ioctl = ioctl,
3928         .throttle = throttle,
3929         .unthrottle = unthrottle,
3930         .send_xchar = send_xchar,
3931         .break_ctl = set_break,
3932         .wait_until_sent = wait_until_sent,
3933         .read_proc = read_proc,
3934         .set_termios = set_termios,
3935         .stop = tx_hold,
3936         .start = tx_release,
3937         .hangup = hangup,
3938         .tiocmget = tiocmget,
3939         .tiocmset = tiocmset,
3940 };
3941
3942 static void synclinkmp_cleanup(void)
3943 {
3944         int rc;
3945         SLMP_INFO *info;
3946         SLMP_INFO *tmp;
3947
3948         printk("Unloading %s %s\n", driver_name, driver_version);
3949
3950         if (serial_driver) {
3951                 if ((rc = tty_unregister_driver(serial_driver)))
3952                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3953                                __FILE__,__LINE__,rc);
3954                 put_tty_driver(serial_driver);
3955         }
3956
3957         /* reset devices */
3958         info = synclinkmp_device_list;
3959         while(info) {
3960                 reset_port(info);
3961                 info = info->next_device;
3962         }
3963
3964         /* release devices */
3965         info = synclinkmp_device_list;
3966         while(info) {
3967 #if SYNCLINK_GENERIC_HDLC
3968                 hdlcdev_exit(info);
3969 #endif
3970                 free_dma_bufs(info);
3971                 free_tmp_rx_buf(info);
3972                 if ( info->port_num == 0 ) {
3973                         if (info->sca_base)
3974                                 write_reg(info, LPR, 1); /* set low power mode */
3975                         release_resources(info);
3976                 }
3977                 tmp = info;
3978                 info = info->next_device;
3979                 kfree(tmp);
3980         }
3981
3982         pci_unregister_driver(&synclinkmp_pci_driver);
3983 }
3984
3985 /* Driver initialization entry point.
3986  */
3987
3988 static int __init synclinkmp_init(void)
3989 {
3990         int rc;
3991
3992         if (break_on_load) {
3993                 synclinkmp_get_text_ptr();
3994                 BREAKPOINT();
3995         }
3996
3997         printk("%s %s\n", driver_name, driver_version);
3998
3999         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4000                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4001                 return rc;
4002         }
4003
4004         serial_driver = alloc_tty_driver(128);
4005         if (!serial_driver) {
4006                 rc = -ENOMEM;
4007                 goto error;
4008         }
4009
4010         /* Initialize the tty_driver structure */
4011
4012         serial_driver->owner = THIS_MODULE;
4013         serial_driver->driver_name = "synclinkmp";
4014         serial_driver->name = "ttySLM";
4015         serial_driver->major = ttymajor;
4016         serial_driver->minor_start = 64;
4017         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4018         serial_driver->subtype = SERIAL_TYPE_NORMAL;
4019         serial_driver->init_termios = tty_std_termios;
4020         serial_driver->init_termios.c_cflag =
4021                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4022         serial_driver->init_termios.c_ispeed = 9600;
4023         serial_driver->init_termios.c_ospeed = 9600;
4024         serial_driver->flags = TTY_DRIVER_REAL_RAW;
4025         tty_set_operations(serial_driver, &ops);
4026         if ((rc = tty_register_driver(serial_driver)) < 0) {
4027                 printk("%s(%d):Couldn't register serial driver\n",
4028                         __FILE__,__LINE__);
4029                 put_tty_driver(serial_driver);
4030                 serial_driver = NULL;
4031                 goto error;
4032         }
4033
4034         printk("%s %s, tty major#%d\n",
4035                 driver_name, driver_version,
4036                 serial_driver->major);
4037
4038         return 0;
4039
4040 error:
4041         synclinkmp_cleanup();
4042         return rc;
4043 }
4044
4045 static void __exit synclinkmp_exit(void)
4046 {
4047         synclinkmp_cleanup();
4048 }
4049
4050 module_init(synclinkmp_init);
4051 module_exit(synclinkmp_exit);
4052
4053 /* Set the port for internal loopback mode.
4054  * The TxCLK and RxCLK signals are generated from the BRG and
4055  * the TxD is looped back to the RxD internally.
4056  */
4057 static void enable_loopback(SLMP_INFO *info, int enable)
4058 {
4059         if (enable) {
4060                 /* MD2 (Mode Register 2)
4061                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4062                  */
4063                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4064
4065                 /* degate external TxC clock source */
4066                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4067                 write_control_reg(info);
4068
4069                 /* RXS/TXS (Rx/Tx clock source)
4070                  * 07      Reserved, must be 0
4071                  * 06..04  Clock Source, 100=BRG
4072                  * 03..00  Clock Divisor, 0000=1
4073                  */
4074                 write_reg(info, RXS, 0x40);
4075                 write_reg(info, TXS, 0x40);
4076
4077         } else {
4078                 /* MD2 (Mode Register 2)
4079                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4080                  */
4081                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4082
4083                 /* RXS/TXS (Rx/Tx clock source)
4084                  * 07      Reserved, must be 0
4085                  * 06..04  Clock Source, 000=RxC/TxC Pin
4086                  * 03..00  Clock Divisor, 0000=1
4087                  */
4088                 write_reg(info, RXS, 0x00);
4089                 write_reg(info, TXS, 0x00);
4090         }
4091
4092         /* set LinkSpeed if available, otherwise default to 2Mbps */
4093         if (info->params.clock_speed)
4094                 set_rate(info, info->params.clock_speed);
4095         else
4096                 set_rate(info, 3686400);
4097 }
4098
4099 /* Set the baud rate register to the desired speed
4100  *
4101  *      data_rate       data rate of clock in bits per second
4102  *                      A data rate of 0 disables the AUX clock.
4103  */
4104 static void set_rate( SLMP_INFO *info, u32 data_rate )
4105 {
4106         u32 TMCValue;
4107         unsigned char BRValue;
4108         u32 Divisor=0;
4109
4110         /* fBRG = fCLK/(TMC * 2^BR)
4111          */
4112         if (data_rate != 0) {
4113                 Divisor = 14745600/data_rate;
4114                 if (!Divisor)
4115                         Divisor = 1;
4116
4117                 TMCValue = Divisor;
4118
4119                 BRValue = 0;
4120                 if (TMCValue != 1 && TMCValue != 2) {
4121                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4122                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4123                          * 50/50 duty cycle.
4124                          */
4125                         BRValue = 1;
4126                         TMCValue >>= 1;
4127                 }
4128
4129                 /* while TMCValue is too big for TMC register, divide
4130                  * by 2 and increment BR exponent.
4131                  */
4132                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4133                         TMCValue >>= 1;
4134
4135                 write_reg(info, TXS,
4136                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4137                 write_reg(info, RXS,
4138                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4139                 write_reg(info, TMC, (unsigned char)TMCValue);
4140         }
4141         else {
4142                 write_reg(info, TXS,0);
4143                 write_reg(info, RXS,0);
4144                 write_reg(info, TMC, 0);
4145         }
4146 }
4147
4148 /* Disable receiver
4149  */
4150 static void rx_stop(SLMP_INFO *info)
4151 {
4152         if (debug_level >= DEBUG_LEVEL_ISR)
4153                 printk("%s(%d):%s rx_stop()\n",
4154                          __FILE__,__LINE__, info->device_name );
4155
4156         write_reg(info, CMD, RXRESET);
4157
4158         info->ie0_value &= ~RXRDYE;
4159         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4160
4161         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4162         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4163         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4164
4165         info->rx_enabled = false;
4166         info->rx_overflow = false;
4167 }
4168
4169 /* enable the receiver
4170  */
4171 static void rx_start(SLMP_INFO *info)
4172 {
4173         int i;
4174
4175         if (debug_level >= DEBUG_LEVEL_ISR)
4176                 printk("%s(%d):%s rx_start()\n",
4177                          __FILE__,__LINE__, info->device_name );
4178
4179         write_reg(info, CMD, RXRESET);
4180
4181         if ( info->params.mode == MGSL_MODE_HDLC ) {
4182                 /* HDLC, disabe IRQ on rxdata */
4183                 info->ie0_value &= ~RXRDYE;
4184                 write_reg(info, IE0, info->ie0_value);
4185
4186                 /* Reset all Rx DMA buffers and program rx dma */
4187                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4188                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4189
4190                 for (i = 0; i < info->rx_buf_count; i++) {
4191                         info->rx_buf_list[i].status = 0xff;
4192
4193                         // throttle to 4 shared memory writes at a time to prevent
4194                         // hogging local bus (keep latency time for DMA requests low).
4195                         if (!(i % 4))
4196                                 read_status_reg(info);
4197                 }
4198                 info->current_rx_buf = 0;
4199
4200                 /* set current/1st descriptor address */
4201                 write_reg16(info, RXDMA + CDA,
4202                         info->rx_buf_list_ex[0].phys_entry);
4203
4204                 /* set new last rx descriptor address */
4205                 write_reg16(info, RXDMA + EDA,
4206                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4207
4208                 /* set buffer length (shared by all rx dma data buffers) */
4209                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4210
4211                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4212                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4213         } else {
4214                 /* async, enable IRQ on rxdata */
4215                 info->ie0_value |= RXRDYE;
4216                 write_reg(info, IE0, info->ie0_value);
4217         }
4218
4219         write_reg(info, CMD, RXENABLE);
4220
4221         info->rx_overflow = false;
4222         info->rx_enabled = true;
4223 }
4224
4225 /* Enable the transmitter and send a transmit frame if
4226  * one is loaded in the DMA buffers.
4227  */
4228 static void tx_start(SLMP_INFO *info)
4229 {
4230         if (debug_level >= DEBUG_LEVEL_ISR)
4231                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4232                          __FILE__,__LINE__, info->device_name,info->tx_count );
4233
4234         if (!info->tx_enabled ) {
4235                 write_reg(info, CMD, TXRESET);
4236                 write_reg(info, CMD, TXENABLE);
4237                 info->tx_enabled = true;
4238         }
4239
4240         if ( info->tx_count ) {
4241
4242                 /* If auto RTS enabled and RTS is inactive, then assert */
4243                 /* RTS and set a flag indicating that the driver should */
4244                 /* negate RTS when the transmission completes. */
4245
4246                 info->drop_rts_on_tx_done = false;
4247
4248                 if (info->params.mode != MGSL_MODE_ASYNC) {
4249
4250                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4251                                 get_signals( info );
4252                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4253                                         info->serial_signals |= SerialSignal_RTS;
4254                                         set_signals( info );
4255                                         info->drop_rts_on_tx_done = true;
4256                                 }
4257                         }
4258
4259                         write_reg16(info, TRC0,
4260                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4261
4262                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4263                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4264         
4265                         /* set TX CDA (current descriptor address) */
4266                         write_reg16(info, TXDMA + CDA,
4267                                 info->tx_buf_list_ex[0].phys_entry);
4268         
4269                         /* set TX EDA (last descriptor address) */
4270                         write_reg16(info, TXDMA + EDA,
4271                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4272         
4273                         /* enable underrun IRQ */
4274                         info->ie1_value &= ~IDLE;
4275                         info->ie1_value |= UDRN;
4276                         write_reg(info, IE1, info->ie1_value);
4277                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4278         
4279                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4280                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4281         
4282                         mod_timer(&info->tx_timer, jiffies +
4283                                         msecs_to_jiffies(5000));
4284                 }
4285                 else {
4286                         tx_load_fifo(info);
4287                         /* async, enable IRQ on txdata */
4288                         info->ie0_value |= TXRDYE;
4289                         write_reg(info, IE0, info->ie0_value);
4290                 }
4291
4292                 info->tx_active = true;
4293         }
4294 }
4295
4296 /* stop the transmitter and DMA
4297  */
4298 static void tx_stop( SLMP_INFO *info )
4299 {
4300         if (debug_level >= DEBUG_LEVEL_ISR)
4301                 printk("%s(%d):%s tx_stop()\n",
4302                          __FILE__,__LINE__, info->device_name );
4303
4304         del_timer(&info->tx_timer);
4305
4306         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4307         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4308
4309         write_reg(info, CMD, TXRESET);
4310
4311         info->ie1_value &= ~(UDRN + IDLE);
4312         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4313         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4314
4315         info->ie0_value &= ~TXRDYE;
4316         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4317
4318         info->tx_enabled = false;
4319         info->tx_active = false;
4320 }
4321
4322 /* Fill the transmit FIFO until the FIFO is full or
4323  * there is no more data to load.
4324  */
4325 static void tx_load_fifo(SLMP_INFO *info)
4326 {
4327         u8 TwoBytes[2];
4328
4329         /* do nothing is now tx data available and no XON/XOFF pending */
4330
4331         if ( !info->tx_count && !info->x_char )
4332                 return;
4333
4334         /* load the Transmit FIFO until FIFOs full or all data sent */
4335
4336         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4337
4338                 /* there is more space in the transmit FIFO and */
4339                 /* there is more data in transmit buffer */
4340
4341                 if ( (info->tx_count > 1) && !info->x_char ) {
4342                         /* write 16-bits */
4343                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4344                         if (info->tx_get >= info->max_frame_size)
4345                                 info->tx_get -= info->max_frame_size;
4346                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4347                         if (info->tx_get >= info->max_frame_size)
4348                                 info->tx_get -= info->max_frame_size;
4349
4350                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4351
4352                         info->tx_count -= 2;
4353                         info->icount.tx += 2;
4354                 } else {
4355                         /* only 1 byte left to transmit or 1 FIFO slot left */
4356
4357                         if (info->x_char) {
4358                                 /* transmit pending high priority char */
4359                                 write_reg(info, TRB, info->x_char);
4360                                 info->x_char = 0;
4361                         } else {
4362                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4363                                 if (info->tx_get >= info->max_frame_size)
4364                                         info->tx_get -= info->max_frame_size;
4365                                 info->tx_count--;
4366                         }
4367                         info->icount.tx++;
4368                 }
4369         }
4370 }
4371
4372 /* Reset a port to a known state
4373  */
4374 static void reset_port(SLMP_INFO *info)
4375 {
4376         if (info->sca_base) {
4377
4378                 tx_stop(info);
4379                 rx_stop(info);
4380
4381                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4382                 set_signals(info);
4383
4384                 /* disable all port interrupts */
4385                 info->ie0_value = 0;
4386                 info->ie1_value = 0;
4387                 info->ie2_value = 0;
4388                 write_reg(info, IE0, info->ie0_value);
4389                 write_reg(info, IE1, info->ie1_value);
4390                 write_reg(info, IE2, info->ie2_value);
4391
4392                 write_reg(info, CMD, CHRESET);
4393         }
4394 }
4395
4396 /* Reset all the ports to a known state.
4397  */
4398 static void reset_adapter(SLMP_INFO *info)
4399 {
4400         int i;
4401
4402         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4403                 if (info->port_array[i])
4404                         reset_port(info->port_array[i]);
4405         }
4406 }
4407
4408 /* Program port for asynchronous communications.
4409  */
4410 static void async_mode(SLMP_INFO *info)
4411 {
4412
4413         unsigned char RegValue;
4414
4415         tx_stop(info);
4416         rx_stop(info);
4417
4418         /* MD0, Mode Register 0
4419          *
4420          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4421          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4422          * 03      Reserved, must be 0
4423          * 02      CRCCC, CRC Calculation, 0=disabled
4424          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4425          *
4426          * 0000 0000
4427          */
4428         RegValue = 0x00;
4429         if (info->params.stop_bits != 1)
4430                 RegValue |= BIT1;
4431         write_reg(info, MD0, RegValue);
4432
4433         /* MD1, Mode Register 1
4434          *
4435          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4436          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4437          * 03..02  RXCHR<1..0>, rx char size
4438          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4439          *
4440          * 0100 0000
4441          */
4442         RegValue = 0x40;
4443         switch (info->params.data_bits) {
4444         case 7: RegValue |= BIT4 + BIT2; break;
4445         case 6: RegValue |= BIT5 + BIT3; break;
4446         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4447         }
4448         if (info->params.parity != ASYNC_PARITY_NONE) {
4449                 RegValue |= BIT1;
4450                 if (info->params.parity == ASYNC_PARITY_ODD)
4451                         RegValue |= BIT0;
4452         }
4453         write_reg(info, MD1, RegValue);
4454
4455         /* MD2, Mode Register 2
4456          *
4457          * 07..02  Reserved, must be 0
4458          * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4459          *
4460          * 0000 0000
4461          */
4462         RegValue = 0x00;
4463         if (info->params.loopback)
4464                 RegValue |= (BIT1 + BIT0);
4465         write_reg(info, MD2, RegValue);
4466
4467         /* RXS, Receive clock source
4468          *
4469          * 07      Reserved, must be 0
4470          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4471          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4472          */
4473         RegValue=BIT6;
4474         write_reg(info, RXS, RegValue);
4475
4476         /* TXS, Transmit clock source
4477          *
4478          * 07      Reserved, must be 0
4479          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4480          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4481          */
4482         RegValue=BIT6;
4483         write_reg(info, TXS, RegValue);
4484
4485         /* Control Register
4486          *
4487          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4488          */
4489         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4490         write_control_reg(info);
4491
4492         tx_set_idle(info);
4493
4494         /* RRC Receive Ready Control 0
4495          *
4496          * 07..05  Reserved, must be 0
4497          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4498          */
4499         write_reg(info, RRC, 0x00);
4500
4501         /* TRC0 Transmit Ready Control 0
4502          *
4503          * 07..05  Reserved, must be 0
4504          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4505          */
4506         write_reg(info, TRC0, 0x10);
4507
4508         /* TRC1 Transmit Ready Control 1
4509          *
4510          * 07..05  Reserved, must be 0
4511          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4512          */
4513         write_reg(info, TRC1, 0x1e);
4514
4515         /* CTL, MSCI control register
4516          *
4517          * 07..06  Reserved, set to 0
4518          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4519          * 04      IDLC, idle control, 0=mark 1=idle register
4520          * 03      BRK, break, 0=off 1 =on (async)
4521          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4522          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4523          * 00      RTS, RTS output control, 0=active 1=inactive
4524          *
4525          * 0001 0001
4526          */
4527         RegValue = 0x10;
4528         if (!(info->serial_signals & SerialSignal_RTS))
4529                 RegValue |= 0x01;
4530         write_reg(info, CTL, RegValue);
4531
4532         /* enable status interrupts */
4533         info->ie0_value |= TXINTE + RXINTE;
4534         write_reg(info, IE0, info->ie0_value);
4535
4536         /* enable break detect interrupt */
4537         info->ie1_value = BRKD;
4538         write_reg(info, IE1, info->ie1_value);
4539
4540         /* enable rx overrun interrupt */
4541         info->ie2_value = OVRN;
4542         write_reg(info, IE2, info->ie2_value);
4543
4544         set_rate( info, info->params.data_rate * 16 );
4545 }
4546
4547 /* Program the SCA for HDLC communications.
4548  */
4549 static void hdlc_mode(SLMP_INFO *info)
4550 {
4551         unsigned char RegValue;
4552         u32 DpllDivisor;
4553
4554         // Can't use DPLL because SCA outputs recovered clock on RxC when
4555         // DPLL mode selected. This causes output contention with RxC receiver.
4556         // Use of DPLL would require external hardware to disable RxC receiver
4557         // when DPLL mode selected.
4558         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4559
4560         /* disable DMA interrupts */
4561         write_reg(info, TXDMA + DIR, 0);
4562         write_reg(info, RXDMA + DIR, 0);
4563
4564         /* MD0, Mode Register 0
4565          *
4566          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4567          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4568          * 03      Reserved, must be 0
4569          * 02      CRCCC, CRC Calculation, 1=enabled
4570          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4571          * 00      CRC0, CRC initial value, 1 = all 1s
4572          *
4573          * 1000 0001
4574          */
4575         RegValue = 0x81;
4576         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4577                 RegValue |= BIT4;
4578         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4579                 RegValue |= BIT4;
4580         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4581                 RegValue |= BIT2 + BIT1;
4582         write_reg(info, MD0, RegValue);
4583
4584         /* MD1, Mode Register 1
4585          *
4586          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4587          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4588          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4589          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4590          *
4591          * 0000 0000
4592          */
4593         RegValue = 0x00;
4594         write_reg(info, MD1, RegValue);
4595
4596         /* MD2, Mode Register 2
4597          *
4598          * 07      NRZFM, 0=NRZ, 1=FM
4599          * 06..05  CODE<1..0> Encoding, 00=NRZ
4600          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4601          * 02      Reserved, must be 0
4602          * 01..00  CNCT<1..0> Channel connection, 0=normal
4603          *
4604          * 0000 0000
4605          */
4606         RegValue = 0x00;
4607         switch(info->params.encoding) {
4608         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4609         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4610         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4611         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4612 #if 0
4613         case HDLC_ENCODING_NRZB:                                        /* not supported */
4614         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4615         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4616 #endif
4617         }
4618         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4619                 DpllDivisor = 16;
4620                 RegValue |= BIT3;
4621         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4622                 DpllDivisor = 8;
4623         } else {
4624                 DpllDivisor = 32;
4625                 RegValue |= BIT4;
4626         }
4627         write_reg(info, MD2, RegValue);
4628
4629
4630         /* RXS, Receive clock source
4631          *
4632          * 07      Reserved, must be 0
4633          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4634          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4635          */
4636         RegValue=0;
4637         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4638                 RegValue |= BIT6;
4639         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4640                 RegValue |= BIT6 + BIT5;
4641         write_reg(info, RXS, RegValue);
4642
4643         /* TXS, Transmit clock source
4644          *
4645          * 07      Reserved, must be 0
4646          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4647          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4648          */
4649         RegValue=0;
4650         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4651                 RegValue |= BIT6;
4652         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4653                 RegValue |= BIT6 + BIT5;
4654         write_reg(info, TXS, RegValue);
4655
4656         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4657                 set_rate(info, info->params.clock_speed * DpllDivisor);
4658         else
4659                 set_rate(info, info->params.clock_speed);
4660
4661         /* GPDATA (General Purpose I/O Data Register)
4662          *
4663          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4664          */
4665         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4666                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4667         else
4668                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4669         write_control_reg(info);
4670
4671         /* RRC Receive Ready Control 0
4672          *
4673          * 07..05  Reserved, must be 0
4674          * 04..00  RRC<4..0> Rx FIFO trigger active
4675          */
4676         write_reg(info, RRC, rx_active_fifo_level);
4677
4678         /* TRC0 Transmit Ready Control 0
4679          *
4680          * 07..05  Reserved, must be 0
4681          * 04..00  TRC<4..0> Tx FIFO trigger active
4682          */
4683         write_reg(info, TRC0, tx_active_fifo_level);
4684
4685         /* TRC1 Transmit Ready Control 1
4686          *
4687          * 07..05  Reserved, must be 0
4688          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4689          */
4690         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4691
4692         /* DMR, DMA Mode Register
4693          *
4694          * 07..05  Reserved, must be 0
4695          * 04      TMOD, Transfer Mode: 1=chained-block
4696          * 03      Reserved, must be 0
4697          * 02      NF, Number of Frames: 1=multi-frame
4698          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4699          * 00      Reserved, must be 0
4700          *
4701          * 0001 0100
4702          */
4703         write_reg(info, TXDMA + DMR, 0x14);
4704         write_reg(info, RXDMA + DMR, 0x14);
4705
4706         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4707         write_reg(info, RXDMA + CPB,
4708                 (unsigned char)(info->buffer_list_phys >> 16));
4709
4710         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4711         write_reg(info, TXDMA + CPB,
4712                 (unsigned char)(info->buffer_list_phys >> 16));
4713
4714         /* enable status interrupts. other code enables/disables
4715          * the individual sources for these two interrupt classes.
4716          */
4717         info->ie0_value |= TXINTE + RXINTE;
4718         write_reg(info, IE0, info->ie0_value);
4719
4720         /* CTL, MSCI control register
4721          *
4722          * 07..06  Reserved, set to 0
4723          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4724          * 04      IDLC, idle control, 0=mark 1=idle register
4725          * 03      BRK, break, 0=off 1 =on (async)
4726          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4727          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4728          * 00      RTS, RTS output control, 0=active 1=inactive
4729          *
4730          * 0001 0001
4731          */
4732         RegValue = 0x10;
4733         if (!(info->serial_signals & SerialSignal_RTS))
4734                 RegValue |= 0x01;
4735         write_reg(info, CTL, RegValue);
4736
4737         /* preamble not supported ! */
4738
4739         tx_set_idle(info);
4740         tx_stop(info);
4741         rx_stop(info);
4742
4743         set_rate(info, info->params.clock_speed);
4744
4745         if (info->params.loopback)
4746                 enable_loopback(info,1);
4747 }
4748
4749 /* Set the transmit HDLC idle mode
4750  */
4751 static void tx_set_idle(SLMP_INFO *info)
4752 {
4753         unsigned char RegValue = 0xff;
4754
4755         /* Map API idle mode to SCA register bits */
4756         switch(info->idle_mode) {
4757         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4758         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4759         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4760         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4761         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4762         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4763         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4764         }
4765
4766         write_reg(info, IDL, RegValue);
4767 }
4768
4769 /* Query the adapter for the state of the V24 status (input) signals.
4770  */
4771 static void get_signals(SLMP_INFO *info)
4772 {
4773         u16 status = read_reg(info, SR3);
4774         u16 gpstatus = read_status_reg(info);
4775         u16 testbit;
4776
4777         /* clear all serial signals except DTR and RTS */
4778         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4779
4780         /* set serial signal bits to reflect MISR */
4781
4782         if (!(status & BIT3))
4783                 info->serial_signals |= SerialSignal_CTS;
4784
4785         if ( !(status & BIT2))
4786                 info->serial_signals |= SerialSignal_DCD;
4787
4788         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4789         if (!(gpstatus & testbit))
4790                 info->serial_signals |= SerialSignal_RI;
4791
4792         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4793         if (!(gpstatus & testbit))
4794                 info->serial_signals |= SerialSignal_DSR;
4795 }
4796
4797 /* Set the state of DTR and RTS based on contents of
4798  * serial_signals member of device context.
4799  */
4800 static void set_signals(SLMP_INFO *info)
4801 {
4802         unsigned char RegValue;
4803         u16 EnableBit;
4804
4805         RegValue = read_reg(info, CTL);
4806         if (info->serial_signals & SerialSignal_RTS)
4807                 RegValue &= ~BIT0;
4808         else
4809                 RegValue |= BIT0;
4810         write_reg(info, CTL, RegValue);
4811
4812         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4813         EnableBit = BIT1 << (info->port_num*2);
4814         if (info->serial_signals & SerialSignal_DTR)
4815                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4816         else
4817                 info->port_array[0]->ctrlreg_value |= EnableBit;
4818         write_control_reg(info);
4819 }
4820
4821 /*******************/
4822 /* DMA Buffer Code */
4823 /*******************/
4824
4825 /* Set the count for all receive buffers to SCABUFSIZE
4826  * and set the current buffer to the first buffer. This effectively
4827  * makes all buffers free and discards any data in buffers.
4828  */
4829 static void rx_reset_buffers(SLMP_INFO *info)
4830 {
4831         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4832 }
4833
4834 /* Free the buffers used by a received frame
4835  *
4836  * info   pointer to device instance data
4837  * first  index of 1st receive buffer of frame
4838  * last   index of last receive buffer of frame
4839  */
4840 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4841 {
4842         bool done = false;
4843
4844         while(!done) {
4845                 /* reset current buffer for reuse */
4846                 info->rx_buf_list[first].status = 0xff;
4847
4848                 if (first == last) {
4849                         done = true;
4850                         /* set new last rx descriptor address */
4851                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4852                 }
4853
4854                 first++;
4855                 if (first == info->rx_buf_count)
4856                         first = 0;
4857         }
4858
4859         /* set current buffer to next buffer after last buffer of frame */
4860         info->current_rx_buf = first;
4861 }
4862
4863 /* Return a received frame from the receive DMA buffers.
4864  * Only frames received without errors are returned.
4865  *
4866  * Return Value:        true if frame returned, otherwise false
4867  */
4868 static bool rx_get_frame(SLMP_INFO *info)
4869 {
4870         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4871         unsigned short status;
4872         unsigned int framesize = 0;
4873         bool ReturnCode = false;
4874         unsigned long flags;
4875         struct tty_struct *tty = info->port.tty;
4876         unsigned char addr_field = 0xff;
4877         SCADESC *desc;
4878         SCADESC_EX *desc_ex;
4879
4880 CheckAgain:
4881         /* assume no frame returned, set zero length */
4882         framesize = 0;
4883         addr_field = 0xff;
4884
4885         /*
4886          * current_rx_buf points to the 1st buffer of the next available
4887          * receive frame. To find the last buffer of the frame look for
4888          * a non-zero status field in the buffer entries. (The status
4889          * field is set by the 16C32 after completing a receive frame.
4890          */
4891         StartIndex = EndIndex = info->current_rx_buf;
4892
4893         for ( ;; ) {
4894                 desc = &info->rx_buf_list[EndIndex];
4895                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4896
4897                 if (desc->status == 0xff)
4898                         goto Cleanup;   /* current desc still in use, no frames available */
4899
4900                 if (framesize == 0 && info->params.addr_filter != 0xff)
4901                         addr_field = desc_ex->virt_addr[0];
4902
4903                 framesize += desc->length;
4904
4905                 /* Status != 0 means last buffer of frame */
4906                 if (desc->status)
4907                         break;
4908
4909                 EndIndex++;
4910                 if (EndIndex == info->rx_buf_count)
4911                         EndIndex = 0;
4912
4913                 if (EndIndex == info->current_rx_buf) {
4914                         /* all buffers have been 'used' but none mark      */
4915                         /* the end of a frame. Reset buffers and receiver. */
4916                         if ( info->rx_enabled ){
4917                                 spin_lock_irqsave(&info->lock,flags);
4918                                 rx_start(info);
4919                                 spin_unlock_irqrestore(&info->lock,flags);
4920                         }
4921                         goto Cleanup;
4922                 }
4923
4924         }
4925
4926         /* check status of receive frame */
4927
4928         /* frame status is byte stored after frame data
4929          *
4930          * 7 EOM (end of msg), 1 = last buffer of frame
4931          * 6 Short Frame, 1 = short frame
4932          * 5 Abort, 1 = frame aborted
4933          * 4 Residue, 1 = last byte is partial
4934          * 3 Overrun, 1 = overrun occurred during frame reception
4935          * 2 CRC,     1 = CRC error detected
4936          *
4937          */
4938         status = desc->status;
4939
4940         /* ignore CRC bit if not using CRC (bit is undefined) */
4941         /* Note:CRC is not save to data buffer */
4942         if (info->params.crc_type == HDLC_CRC_NONE)
4943                 status &= ~BIT2;
4944
4945         if (framesize == 0 ||
4946                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4947                 /* discard 0 byte frames, this seems to occur sometime
4948                  * when remote is idling flags.
4949                  */
4950                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4951                 goto CheckAgain;
4952         }
4953
4954         if (framesize < 2)
4955                 status |= BIT6;
4956
4957         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4958                 /* received frame has errors,
4959                  * update counts and mark frame size as 0
4960                  */
4961                 if (status & BIT6)
4962                         info->icount.rxshort++;
4963                 else if (status & BIT5)
4964                         info->icount.rxabort++;
4965                 else if (status & BIT3)
4966                         info->icount.rxover++;
4967                 else
4968                         info->icount.rxcrc++;
4969
4970                 framesize = 0;
4971 #if SYNCLINK_GENERIC_HDLC
4972                 {
4973                         info->netdev->stats.rx_errors++;
4974                         info->netdev->stats.rx_frame_errors++;
4975                 }
4976 #endif
4977         }
4978
4979         if ( debug_level >= DEBUG_LEVEL_BH )
4980                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4981                         __FILE__,__LINE__,info->device_name,status,framesize);
4982
4983         if ( debug_level >= DEBUG_LEVEL_DATA )
4984                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4985                         min_t(int, framesize,SCABUFSIZE),0);
4986
4987         if (framesize) {
4988                 if (framesize > info->max_frame_size)
4989                         info->icount.rxlong++;
4990                 else {
4991                         /* copy dma buffer(s) to contiguous intermediate buffer */
4992                         int copy_count = framesize;
4993                         int index = StartIndex;
4994                         unsigned char *ptmp = info->tmp_rx_buf;
4995                         info->tmp_rx_buf_count = framesize;
4996
4997                         info->icount.rxok++;
4998
4999                         while(copy_count) {
5000                                 int partial_count = min(copy_count,SCABUFSIZE);
5001                                 memcpy( ptmp,
5002                                         info->rx_buf_list_ex[index].virt_addr,
5003                                         partial_count );
5004                                 ptmp += partial_count;
5005                                 copy_count -= partial_count;
5006
5007                                 if ( ++index == info->rx_buf_count )
5008                                         index = 0;
5009                         }
5010
5011 #if SYNCLINK_GENERIC_HDLC
5012                         if (info->netcount)
5013                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5014                         else
5015 #endif
5016                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
5017                                                   info->flag_buf, framesize);
5018                 }
5019         }
5020         /* Free the buffers used by this frame. */
5021         rx_free_frame_buffers( info, StartIndex, EndIndex );
5022
5023         ReturnCode = true;
5024
5025 Cleanup:
5026         if ( info->rx_enabled && info->rx_overflow ) {
5027                 /* Receiver is enabled, but needs to restarted due to
5028                  * rx buffer overflow. If buffers are empty, restart receiver.
5029                  */
5030                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5031                         spin_lock_irqsave(&info->lock,flags);
5032                         rx_start(info);
5033                         spin_unlock_irqrestore(&info->lock,flags);
5034                 }
5035         }
5036
5037         return ReturnCode;
5038 }
5039
5040 /* load the transmit DMA buffer with data
5041  */
5042 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5043 {
5044         unsigned short copy_count;
5045         unsigned int i = 0;
5046         SCADESC *desc;
5047         SCADESC_EX *desc_ex;
5048
5049         if ( debug_level >= DEBUG_LEVEL_DATA )
5050                 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5051
5052         /* Copy source buffer to one or more DMA buffers, starting with
5053          * the first transmit dma buffer.
5054          */
5055         for(i=0;;)
5056         {
5057                 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5058
5059                 desc = &info->tx_buf_list[i];
5060                 desc_ex = &info->tx_buf_list_ex[i];
5061
5062                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5063
5064                 desc->length = copy_count;
5065                 desc->status = 0;
5066
5067                 buf += copy_count;
5068                 count -= copy_count;
5069
5070                 if (!count)
5071                         break;
5072
5073                 i++;
5074                 if (i >= info->tx_buf_count)
5075                         i = 0;
5076         }
5077
5078         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5079         info->last_tx_buf = ++i;
5080 }
5081
5082 static bool register_test(SLMP_INFO *info)
5083 {
5084         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5085         static unsigned int count = ARRAY_SIZE(testval);
5086         unsigned int i;
5087         bool rc = true;
5088         unsigned long flags;
5089
5090         spin_lock_irqsave(&info->lock,flags);
5091         reset_port(info);
5092
5093         /* assume failure */
5094         info->init_error = DiagStatus_AddressFailure;
5095
5096         /* Write bit patterns to various registers but do it out of */
5097         /* sync, then read back and verify values. */
5098
5099         for (i = 0 ; i < count ; i++) {
5100                 write_reg(info, TMC, testval[i]);
5101                 write_reg(info, IDL, testval[(i+1)%count]);
5102                 write_reg(info, SA0, testval[(i+2)%count]);
5103                 write_reg(info, SA1, testval[(i+3)%count]);
5104
5105                 if ( (read_reg(info, TMC) != testval[i]) ||
5106                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5107                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5108                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5109                 {
5110                         rc = false;
5111                         break;
5112                 }
5113         }
5114
5115         reset_port(info);
5116         spin_unlock_irqrestore(&info->lock,flags);
5117
5118         return rc;
5119 }
5120
5121 static bool irq_test(SLMP_INFO *info)
5122 {
5123         unsigned long timeout;
5124         unsigned long flags;
5125
5126         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5127
5128         spin_lock_irqsave(&info->lock,flags);
5129         reset_port(info);
5130
5131         /* assume failure */
5132         info->init_error = DiagStatus_IrqFailure;
5133         info->irq_occurred = false;
5134
5135         /* setup timer0 on SCA0 to interrupt */
5136
5137         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5138         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5139
5140         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5141         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5142
5143
5144         /* TMCS, Timer Control/Status Register
5145          *
5146          * 07      CMF, Compare match flag (read only) 1=match
5147          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5148          * 05      Reserved, must be 0
5149          * 04      TME, Timer Enable
5150          * 03..00  Reserved, must be 0
5151          *
5152          * 0101 0000
5153          */
5154         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5155
5156         spin_unlock_irqrestore(&info->lock,flags);
5157
5158         timeout=100;
5159         while( timeout-- && !info->irq_occurred ) {
5160                 msleep_interruptible(10);
5161         }
5162
5163         spin_lock_irqsave(&info->lock,flags);
5164         reset_port(info);
5165         spin_unlock_irqrestore(&info->lock,flags);
5166
5167         return info->irq_occurred;
5168 }
5169
5170 /* initialize individual SCA device (2 ports)
5171  */
5172 static bool sca_init(SLMP_INFO *info)
5173 {
5174         /* set wait controller to single mem partition (low), no wait states */
5175         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5176         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5177         write_reg(info, WCRL, 0);       /* wait controller low range */
5178         write_reg(info, WCRM, 0);       /* wait controller mid range */
5179         write_reg(info, WCRH, 0);       /* wait controller high range */
5180
5181         /* DPCR, DMA Priority Control
5182          *
5183          * 07..05  Not used, must be 0
5184          * 04      BRC, bus release condition: 0=all transfers complete
5185          * 03      CCC, channel change condition: 0=every cycle
5186          * 02..00  PR<2..0>, priority 100=round robin
5187          *
5188          * 00000100 = 0x04
5189          */
5190         write_reg(info, DPCR, dma_priority);
5191
5192         /* DMA Master Enable, BIT7: 1=enable all channels */
5193         write_reg(info, DMER, 0x80);
5194
5195         /* enable all interrupt classes */
5196         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5197         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5198         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5199
5200         /* ITCR, interrupt control register
5201          * 07      IPC, interrupt priority, 0=MSCI->DMA
5202          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5203          * 04      VOS, Vector Output, 0=unmodified vector
5204          * 03..00  Reserved, must be 0
5205          */
5206         write_reg(info, ITCR, 0);
5207
5208         return true;
5209 }
5210
5211 /* initialize adapter hardware
5212  */
5213 static bool init_adapter(SLMP_INFO *info)
5214 {
5215         int i;
5216
5217         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5218         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5219         u32 readval;
5220
5221         info->misc_ctrl_value |= BIT30;
5222         *MiscCtrl = info->misc_ctrl_value;
5223
5224         /*
5225          * Force at least 170ns delay before clearing
5226          * reset bit. Each read from LCR takes at least
5227          * 30ns so 10 times for 300ns to be safe.
5228          */
5229         for(i=0;i<10;i++)
5230                 readval = *MiscCtrl;
5231
5232         info->misc_ctrl_value &= ~BIT30;
5233         *MiscCtrl = info->misc_ctrl_value;
5234
5235         /* init control reg (all DTRs off, all clksel=input) */
5236         info->ctrlreg_value = 0xaa;
5237         write_control_reg(info);
5238
5239         {
5240                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5241                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5242
5243                 switch(read_ahead_count)
5244                 {
5245                 case 16:
5246                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5247                         break;
5248                 case 8:
5249                         lcr1_brdr_value |= BIT5 + BIT4;
5250                         break;
5251                 case 4:
5252                         lcr1_brdr_value |= BIT5 + BIT3;
5253                         break;
5254                 case 0:
5255                         lcr1_brdr_value |= BIT5;
5256                         break;
5257                 }
5258
5259                 *LCR1BRDR = lcr1_brdr_value;
5260                 *MiscCtrl = misc_ctrl_value;
5261         }
5262
5263         sca_init(info->port_array[0]);
5264         sca_init(info->port_array[2]);
5265
5266         return true;
5267 }
5268
5269 /* Loopback an HDLC frame to test the hardware
5270  * interrupt and DMA functions.
5271  */
5272 static bool loopback_test(SLMP_INFO *info)
5273 {
5274 #define TESTFRAMESIZE 20
5275
5276         unsigned long timeout;
5277         u16 count = TESTFRAMESIZE;
5278         unsigned char buf[TESTFRAMESIZE];
5279         bool rc = false;
5280         unsigned long flags;
5281
5282         struct tty_struct *oldtty = info->port.tty;
5283         u32 speed = info->params.clock_speed;
5284
5285         info->params.clock_speed = 3686400;
5286         info->port.tty = NULL;
5287
5288         /* assume failure */
5289         info->init_error = DiagStatus_DmaFailure;
5290
5291         /* build and send transmit frame */
5292         for (count = 0; count < TESTFRAMESIZE;++count)
5293                 buf[count] = (unsigned char)count;
5294
5295         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5296
5297         /* program hardware for HDLC and enabled receiver */
5298         spin_lock_irqsave(&info->lock,flags);
5299         hdlc_mode(info);
5300         enable_loopback(info,1);
5301         rx_start(info);
5302         info->tx_count = count;
5303         tx_load_dma_buffer(info,buf,count);
5304         tx_start(info);
5305         spin_unlock_irqrestore(&info->lock,flags);
5306
5307         /* wait for receive complete */
5308         /* Set a timeout for waiting for interrupt. */
5309         for ( timeout = 100; timeout; --timeout ) {
5310                 msleep_interruptible(10);
5311
5312                 if (rx_get_frame(info)) {
5313                         rc = true;
5314                         break;
5315                 }
5316         }
5317
5318         /* verify received frame length and contents */
5319         if (rc &&
5320             ( info->tmp_rx_buf_count != count ||
5321               memcmp(buf, info->tmp_rx_buf,count))) {
5322                 rc = false;
5323         }
5324
5325         spin_lock_irqsave(&info->lock,flags);
5326         reset_adapter(info);
5327         spin_unlock_irqrestore(&info->lock,flags);
5328
5329         info->params.clock_speed = speed;
5330         info->port.tty = oldtty;
5331
5332         return rc;
5333 }
5334
5335 /* Perform diagnostics on hardware
5336  */
5337 static int adapter_test( SLMP_INFO *info )
5338 {
5339         unsigned long flags;
5340         if ( debug_level >= DEBUG_LEVEL_INFO )
5341                 printk( "%s(%d):Testing device %s\n",
5342                         __FILE__,__LINE__,info->device_name );
5343
5344         spin_lock_irqsave(&info->lock,flags);
5345         init_adapter(info);
5346         spin_unlock_irqrestore(&info->lock,flags);
5347
5348         info->port_array[0]->port_count = 0;
5349
5350         if ( register_test(info->port_array[0]) &&
5351                 register_test(info->port_array[1])) {
5352
5353                 info->port_array[0]->port_count = 2;
5354
5355                 if ( register_test(info->port_array[2]) &&
5356                         register_test(info->port_array[3]) )
5357                         info->port_array[0]->port_count += 2;
5358         }
5359         else {
5360                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5361                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5362                 return -ENODEV;
5363         }
5364
5365         if ( !irq_test(info->port_array[0]) ||
5366                 !irq_test(info->port_array[1]) ||
5367                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5368                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5369                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5370                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5371                 return -ENODEV;
5372         }
5373
5374         if (!loopback_test(info->port_array[0]) ||
5375                 !loopback_test(info->port_array[1]) ||
5376                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5377                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5378                 printk( "%s(%d):DMA test failure for device %s\n",
5379                         __FILE__,__LINE__,info->device_name);
5380                 return -ENODEV;
5381         }
5382
5383         if ( debug_level >= DEBUG_LEVEL_INFO )
5384                 printk( "%s(%d):device %s passed diagnostics\n",
5385                         __FILE__,__LINE__,info->device_name );
5386
5387         info->port_array[0]->init_error = 0;
5388         info->port_array[1]->init_error = 0;
5389         if ( info->port_count > 2 ) {
5390                 info->port_array[2]->init_error = 0;
5391                 info->port_array[3]->init_error = 0;
5392         }
5393
5394         return 0;
5395 }
5396
5397 /* Test the shared memory on a PCI adapter.
5398  */
5399 static bool memory_test(SLMP_INFO *info)
5400 {
5401         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5402                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5403         unsigned long count = ARRAY_SIZE(testval);
5404         unsigned long i;
5405         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5406         unsigned long * addr = (unsigned long *)info->memory_base;
5407
5408         /* Test data lines with test pattern at one location. */
5409
5410         for ( i = 0 ; i < count ; i++ ) {
5411                 *addr = testval[i];
5412                 if ( *addr != testval[i] )
5413                         return false;
5414         }
5415
5416         /* Test address lines with incrementing pattern over */
5417         /* entire address range. */
5418
5419         for ( i = 0 ; i < limit ; i++ ) {
5420                 *addr = i * 4;
5421                 addr++;
5422         }
5423
5424         addr = (unsigned long *)info->memory_base;
5425
5426         for ( i = 0 ; i < limit ; i++ ) {
5427                 if ( *addr != i * 4 )
5428                         return false;
5429                 addr++;
5430         }
5431
5432         memset( info->memory_base, 0, SCA_MEM_SIZE );
5433         return true;
5434 }
5435
5436 /* Load data into PCI adapter shared memory.
5437  *
5438  * The PCI9050 releases control of the local bus
5439  * after completing the current read or write operation.
5440  *
5441  * While the PCI9050 write FIFO not empty, the
5442  * PCI9050 treats all of the writes as a single transaction
5443  * and does not release the bus. This causes DMA latency problems
5444  * at high speeds when copying large data blocks to the shared memory.
5445  *
5446  * This function breaks a write into multiple transations by
5447  * interleaving a read which flushes the write FIFO and 'completes'
5448  * the write transation. This allows any pending DMA request to gain control
5449  * of the local bus in a timely fasion.
5450  */
5451 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5452 {
5453         /* A load interval of 16 allows for 4 32-bit writes at */
5454         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5455
5456         unsigned short interval = count / sca_pci_load_interval;
5457         unsigned short i;
5458
5459         for ( i = 0 ; i < interval ; i++ )
5460         {
5461                 memcpy(dest, src, sca_pci_load_interval);
5462                 read_status_reg(info);
5463                 dest += sca_pci_load_interval;
5464                 src += sca_pci_load_interval;
5465         }
5466
5467         memcpy(dest, src, count % sca_pci_load_interval);
5468 }
5469
5470 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5471 {
5472         int i;
5473         int linecount;
5474         if (xmit)
5475                 printk("%s tx data:\n",info->device_name);
5476         else
5477                 printk("%s rx data:\n",info->device_name);
5478
5479         while(count) {
5480                 if (count > 16)
5481                         linecount = 16;
5482                 else
5483                         linecount = count;
5484
5485                 for(i=0;i<linecount;i++)
5486                         printk("%02X ",(unsigned char)data[i]);
5487                 for(;i<17;i++)
5488                         printk("   ");
5489                 for(i=0;i<linecount;i++) {
5490                         if (data[i]>=040 && data[i]<=0176)
5491                                 printk("%c",data[i]);
5492                         else
5493                                 printk(".");
5494                 }
5495                 printk("\n");
5496
5497                 data  += linecount;
5498                 count -= linecount;
5499         }
5500 }       /* end of trace_block() */
5501
5502 /* called when HDLC frame times out
5503  * update stats and do tx completion processing
5504  */
5505 static void tx_timeout(unsigned long context)
5506 {
5507         SLMP_INFO *info = (SLMP_INFO*)context;
5508         unsigned long flags;
5509
5510         if ( debug_level >= DEBUG_LEVEL_INFO )
5511                 printk( "%s(%d):%s tx_timeout()\n",
5512                         __FILE__,__LINE__,info->device_name);
5513         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5514                 info->icount.txtimeout++;
5515         }
5516         spin_lock_irqsave(&info->lock,flags);
5517         info->tx_active = false;
5518         info->tx_count = info->tx_put = info->tx_get = 0;
5519
5520         spin_unlock_irqrestore(&info->lock,flags);
5521
5522 #if SYNCLINK_GENERIC_HDLC
5523         if (info->netcount)
5524                 hdlcdev_tx_done(info);
5525         else
5526 #endif
5527                 bh_transmit(info);
5528 }
5529
5530 /* called to periodically check the DSR/RI modem signal input status
5531  */
5532 static void status_timeout(unsigned long context)
5533 {
5534         u16 status = 0;
5535         SLMP_INFO *info = (SLMP_INFO*)context;
5536         unsigned long flags;
5537         unsigned char delta;
5538
5539
5540         spin_lock_irqsave(&info->lock,flags);
5541         get_signals(info);
5542         spin_unlock_irqrestore(&info->lock,flags);
5543
5544         /* check for DSR/RI state change */
5545
5546         delta = info->old_signals ^ info->serial_signals;
5547         info->old_signals = info->serial_signals;
5548
5549         if (delta & SerialSignal_DSR)
5550                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5551
5552         if (delta & SerialSignal_RI)
5553                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5554
5555         if (delta & SerialSignal_DCD)
5556                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5557
5558         if (delta & SerialSignal_CTS)
5559                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5560
5561         if (status)
5562                 isr_io_pin(info,status);
5563
5564         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5565 }
5566
5567
5568 /* Register Access Routines -
5569  * All registers are memory mapped
5570  */
5571 #define CALC_REGADDR() \
5572         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5573         if (info->port_num > 1) \
5574                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5575         if ( info->port_num & 1) { \
5576                 if (Addr > 0x7f) \
5577                         RegAddr += 0x40;        /* DMA access */ \
5578                 else if (Addr > 0x1f && Addr < 0x60) \
5579                         RegAddr += 0x20;        /* MSCI access */ \
5580         }
5581
5582
5583 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5584 {
5585         CALC_REGADDR();
5586         return *RegAddr;
5587 }
5588 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5589 {
5590         CALC_REGADDR();
5591         *RegAddr = Value;
5592 }
5593
5594 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5595 {
5596         CALC_REGADDR();
5597         return *((u16 *)RegAddr);
5598 }
5599
5600 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5601 {
5602         CALC_REGADDR();
5603         *((u16 *)RegAddr) = Value;
5604 }
5605
5606 static unsigned char read_status_reg(SLMP_INFO * info)
5607 {
5608         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5609         return *RegAddr;
5610 }
5611
5612 static void write_control_reg(SLMP_INFO * info)
5613 {
5614         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5615         *RegAddr = info->port_array[0]->ctrlreg_value;
5616 }
5617
5618
5619 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5620                                           const struct pci_device_id *ent)
5621 {
5622         if (pci_enable_device(dev)) {
5623                 printk("error enabling pci device %p\n", dev);
5624                 return -EIO;
5625         }
5626         device_init( ++synclinkmp_adapter_count, dev );
5627         return 0;
5628 }
5629
5630 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5631 {
5632 }