[MIPS] IP32: Enable PCI bridges
[linux-2.6.git] / drivers / char / agp / intel-agp.c
1 /*
2  * Intel AGPGART routines.
3  */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
11 #include "agp.h"
12
13 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
14 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
15 #define PCI_DEVICE_ID_INTEL_82965G_1_HB     0x2980
16 #define PCI_DEVICE_ID_INTEL_82965G_1_IG     0x2982
17 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
18 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
19 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
20 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
21 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
22 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
23 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
24 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
25 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
26 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
27 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
28 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
29 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
30 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
31 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
32 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
33
34 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
35                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
36                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
37                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
38                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
39                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
40
41 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
42                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
43                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
44
45 extern int agp_memory_reserved;
46
47
48 /* Intel 815 register */
49 #define INTEL_815_APCONT        0x51
50 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
51
52 /* Intel i820 registers */
53 #define INTEL_I820_RDCR         0x51
54 #define INTEL_I820_ERRSTS       0xc8
55
56 /* Intel i840 registers */
57 #define INTEL_I840_MCHCFG       0x50
58 #define INTEL_I840_ERRSTS       0xc8
59
60 /* Intel i850 registers */
61 #define INTEL_I850_MCHCFG       0x50
62 #define INTEL_I850_ERRSTS       0xc8
63
64 /* intel 915G registers */
65 #define I915_GMADDR     0x18
66 #define I915_MMADDR     0x10
67 #define I915_PTEADDR    0x1C
68 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
69 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
70 #define G33_GMCH_GMS_STOLEN_128M       (0x8 << 4)
71 #define G33_GMCH_GMS_STOLEN_256M       (0x9 << 4)
72
73 /* Intel 965G registers */
74 #define I965_MSAC 0x62
75
76 /* Intel 7505 registers */
77 #define INTEL_I7505_APSIZE      0x74
78 #define INTEL_I7505_NCAPID      0x60
79 #define INTEL_I7505_NISTAT      0x6c
80 #define INTEL_I7505_ATTBASE     0x78
81 #define INTEL_I7505_ERRSTS      0x42
82 #define INTEL_I7505_AGPCTRL     0x70
83 #define INTEL_I7505_MCHCFG      0x50
84
85 static const struct aper_size_info_fixed intel_i810_sizes[] =
86 {
87         {64, 16384, 4},
88         /* The 32M mode still requires a 64k gatt */
89         {32, 8192, 4}
90 };
91
92 #define AGP_DCACHE_MEMORY       1
93 #define AGP_PHYS_MEMORY         2
94 #define INTEL_AGP_CACHED_MEMORY 3
95
96 static struct gatt_mask intel_i810_masks[] =
97 {
98         {.mask = I810_PTE_VALID, .type = 0},
99         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
100         {.mask = I810_PTE_VALID, .type = 0},
101         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
102          .type = INTEL_AGP_CACHED_MEMORY}
103 };
104
105 static struct _intel_private {
106         struct pci_dev *pcidev; /* device one */
107         u8 __iomem *registers;
108         u32 __iomem *gtt;               /* I915G */
109         int num_dcache_entries;
110         /* gtt_entries is the number of gtt entries that are already mapped
111          * to stolen memory.  Stolen memory is larger than the memory mapped
112          * through gtt_entries, as it includes some reserved space for the BIOS
113          * popup and for the GTT.
114          */
115         int gtt_entries;                        /* i830+ */
116 } intel_private;
117
118 static int intel_i810_fetch_size(void)
119 {
120         u32 smram_miscc;
121         struct aper_size_info_fixed *values;
122
123         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
124         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
125
126         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
127                 printk(KERN_WARNING PFX "i810 is disabled\n");
128                 return 0;
129         }
130         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
131                 agp_bridge->previous_size =
132                         agp_bridge->current_size = (void *) (values + 1);
133                 agp_bridge->aperture_size_idx = 1;
134                 return values[1].size;
135         } else {
136                 agp_bridge->previous_size =
137                         agp_bridge->current_size = (void *) (values);
138                 agp_bridge->aperture_size_idx = 0;
139                 return values[0].size;
140         }
141
142         return 0;
143 }
144
145 static int intel_i810_configure(void)
146 {
147         struct aper_size_info_fixed *current_size;
148         u32 temp;
149         int i;
150
151         current_size = A_SIZE_FIX(agp_bridge->current_size);
152
153         if (!intel_private.registers) {
154                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
155                 temp &= 0xfff80000;
156
157                 intel_private.registers = ioremap(temp, 128 * 4096);
158                 if (!intel_private.registers) {
159                         printk(KERN_ERR PFX "Unable to remap memory.\n");
160                         return -ENOMEM;
161                 }
162         }
163
164         if ((readl(intel_private.registers+I810_DRAM_CTL)
165                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
166                 /* This will need to be dynamically assigned */
167                 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
168                 intel_private.num_dcache_entries = 1024;
169         }
170         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
171         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
172         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
173         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
174
175         if (agp_bridge->driver->needs_scratch_page) {
176                 for (i = 0; i < current_size->num_entries; i++) {
177                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
178                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI posting. */
179                 }
180         }
181         global_cache_flush();
182         return 0;
183 }
184
185 static void intel_i810_cleanup(void)
186 {
187         writel(0, intel_private.registers+I810_PGETBL_CTL);
188         readl(intel_private.registers); /* PCI Posting. */
189         iounmap(intel_private.registers);
190 }
191
192 static void intel_i810_tlbflush(struct agp_memory *mem)
193 {
194         return;
195 }
196
197 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
198 {
199         return;
200 }
201
202 /* Exists to support ARGB cursors */
203 static void *i8xx_alloc_pages(void)
204 {
205         struct page * page;
206
207         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
208         if (page == NULL)
209                 return NULL;
210
211         if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) {
212                 change_page_attr(page, 4, PAGE_KERNEL);
213                 global_flush_tlb();
214                 __free_pages(page, 2);
215                 return NULL;
216         }
217         global_flush_tlb();
218         get_page(page);
219         atomic_inc(&agp_bridge->current_memory_agp);
220         return page_address(page);
221 }
222
223 static void i8xx_destroy_pages(void *addr)
224 {
225         struct page *page;
226
227         if (addr == NULL)
228                 return;
229
230         page = virt_to_page(addr);
231         change_page_attr(page, 4, PAGE_KERNEL);
232         global_flush_tlb();
233         put_page(page);
234         __free_pages(page, 2);
235         atomic_dec(&agp_bridge->current_memory_agp);
236 }
237
238 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
239                                         int type)
240 {
241         if (type < AGP_USER_TYPES)
242                 return type;
243         else if (type == AGP_USER_CACHED_MEMORY)
244                 return INTEL_AGP_CACHED_MEMORY;
245         else
246                 return 0;
247 }
248
249 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
250                                 int type)
251 {
252         int i, j, num_entries;
253         void *temp;
254         int ret = -EINVAL;
255         int mask_type;
256
257         if (mem->page_count == 0)
258                 goto out;
259
260         temp = agp_bridge->current_size;
261         num_entries = A_SIZE_FIX(temp)->num_entries;
262
263         if ((pg_start + mem->page_count) > num_entries)
264                 goto out_err;
265
266
267         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
268                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
269                         ret = -EBUSY;
270                         goto out_err;
271                 }
272         }
273
274         if (type != mem->type)
275                 goto out_err;
276
277         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
278
279         switch (mask_type) {
280         case AGP_DCACHE_MEMORY:
281                 if (!mem->is_flushed)
282                         global_cache_flush();
283                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
284                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
285                                intel_private.registers+I810_PTE_BASE+(i*4));
286                 }
287                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
288                 break;
289         case AGP_PHYS_MEMORY:
290         case AGP_NORMAL_MEMORY:
291                 if (!mem->is_flushed)
292                         global_cache_flush();
293                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
294                         writel(agp_bridge->driver->mask_memory(agp_bridge,
295                                                                mem->memory[i],
296                                                                mask_type),
297                                intel_private.registers+I810_PTE_BASE+(j*4));
298                 }
299                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
300                 break;
301         default:
302                 goto out_err;
303         }
304
305         agp_bridge->driver->tlb_flush(mem);
306 out:
307         ret = 0;
308 out_err:
309         mem->is_flushed = 1;
310         return ret;
311 }
312
313 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
314                                 int type)
315 {
316         int i;
317
318         if (mem->page_count == 0)
319                 return 0;
320
321         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
322                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
323         }
324         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
325
326         agp_bridge->driver->tlb_flush(mem);
327         return 0;
328 }
329
330 /*
331  * The i810/i830 requires a physical address to program its mouse
332  * pointer into hardware.
333  * However the Xserver still writes to it through the agp aperture.
334  */
335 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
336 {
337         struct agp_memory *new;
338         void *addr;
339
340         switch (pg_count) {
341         case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
342                 global_flush_tlb();
343                 break;
344         case 4:
345                 /* kludge to get 4 physical pages for ARGB cursor */
346                 addr = i8xx_alloc_pages();
347                 break;
348         default:
349                 return NULL;
350         }
351
352         if (addr == NULL)
353                 return NULL;
354
355         new = agp_create_memory(pg_count);
356         if (new == NULL)
357                 return NULL;
358
359         new->memory[0] = virt_to_gart(addr);
360         if (pg_count == 4) {
361                 /* kludge to get 4 physical pages for ARGB cursor */
362                 new->memory[1] = new->memory[0] + PAGE_SIZE;
363                 new->memory[2] = new->memory[1] + PAGE_SIZE;
364                 new->memory[3] = new->memory[2] + PAGE_SIZE;
365         }
366         new->page_count = pg_count;
367         new->num_scratch_pages = pg_count;
368         new->type = AGP_PHYS_MEMORY;
369         new->physical = new->memory[0];
370         return new;
371 }
372
373 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
374 {
375         struct agp_memory *new;
376
377         if (type == AGP_DCACHE_MEMORY) {
378                 if (pg_count != intel_private.num_dcache_entries)
379                         return NULL;
380
381                 new = agp_create_memory(1);
382                 if (new == NULL)
383                         return NULL;
384
385                 new->type = AGP_DCACHE_MEMORY;
386                 new->page_count = pg_count;
387                 new->num_scratch_pages = 0;
388                 agp_free_page_array(new);
389                 return new;
390         }
391         if (type == AGP_PHYS_MEMORY)
392                 return alloc_agpphysmem_i8xx(pg_count, type);
393         return NULL;
394 }
395
396 static void intel_i810_free_by_type(struct agp_memory *curr)
397 {
398         agp_free_key(curr->key);
399         if (curr->type == AGP_PHYS_MEMORY) {
400                 if (curr->page_count == 4)
401                         i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
402                 else {
403                         agp_bridge->driver->agp_destroy_page(
404                                  gart_to_virt(curr->memory[0]));
405                         global_flush_tlb();
406                 }
407                 agp_free_page_array(curr);
408         }
409         kfree(curr);
410 }
411
412 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
413         unsigned long addr, int type)
414 {
415         /* Type checking must be done elsewhere */
416         return addr | bridge->driver->masks[type].mask;
417 }
418
419 static struct aper_size_info_fixed intel_i830_sizes[] =
420 {
421         {128, 32768, 5},
422         /* The 64M mode still requires a 128k gatt */
423         {64, 16384, 5},
424         {256, 65536, 6},
425         {512, 131072, 7},
426 };
427
428 static void intel_i830_init_gtt_entries(void)
429 {
430         u16 gmch_ctrl;
431         int gtt_entries;
432         u8 rdct;
433         int local = 0;
434         static const int ddt[4] = { 0, 16, 32, 64 };
435         int size; /* reserved space (in kb) at the top of stolen memory */
436
437         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
438
439         if (IS_I965) {
440                 u32 pgetbl_ctl;
441                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
442
443                 /* The 965 has a field telling us the size of the GTT,
444                  * which may be larger than what is necessary to map the
445                  * aperture.
446                  */
447                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
448                 case I965_PGETBL_SIZE_128KB:
449                         size = 128;
450                         break;
451                 case I965_PGETBL_SIZE_256KB:
452                         size = 256;
453                         break;
454                 case I965_PGETBL_SIZE_512KB:
455                         size = 512;
456                         break;
457                 default:
458                         printk(KERN_INFO PFX "Unknown page table size, "
459                                "assuming 512KB\n");
460                         size = 512;
461                 }
462                 size += 4; /* add in BIOS popup space */
463         } else if (IS_G33) {
464         /* G33's GTT size defined in gmch_ctrl */
465                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
466                 case G33_PGETBL_SIZE_1M:
467                         size = 1024;
468                         break;
469                 case G33_PGETBL_SIZE_2M:
470                         size = 2048;
471                         break;
472                 default:
473                         printk(KERN_INFO PFX "Unknown page table size 0x%x, "
474                                 "assuming 512KB\n",
475                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
476                         size = 512;
477                 }
478                 size += 4;
479         } else {
480                 /* On previous hardware, the GTT size was just what was
481                  * required to map the aperture.
482                  */
483                 size = agp_bridge->driver->fetch_size() + 4;
484         }
485
486         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
487             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
488                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
489                 case I830_GMCH_GMS_STOLEN_512:
490                         gtt_entries = KB(512) - KB(size);
491                         break;
492                 case I830_GMCH_GMS_STOLEN_1024:
493                         gtt_entries = MB(1) - KB(size);
494                         break;
495                 case I830_GMCH_GMS_STOLEN_8192:
496                         gtt_entries = MB(8) - KB(size);
497                         break;
498                 case I830_GMCH_GMS_LOCAL:
499                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
500                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
501                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
502                         local = 1;
503                         break;
504                 default:
505                         gtt_entries = 0;
506                         break;
507                 }
508         } else {
509                 /* G33's GTT stolen memory is separate from gfx data
510                  * stolen memory.
511                  */
512                 if (IS_G33)
513                         size = 0;
514                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
515                 case I855_GMCH_GMS_STOLEN_1M:
516                         gtt_entries = MB(1) - KB(size);
517                         break;
518                 case I855_GMCH_GMS_STOLEN_4M:
519                         gtt_entries = MB(4) - KB(size);
520                         break;
521                 case I855_GMCH_GMS_STOLEN_8M:
522                         gtt_entries = MB(8) - KB(size);
523                         break;
524                 case I855_GMCH_GMS_STOLEN_16M:
525                         gtt_entries = MB(16) - KB(size);
526                         break;
527                 case I855_GMCH_GMS_STOLEN_32M:
528                         gtt_entries = MB(32) - KB(size);
529                         break;
530                 case I915_GMCH_GMS_STOLEN_48M:
531                         /* Check it's really I915G */
532                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
533                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
534                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
535                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
536                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
537                             IS_I965 || IS_G33)
538                                 gtt_entries = MB(48) - KB(size);
539                         else
540                                 gtt_entries = 0;
541                         break;
542                 case I915_GMCH_GMS_STOLEN_64M:
543                         /* Check it's really I915G */
544                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
545                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
546                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
547                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
548                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
549                             IS_I965 || IS_G33)
550                                 gtt_entries = MB(64) - KB(size);
551                         else
552                                 gtt_entries = 0;
553                         break;
554                 case G33_GMCH_GMS_STOLEN_128M:
555                         if (IS_G33)
556                                 gtt_entries = MB(128) - KB(size);
557                         else
558                                 gtt_entries = 0;
559                         break;
560                 case G33_GMCH_GMS_STOLEN_256M:
561                         if (IS_G33)
562                                 gtt_entries = MB(256) - KB(size);
563                         else
564                                 gtt_entries = 0;
565                         break;
566                 default:
567                         gtt_entries = 0;
568                         break;
569                 }
570         }
571         if (gtt_entries > 0)
572                 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
573                        gtt_entries / KB(1), local ? "local" : "stolen");
574         else
575                 printk(KERN_INFO PFX
576                        "No pre-allocated video memory detected.\n");
577         gtt_entries /= KB(4);
578
579         intel_private.gtt_entries = gtt_entries;
580 }
581
582 /* The intel i830 automatically initializes the agp aperture during POST.
583  * Use the memory already set aside for in the GTT.
584  */
585 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
586 {
587         int page_order;
588         struct aper_size_info_fixed *size;
589         int num_entries;
590         u32 temp;
591
592         size = agp_bridge->current_size;
593         page_order = size->page_order;
594         num_entries = size->num_entries;
595         agp_bridge->gatt_table_real = NULL;
596
597         pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
598         temp &= 0xfff80000;
599
600         intel_private.registers = ioremap(temp,128 * 4096);
601         if (!intel_private.registers)
602                 return -ENOMEM;
603
604         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
605         global_cache_flush();   /* FIXME: ?? */
606
607         /* we have to call this as early as possible after the MMIO base address is known */
608         intel_i830_init_gtt_entries();
609
610         agp_bridge->gatt_table = NULL;
611
612         agp_bridge->gatt_bus_addr = temp;
613
614         return 0;
615 }
616
617 /* Return the gatt table to a sane state. Use the top of stolen
618  * memory for the GTT.
619  */
620 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
621 {
622         return 0;
623 }
624
625 static int intel_i830_fetch_size(void)
626 {
627         u16 gmch_ctrl;
628         struct aper_size_info_fixed *values;
629
630         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
631
632         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
633             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
634                 /* 855GM/852GM/865G has 128MB aperture size */
635                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
636                 agp_bridge->aperture_size_idx = 0;
637                 return values[0].size;
638         }
639
640         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
641
642         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
643                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
644                 agp_bridge->aperture_size_idx = 0;
645                 return values[0].size;
646         } else {
647                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
648                 agp_bridge->aperture_size_idx = 1;
649                 return values[1].size;
650         }
651
652         return 0;
653 }
654
655 static int intel_i830_configure(void)
656 {
657         struct aper_size_info_fixed *current_size;
658         u32 temp;
659         u16 gmch_ctrl;
660         int i;
661
662         current_size = A_SIZE_FIX(agp_bridge->current_size);
663
664         pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
665         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
666
667         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
668         gmch_ctrl |= I830_GMCH_ENABLED;
669         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
670
671         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
672         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
673
674         if (agp_bridge->driver->needs_scratch_page) {
675                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
676                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
677                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI Posting. */
678                 }
679         }
680
681         global_cache_flush();
682         return 0;
683 }
684
685 static void intel_i830_cleanup(void)
686 {
687         iounmap(intel_private.registers);
688 }
689
690 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
691 {
692         int i,j,num_entries;
693         void *temp;
694         int ret = -EINVAL;
695         int mask_type;
696
697         if (mem->page_count == 0)
698                 goto out;
699
700         temp = agp_bridge->current_size;
701         num_entries = A_SIZE_FIX(temp)->num_entries;
702
703         if (pg_start < intel_private.gtt_entries) {
704                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
705                                 pg_start,intel_private.gtt_entries);
706
707                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
708                 goto out_err;
709         }
710
711         if ((pg_start + mem->page_count) > num_entries)
712                 goto out_err;
713
714         /* The i830 can't check the GTT for entries since its read only,
715          * depend on the caller to make the correct offset decisions.
716          */
717
718         if (type != mem->type)
719                 goto out_err;
720
721         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
722
723         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
724             mask_type != INTEL_AGP_CACHED_MEMORY)
725                 goto out_err;
726
727         if (!mem->is_flushed)
728                 global_cache_flush();
729
730         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
731                 writel(agp_bridge->driver->mask_memory(agp_bridge,
732                                                        mem->memory[i], mask_type),
733                        intel_private.registers+I810_PTE_BASE+(j*4));
734         }
735         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
736         agp_bridge->driver->tlb_flush(mem);
737
738 out:
739         ret = 0;
740 out_err:
741         mem->is_flushed = 1;
742         return ret;
743 }
744
745 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
746                                 int type)
747 {
748         int i;
749
750         if (mem->page_count == 0)
751                 return 0;
752
753         if (pg_start < intel_private.gtt_entries) {
754                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
755                 return -EINVAL;
756         }
757
758         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
759                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
760         }
761         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
762
763         agp_bridge->driver->tlb_flush(mem);
764         return 0;
765 }
766
767 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
768 {
769         if (type == AGP_PHYS_MEMORY)
770                 return alloc_agpphysmem_i8xx(pg_count, type);
771         /* always return NULL for other allocation types for now */
772         return NULL;
773 }
774
775 static int intel_i915_configure(void)
776 {
777         struct aper_size_info_fixed *current_size;
778         u32 temp;
779         u16 gmch_ctrl;
780         int i;
781
782         current_size = A_SIZE_FIX(agp_bridge->current_size);
783
784         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
785
786         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
787
788         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
789         gmch_ctrl |= I830_GMCH_ENABLED;
790         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
791
792         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
793         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
794
795         if (agp_bridge->driver->needs_scratch_page) {
796                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
797                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
798                         readl(intel_private.gtt+i);     /* PCI Posting. */
799                 }
800         }
801
802         global_cache_flush();
803         return 0;
804 }
805
806 static void intel_i915_cleanup(void)
807 {
808         iounmap(intel_private.gtt);
809         iounmap(intel_private.registers);
810 }
811
812 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
813                                 int type)
814 {
815         int i,j,num_entries;
816         void *temp;
817         int ret = -EINVAL;
818         int mask_type;
819
820         if (mem->page_count == 0)
821                 goto out;
822
823         temp = agp_bridge->current_size;
824         num_entries = A_SIZE_FIX(temp)->num_entries;
825
826         if (pg_start < intel_private.gtt_entries) {
827                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
828                                 pg_start,intel_private.gtt_entries);
829
830                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
831                 goto out_err;
832         }
833
834         if ((pg_start + mem->page_count) > num_entries)
835                 goto out_err;
836
837         /* The i915 can't check the GTT for entries since its read only,
838          * depend on the caller to make the correct offset decisions.
839          */
840
841         if (type != mem->type)
842                 goto out_err;
843
844         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
845
846         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
847             mask_type != INTEL_AGP_CACHED_MEMORY)
848                 goto out_err;
849
850         if (!mem->is_flushed)
851                 global_cache_flush();
852
853         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
854                 writel(agp_bridge->driver->mask_memory(agp_bridge,
855                         mem->memory[i], mask_type), intel_private.gtt+j);
856         }
857
858         readl(intel_private.gtt+j-1);
859         agp_bridge->driver->tlb_flush(mem);
860
861  out:
862         ret = 0;
863  out_err:
864         mem->is_flushed = 1;
865         return ret;
866 }
867
868 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
869                                 int type)
870 {
871         int i;
872
873         if (mem->page_count == 0)
874                 return 0;
875
876         if (pg_start < intel_private.gtt_entries) {
877                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
878                 return -EINVAL;
879         }
880
881         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
882                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
883         }
884         readl(intel_private.gtt+i-1);
885
886         agp_bridge->driver->tlb_flush(mem);
887         return 0;
888 }
889
890 /* Return the aperture size by just checking the resource length.  The effect
891  * described in the spec of the MSAC registers is just changing of the
892  * resource size.
893  */
894 static int intel_i9xx_fetch_size(void)
895 {
896         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
897         int aper_size; /* size in megabytes */
898         int i;
899
900         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
901
902         for (i = 0; i < num_sizes; i++) {
903                 if (aper_size == intel_i830_sizes[i].size) {
904                         agp_bridge->current_size = intel_i830_sizes + i;
905                         agp_bridge->previous_size = agp_bridge->current_size;
906                         return aper_size;
907                 }
908         }
909
910         return 0;
911 }
912
913 /* The intel i915 automatically initializes the agp aperture during POST.
914  * Use the memory already set aside for in the GTT.
915  */
916 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
917 {
918         int page_order;
919         struct aper_size_info_fixed *size;
920         int num_entries;
921         u32 temp, temp2;
922         int gtt_map_size = 256 * 1024;
923
924         size = agp_bridge->current_size;
925         page_order = size->page_order;
926         num_entries = size->num_entries;
927         agp_bridge->gatt_table_real = NULL;
928
929         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
930         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
931
932         if (IS_G33)
933             gtt_map_size = 1024 * 1024; /* 1M on G33 */
934         intel_private.gtt = ioremap(temp2, gtt_map_size);
935         if (!intel_private.gtt)
936                 return -ENOMEM;
937
938         temp &= 0xfff80000;
939
940         intel_private.registers = ioremap(temp,128 * 4096);
941         if (!intel_private.registers) {
942                 iounmap(intel_private.gtt);
943                 return -ENOMEM;
944         }
945
946         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
947         global_cache_flush();   /* FIXME: ? */
948
949         /* we have to call this as early as possible after the MMIO base address is known */
950         intel_i830_init_gtt_entries();
951
952         agp_bridge->gatt_table = NULL;
953
954         agp_bridge->gatt_bus_addr = temp;
955
956         return 0;
957 }
958
959 /*
960  * The i965 supports 36-bit physical addresses, but to keep
961  * the format of the GTT the same, the bits that don't fit
962  * in a 32-bit word are shifted down to bits 4..7.
963  *
964  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
965  * is always zero on 32-bit architectures, so no need to make
966  * this conditional.
967  */
968 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
969         unsigned long addr, int type)
970 {
971         /* Shift high bits down */
972         addr |= (addr >> 28) & 0xf0;
973
974         /* Type checking must be done elsewhere */
975         return addr | bridge->driver->masks[type].mask;
976 }
977
978 /* The intel i965 automatically initializes the agp aperture during POST.
979  * Use the memory already set aside for in the GTT.
980  */
981 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
982 {
983        int page_order;
984        struct aper_size_info_fixed *size;
985        int num_entries;
986        u32 temp;
987
988        size = agp_bridge->current_size;
989        page_order = size->page_order;
990        num_entries = size->num_entries;
991        agp_bridge->gatt_table_real = NULL;
992
993        pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
994
995        temp &= 0xfff00000;
996        intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
997
998         if (!intel_private.gtt)
999                 return -ENOMEM;
1000
1001
1002        intel_private.registers = ioremap(temp,128 * 4096);
1003        if (!intel_private.registers) {
1004                 iounmap(intel_private.gtt);
1005                 return -ENOMEM;
1006         }
1007
1008        temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1009        global_cache_flush();   /* FIXME: ? */
1010
1011        /* we have to call this as early as possible after the MMIO base address is known */
1012        intel_i830_init_gtt_entries();
1013
1014        agp_bridge->gatt_table = NULL;
1015
1016        agp_bridge->gatt_bus_addr = temp;
1017
1018        return 0;
1019 }
1020
1021
1022 static int intel_fetch_size(void)
1023 {
1024         int i;
1025         u16 temp;
1026         struct aper_size_info_16 *values;
1027
1028         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1029         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1030
1031         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1032                 if (temp == values[i].size_value) {
1033                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1034                         agp_bridge->aperture_size_idx = i;
1035                         return values[i].size;
1036                 }
1037         }
1038
1039         return 0;
1040 }
1041
1042 static int __intel_8xx_fetch_size(u8 temp)
1043 {
1044         int i;
1045         struct aper_size_info_8 *values;
1046
1047         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1048
1049         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1050                 if (temp == values[i].size_value) {
1051                         agp_bridge->previous_size =
1052                                 agp_bridge->current_size = (void *) (values + i);
1053                         agp_bridge->aperture_size_idx = i;
1054                         return values[i].size;
1055                 }
1056         }
1057         return 0;
1058 }
1059
1060 static int intel_8xx_fetch_size(void)
1061 {
1062         u8 temp;
1063
1064         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1065         return __intel_8xx_fetch_size(temp);
1066 }
1067
1068 static int intel_815_fetch_size(void)
1069 {
1070         u8 temp;
1071
1072         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1073          * one non-reserved bit, so mask the others out ... */
1074         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1075         temp &= (1 << 3);
1076
1077         return __intel_8xx_fetch_size(temp);
1078 }
1079
1080 static void intel_tlbflush(struct agp_memory *mem)
1081 {
1082         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1083         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1084 }
1085
1086
1087 static void intel_8xx_tlbflush(struct agp_memory *mem)
1088 {
1089         u32 temp;
1090         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1091         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1092         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1093         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1094 }
1095
1096
1097 static void intel_cleanup(void)
1098 {
1099         u16 temp;
1100         struct aper_size_info_16 *previous_size;
1101
1102         previous_size = A_SIZE_16(agp_bridge->previous_size);
1103         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1104         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1105         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1106 }
1107
1108
1109 static void intel_8xx_cleanup(void)
1110 {
1111         u16 temp;
1112         struct aper_size_info_8 *previous_size;
1113
1114         previous_size = A_SIZE_8(agp_bridge->previous_size);
1115         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1116         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1117         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1118 }
1119
1120
1121 static int intel_configure(void)
1122 {
1123         u32 temp;
1124         u16 temp2;
1125         struct aper_size_info_16 *current_size;
1126
1127         current_size = A_SIZE_16(agp_bridge->current_size);
1128
1129         /* aperture size */
1130         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1131
1132         /* address to map to */
1133         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1134         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1135
1136         /* attbase - aperture base */
1137         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1138
1139         /* agpctrl */
1140         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1141
1142         /* paccfg/nbxcfg */
1143         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1144         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1145                         (temp2 & ~(1 << 10)) | (1 << 9));
1146         /* clear any possible error conditions */
1147         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1148         return 0;
1149 }
1150
1151 static int intel_815_configure(void)
1152 {
1153         u32 temp, addr;
1154         u8 temp2;
1155         struct aper_size_info_8 *current_size;
1156
1157         /* attbase - aperture base */
1158         /* the Intel 815 chipset spec. says that bits 29-31 in the
1159         * ATTBASE register are reserved -> try not to write them */
1160         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1161                 printk (KERN_EMERG PFX "gatt bus addr too high");
1162                 return -EINVAL;
1163         }
1164
1165         current_size = A_SIZE_8(agp_bridge->current_size);
1166
1167         /* aperture size */
1168         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1169                         current_size->size_value);
1170
1171         /* address to map to */
1172         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1173         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1174
1175         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1176         addr &= INTEL_815_ATTBASE_MASK;
1177         addr |= agp_bridge->gatt_bus_addr;
1178         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1179
1180         /* agpctrl */
1181         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1182
1183         /* apcont */
1184         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1185         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1186
1187         /* clear any possible error conditions */
1188         /* Oddness : this chipset seems to have no ERRSTS register ! */
1189         return 0;
1190 }
1191
1192 static void intel_820_tlbflush(struct agp_memory *mem)
1193 {
1194         return;
1195 }
1196
1197 static void intel_820_cleanup(void)
1198 {
1199         u8 temp;
1200         struct aper_size_info_8 *previous_size;
1201
1202         previous_size = A_SIZE_8(agp_bridge->previous_size);
1203         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1204         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1205                         temp & ~(1 << 1));
1206         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1207                         previous_size->size_value);
1208 }
1209
1210
1211 static int intel_820_configure(void)
1212 {
1213         u32 temp;
1214         u8 temp2;
1215         struct aper_size_info_8 *current_size;
1216
1217         current_size = A_SIZE_8(agp_bridge->current_size);
1218
1219         /* aperture size */
1220         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1221
1222         /* address to map to */
1223         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1224         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1225
1226         /* attbase - aperture base */
1227         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1228
1229         /* agpctrl */
1230         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1231
1232         /* global enable aperture access */
1233         /* This flag is not accessed through MCHCFG register as in */
1234         /* i850 chipset. */
1235         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1236         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1237         /* clear any possible AGP-related error conditions */
1238         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1239         return 0;
1240 }
1241
1242 static int intel_840_configure(void)
1243 {
1244         u32 temp;
1245         u16 temp2;
1246         struct aper_size_info_8 *current_size;
1247
1248         current_size = A_SIZE_8(agp_bridge->current_size);
1249
1250         /* aperture size */
1251         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1252
1253         /* address to map to */
1254         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1255         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1256
1257         /* attbase - aperture base */
1258         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1259
1260         /* agpctrl */
1261         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1262
1263         /* mcgcfg */
1264         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1265         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1266         /* clear any possible error conditions */
1267         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1268         return 0;
1269 }
1270
1271 static int intel_845_configure(void)
1272 {
1273         u32 temp;
1274         u8 temp2;
1275         struct aper_size_info_8 *current_size;
1276
1277         current_size = A_SIZE_8(agp_bridge->current_size);
1278
1279         /* aperture size */
1280         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1281
1282         if (agp_bridge->apbase_config != 0) {
1283                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1284                                        agp_bridge->apbase_config);
1285         } else {
1286                 /* address to map to */
1287                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1288                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1289                 agp_bridge->apbase_config = temp;
1290         }
1291
1292         /* attbase - aperture base */
1293         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1294
1295         /* agpctrl */
1296         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1297
1298         /* agpm */
1299         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1300         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1301         /* clear any possible error conditions */
1302         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1303         return 0;
1304 }
1305
1306 static int intel_850_configure(void)
1307 {
1308         u32 temp;
1309         u16 temp2;
1310         struct aper_size_info_8 *current_size;
1311
1312         current_size = A_SIZE_8(agp_bridge->current_size);
1313
1314         /* aperture size */
1315         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1316
1317         /* address to map to */
1318         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1319         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1320
1321         /* attbase - aperture base */
1322         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1323
1324         /* agpctrl */
1325         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1326
1327         /* mcgcfg */
1328         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1329         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1330         /* clear any possible AGP-related error conditions */
1331         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1332         return 0;
1333 }
1334
1335 static int intel_860_configure(void)
1336 {
1337         u32 temp;
1338         u16 temp2;
1339         struct aper_size_info_8 *current_size;
1340
1341         current_size = A_SIZE_8(agp_bridge->current_size);
1342
1343         /* aperture size */
1344         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1345
1346         /* address to map to */
1347         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1348         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1349
1350         /* attbase - aperture base */
1351         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1352
1353         /* agpctrl */
1354         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1355
1356         /* mcgcfg */
1357         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1358         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1359         /* clear any possible AGP-related error conditions */
1360         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1361         return 0;
1362 }
1363
1364 static int intel_830mp_configure(void)
1365 {
1366         u32 temp;
1367         u16 temp2;
1368         struct aper_size_info_8 *current_size;
1369
1370         current_size = A_SIZE_8(agp_bridge->current_size);
1371
1372         /* aperture size */
1373         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1374
1375         /* address to map to */
1376         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1377         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1378
1379         /* attbase - aperture base */
1380         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1381
1382         /* agpctrl */
1383         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1384
1385         /* gmch */
1386         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1387         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1388         /* clear any possible AGP-related error conditions */
1389         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1390         return 0;
1391 }
1392
1393 static int intel_7505_configure(void)
1394 {
1395         u32 temp;
1396         u16 temp2;
1397         struct aper_size_info_8 *current_size;
1398
1399         current_size = A_SIZE_8(agp_bridge->current_size);
1400
1401         /* aperture size */
1402         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1403
1404         /* address to map to */
1405         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1406         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1407
1408         /* attbase - aperture base */
1409         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1410
1411         /* agpctrl */
1412         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1413
1414         /* mchcfg */
1415         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1416         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1417
1418         return 0;
1419 }
1420
1421 /* Setup function */
1422 static const struct gatt_mask intel_generic_masks[] =
1423 {
1424         {.mask = 0x00000017, .type = 0}
1425 };
1426
1427 static const struct aper_size_info_8 intel_815_sizes[2] =
1428 {
1429         {64, 16384, 4, 0},
1430         {32, 8192, 3, 8},
1431 };
1432
1433 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1434 {
1435         {256, 65536, 6, 0},
1436         {128, 32768, 5, 32},
1437         {64, 16384, 4, 48},
1438         {32, 8192, 3, 56},
1439         {16, 4096, 2, 60},
1440         {8, 2048, 1, 62},
1441         {4, 1024, 0, 63}
1442 };
1443
1444 static const struct aper_size_info_16 intel_generic_sizes[7] =
1445 {
1446         {256, 65536, 6, 0},
1447         {128, 32768, 5, 32},
1448         {64, 16384, 4, 48},
1449         {32, 8192, 3, 56},
1450         {16, 4096, 2, 60},
1451         {8, 2048, 1, 62},
1452         {4, 1024, 0, 63}
1453 };
1454
1455 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1456 {
1457         {256, 65536, 6, 0},
1458         {128, 32768, 5, 32},
1459         {64, 16384, 4, 48},
1460         {32, 8192, 3, 56}
1461 };
1462
1463 static const struct agp_bridge_driver intel_generic_driver = {
1464         .owner                  = THIS_MODULE,
1465         .aperture_sizes         = intel_generic_sizes,
1466         .size_type              = U16_APER_SIZE,
1467         .num_aperture_sizes     = 7,
1468         .configure              = intel_configure,
1469         .fetch_size             = intel_fetch_size,
1470         .cleanup                = intel_cleanup,
1471         .tlb_flush              = intel_tlbflush,
1472         .mask_memory            = agp_generic_mask_memory,
1473         .masks                  = intel_generic_masks,
1474         .agp_enable             = agp_generic_enable,
1475         .cache_flush            = global_cache_flush,
1476         .create_gatt_table      = agp_generic_create_gatt_table,
1477         .free_gatt_table        = agp_generic_free_gatt_table,
1478         .insert_memory          = agp_generic_insert_memory,
1479         .remove_memory          = agp_generic_remove_memory,
1480         .alloc_by_type          = agp_generic_alloc_by_type,
1481         .free_by_type           = agp_generic_free_by_type,
1482         .agp_alloc_page         = agp_generic_alloc_page,
1483         .agp_destroy_page       = agp_generic_destroy_page,
1484         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1485 };
1486
1487 static const struct agp_bridge_driver intel_810_driver = {
1488         .owner                  = THIS_MODULE,
1489         .aperture_sizes         = intel_i810_sizes,
1490         .size_type              = FIXED_APER_SIZE,
1491         .num_aperture_sizes     = 2,
1492         .needs_scratch_page     = TRUE,
1493         .configure              = intel_i810_configure,
1494         .fetch_size             = intel_i810_fetch_size,
1495         .cleanup                = intel_i810_cleanup,
1496         .tlb_flush              = intel_i810_tlbflush,
1497         .mask_memory            = intel_i810_mask_memory,
1498         .masks                  = intel_i810_masks,
1499         .agp_enable             = intel_i810_agp_enable,
1500         .cache_flush            = global_cache_flush,
1501         .create_gatt_table      = agp_generic_create_gatt_table,
1502         .free_gatt_table        = agp_generic_free_gatt_table,
1503         .insert_memory          = intel_i810_insert_entries,
1504         .remove_memory          = intel_i810_remove_entries,
1505         .alloc_by_type          = intel_i810_alloc_by_type,
1506         .free_by_type           = intel_i810_free_by_type,
1507         .agp_alloc_page         = agp_generic_alloc_page,
1508         .agp_destroy_page       = agp_generic_destroy_page,
1509         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1510 };
1511
1512 static const struct agp_bridge_driver intel_815_driver = {
1513         .owner                  = THIS_MODULE,
1514         .aperture_sizes         = intel_815_sizes,
1515         .size_type              = U8_APER_SIZE,
1516         .num_aperture_sizes     = 2,
1517         .configure              = intel_815_configure,
1518         .fetch_size             = intel_815_fetch_size,
1519         .cleanup                = intel_8xx_cleanup,
1520         .tlb_flush              = intel_8xx_tlbflush,
1521         .mask_memory            = agp_generic_mask_memory,
1522         .masks                  = intel_generic_masks,
1523         .agp_enable             = agp_generic_enable,
1524         .cache_flush            = global_cache_flush,
1525         .create_gatt_table      = agp_generic_create_gatt_table,
1526         .free_gatt_table        = agp_generic_free_gatt_table,
1527         .insert_memory          = agp_generic_insert_memory,
1528         .remove_memory          = agp_generic_remove_memory,
1529         .alloc_by_type          = agp_generic_alloc_by_type,
1530         .free_by_type           = agp_generic_free_by_type,
1531         .agp_alloc_page         = agp_generic_alloc_page,
1532         .agp_destroy_page       = agp_generic_destroy_page,
1533         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1534 };
1535
1536 static const struct agp_bridge_driver intel_830_driver = {
1537         .owner                  = THIS_MODULE,
1538         .aperture_sizes         = intel_i830_sizes,
1539         .size_type              = FIXED_APER_SIZE,
1540         .num_aperture_sizes     = 4,
1541         .needs_scratch_page     = TRUE,
1542         .configure              = intel_i830_configure,
1543         .fetch_size             = intel_i830_fetch_size,
1544         .cleanup                = intel_i830_cleanup,
1545         .tlb_flush              = intel_i810_tlbflush,
1546         .mask_memory            = intel_i810_mask_memory,
1547         .masks                  = intel_i810_masks,
1548         .agp_enable             = intel_i810_agp_enable,
1549         .cache_flush            = global_cache_flush,
1550         .create_gatt_table      = intel_i830_create_gatt_table,
1551         .free_gatt_table        = intel_i830_free_gatt_table,
1552         .insert_memory          = intel_i830_insert_entries,
1553         .remove_memory          = intel_i830_remove_entries,
1554         .alloc_by_type          = intel_i830_alloc_by_type,
1555         .free_by_type           = intel_i810_free_by_type,
1556         .agp_alloc_page         = agp_generic_alloc_page,
1557         .agp_destroy_page       = agp_generic_destroy_page,
1558         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1559 };
1560
1561 static const struct agp_bridge_driver intel_820_driver = {
1562         .owner                  = THIS_MODULE,
1563         .aperture_sizes         = intel_8xx_sizes,
1564         .size_type              = U8_APER_SIZE,
1565         .num_aperture_sizes     = 7,
1566         .configure              = intel_820_configure,
1567         .fetch_size             = intel_8xx_fetch_size,
1568         .cleanup                = intel_820_cleanup,
1569         .tlb_flush              = intel_820_tlbflush,
1570         .mask_memory            = agp_generic_mask_memory,
1571         .masks                  = intel_generic_masks,
1572         .agp_enable             = agp_generic_enable,
1573         .cache_flush            = global_cache_flush,
1574         .create_gatt_table      = agp_generic_create_gatt_table,
1575         .free_gatt_table        = agp_generic_free_gatt_table,
1576         .insert_memory          = agp_generic_insert_memory,
1577         .remove_memory          = agp_generic_remove_memory,
1578         .alloc_by_type          = agp_generic_alloc_by_type,
1579         .free_by_type           = agp_generic_free_by_type,
1580         .agp_alloc_page         = agp_generic_alloc_page,
1581         .agp_destroy_page       = agp_generic_destroy_page,
1582         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1583 };
1584
1585 static const struct agp_bridge_driver intel_830mp_driver = {
1586         .owner                  = THIS_MODULE,
1587         .aperture_sizes         = intel_830mp_sizes,
1588         .size_type              = U8_APER_SIZE,
1589         .num_aperture_sizes     = 4,
1590         .configure              = intel_830mp_configure,
1591         .fetch_size             = intel_8xx_fetch_size,
1592         .cleanup                = intel_8xx_cleanup,
1593         .tlb_flush              = intel_8xx_tlbflush,
1594         .mask_memory            = agp_generic_mask_memory,
1595         .masks                  = intel_generic_masks,
1596         .agp_enable             = agp_generic_enable,
1597         .cache_flush            = global_cache_flush,
1598         .create_gatt_table      = agp_generic_create_gatt_table,
1599         .free_gatt_table        = agp_generic_free_gatt_table,
1600         .insert_memory          = agp_generic_insert_memory,
1601         .remove_memory          = agp_generic_remove_memory,
1602         .alloc_by_type          = agp_generic_alloc_by_type,
1603         .free_by_type           = agp_generic_free_by_type,
1604         .agp_alloc_page         = agp_generic_alloc_page,
1605         .agp_destroy_page       = agp_generic_destroy_page,
1606         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1607 };
1608
1609 static const struct agp_bridge_driver intel_840_driver = {
1610         .owner                  = THIS_MODULE,
1611         .aperture_sizes         = intel_8xx_sizes,
1612         .size_type              = U8_APER_SIZE,
1613         .num_aperture_sizes     = 7,
1614         .configure              = intel_840_configure,
1615         .fetch_size             = intel_8xx_fetch_size,
1616         .cleanup                = intel_8xx_cleanup,
1617         .tlb_flush              = intel_8xx_tlbflush,
1618         .mask_memory            = agp_generic_mask_memory,
1619         .masks                  = intel_generic_masks,
1620         .agp_enable             = agp_generic_enable,
1621         .cache_flush            = global_cache_flush,
1622         .create_gatt_table      = agp_generic_create_gatt_table,
1623         .free_gatt_table        = agp_generic_free_gatt_table,
1624         .insert_memory          = agp_generic_insert_memory,
1625         .remove_memory          = agp_generic_remove_memory,
1626         .alloc_by_type          = agp_generic_alloc_by_type,
1627         .free_by_type           = agp_generic_free_by_type,
1628         .agp_alloc_page         = agp_generic_alloc_page,
1629         .agp_destroy_page       = agp_generic_destroy_page,
1630         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1631 };
1632
1633 static const struct agp_bridge_driver intel_845_driver = {
1634         .owner                  = THIS_MODULE,
1635         .aperture_sizes         = intel_8xx_sizes,
1636         .size_type              = U8_APER_SIZE,
1637         .num_aperture_sizes     = 7,
1638         .configure              = intel_845_configure,
1639         .fetch_size             = intel_8xx_fetch_size,
1640         .cleanup                = intel_8xx_cleanup,
1641         .tlb_flush              = intel_8xx_tlbflush,
1642         .mask_memory            = agp_generic_mask_memory,
1643         .masks                  = intel_generic_masks,
1644         .agp_enable             = agp_generic_enable,
1645         .cache_flush            = global_cache_flush,
1646         .create_gatt_table      = agp_generic_create_gatt_table,
1647         .free_gatt_table        = agp_generic_free_gatt_table,
1648         .insert_memory          = agp_generic_insert_memory,
1649         .remove_memory          = agp_generic_remove_memory,
1650         .alloc_by_type          = agp_generic_alloc_by_type,
1651         .free_by_type           = agp_generic_free_by_type,
1652         .agp_alloc_page         = agp_generic_alloc_page,
1653         .agp_destroy_page       = agp_generic_destroy_page,
1654         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1655 };
1656
1657 static const struct agp_bridge_driver intel_850_driver = {
1658         .owner                  = THIS_MODULE,
1659         .aperture_sizes         = intel_8xx_sizes,
1660         .size_type              = U8_APER_SIZE,
1661         .num_aperture_sizes     = 7,
1662         .configure              = intel_850_configure,
1663         .fetch_size             = intel_8xx_fetch_size,
1664         .cleanup                = intel_8xx_cleanup,
1665         .tlb_flush              = intel_8xx_tlbflush,
1666         .mask_memory            = agp_generic_mask_memory,
1667         .masks                  = intel_generic_masks,
1668         .agp_enable             = agp_generic_enable,
1669         .cache_flush            = global_cache_flush,
1670         .create_gatt_table      = agp_generic_create_gatt_table,
1671         .free_gatt_table        = agp_generic_free_gatt_table,
1672         .insert_memory          = agp_generic_insert_memory,
1673         .remove_memory          = agp_generic_remove_memory,
1674         .alloc_by_type          = agp_generic_alloc_by_type,
1675         .free_by_type           = agp_generic_free_by_type,
1676         .agp_alloc_page         = agp_generic_alloc_page,
1677         .agp_destroy_page       = agp_generic_destroy_page,
1678         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1679 };
1680
1681 static const struct agp_bridge_driver intel_860_driver = {
1682         .owner                  = THIS_MODULE,
1683         .aperture_sizes         = intel_8xx_sizes,
1684         .size_type              = U8_APER_SIZE,
1685         .num_aperture_sizes     = 7,
1686         .configure              = intel_860_configure,
1687         .fetch_size             = intel_8xx_fetch_size,
1688         .cleanup                = intel_8xx_cleanup,
1689         .tlb_flush              = intel_8xx_tlbflush,
1690         .mask_memory            = agp_generic_mask_memory,
1691         .masks                  = intel_generic_masks,
1692         .agp_enable             = agp_generic_enable,
1693         .cache_flush            = global_cache_flush,
1694         .create_gatt_table      = agp_generic_create_gatt_table,
1695         .free_gatt_table        = agp_generic_free_gatt_table,
1696         .insert_memory          = agp_generic_insert_memory,
1697         .remove_memory          = agp_generic_remove_memory,
1698         .alloc_by_type          = agp_generic_alloc_by_type,
1699         .free_by_type           = agp_generic_free_by_type,
1700         .agp_alloc_page         = agp_generic_alloc_page,
1701         .agp_destroy_page       = agp_generic_destroy_page,
1702         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1703 };
1704
1705 static const struct agp_bridge_driver intel_915_driver = {
1706         .owner                  = THIS_MODULE,
1707         .aperture_sizes         = intel_i830_sizes,
1708         .size_type              = FIXED_APER_SIZE,
1709         .num_aperture_sizes     = 4,
1710         .needs_scratch_page     = TRUE,
1711         .configure              = intel_i915_configure,
1712         .fetch_size             = intel_i9xx_fetch_size,
1713         .cleanup                = intel_i915_cleanup,
1714         .tlb_flush              = intel_i810_tlbflush,
1715         .mask_memory            = intel_i810_mask_memory,
1716         .masks                  = intel_i810_masks,
1717         .agp_enable             = intel_i810_agp_enable,
1718         .cache_flush            = global_cache_flush,
1719         .create_gatt_table      = intel_i915_create_gatt_table,
1720         .free_gatt_table        = intel_i830_free_gatt_table,
1721         .insert_memory          = intel_i915_insert_entries,
1722         .remove_memory          = intel_i915_remove_entries,
1723         .alloc_by_type          = intel_i830_alloc_by_type,
1724         .free_by_type           = intel_i810_free_by_type,
1725         .agp_alloc_page         = agp_generic_alloc_page,
1726         .agp_destroy_page       = agp_generic_destroy_page,
1727         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1728 };
1729
1730 static const struct agp_bridge_driver intel_i965_driver = {
1731        .owner                  = THIS_MODULE,
1732        .aperture_sizes         = intel_i830_sizes,
1733        .size_type              = FIXED_APER_SIZE,
1734        .num_aperture_sizes     = 4,
1735        .needs_scratch_page     = TRUE,
1736        .configure              = intel_i915_configure,
1737        .fetch_size             = intel_i9xx_fetch_size,
1738        .cleanup                = intel_i915_cleanup,
1739        .tlb_flush              = intel_i810_tlbflush,
1740        .mask_memory            = intel_i965_mask_memory,
1741        .masks                  = intel_i810_masks,
1742        .agp_enable             = intel_i810_agp_enable,
1743        .cache_flush            = global_cache_flush,
1744        .create_gatt_table      = intel_i965_create_gatt_table,
1745        .free_gatt_table        = intel_i830_free_gatt_table,
1746        .insert_memory          = intel_i915_insert_entries,
1747        .remove_memory          = intel_i915_remove_entries,
1748        .alloc_by_type          = intel_i830_alloc_by_type,
1749        .free_by_type           = intel_i810_free_by_type,
1750        .agp_alloc_page         = agp_generic_alloc_page,
1751        .agp_destroy_page       = agp_generic_destroy_page,
1752        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1753 };
1754
1755 static const struct agp_bridge_driver intel_7505_driver = {
1756         .owner                  = THIS_MODULE,
1757         .aperture_sizes         = intel_8xx_sizes,
1758         .size_type              = U8_APER_SIZE,
1759         .num_aperture_sizes     = 7,
1760         .configure              = intel_7505_configure,
1761         .fetch_size             = intel_8xx_fetch_size,
1762         .cleanup                = intel_8xx_cleanup,
1763         .tlb_flush              = intel_8xx_tlbflush,
1764         .mask_memory            = agp_generic_mask_memory,
1765         .masks                  = intel_generic_masks,
1766         .agp_enable             = agp_generic_enable,
1767         .cache_flush            = global_cache_flush,
1768         .create_gatt_table      = agp_generic_create_gatt_table,
1769         .free_gatt_table        = agp_generic_free_gatt_table,
1770         .insert_memory          = agp_generic_insert_memory,
1771         .remove_memory          = agp_generic_remove_memory,
1772         .alloc_by_type          = agp_generic_alloc_by_type,
1773         .free_by_type           = agp_generic_free_by_type,
1774         .agp_alloc_page         = agp_generic_alloc_page,
1775         .agp_destroy_page       = agp_generic_destroy_page,
1776         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1777 };
1778
1779 static const struct agp_bridge_driver intel_g33_driver = {
1780         .owner                  = THIS_MODULE,
1781         .aperture_sizes         = intel_i830_sizes,
1782         .size_type              = FIXED_APER_SIZE,
1783         .num_aperture_sizes     = 4,
1784         .needs_scratch_page     = TRUE,
1785         .configure              = intel_i915_configure,
1786         .fetch_size             = intel_i9xx_fetch_size,
1787         .cleanup                = intel_i915_cleanup,
1788         .tlb_flush              = intel_i810_tlbflush,
1789         .mask_memory            = intel_i965_mask_memory,
1790         .masks                  = intel_i810_masks,
1791         .agp_enable             = intel_i810_agp_enable,
1792         .cache_flush            = global_cache_flush,
1793         .create_gatt_table      = intel_i915_create_gatt_table,
1794         .free_gatt_table        = intel_i830_free_gatt_table,
1795         .insert_memory          = intel_i915_insert_entries,
1796         .remove_memory          = intel_i915_remove_entries,
1797         .alloc_by_type          = intel_i830_alloc_by_type,
1798         .free_by_type           = intel_i810_free_by_type,
1799         .agp_alloc_page         = agp_generic_alloc_page,
1800         .agp_destroy_page       = agp_generic_destroy_page,
1801         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1802 };
1803
1804 static int find_gmch(u16 device)
1805 {
1806         struct pci_dev *gmch_device;
1807
1808         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1809         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1810                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1811                                 device, gmch_device);
1812         }
1813
1814         if (!gmch_device)
1815                 return 0;
1816
1817         intel_private.pcidev = gmch_device;
1818         return 1;
1819 }
1820
1821 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1822  * driver and gmch_driver must be non-null, and find_gmch will determine
1823  * which one should be used if a gmch_chip_id is present.
1824  */
1825 static const struct intel_driver_description {
1826         unsigned int chip_id;
1827         unsigned int gmch_chip_id;
1828         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
1829         char *name;
1830         const struct agp_bridge_driver *driver;
1831         const struct agp_bridge_driver *gmch_driver;
1832 } intel_agp_chipsets[] = {
1833         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
1834         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
1835         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
1836         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
1837                 NULL, &intel_810_driver },
1838         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
1839                 NULL, &intel_810_driver },
1840         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
1841                 NULL, &intel_810_driver },
1842         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
1843                 &intel_815_driver, &intel_810_driver },
1844         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
1845         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
1846         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
1847                 &intel_830mp_driver, &intel_830_driver },
1848         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
1849         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
1850         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
1851                 &intel_845_driver, &intel_830_driver },
1852         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
1853         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
1854         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
1855                 &intel_845_driver, &intel_830_driver },
1856         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
1857         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
1858                 &intel_845_driver, &intel_830_driver },
1859         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
1860         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
1861                 NULL, &intel_915_driver },
1862         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
1863                 NULL, &intel_915_driver },
1864         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
1865                 NULL, &intel_915_driver },
1866         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
1867                 NULL, &intel_915_driver },
1868         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
1869                 NULL, &intel_915_driver },
1870         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
1871                 NULL, &intel_i965_driver },
1872         { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, 0, "965G",
1873                 NULL, &intel_i965_driver },
1874         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
1875                 NULL, &intel_i965_driver },
1876         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
1877                 NULL, &intel_i965_driver },
1878         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
1879                 NULL, &intel_i965_driver },
1880         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
1881                 NULL, &intel_i965_driver },
1882         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
1883         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
1884         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
1885                 NULL, &intel_g33_driver },
1886         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
1887                 NULL, &intel_g33_driver },
1888         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
1889                 NULL, &intel_g33_driver },
1890         { 0, 0, 0, NULL, NULL, NULL }
1891 };
1892
1893 static int __devinit agp_intel_probe(struct pci_dev *pdev,
1894                                      const struct pci_device_id *ent)
1895 {
1896         struct agp_bridge_data *bridge;
1897         u8 cap_ptr = 0;
1898         struct resource *r;
1899         int i;
1900
1901         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
1902
1903         bridge = agp_alloc_bridge();
1904         if (!bridge)
1905                 return -ENOMEM;
1906
1907         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
1908                 /* In case that multiple models of gfx chip may
1909                    stand on same host bridge type, this can be
1910                    sure we detect the right IGD. */
1911                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
1912                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
1913                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
1914                                 bridge->driver =
1915                                         intel_agp_chipsets[i].gmch_driver;
1916                                 break;
1917                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
1918                                 continue;
1919                         } else {
1920                                 bridge->driver = intel_agp_chipsets[i].driver;
1921                                 break;
1922                         }
1923                 }
1924         }
1925
1926         if (intel_agp_chipsets[i].name == NULL) {
1927                 if (cap_ptr)
1928                         printk(KERN_WARNING PFX "Unsupported Intel chipset"
1929                                "(device id: %04x)\n", pdev->device);
1930                 agp_put_bridge(bridge);
1931                 return -ENODEV;
1932         }
1933
1934         if (bridge->driver == NULL) {
1935                 /* bridge has no AGP and no IGD detected */
1936                 if (cap_ptr)
1937                         printk(KERN_WARNING PFX "Failed to find bridge device "
1938                                 "(chip_id: %04x)\n",
1939                                 intel_agp_chipsets[i].gmch_chip_id);
1940                 agp_put_bridge(bridge);
1941                 return -ENODEV;
1942         }
1943
1944         bridge->dev = pdev;
1945         bridge->capndx = cap_ptr;
1946         bridge->dev_private_data = &intel_private;
1947
1948         printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
1949                 intel_agp_chipsets[i].name);
1950
1951         /*
1952         * The following fixes the case where the BIOS has "forgotten" to
1953         * provide an address range for the GART.
1954         * 20030610 - hamish@zot.org
1955         */
1956         r = &pdev->resource[0];
1957         if (!r->start && r->end) {
1958                 if (pci_assign_resource(pdev, 0)) {
1959                         printk(KERN_ERR PFX "could not assign resource 0\n");
1960                         agp_put_bridge(bridge);
1961                         return -ENODEV;
1962                 }
1963         }
1964
1965         /*
1966         * If the device has not been properly setup, the following will catch
1967         * the problem and should stop the system from crashing.
1968         * 20030610 - hamish@zot.org
1969         */
1970         if (pci_enable_device(pdev)) {
1971                 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
1972                 agp_put_bridge(bridge);
1973                 return -ENODEV;
1974         }
1975
1976         /* Fill in the mode register */
1977         if (cap_ptr) {
1978                 pci_read_config_dword(pdev,
1979                                 bridge->capndx+PCI_AGP_STATUS,
1980                                 &bridge->mode);
1981         }
1982
1983         pci_set_drvdata(pdev, bridge);
1984         return agp_add_bridge(bridge);
1985 }
1986
1987 static void __devexit agp_intel_remove(struct pci_dev *pdev)
1988 {
1989         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1990
1991         agp_remove_bridge(bridge);
1992
1993         if (intel_private.pcidev)
1994                 pci_dev_put(intel_private.pcidev);
1995
1996         agp_put_bridge(bridge);
1997 }
1998
1999 #ifdef CONFIG_PM
2000 static int agp_intel_resume(struct pci_dev *pdev)
2001 {
2002         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2003
2004         pci_restore_state(pdev);
2005
2006         /* We should restore our graphics device's config space,
2007          * as host bridge (00:00) resumes before graphics device (02:00),
2008          * then our access to its pci space can work right.
2009          */
2010         if (intel_private.pcidev)
2011                 pci_restore_state(intel_private.pcidev);
2012
2013         if (bridge->driver == &intel_generic_driver)
2014                 intel_configure();
2015         else if (bridge->driver == &intel_850_driver)
2016                 intel_850_configure();
2017         else if (bridge->driver == &intel_845_driver)
2018                 intel_845_configure();
2019         else if (bridge->driver == &intel_830mp_driver)
2020                 intel_830mp_configure();
2021         else if (bridge->driver == &intel_915_driver)
2022                 intel_i915_configure();
2023         else if (bridge->driver == &intel_830_driver)
2024                 intel_i830_configure();
2025         else if (bridge->driver == &intel_810_driver)
2026                 intel_i810_configure();
2027         else if (bridge->driver == &intel_i965_driver)
2028                 intel_i915_configure();
2029
2030         return 0;
2031 }
2032 #endif
2033
2034 static struct pci_device_id agp_intel_pci_table[] = {
2035 #define ID(x)                                           \
2036         {                                               \
2037         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2038         .class_mask     = ~0,                           \
2039         .vendor         = PCI_VENDOR_ID_INTEL,          \
2040         .device         = x,                            \
2041         .subvendor      = PCI_ANY_ID,                   \
2042         .subdevice      = PCI_ANY_ID,                   \
2043         }
2044         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2045         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2046         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2047         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2048         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2049         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2050         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2051         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2052         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2053         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2054         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2055         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2056         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2057         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2058         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2059         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2060         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2061         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2062         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2063         ID(PCI_DEVICE_ID_INTEL_7505_0),
2064         ID(PCI_DEVICE_ID_INTEL_7205_0),
2065         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2066         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2067         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2068         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2069         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2070         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2071         ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
2072         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2073         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2074         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2075         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2076         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2077         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2078         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2079         { }
2080 };
2081
2082 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2083
2084 static struct pci_driver agp_intel_pci_driver = {
2085         .name           = "agpgart-intel",
2086         .id_table       = agp_intel_pci_table,
2087         .probe          = agp_intel_probe,
2088         .remove         = __devexit_p(agp_intel_remove),
2089 #ifdef CONFIG_PM
2090         .resume         = agp_intel_resume,
2091 #endif
2092 };
2093
2094 static int __init agp_intel_init(void)
2095 {
2096         if (agp_off)
2097                 return -EINVAL;
2098         return pci_register_driver(&agp_intel_pci_driver);
2099 }
2100
2101 static void __exit agp_intel_cleanup(void)
2102 {
2103         pci_unregister_driver(&agp_intel_pci_driver);
2104 }
2105
2106 module_init(agp_intel_init);
2107 module_exit(agp_intel_cleanup);
2108
2109 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2110 MODULE_LICENSE("GPL and additional rights");