Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
[linux-2.6.git] / drivers / char / agp / intel-agp.c
1 /*
2  * Intel AGPGART routines.
3  */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
11 #include "agp.h"
12
13 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
14 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
15 #define PCI_DEVICE_ID_INTEL_82965G_1_HB     0x2980
16 #define PCI_DEVICE_ID_INTEL_82965G_1_IG     0x2982
17 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
18 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
19 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
20 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
21 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
22 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
23 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
24 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
25 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
26 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
27 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
28 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
29 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
30 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
31 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
32 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
33
34 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
35                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
36                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
37                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
38                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
39                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
40
41 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
42                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
43                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
44
45 extern int agp_memory_reserved;
46
47
48 /* Intel 815 register */
49 #define INTEL_815_APCONT        0x51
50 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
51
52 /* Intel i820 registers */
53 #define INTEL_I820_RDCR         0x51
54 #define INTEL_I820_ERRSTS       0xc8
55
56 /* Intel i840 registers */
57 #define INTEL_I840_MCHCFG       0x50
58 #define INTEL_I840_ERRSTS       0xc8
59
60 /* Intel i850 registers */
61 #define INTEL_I850_MCHCFG       0x50
62 #define INTEL_I850_ERRSTS       0xc8
63
64 /* intel 915G registers */
65 #define I915_GMADDR     0x18
66 #define I915_MMADDR     0x10
67 #define I915_PTEADDR    0x1C
68 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
69 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
70 #define G33_GMCH_GMS_STOLEN_128M       (0x8 << 4)
71 #define G33_GMCH_GMS_STOLEN_256M       (0x9 << 4)
72
73 /* Intel 965G registers */
74 #define I965_MSAC 0x62
75
76 /* Intel 7505 registers */
77 #define INTEL_I7505_APSIZE      0x74
78 #define INTEL_I7505_NCAPID      0x60
79 #define INTEL_I7505_NISTAT      0x6c
80 #define INTEL_I7505_ATTBASE     0x78
81 #define INTEL_I7505_ERRSTS      0x42
82 #define INTEL_I7505_AGPCTRL     0x70
83 #define INTEL_I7505_MCHCFG      0x50
84
85 static const struct aper_size_info_fixed intel_i810_sizes[] =
86 {
87         {64, 16384, 4},
88         /* The 32M mode still requires a 64k gatt */
89         {32, 8192, 4}
90 };
91
92 #define AGP_DCACHE_MEMORY       1
93 #define AGP_PHYS_MEMORY         2
94 #define INTEL_AGP_CACHED_MEMORY 3
95
96 static struct gatt_mask intel_i810_masks[] =
97 {
98         {.mask = I810_PTE_VALID, .type = 0},
99         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
100         {.mask = I810_PTE_VALID, .type = 0},
101         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
102          .type = INTEL_AGP_CACHED_MEMORY}
103 };
104
105 static struct _intel_private {
106         struct pci_dev *pcidev; /* device one */
107         u8 __iomem *registers;
108         u32 __iomem *gtt;               /* I915G */
109         int num_dcache_entries;
110         /* gtt_entries is the number of gtt entries that are already mapped
111          * to stolen memory.  Stolen memory is larger than the memory mapped
112          * through gtt_entries, as it includes some reserved space for the BIOS
113          * popup and for the GTT.
114          */
115         int gtt_entries;                        /* i830+ */
116 } intel_private;
117
118 static int intel_i810_fetch_size(void)
119 {
120         u32 smram_miscc;
121         struct aper_size_info_fixed *values;
122
123         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
124         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
125
126         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
127                 printk(KERN_WARNING PFX "i810 is disabled\n");
128                 return 0;
129         }
130         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
131                 agp_bridge->previous_size =
132                         agp_bridge->current_size = (void *) (values + 1);
133                 agp_bridge->aperture_size_idx = 1;
134                 return values[1].size;
135         } else {
136                 agp_bridge->previous_size =
137                         agp_bridge->current_size = (void *) (values);
138                 agp_bridge->aperture_size_idx = 0;
139                 return values[0].size;
140         }
141
142         return 0;
143 }
144
145 static int intel_i810_configure(void)
146 {
147         struct aper_size_info_fixed *current_size;
148         u32 temp;
149         int i;
150
151         current_size = A_SIZE_FIX(agp_bridge->current_size);
152
153         if (!intel_private.registers) {
154                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
155                 temp &= 0xfff80000;
156
157                 intel_private.registers = ioremap(temp, 128 * 4096);
158                 if (!intel_private.registers) {
159                         printk(KERN_ERR PFX "Unable to remap memory.\n");
160                         return -ENOMEM;
161                 }
162         }
163
164         if ((readl(intel_private.registers+I810_DRAM_CTL)
165                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
166                 /* This will need to be dynamically assigned */
167                 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
168                 intel_private.num_dcache_entries = 1024;
169         }
170         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
171         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
172         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
173         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
174
175         if (agp_bridge->driver->needs_scratch_page) {
176                 for (i = 0; i < current_size->num_entries; i++) {
177                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
178                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI posting. */
179                 }
180         }
181         global_cache_flush();
182         return 0;
183 }
184
185 static void intel_i810_cleanup(void)
186 {
187         writel(0, intel_private.registers+I810_PGETBL_CTL);
188         readl(intel_private.registers); /* PCI Posting. */
189         iounmap(intel_private.registers);
190 }
191
192 static void intel_i810_tlbflush(struct agp_memory *mem)
193 {
194         return;
195 }
196
197 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
198 {
199         return;
200 }
201
202 /* Exists to support ARGB cursors */
203 static void *i8xx_alloc_pages(void)
204 {
205         struct page * page;
206
207         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
208         if (page == NULL)
209                 return NULL;
210
211         if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) {
212                 change_page_attr(page, 4, PAGE_KERNEL);
213                 global_flush_tlb();
214                 __free_pages(page, 2);
215                 return NULL;
216         }
217         global_flush_tlb();
218         get_page(page);
219         atomic_inc(&agp_bridge->current_memory_agp);
220         return page_address(page);
221 }
222
223 static void i8xx_destroy_pages(void *addr)
224 {
225         struct page *page;
226
227         if (addr == NULL)
228                 return;
229
230         page = virt_to_page(addr);
231         change_page_attr(page, 4, PAGE_KERNEL);
232         global_flush_tlb();
233         put_page(page);
234         __free_pages(page, 2);
235         atomic_dec(&agp_bridge->current_memory_agp);
236 }
237
238 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
239                                         int type)
240 {
241         if (type < AGP_USER_TYPES)
242                 return type;
243         else if (type == AGP_USER_CACHED_MEMORY)
244                 return INTEL_AGP_CACHED_MEMORY;
245         else
246                 return 0;
247 }
248
249 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
250                                 int type)
251 {
252         int i, j, num_entries;
253         void *temp;
254         int ret = -EINVAL;
255         int mask_type;
256
257         if (mem->page_count == 0)
258                 goto out;
259
260         temp = agp_bridge->current_size;
261         num_entries = A_SIZE_FIX(temp)->num_entries;
262
263         if ((pg_start + mem->page_count) > num_entries)
264                 goto out_err;
265
266
267         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
268                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
269                         ret = -EBUSY;
270                         goto out_err;
271                 }
272         }
273
274         if (type != mem->type)
275                 goto out_err;
276
277         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
278
279         switch (mask_type) {
280         case AGP_DCACHE_MEMORY:
281                 if (!mem->is_flushed)
282                         global_cache_flush();
283                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
284                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
285                                intel_private.registers+I810_PTE_BASE+(i*4));
286                 }
287                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
288                 break;
289         case AGP_PHYS_MEMORY:
290         case AGP_NORMAL_MEMORY:
291                 if (!mem->is_flushed)
292                         global_cache_flush();
293                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
294                         writel(agp_bridge->driver->mask_memory(agp_bridge,
295                                                                mem->memory[i],
296                                                                mask_type),
297                                intel_private.registers+I810_PTE_BASE+(j*4));
298                 }
299                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
300                 break;
301         default:
302                 goto out_err;
303         }
304
305         agp_bridge->driver->tlb_flush(mem);
306 out:
307         ret = 0;
308 out_err:
309         mem->is_flushed = 1;
310         return ret;
311 }
312
313 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
314                                 int type)
315 {
316         int i;
317
318         if (mem->page_count == 0)
319                 return 0;
320
321         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
322                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
323         }
324         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
325
326         agp_bridge->driver->tlb_flush(mem);
327         return 0;
328 }
329
330 /*
331  * The i810/i830 requires a physical address to program its mouse
332  * pointer into hardware.
333  * However the Xserver still writes to it through the agp aperture.
334  */
335 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
336 {
337         struct agp_memory *new;
338         void *addr;
339
340         switch (pg_count) {
341         case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
342                 global_flush_tlb();
343                 break;
344         case 4:
345                 /* kludge to get 4 physical pages for ARGB cursor */
346                 addr = i8xx_alloc_pages();
347                 break;
348         default:
349                 return NULL;
350         }
351
352         if (addr == NULL)
353                 return NULL;
354
355         new = agp_create_memory(pg_count);
356         if (new == NULL)
357                 return NULL;
358
359         new->memory[0] = virt_to_gart(addr);
360         if (pg_count == 4) {
361                 /* kludge to get 4 physical pages for ARGB cursor */
362                 new->memory[1] = new->memory[0] + PAGE_SIZE;
363                 new->memory[2] = new->memory[1] + PAGE_SIZE;
364                 new->memory[3] = new->memory[2] + PAGE_SIZE;
365         }
366         new->page_count = pg_count;
367         new->num_scratch_pages = pg_count;
368         new->type = AGP_PHYS_MEMORY;
369         new->physical = new->memory[0];
370         return new;
371 }
372
373 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
374 {
375         struct agp_memory *new;
376
377         if (type == AGP_DCACHE_MEMORY) {
378                 if (pg_count != intel_private.num_dcache_entries)
379                         return NULL;
380
381                 new = agp_create_memory(1);
382                 if (new == NULL)
383                         return NULL;
384
385                 new->type = AGP_DCACHE_MEMORY;
386                 new->page_count = pg_count;
387                 new->num_scratch_pages = 0;
388                 agp_free_page_array(new);
389                 return new;
390         }
391         if (type == AGP_PHYS_MEMORY)
392                 return alloc_agpphysmem_i8xx(pg_count, type);
393         return NULL;
394 }
395
396 static void intel_i810_free_by_type(struct agp_memory *curr)
397 {
398         agp_free_key(curr->key);
399         if (curr->type == AGP_PHYS_MEMORY) {
400                 if (curr->page_count == 4)
401                         i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
402                 else {
403                         agp_bridge->driver->agp_destroy_page(
404                                  gart_to_virt(curr->memory[0]));
405                         global_flush_tlb();
406                 }
407                 agp_free_page_array(curr);
408         }
409         kfree(curr);
410 }
411
412 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
413         unsigned long addr, int type)
414 {
415         /* Type checking must be done elsewhere */
416         return addr | bridge->driver->masks[type].mask;
417 }
418
419 static struct aper_size_info_fixed intel_i830_sizes[] =
420 {
421         {128, 32768, 5},
422         /* The 64M mode still requires a 128k gatt */
423         {64, 16384, 5},
424         {256, 65536, 6},
425         {512, 131072, 7},
426 };
427
428 static void intel_i830_init_gtt_entries(void)
429 {
430         u16 gmch_ctrl;
431         int gtt_entries;
432         u8 rdct;
433         int local = 0;
434         static const int ddt[4] = { 0, 16, 32, 64 };
435         int size; /* reserved space (in kb) at the top of stolen memory */
436
437         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
438
439         if (IS_I965) {
440                 u32 pgetbl_ctl;
441                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
442
443                 /* The 965 has a field telling us the size of the GTT,
444                  * which may be larger than what is necessary to map the
445                  * aperture.
446                  */
447                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
448                 case I965_PGETBL_SIZE_128KB:
449                         size = 128;
450                         break;
451                 case I965_PGETBL_SIZE_256KB:
452                         size = 256;
453                         break;
454                 case I965_PGETBL_SIZE_512KB:
455                         size = 512;
456                         break;
457                 default:
458                         printk(KERN_INFO PFX "Unknown page table size, "
459                                "assuming 512KB\n");
460                         size = 512;
461                 }
462                 size += 4; /* add in BIOS popup space */
463         } else if (IS_G33) {
464         /* G33's GTT size defined in gmch_ctrl */
465                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
466                 case G33_PGETBL_SIZE_1M:
467                         size = 1024;
468                         break;
469                 case G33_PGETBL_SIZE_2M:
470                         size = 2048;
471                         break;
472                 default:
473                         printk(KERN_INFO PFX "Unknown page table size 0x%x, "
474                                 "assuming 512KB\n",
475                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
476                         size = 512;
477                 }
478                 size += 4;
479         } else {
480                 /* On previous hardware, the GTT size was just what was
481                  * required to map the aperture.
482                  */
483                 size = agp_bridge->driver->fetch_size() + 4;
484         }
485
486         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
487             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
488                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
489                 case I830_GMCH_GMS_STOLEN_512:
490                         gtt_entries = KB(512) - KB(size);
491                         break;
492                 case I830_GMCH_GMS_STOLEN_1024:
493                         gtt_entries = MB(1) - KB(size);
494                         break;
495                 case I830_GMCH_GMS_STOLEN_8192:
496                         gtt_entries = MB(8) - KB(size);
497                         break;
498                 case I830_GMCH_GMS_LOCAL:
499                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
500                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
501                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
502                         local = 1;
503                         break;
504                 default:
505                         gtt_entries = 0;
506                         break;
507                 }
508         } else {
509                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
510                 case I855_GMCH_GMS_STOLEN_1M:
511                         gtt_entries = MB(1) - KB(size);
512                         break;
513                 case I855_GMCH_GMS_STOLEN_4M:
514                         gtt_entries = MB(4) - KB(size);
515                         break;
516                 case I855_GMCH_GMS_STOLEN_8M:
517                         gtt_entries = MB(8) - KB(size);
518                         break;
519                 case I855_GMCH_GMS_STOLEN_16M:
520                         gtt_entries = MB(16) - KB(size);
521                         break;
522                 case I855_GMCH_GMS_STOLEN_32M:
523                         gtt_entries = MB(32) - KB(size);
524                         break;
525                 case I915_GMCH_GMS_STOLEN_48M:
526                         /* Check it's really I915G */
527                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
528                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
529                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
530                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
531                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
532                             IS_I965 || IS_G33)
533                                 gtt_entries = MB(48) - KB(size);
534                         else
535                                 gtt_entries = 0;
536                         break;
537                 case I915_GMCH_GMS_STOLEN_64M:
538                         /* Check it's really I915G */
539                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
540                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
541                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
542                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
543                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
544                             IS_I965 || IS_G33)
545                                 gtt_entries = MB(64) - KB(size);
546                         else
547                                 gtt_entries = 0;
548                         break;
549                 case G33_GMCH_GMS_STOLEN_128M:
550                         if (IS_G33)
551                                 gtt_entries = MB(128) - KB(size);
552                         else
553                                 gtt_entries = 0;
554                         break;
555                 case G33_GMCH_GMS_STOLEN_256M:
556                         if (IS_G33)
557                                 gtt_entries = MB(256) - KB(size);
558                         else
559                                 gtt_entries = 0;
560                         break;
561                 default:
562                         gtt_entries = 0;
563                         break;
564                 }
565         }
566         if (gtt_entries > 0)
567                 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
568                        gtt_entries / KB(1), local ? "local" : "stolen");
569         else
570                 printk(KERN_INFO PFX
571                        "No pre-allocated video memory detected.\n");
572         gtt_entries /= KB(4);
573
574         intel_private.gtt_entries = gtt_entries;
575 }
576
577 /* The intel i830 automatically initializes the agp aperture during POST.
578  * Use the memory already set aside for in the GTT.
579  */
580 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
581 {
582         int page_order;
583         struct aper_size_info_fixed *size;
584         int num_entries;
585         u32 temp;
586
587         size = agp_bridge->current_size;
588         page_order = size->page_order;
589         num_entries = size->num_entries;
590         agp_bridge->gatt_table_real = NULL;
591
592         pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
593         temp &= 0xfff80000;
594
595         intel_private.registers = ioremap(temp,128 * 4096);
596         if (!intel_private.registers)
597                 return -ENOMEM;
598
599         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
600         global_cache_flush();   /* FIXME: ?? */
601
602         /* we have to call this as early as possible after the MMIO base address is known */
603         intel_i830_init_gtt_entries();
604
605         agp_bridge->gatt_table = NULL;
606
607         agp_bridge->gatt_bus_addr = temp;
608
609         return 0;
610 }
611
612 /* Return the gatt table to a sane state. Use the top of stolen
613  * memory for the GTT.
614  */
615 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
616 {
617         return 0;
618 }
619
620 static int intel_i830_fetch_size(void)
621 {
622         u16 gmch_ctrl;
623         struct aper_size_info_fixed *values;
624
625         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
626
627         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
628             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
629                 /* 855GM/852GM/865G has 128MB aperture size */
630                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
631                 agp_bridge->aperture_size_idx = 0;
632                 return values[0].size;
633         }
634
635         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
636
637         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
638                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
639                 agp_bridge->aperture_size_idx = 0;
640                 return values[0].size;
641         } else {
642                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
643                 agp_bridge->aperture_size_idx = 1;
644                 return values[1].size;
645         }
646
647         return 0;
648 }
649
650 static int intel_i830_configure(void)
651 {
652         struct aper_size_info_fixed *current_size;
653         u32 temp;
654         u16 gmch_ctrl;
655         int i;
656
657         current_size = A_SIZE_FIX(agp_bridge->current_size);
658
659         pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
660         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
661
662         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
663         gmch_ctrl |= I830_GMCH_ENABLED;
664         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
665
666         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
667         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
668
669         if (agp_bridge->driver->needs_scratch_page) {
670                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
671                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
672                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI Posting. */
673                 }
674         }
675
676         global_cache_flush();
677         return 0;
678 }
679
680 static void intel_i830_cleanup(void)
681 {
682         iounmap(intel_private.registers);
683 }
684
685 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
686 {
687         int i,j,num_entries;
688         void *temp;
689         int ret = -EINVAL;
690         int mask_type;
691
692         if (mem->page_count == 0)
693                 goto out;
694
695         temp = agp_bridge->current_size;
696         num_entries = A_SIZE_FIX(temp)->num_entries;
697
698         if (pg_start < intel_private.gtt_entries) {
699                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
700                                 pg_start,intel_private.gtt_entries);
701
702                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
703                 goto out_err;
704         }
705
706         if ((pg_start + mem->page_count) > num_entries)
707                 goto out_err;
708
709         /* The i830 can't check the GTT for entries since its read only,
710          * depend on the caller to make the correct offset decisions.
711          */
712
713         if (type != mem->type)
714                 goto out_err;
715
716         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
717
718         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
719             mask_type != INTEL_AGP_CACHED_MEMORY)
720                 goto out_err;
721
722         if (!mem->is_flushed)
723                 global_cache_flush();
724
725         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
726                 writel(agp_bridge->driver->mask_memory(agp_bridge,
727                                                        mem->memory[i], mask_type),
728                        intel_private.registers+I810_PTE_BASE+(j*4));
729         }
730         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
731         agp_bridge->driver->tlb_flush(mem);
732
733 out:
734         ret = 0;
735 out_err:
736         mem->is_flushed = 1;
737         return ret;
738 }
739
740 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
741                                 int type)
742 {
743         int i;
744
745         if (mem->page_count == 0)
746                 return 0;
747
748         if (pg_start < intel_private.gtt_entries) {
749                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
750                 return -EINVAL;
751         }
752
753         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
754                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
755         }
756         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
757
758         agp_bridge->driver->tlb_flush(mem);
759         return 0;
760 }
761
762 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
763 {
764         if (type == AGP_PHYS_MEMORY)
765                 return alloc_agpphysmem_i8xx(pg_count, type);
766         /* always return NULL for other allocation types for now */
767         return NULL;
768 }
769
770 static int intel_i915_configure(void)
771 {
772         struct aper_size_info_fixed *current_size;
773         u32 temp;
774         u16 gmch_ctrl;
775         int i;
776
777         current_size = A_SIZE_FIX(agp_bridge->current_size);
778
779         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
780
781         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
782
783         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
784         gmch_ctrl |= I830_GMCH_ENABLED;
785         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
786
787         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
788         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
789
790         if (agp_bridge->driver->needs_scratch_page) {
791                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
792                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
793                         readl(intel_private.gtt+i);     /* PCI Posting. */
794                 }
795         }
796
797         global_cache_flush();
798         return 0;
799 }
800
801 static void intel_i915_cleanup(void)
802 {
803         iounmap(intel_private.gtt);
804         iounmap(intel_private.registers);
805 }
806
807 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
808                                 int type)
809 {
810         int i,j,num_entries;
811         void *temp;
812         int ret = -EINVAL;
813         int mask_type;
814
815         if (mem->page_count == 0)
816                 goto out;
817
818         temp = agp_bridge->current_size;
819         num_entries = A_SIZE_FIX(temp)->num_entries;
820
821         if (pg_start < intel_private.gtt_entries) {
822                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
823                                 pg_start,intel_private.gtt_entries);
824
825                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
826                 goto out_err;
827         }
828
829         if ((pg_start + mem->page_count) > num_entries)
830                 goto out_err;
831
832         /* The i915 can't check the GTT for entries since its read only,
833          * depend on the caller to make the correct offset decisions.
834          */
835
836         if (type != mem->type)
837                 goto out_err;
838
839         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
840
841         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
842             mask_type != INTEL_AGP_CACHED_MEMORY)
843                 goto out_err;
844
845         if (!mem->is_flushed)
846                 global_cache_flush();
847
848         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
849                 writel(agp_bridge->driver->mask_memory(agp_bridge,
850                         mem->memory[i], mask_type), intel_private.gtt+j);
851         }
852
853         readl(intel_private.gtt+j-1);
854         agp_bridge->driver->tlb_flush(mem);
855
856  out:
857         ret = 0;
858  out_err:
859         mem->is_flushed = 1;
860         return ret;
861 }
862
863 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
864                                 int type)
865 {
866         int i;
867
868         if (mem->page_count == 0)
869                 return 0;
870
871         if (pg_start < intel_private.gtt_entries) {
872                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
873                 return -EINVAL;
874         }
875
876         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
877                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
878         }
879         readl(intel_private.gtt+i-1);
880
881         agp_bridge->driver->tlb_flush(mem);
882         return 0;
883 }
884
885 /* Return the aperture size by just checking the resource length.  The effect
886  * described in the spec of the MSAC registers is just changing of the
887  * resource size.
888  */
889 static int intel_i9xx_fetch_size(void)
890 {
891         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
892         int aper_size; /* size in megabytes */
893         int i;
894
895         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
896
897         for (i = 0; i < num_sizes; i++) {
898                 if (aper_size == intel_i830_sizes[i].size) {
899                         agp_bridge->current_size = intel_i830_sizes + i;
900                         agp_bridge->previous_size = agp_bridge->current_size;
901                         return aper_size;
902                 }
903         }
904
905         return 0;
906 }
907
908 /* The intel i915 automatically initializes the agp aperture during POST.
909  * Use the memory already set aside for in the GTT.
910  */
911 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
912 {
913         int page_order;
914         struct aper_size_info_fixed *size;
915         int num_entries;
916         u32 temp, temp2;
917         int gtt_map_size = 256 * 1024;
918
919         size = agp_bridge->current_size;
920         page_order = size->page_order;
921         num_entries = size->num_entries;
922         agp_bridge->gatt_table_real = NULL;
923
924         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
925         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
926
927         if (IS_G33)
928             gtt_map_size = 1024 * 1024; /* 1M on G33 */
929         intel_private.gtt = ioremap(temp2, gtt_map_size);
930         if (!intel_private.gtt)
931                 return -ENOMEM;
932
933         temp &= 0xfff80000;
934
935         intel_private.registers = ioremap(temp,128 * 4096);
936         if (!intel_private.registers) {
937                 iounmap(intel_private.gtt);
938                 return -ENOMEM;
939         }
940
941         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
942         global_cache_flush();   /* FIXME: ? */
943
944         /* we have to call this as early as possible after the MMIO base address is known */
945         intel_i830_init_gtt_entries();
946
947         agp_bridge->gatt_table = NULL;
948
949         agp_bridge->gatt_bus_addr = temp;
950
951         return 0;
952 }
953
954 /*
955  * The i965 supports 36-bit physical addresses, but to keep
956  * the format of the GTT the same, the bits that don't fit
957  * in a 32-bit word are shifted down to bits 4..7.
958  *
959  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
960  * is always zero on 32-bit architectures, so no need to make
961  * this conditional.
962  */
963 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
964         unsigned long addr, int type)
965 {
966         /* Shift high bits down */
967         addr |= (addr >> 28) & 0xf0;
968
969         /* Type checking must be done elsewhere */
970         return addr | bridge->driver->masks[type].mask;
971 }
972
973 /* The intel i965 automatically initializes the agp aperture during POST.
974  * Use the memory already set aside for in the GTT.
975  */
976 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
977 {
978        int page_order;
979        struct aper_size_info_fixed *size;
980        int num_entries;
981        u32 temp;
982
983        size = agp_bridge->current_size;
984        page_order = size->page_order;
985        num_entries = size->num_entries;
986        agp_bridge->gatt_table_real = NULL;
987
988        pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
989
990        temp &= 0xfff00000;
991        intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
992
993         if (!intel_private.gtt)
994                 return -ENOMEM;
995
996
997        intel_private.registers = ioremap(temp,128 * 4096);
998        if (!intel_private.registers) {
999                 iounmap(intel_private.gtt);
1000                 return -ENOMEM;
1001         }
1002
1003        temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1004        global_cache_flush();   /* FIXME: ? */
1005
1006        /* we have to call this as early as possible after the MMIO base address is known */
1007        intel_i830_init_gtt_entries();
1008
1009        agp_bridge->gatt_table = NULL;
1010
1011        agp_bridge->gatt_bus_addr = temp;
1012
1013        return 0;
1014 }
1015
1016
1017 static int intel_fetch_size(void)
1018 {
1019         int i;
1020         u16 temp;
1021         struct aper_size_info_16 *values;
1022
1023         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1024         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1025
1026         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1027                 if (temp == values[i].size_value) {
1028                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1029                         agp_bridge->aperture_size_idx = i;
1030                         return values[i].size;
1031                 }
1032         }
1033
1034         return 0;
1035 }
1036
1037 static int __intel_8xx_fetch_size(u8 temp)
1038 {
1039         int i;
1040         struct aper_size_info_8 *values;
1041
1042         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1043
1044         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1045                 if (temp == values[i].size_value) {
1046                         agp_bridge->previous_size =
1047                                 agp_bridge->current_size = (void *) (values + i);
1048                         agp_bridge->aperture_size_idx = i;
1049                         return values[i].size;
1050                 }
1051         }
1052         return 0;
1053 }
1054
1055 static int intel_8xx_fetch_size(void)
1056 {
1057         u8 temp;
1058
1059         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1060         return __intel_8xx_fetch_size(temp);
1061 }
1062
1063 static int intel_815_fetch_size(void)
1064 {
1065         u8 temp;
1066
1067         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1068          * one non-reserved bit, so mask the others out ... */
1069         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1070         temp &= (1 << 3);
1071
1072         return __intel_8xx_fetch_size(temp);
1073 }
1074
1075 static void intel_tlbflush(struct agp_memory *mem)
1076 {
1077         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1078         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1079 }
1080
1081
1082 static void intel_8xx_tlbflush(struct agp_memory *mem)
1083 {
1084         u32 temp;
1085         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1086         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1087         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1088         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1089 }
1090
1091
1092 static void intel_cleanup(void)
1093 {
1094         u16 temp;
1095         struct aper_size_info_16 *previous_size;
1096
1097         previous_size = A_SIZE_16(agp_bridge->previous_size);
1098         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1099         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1100         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1101 }
1102
1103
1104 static void intel_8xx_cleanup(void)
1105 {
1106         u16 temp;
1107         struct aper_size_info_8 *previous_size;
1108
1109         previous_size = A_SIZE_8(agp_bridge->previous_size);
1110         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1111         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1112         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1113 }
1114
1115
1116 static int intel_configure(void)
1117 {
1118         u32 temp;
1119         u16 temp2;
1120         struct aper_size_info_16 *current_size;
1121
1122         current_size = A_SIZE_16(agp_bridge->current_size);
1123
1124         /* aperture size */
1125         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1126
1127         /* address to map to */
1128         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1129         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1130
1131         /* attbase - aperture base */
1132         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1133
1134         /* agpctrl */
1135         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1136
1137         /* paccfg/nbxcfg */
1138         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1139         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1140                         (temp2 & ~(1 << 10)) | (1 << 9));
1141         /* clear any possible error conditions */
1142         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1143         return 0;
1144 }
1145
1146 static int intel_815_configure(void)
1147 {
1148         u32 temp, addr;
1149         u8 temp2;
1150         struct aper_size_info_8 *current_size;
1151
1152         /* attbase - aperture base */
1153         /* the Intel 815 chipset spec. says that bits 29-31 in the
1154         * ATTBASE register are reserved -> try not to write them */
1155         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1156                 printk (KERN_EMERG PFX "gatt bus addr too high");
1157                 return -EINVAL;
1158         }
1159
1160         current_size = A_SIZE_8(agp_bridge->current_size);
1161
1162         /* aperture size */
1163         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1164                         current_size->size_value);
1165
1166         /* address to map to */
1167         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1168         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1169
1170         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1171         addr &= INTEL_815_ATTBASE_MASK;
1172         addr |= agp_bridge->gatt_bus_addr;
1173         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1174
1175         /* agpctrl */
1176         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1177
1178         /* apcont */
1179         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1180         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1181
1182         /* clear any possible error conditions */
1183         /* Oddness : this chipset seems to have no ERRSTS register ! */
1184         return 0;
1185 }
1186
1187 static void intel_820_tlbflush(struct agp_memory *mem)
1188 {
1189         return;
1190 }
1191
1192 static void intel_820_cleanup(void)
1193 {
1194         u8 temp;
1195         struct aper_size_info_8 *previous_size;
1196
1197         previous_size = A_SIZE_8(agp_bridge->previous_size);
1198         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1199         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1200                         temp & ~(1 << 1));
1201         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1202                         previous_size->size_value);
1203 }
1204
1205
1206 static int intel_820_configure(void)
1207 {
1208         u32 temp;
1209         u8 temp2;
1210         struct aper_size_info_8 *current_size;
1211
1212         current_size = A_SIZE_8(agp_bridge->current_size);
1213
1214         /* aperture size */
1215         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1216
1217         /* address to map to */
1218         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1219         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1220
1221         /* attbase - aperture base */
1222         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1223
1224         /* agpctrl */
1225         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1226
1227         /* global enable aperture access */
1228         /* This flag is not accessed through MCHCFG register as in */
1229         /* i850 chipset. */
1230         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1231         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1232         /* clear any possible AGP-related error conditions */
1233         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1234         return 0;
1235 }
1236
1237 static int intel_840_configure(void)
1238 {
1239         u32 temp;
1240         u16 temp2;
1241         struct aper_size_info_8 *current_size;
1242
1243         current_size = A_SIZE_8(agp_bridge->current_size);
1244
1245         /* aperture size */
1246         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1247
1248         /* address to map to */
1249         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1250         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1251
1252         /* attbase - aperture base */
1253         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1254
1255         /* agpctrl */
1256         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1257
1258         /* mcgcfg */
1259         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1260         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1261         /* clear any possible error conditions */
1262         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1263         return 0;
1264 }
1265
1266 static int intel_845_configure(void)
1267 {
1268         u32 temp;
1269         u8 temp2;
1270         struct aper_size_info_8 *current_size;
1271
1272         current_size = A_SIZE_8(agp_bridge->current_size);
1273
1274         /* aperture size */
1275         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1276
1277         if (agp_bridge->apbase_config != 0) {
1278                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1279                                        agp_bridge->apbase_config);
1280         } else {
1281                 /* address to map to */
1282                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1283                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1284                 agp_bridge->apbase_config = temp;
1285         }
1286
1287         /* attbase - aperture base */
1288         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1289
1290         /* agpctrl */
1291         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1292
1293         /* agpm */
1294         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1295         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1296         /* clear any possible error conditions */
1297         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1298         return 0;
1299 }
1300
1301 static int intel_850_configure(void)
1302 {
1303         u32 temp;
1304         u16 temp2;
1305         struct aper_size_info_8 *current_size;
1306
1307         current_size = A_SIZE_8(agp_bridge->current_size);
1308
1309         /* aperture size */
1310         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1311
1312         /* address to map to */
1313         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1314         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1315
1316         /* attbase - aperture base */
1317         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1318
1319         /* agpctrl */
1320         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1321
1322         /* mcgcfg */
1323         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1324         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1325         /* clear any possible AGP-related error conditions */
1326         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1327         return 0;
1328 }
1329
1330 static int intel_860_configure(void)
1331 {
1332         u32 temp;
1333         u16 temp2;
1334         struct aper_size_info_8 *current_size;
1335
1336         current_size = A_SIZE_8(agp_bridge->current_size);
1337
1338         /* aperture size */
1339         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1340
1341         /* address to map to */
1342         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1343         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1344
1345         /* attbase - aperture base */
1346         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1347
1348         /* agpctrl */
1349         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1350
1351         /* mcgcfg */
1352         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1353         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1354         /* clear any possible AGP-related error conditions */
1355         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1356         return 0;
1357 }
1358
1359 static int intel_830mp_configure(void)
1360 {
1361         u32 temp;
1362         u16 temp2;
1363         struct aper_size_info_8 *current_size;
1364
1365         current_size = A_SIZE_8(agp_bridge->current_size);
1366
1367         /* aperture size */
1368         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1369
1370         /* address to map to */
1371         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1372         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1373
1374         /* attbase - aperture base */
1375         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1376
1377         /* agpctrl */
1378         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1379
1380         /* gmch */
1381         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1382         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1383         /* clear any possible AGP-related error conditions */
1384         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1385         return 0;
1386 }
1387
1388 static int intel_7505_configure(void)
1389 {
1390         u32 temp;
1391         u16 temp2;
1392         struct aper_size_info_8 *current_size;
1393
1394         current_size = A_SIZE_8(agp_bridge->current_size);
1395
1396         /* aperture size */
1397         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1398
1399         /* address to map to */
1400         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1401         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1402
1403         /* attbase - aperture base */
1404         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1405
1406         /* agpctrl */
1407         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1408
1409         /* mchcfg */
1410         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1411         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1412
1413         return 0;
1414 }
1415
1416 /* Setup function */
1417 static const struct gatt_mask intel_generic_masks[] =
1418 {
1419         {.mask = 0x00000017, .type = 0}
1420 };
1421
1422 static const struct aper_size_info_8 intel_815_sizes[2] =
1423 {
1424         {64, 16384, 4, 0},
1425         {32, 8192, 3, 8},
1426 };
1427
1428 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1429 {
1430         {256, 65536, 6, 0},
1431         {128, 32768, 5, 32},
1432         {64, 16384, 4, 48},
1433         {32, 8192, 3, 56},
1434         {16, 4096, 2, 60},
1435         {8, 2048, 1, 62},
1436         {4, 1024, 0, 63}
1437 };
1438
1439 static const struct aper_size_info_16 intel_generic_sizes[7] =
1440 {
1441         {256, 65536, 6, 0},
1442         {128, 32768, 5, 32},
1443         {64, 16384, 4, 48},
1444         {32, 8192, 3, 56},
1445         {16, 4096, 2, 60},
1446         {8, 2048, 1, 62},
1447         {4, 1024, 0, 63}
1448 };
1449
1450 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1451 {
1452         {256, 65536, 6, 0},
1453         {128, 32768, 5, 32},
1454         {64, 16384, 4, 48},
1455         {32, 8192, 3, 56}
1456 };
1457
1458 static const struct agp_bridge_driver intel_generic_driver = {
1459         .owner                  = THIS_MODULE,
1460         .aperture_sizes         = intel_generic_sizes,
1461         .size_type              = U16_APER_SIZE,
1462         .num_aperture_sizes     = 7,
1463         .configure              = intel_configure,
1464         .fetch_size             = intel_fetch_size,
1465         .cleanup                = intel_cleanup,
1466         .tlb_flush              = intel_tlbflush,
1467         .mask_memory            = agp_generic_mask_memory,
1468         .masks                  = intel_generic_masks,
1469         .agp_enable             = agp_generic_enable,
1470         .cache_flush            = global_cache_flush,
1471         .create_gatt_table      = agp_generic_create_gatt_table,
1472         .free_gatt_table        = agp_generic_free_gatt_table,
1473         .insert_memory          = agp_generic_insert_memory,
1474         .remove_memory          = agp_generic_remove_memory,
1475         .alloc_by_type          = agp_generic_alloc_by_type,
1476         .free_by_type           = agp_generic_free_by_type,
1477         .agp_alloc_page         = agp_generic_alloc_page,
1478         .agp_destroy_page       = agp_generic_destroy_page,
1479         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1480 };
1481
1482 static const struct agp_bridge_driver intel_810_driver = {
1483         .owner                  = THIS_MODULE,
1484         .aperture_sizes         = intel_i810_sizes,
1485         .size_type              = FIXED_APER_SIZE,
1486         .num_aperture_sizes     = 2,
1487         .needs_scratch_page     = TRUE,
1488         .configure              = intel_i810_configure,
1489         .fetch_size             = intel_i810_fetch_size,
1490         .cleanup                = intel_i810_cleanup,
1491         .tlb_flush              = intel_i810_tlbflush,
1492         .mask_memory            = intel_i810_mask_memory,
1493         .masks                  = intel_i810_masks,
1494         .agp_enable             = intel_i810_agp_enable,
1495         .cache_flush            = global_cache_flush,
1496         .create_gatt_table      = agp_generic_create_gatt_table,
1497         .free_gatt_table        = agp_generic_free_gatt_table,
1498         .insert_memory          = intel_i810_insert_entries,
1499         .remove_memory          = intel_i810_remove_entries,
1500         .alloc_by_type          = intel_i810_alloc_by_type,
1501         .free_by_type           = intel_i810_free_by_type,
1502         .agp_alloc_page         = agp_generic_alloc_page,
1503         .agp_destroy_page       = agp_generic_destroy_page,
1504         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1505 };
1506
1507 static const struct agp_bridge_driver intel_815_driver = {
1508         .owner                  = THIS_MODULE,
1509         .aperture_sizes         = intel_815_sizes,
1510         .size_type              = U8_APER_SIZE,
1511         .num_aperture_sizes     = 2,
1512         .configure              = intel_815_configure,
1513         .fetch_size             = intel_815_fetch_size,
1514         .cleanup                = intel_8xx_cleanup,
1515         .tlb_flush              = intel_8xx_tlbflush,
1516         .mask_memory            = agp_generic_mask_memory,
1517         .masks                  = intel_generic_masks,
1518         .agp_enable             = agp_generic_enable,
1519         .cache_flush            = global_cache_flush,
1520         .create_gatt_table      = agp_generic_create_gatt_table,
1521         .free_gatt_table        = agp_generic_free_gatt_table,
1522         .insert_memory          = agp_generic_insert_memory,
1523         .remove_memory          = agp_generic_remove_memory,
1524         .alloc_by_type          = agp_generic_alloc_by_type,
1525         .free_by_type           = agp_generic_free_by_type,
1526         .agp_alloc_page         = agp_generic_alloc_page,
1527         .agp_destroy_page       = agp_generic_destroy_page,
1528         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1529 };
1530
1531 static const struct agp_bridge_driver intel_830_driver = {
1532         .owner                  = THIS_MODULE,
1533         .aperture_sizes         = intel_i830_sizes,
1534         .size_type              = FIXED_APER_SIZE,
1535         .num_aperture_sizes     = 4,
1536         .needs_scratch_page     = TRUE,
1537         .configure              = intel_i830_configure,
1538         .fetch_size             = intel_i830_fetch_size,
1539         .cleanup                = intel_i830_cleanup,
1540         .tlb_flush              = intel_i810_tlbflush,
1541         .mask_memory            = intel_i810_mask_memory,
1542         .masks                  = intel_i810_masks,
1543         .agp_enable             = intel_i810_agp_enable,
1544         .cache_flush            = global_cache_flush,
1545         .create_gatt_table      = intel_i830_create_gatt_table,
1546         .free_gatt_table        = intel_i830_free_gatt_table,
1547         .insert_memory          = intel_i830_insert_entries,
1548         .remove_memory          = intel_i830_remove_entries,
1549         .alloc_by_type          = intel_i830_alloc_by_type,
1550         .free_by_type           = intel_i810_free_by_type,
1551         .agp_alloc_page         = agp_generic_alloc_page,
1552         .agp_destroy_page       = agp_generic_destroy_page,
1553         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1554 };
1555
1556 static const struct agp_bridge_driver intel_820_driver = {
1557         .owner                  = THIS_MODULE,
1558         .aperture_sizes         = intel_8xx_sizes,
1559         .size_type              = U8_APER_SIZE,
1560         .num_aperture_sizes     = 7,
1561         .configure              = intel_820_configure,
1562         .fetch_size             = intel_8xx_fetch_size,
1563         .cleanup                = intel_820_cleanup,
1564         .tlb_flush              = intel_820_tlbflush,
1565         .mask_memory            = agp_generic_mask_memory,
1566         .masks                  = intel_generic_masks,
1567         .agp_enable             = agp_generic_enable,
1568         .cache_flush            = global_cache_flush,
1569         .create_gatt_table      = agp_generic_create_gatt_table,
1570         .free_gatt_table        = agp_generic_free_gatt_table,
1571         .insert_memory          = agp_generic_insert_memory,
1572         .remove_memory          = agp_generic_remove_memory,
1573         .alloc_by_type          = agp_generic_alloc_by_type,
1574         .free_by_type           = agp_generic_free_by_type,
1575         .agp_alloc_page         = agp_generic_alloc_page,
1576         .agp_destroy_page       = agp_generic_destroy_page,
1577         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1578 };
1579
1580 static const struct agp_bridge_driver intel_830mp_driver = {
1581         .owner                  = THIS_MODULE,
1582         .aperture_sizes         = intel_830mp_sizes,
1583         .size_type              = U8_APER_SIZE,
1584         .num_aperture_sizes     = 4,
1585         .configure              = intel_830mp_configure,
1586         .fetch_size             = intel_8xx_fetch_size,
1587         .cleanup                = intel_8xx_cleanup,
1588         .tlb_flush              = intel_8xx_tlbflush,
1589         .mask_memory            = agp_generic_mask_memory,
1590         .masks                  = intel_generic_masks,
1591         .agp_enable             = agp_generic_enable,
1592         .cache_flush            = global_cache_flush,
1593         .create_gatt_table      = agp_generic_create_gatt_table,
1594         .free_gatt_table        = agp_generic_free_gatt_table,
1595         .insert_memory          = agp_generic_insert_memory,
1596         .remove_memory          = agp_generic_remove_memory,
1597         .alloc_by_type          = agp_generic_alloc_by_type,
1598         .free_by_type           = agp_generic_free_by_type,
1599         .agp_alloc_page         = agp_generic_alloc_page,
1600         .agp_destroy_page       = agp_generic_destroy_page,
1601         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1602 };
1603
1604 static const struct agp_bridge_driver intel_840_driver = {
1605         .owner                  = THIS_MODULE,
1606         .aperture_sizes         = intel_8xx_sizes,
1607         .size_type              = U8_APER_SIZE,
1608         .num_aperture_sizes     = 7,
1609         .configure              = intel_840_configure,
1610         .fetch_size             = intel_8xx_fetch_size,
1611         .cleanup                = intel_8xx_cleanup,
1612         .tlb_flush              = intel_8xx_tlbflush,
1613         .mask_memory            = agp_generic_mask_memory,
1614         .masks                  = intel_generic_masks,
1615         .agp_enable             = agp_generic_enable,
1616         .cache_flush            = global_cache_flush,
1617         .create_gatt_table      = agp_generic_create_gatt_table,
1618         .free_gatt_table        = agp_generic_free_gatt_table,
1619         .insert_memory          = agp_generic_insert_memory,
1620         .remove_memory          = agp_generic_remove_memory,
1621         .alloc_by_type          = agp_generic_alloc_by_type,
1622         .free_by_type           = agp_generic_free_by_type,
1623         .agp_alloc_page         = agp_generic_alloc_page,
1624         .agp_destroy_page       = agp_generic_destroy_page,
1625         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1626 };
1627
1628 static const struct agp_bridge_driver intel_845_driver = {
1629         .owner                  = THIS_MODULE,
1630         .aperture_sizes         = intel_8xx_sizes,
1631         .size_type              = U8_APER_SIZE,
1632         .num_aperture_sizes     = 7,
1633         .configure              = intel_845_configure,
1634         .fetch_size             = intel_8xx_fetch_size,
1635         .cleanup                = intel_8xx_cleanup,
1636         .tlb_flush              = intel_8xx_tlbflush,
1637         .mask_memory            = agp_generic_mask_memory,
1638         .masks                  = intel_generic_masks,
1639         .agp_enable             = agp_generic_enable,
1640         .cache_flush            = global_cache_flush,
1641         .create_gatt_table      = agp_generic_create_gatt_table,
1642         .free_gatt_table        = agp_generic_free_gatt_table,
1643         .insert_memory          = agp_generic_insert_memory,
1644         .remove_memory          = agp_generic_remove_memory,
1645         .alloc_by_type          = agp_generic_alloc_by_type,
1646         .free_by_type           = agp_generic_free_by_type,
1647         .agp_alloc_page         = agp_generic_alloc_page,
1648         .agp_destroy_page       = agp_generic_destroy_page,
1649         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1650 };
1651
1652 static const struct agp_bridge_driver intel_850_driver = {
1653         .owner                  = THIS_MODULE,
1654         .aperture_sizes         = intel_8xx_sizes,
1655         .size_type              = U8_APER_SIZE,
1656         .num_aperture_sizes     = 7,
1657         .configure              = intel_850_configure,
1658         .fetch_size             = intel_8xx_fetch_size,
1659         .cleanup                = intel_8xx_cleanup,
1660         .tlb_flush              = intel_8xx_tlbflush,
1661         .mask_memory            = agp_generic_mask_memory,
1662         .masks                  = intel_generic_masks,
1663         .agp_enable             = agp_generic_enable,
1664         .cache_flush            = global_cache_flush,
1665         .create_gatt_table      = agp_generic_create_gatt_table,
1666         .free_gatt_table        = agp_generic_free_gatt_table,
1667         .insert_memory          = agp_generic_insert_memory,
1668         .remove_memory          = agp_generic_remove_memory,
1669         .alloc_by_type          = agp_generic_alloc_by_type,
1670         .free_by_type           = agp_generic_free_by_type,
1671         .agp_alloc_page         = agp_generic_alloc_page,
1672         .agp_destroy_page       = agp_generic_destroy_page,
1673         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1674 };
1675
1676 static const struct agp_bridge_driver intel_860_driver = {
1677         .owner                  = THIS_MODULE,
1678         .aperture_sizes         = intel_8xx_sizes,
1679         .size_type              = U8_APER_SIZE,
1680         .num_aperture_sizes     = 7,
1681         .configure              = intel_860_configure,
1682         .fetch_size             = intel_8xx_fetch_size,
1683         .cleanup                = intel_8xx_cleanup,
1684         .tlb_flush              = intel_8xx_tlbflush,
1685         .mask_memory            = agp_generic_mask_memory,
1686         .masks                  = intel_generic_masks,
1687         .agp_enable             = agp_generic_enable,
1688         .cache_flush            = global_cache_flush,
1689         .create_gatt_table      = agp_generic_create_gatt_table,
1690         .free_gatt_table        = agp_generic_free_gatt_table,
1691         .insert_memory          = agp_generic_insert_memory,
1692         .remove_memory          = agp_generic_remove_memory,
1693         .alloc_by_type          = agp_generic_alloc_by_type,
1694         .free_by_type           = agp_generic_free_by_type,
1695         .agp_alloc_page         = agp_generic_alloc_page,
1696         .agp_destroy_page       = agp_generic_destroy_page,
1697         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1698 };
1699
1700 static const struct agp_bridge_driver intel_915_driver = {
1701         .owner                  = THIS_MODULE,
1702         .aperture_sizes         = intel_i830_sizes,
1703         .size_type              = FIXED_APER_SIZE,
1704         .num_aperture_sizes     = 4,
1705         .needs_scratch_page     = TRUE,
1706         .configure              = intel_i915_configure,
1707         .fetch_size             = intel_i9xx_fetch_size,
1708         .cleanup                = intel_i915_cleanup,
1709         .tlb_flush              = intel_i810_tlbflush,
1710         .mask_memory            = intel_i810_mask_memory,
1711         .masks                  = intel_i810_masks,
1712         .agp_enable             = intel_i810_agp_enable,
1713         .cache_flush            = global_cache_flush,
1714         .create_gatt_table      = intel_i915_create_gatt_table,
1715         .free_gatt_table        = intel_i830_free_gatt_table,
1716         .insert_memory          = intel_i915_insert_entries,
1717         .remove_memory          = intel_i915_remove_entries,
1718         .alloc_by_type          = intel_i830_alloc_by_type,
1719         .free_by_type           = intel_i810_free_by_type,
1720         .agp_alloc_page         = agp_generic_alloc_page,
1721         .agp_destroy_page       = agp_generic_destroy_page,
1722         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1723 };
1724
1725 static const struct agp_bridge_driver intel_i965_driver = {
1726        .owner                  = THIS_MODULE,
1727        .aperture_sizes         = intel_i830_sizes,
1728        .size_type              = FIXED_APER_SIZE,
1729        .num_aperture_sizes     = 4,
1730        .needs_scratch_page     = TRUE,
1731        .configure              = intel_i915_configure,
1732        .fetch_size             = intel_i9xx_fetch_size,
1733        .cleanup                = intel_i915_cleanup,
1734        .tlb_flush              = intel_i810_tlbflush,
1735        .mask_memory            = intel_i965_mask_memory,
1736        .masks                  = intel_i810_masks,
1737        .agp_enable             = intel_i810_agp_enable,
1738        .cache_flush            = global_cache_flush,
1739        .create_gatt_table      = intel_i965_create_gatt_table,
1740        .free_gatt_table        = intel_i830_free_gatt_table,
1741        .insert_memory          = intel_i915_insert_entries,
1742        .remove_memory          = intel_i915_remove_entries,
1743        .alloc_by_type          = intel_i830_alloc_by_type,
1744        .free_by_type           = intel_i810_free_by_type,
1745        .agp_alloc_page         = agp_generic_alloc_page,
1746        .agp_destroy_page       = agp_generic_destroy_page,
1747        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1748 };
1749
1750 static const struct agp_bridge_driver intel_7505_driver = {
1751         .owner                  = THIS_MODULE,
1752         .aperture_sizes         = intel_8xx_sizes,
1753         .size_type              = U8_APER_SIZE,
1754         .num_aperture_sizes     = 7,
1755         .configure              = intel_7505_configure,
1756         .fetch_size             = intel_8xx_fetch_size,
1757         .cleanup                = intel_8xx_cleanup,
1758         .tlb_flush              = intel_8xx_tlbflush,
1759         .mask_memory            = agp_generic_mask_memory,
1760         .masks                  = intel_generic_masks,
1761         .agp_enable             = agp_generic_enable,
1762         .cache_flush            = global_cache_flush,
1763         .create_gatt_table      = agp_generic_create_gatt_table,
1764         .free_gatt_table        = agp_generic_free_gatt_table,
1765         .insert_memory          = agp_generic_insert_memory,
1766         .remove_memory          = agp_generic_remove_memory,
1767         .alloc_by_type          = agp_generic_alloc_by_type,
1768         .free_by_type           = agp_generic_free_by_type,
1769         .agp_alloc_page         = agp_generic_alloc_page,
1770         .agp_destroy_page       = agp_generic_destroy_page,
1771         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1772 };
1773
1774 static const struct agp_bridge_driver intel_g33_driver = {
1775         .owner                  = THIS_MODULE,
1776         .aperture_sizes         = intel_i830_sizes,
1777         .size_type              = FIXED_APER_SIZE,
1778         .num_aperture_sizes     = 4,
1779         .needs_scratch_page     = TRUE,
1780         .configure              = intel_i915_configure,
1781         .fetch_size             = intel_i9xx_fetch_size,
1782         .cleanup                = intel_i915_cleanup,
1783         .tlb_flush              = intel_i810_tlbflush,
1784         .mask_memory            = intel_i965_mask_memory,
1785         .masks                  = intel_i810_masks,
1786         .agp_enable             = intel_i810_agp_enable,
1787         .cache_flush            = global_cache_flush,
1788         .create_gatt_table      = intel_i915_create_gatt_table,
1789         .free_gatt_table        = intel_i830_free_gatt_table,
1790         .insert_memory          = intel_i915_insert_entries,
1791         .remove_memory          = intel_i915_remove_entries,
1792         .alloc_by_type          = intel_i830_alloc_by_type,
1793         .free_by_type           = intel_i810_free_by_type,
1794         .agp_alloc_page         = agp_generic_alloc_page,
1795         .agp_destroy_page       = agp_generic_destroy_page,
1796         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1797 };
1798
1799 static int find_gmch(u16 device)
1800 {
1801         struct pci_dev *gmch_device;
1802
1803         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1804         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1805                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1806                                 device, gmch_device);
1807         }
1808
1809         if (!gmch_device)
1810                 return 0;
1811
1812         intel_private.pcidev = gmch_device;
1813         return 1;
1814 }
1815
1816 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1817  * driver and gmch_driver must be non-null, and find_gmch will determine
1818  * which one should be used if a gmch_chip_id is present.
1819  */
1820 static const struct intel_driver_description {
1821         unsigned int chip_id;
1822         unsigned int gmch_chip_id;
1823         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
1824         char *name;
1825         const struct agp_bridge_driver *driver;
1826         const struct agp_bridge_driver *gmch_driver;
1827 } intel_agp_chipsets[] = {
1828         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
1829         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
1830         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
1831         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
1832                 NULL, &intel_810_driver },
1833         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
1834                 NULL, &intel_810_driver },
1835         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
1836                 NULL, &intel_810_driver },
1837         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
1838                 &intel_815_driver, &intel_810_driver },
1839         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
1840         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
1841         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
1842                 &intel_830mp_driver, &intel_830_driver },
1843         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
1844         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
1845         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
1846                 &intel_845_driver, &intel_830_driver },
1847         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
1848         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
1849         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
1850                 &intel_845_driver, &intel_830_driver },
1851         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
1852         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
1853                 &intel_845_driver, &intel_830_driver },
1854         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
1855         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
1856                 NULL, &intel_915_driver },
1857         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
1858                 NULL, &intel_915_driver },
1859         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
1860                 NULL, &intel_915_driver },
1861         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
1862                 NULL, &intel_915_driver },
1863         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
1864                 NULL, &intel_915_driver },
1865         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
1866                 NULL, &intel_i965_driver },
1867         { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, 0, "965G",
1868                 NULL, &intel_i965_driver },
1869         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
1870                 NULL, &intel_i965_driver },
1871         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
1872                 NULL, &intel_i965_driver },
1873         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
1874                 NULL, &intel_i965_driver },
1875         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
1876                 NULL, &intel_i965_driver },
1877         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
1878         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
1879         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
1880                 NULL, &intel_g33_driver },
1881         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
1882                 NULL, &intel_g33_driver },
1883         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
1884                 NULL, &intel_g33_driver },
1885         { 0, 0, 0, NULL, NULL, NULL }
1886 };
1887
1888 static int __devinit agp_intel_probe(struct pci_dev *pdev,
1889                                      const struct pci_device_id *ent)
1890 {
1891         struct agp_bridge_data *bridge;
1892         u8 cap_ptr = 0;
1893         struct resource *r;
1894         int i;
1895
1896         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
1897
1898         bridge = agp_alloc_bridge();
1899         if (!bridge)
1900                 return -ENOMEM;
1901
1902         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
1903                 /* In case that multiple models of gfx chip may
1904                    stand on same host bridge type, this can be
1905                    sure we detect the right IGD. */
1906                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
1907                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
1908                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
1909                                 bridge->driver =
1910                                         intel_agp_chipsets[i].gmch_driver;
1911                                 break;
1912                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
1913                                 continue;
1914                         } else {
1915                                 bridge->driver = intel_agp_chipsets[i].driver;
1916                                 break;
1917                         }
1918                 }
1919         }
1920
1921         if (intel_agp_chipsets[i].name == NULL) {
1922                 if (cap_ptr)
1923                         printk(KERN_WARNING PFX "Unsupported Intel chipset"
1924                                "(device id: %04x)\n", pdev->device);
1925                 agp_put_bridge(bridge);
1926                 return -ENODEV;
1927         }
1928
1929         if (bridge->driver == NULL) {
1930                 /* bridge has no AGP and no IGD detected */
1931                 if (cap_ptr)
1932                         printk(KERN_WARNING PFX "Failed to find bridge device "
1933                                 "(chip_id: %04x)\n",
1934                                 intel_agp_chipsets[i].gmch_chip_id);
1935                 agp_put_bridge(bridge);
1936                 return -ENODEV;
1937         }
1938
1939         bridge->dev = pdev;
1940         bridge->capndx = cap_ptr;
1941         bridge->dev_private_data = &intel_private;
1942
1943         printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
1944                 intel_agp_chipsets[i].name);
1945
1946         /*
1947         * The following fixes the case where the BIOS has "forgotten" to
1948         * provide an address range for the GART.
1949         * 20030610 - hamish@zot.org
1950         */
1951         r = &pdev->resource[0];
1952         if (!r->start && r->end) {
1953                 if (pci_assign_resource(pdev, 0)) {
1954                         printk(KERN_ERR PFX "could not assign resource 0\n");
1955                         agp_put_bridge(bridge);
1956                         return -ENODEV;
1957                 }
1958         }
1959
1960         /*
1961         * If the device has not been properly setup, the following will catch
1962         * the problem and should stop the system from crashing.
1963         * 20030610 - hamish@zot.org
1964         */
1965         if (pci_enable_device(pdev)) {
1966                 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
1967                 agp_put_bridge(bridge);
1968                 return -ENODEV;
1969         }
1970
1971         /* Fill in the mode register */
1972         if (cap_ptr) {
1973                 pci_read_config_dword(pdev,
1974                                 bridge->capndx+PCI_AGP_STATUS,
1975                                 &bridge->mode);
1976         }
1977
1978         pci_set_drvdata(pdev, bridge);
1979         return agp_add_bridge(bridge);
1980 }
1981
1982 static void __devexit agp_intel_remove(struct pci_dev *pdev)
1983 {
1984         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1985
1986         agp_remove_bridge(bridge);
1987
1988         if (intel_private.pcidev)
1989                 pci_dev_put(intel_private.pcidev);
1990
1991         agp_put_bridge(bridge);
1992 }
1993
1994 #ifdef CONFIG_PM
1995 static int agp_intel_resume(struct pci_dev *pdev)
1996 {
1997         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1998
1999         pci_restore_state(pdev);
2000
2001         /* We should restore our graphics device's config space,
2002          * as host bridge (00:00) resumes before graphics device (02:00),
2003          * then our access to its pci space can work right.
2004          */
2005         if (intel_private.pcidev)
2006                 pci_restore_state(intel_private.pcidev);
2007
2008         if (bridge->driver == &intel_generic_driver)
2009                 intel_configure();
2010         else if (bridge->driver == &intel_850_driver)
2011                 intel_850_configure();
2012         else if (bridge->driver == &intel_845_driver)
2013                 intel_845_configure();
2014         else if (bridge->driver == &intel_830mp_driver)
2015                 intel_830mp_configure();
2016         else if (bridge->driver == &intel_915_driver)
2017                 intel_i915_configure();
2018         else if (bridge->driver == &intel_830_driver)
2019                 intel_i830_configure();
2020         else if (bridge->driver == &intel_810_driver)
2021                 intel_i810_configure();
2022         else if (bridge->driver == &intel_i965_driver)
2023                 intel_i915_configure();
2024
2025         return 0;
2026 }
2027 #endif
2028
2029 static struct pci_device_id agp_intel_pci_table[] = {
2030 #define ID(x)                                           \
2031         {                                               \
2032         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2033         .class_mask     = ~0,                           \
2034         .vendor         = PCI_VENDOR_ID_INTEL,          \
2035         .device         = x,                            \
2036         .subvendor      = PCI_ANY_ID,                   \
2037         .subdevice      = PCI_ANY_ID,                   \
2038         }
2039         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2040         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2041         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2042         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2043         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2044         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2045         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2046         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2047         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2048         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2049         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2050         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2051         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2052         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2053         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2054         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2055         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2056         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2057         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2058         ID(PCI_DEVICE_ID_INTEL_7505_0),
2059         ID(PCI_DEVICE_ID_INTEL_7205_0),
2060         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2061         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2062         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2063         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2064         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2065         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2066         ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
2067         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2068         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2069         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2070         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2071         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2072         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2073         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2074         { }
2075 };
2076
2077 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2078
2079 static struct pci_driver agp_intel_pci_driver = {
2080         .name           = "agpgart-intel",
2081         .id_table       = agp_intel_pci_table,
2082         .probe          = agp_intel_probe,
2083         .remove         = __devexit_p(agp_intel_remove),
2084 #ifdef CONFIG_PM
2085         .resume         = agp_intel_resume,
2086 #endif
2087 };
2088
2089 static int __init agp_intel_init(void)
2090 {
2091         if (agp_off)
2092                 return -EINVAL;
2093         return pci_register_driver(&agp_intel_pci_driver);
2094 }
2095
2096 static void __exit agp_intel_cleanup(void)
2097 {
2098         pci_unregister_driver(&agp_intel_pci_driver);
2099 }
2100
2101 module_init(agp_intel_init);
2102 module_exit(agp_intel_cleanup);
2103
2104 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2105 MODULE_LICENSE("GPL and additional rights");