oprofile: fix printk in cpu_buffer.c
[linux-2.6.git] / arch / x86 / oprofile / op_model_amd.c
1 /*
2  * @file op_model_amd.c
3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
4  *
5  * @remark Copyright 2002-2008 OProfile authors
6  * @remark Read the file COPYING
7  *
8  * @author John Levon
9  * @author Philippe Elie
10  * @author Graydon Hoare
11  * @author Robert Richter <robert.richter@amd.com>
12  * @author Barry Kasindorf
13 */
14
15 #include <linux/oprofile.h>
16 #include <linux/device.h>
17 #include <linux/pci.h>
18
19 #include <asm/ptrace.h>
20 #include <asm/msr.h>
21 #include <asm/nmi.h>
22
23 #include "op_x86_model.h"
24 #include "op_counter.h"
25
26 #define NUM_COUNTERS 4
27 #define NUM_CONTROLS 4
28
29 #define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
30 #define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
31 #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1); } while (0)
32 #define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))
33
34 #define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
35 #define CTRL_READ(l, h, msrs, c) do {rdmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
36 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
37 #define CTRL_SET_ACTIVE(n) (n |= (1<<22))
38 #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
39 #define CTRL_CLEAR_LO(x) (x &= (1<<21))
40 #define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0)
41 #define CTRL_SET_ENABLE(val) (val |= 1<<20)
42 #define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))
43 #define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))
44 #define CTRL_SET_UM(val, m) (val |= (m << 8))
45 #define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff))
46 #define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf))
47 #define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
48 #define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
49
50 static unsigned long reset_value[NUM_COUNTERS];
51
52 #ifdef CONFIG_OPROFILE_IBS
53
54 /* IbsFetchCtl bits/masks */
55 #define IBS_FETCH_HIGH_VALID_BIT        (1UL << 17)     /* bit 49 */
56 #define IBS_FETCH_HIGH_ENABLE           (1UL << 16)     /* bit 48 */
57 #define IBS_FETCH_LOW_MAX_CNT_MASK      0x0000FFFFUL    /* MaxCnt mask */
58
59 /*IbsOpCtl bits */
60 #define IBS_OP_LOW_VALID_BIT            (1ULL<<18)      /* bit 18 */
61 #define IBS_OP_LOW_ENABLE               (1ULL<<17)      /* bit 17 */
62
63 /* Codes used in cpu_buffer.c */
64 /* This produces duplicate code, need to be fixed */
65 #define IBS_FETCH_BEGIN 3
66 #define IBS_OP_BEGIN    4
67
68 /* The function interface needs to be fixed, something like add
69    data. Should then be added to linux/oprofile.h. */
70 extern void oprofile_add_ibs_sample(struct pt_regs *const regs,
71                                     unsigned int * const ibs_sample, u8 code);
72
73 struct ibs_fetch_sample {
74         /* MSRC001_1031 IBS Fetch Linear Address Register */
75         unsigned int ibs_fetch_lin_addr_low;
76         unsigned int ibs_fetch_lin_addr_high;
77         /* MSRC001_1030 IBS Fetch Control Register */
78         unsigned int ibs_fetch_ctl_low;
79         unsigned int ibs_fetch_ctl_high;
80         /* MSRC001_1032 IBS Fetch Physical Address Register */
81         unsigned int ibs_fetch_phys_addr_low;
82         unsigned int ibs_fetch_phys_addr_high;
83 };
84
85 struct ibs_op_sample {
86         /* MSRC001_1034 IBS Op Logical Address Register (IbsRIP) */
87         unsigned int ibs_op_rip_low;
88         unsigned int ibs_op_rip_high;
89         /* MSRC001_1035 IBS Op Data Register */
90         unsigned int ibs_op_data1_low;
91         unsigned int ibs_op_data1_high;
92         /* MSRC001_1036 IBS Op Data 2 Register */
93         unsigned int ibs_op_data2_low;
94         unsigned int ibs_op_data2_high;
95         /* MSRC001_1037 IBS Op Data 3 Register */
96         unsigned int ibs_op_data3_low;
97         unsigned int ibs_op_data3_high;
98         /* MSRC001_1038 IBS DC Linear Address Register (IbsDcLinAd) */
99         unsigned int ibs_dc_linear_low;
100         unsigned int ibs_dc_linear_high;
101         /* MSRC001_1039 IBS DC Physical Address Register (IbsDcPhysAd) */
102         unsigned int ibs_dc_phys_low;
103         unsigned int ibs_dc_phys_high;
104 };
105
106 /*
107  * unitialize the APIC for the IBS interrupts if needed on AMD Family10h+
108 */
109 static void clear_ibs_nmi(void);
110
111 static int ibs_allowed; /* AMD Family10h and later */
112
113 struct op_ibs_config {
114         unsigned long op_enabled;
115         unsigned long fetch_enabled;
116         unsigned long max_cnt_fetch;
117         unsigned long max_cnt_op;
118         unsigned long rand_en;
119         unsigned long dispatched_ops;
120 };
121
122 static struct op_ibs_config ibs_config;
123
124 #endif
125
126 /* functions for op_amd_spec */
127
128 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
129 {
130         int i;
131
132         for (i = 0; i < NUM_COUNTERS; i++) {
133                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
134                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
135                 else
136                         msrs->counters[i].addr = 0;
137         }
138
139         for (i = 0; i < NUM_CONTROLS; i++) {
140                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
141                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
142                 else
143                         msrs->controls[i].addr = 0;
144         }
145 }
146
147
148 static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
149 {
150         unsigned int low, high;
151         int i;
152
153         /* clear all counters */
154         for (i = 0 ; i < NUM_CONTROLS; ++i) {
155                 if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
156                         continue;
157                 CTRL_READ(low, high, msrs, i);
158                 CTRL_CLEAR_LO(low);
159                 CTRL_CLEAR_HI(high);
160                 CTRL_WRITE(low, high, msrs, i);
161         }
162
163         /* avoid a false detection of ctr overflows in NMI handler */
164         for (i = 0; i < NUM_COUNTERS; ++i) {
165                 if (unlikely(!CTR_IS_RESERVED(msrs, i)))
166                         continue;
167                 CTR_WRITE(1, msrs, i);
168         }
169
170         /* enable active counters */
171         for (i = 0; i < NUM_COUNTERS; ++i) {
172                 if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
173                         reset_value[i] = counter_config[i].count;
174
175                         CTR_WRITE(counter_config[i].count, msrs, i);
176
177                         CTRL_READ(low, high, msrs, i);
178                         CTRL_CLEAR_LO(low);
179                         CTRL_CLEAR_HI(high);
180                         CTRL_SET_ENABLE(low);
181                         CTRL_SET_USR(low, counter_config[i].user);
182                         CTRL_SET_KERN(low, counter_config[i].kernel);
183                         CTRL_SET_UM(low, counter_config[i].unit_mask);
184                         CTRL_SET_EVENT_LOW(low, counter_config[i].event);
185                         CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
186                         CTRL_SET_HOST_ONLY(high, 0);
187                         CTRL_SET_GUEST_ONLY(high, 0);
188
189                         CTRL_WRITE(low, high, msrs, i);
190                 } else {
191                         reset_value[i] = 0;
192                 }
193         }
194 }
195
196 #ifdef CONFIG_OPROFILE_IBS
197
198 static inline int
199 op_amd_handle_ibs(struct pt_regs * const regs,
200                   struct op_msrs const * const msrs)
201 {
202         unsigned int low, high;
203         struct ibs_fetch_sample ibs_fetch;
204         struct ibs_op_sample ibs_op;
205
206         if (!ibs_allowed)
207                 return 1;
208
209         if (ibs_config.fetch_enabled) {
210                 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
211                 if (high & IBS_FETCH_HIGH_VALID_BIT) {
212                         ibs_fetch.ibs_fetch_ctl_high = high;
213                         ibs_fetch.ibs_fetch_ctl_low = low;
214                         rdmsr(MSR_AMD64_IBSFETCHLINAD, low, high);
215                         ibs_fetch.ibs_fetch_lin_addr_high = high;
216                         ibs_fetch.ibs_fetch_lin_addr_low = low;
217                         rdmsr(MSR_AMD64_IBSFETCHPHYSAD, low, high);
218                         ibs_fetch.ibs_fetch_phys_addr_high = high;
219                         ibs_fetch.ibs_fetch_phys_addr_low = low;
220
221                         oprofile_add_ibs_sample(regs,
222                                                 (unsigned int *)&ibs_fetch,
223                                                 IBS_FETCH_BEGIN);
224
225                         /*reenable the IRQ */
226                         rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
227                         high &= ~IBS_FETCH_HIGH_VALID_BIT;
228                         high |= IBS_FETCH_HIGH_ENABLE;
229                         low &= IBS_FETCH_LOW_MAX_CNT_MASK;
230                         wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
231                 }
232         }
233
234         if (ibs_config.op_enabled) {
235                 rdmsr(MSR_AMD64_IBSOPCTL, low, high);
236                 if (low & IBS_OP_LOW_VALID_BIT) {
237                         rdmsr(MSR_AMD64_IBSOPRIP, low, high);
238                         ibs_op.ibs_op_rip_low = low;
239                         ibs_op.ibs_op_rip_high = high;
240                         rdmsr(MSR_AMD64_IBSOPDATA, low, high);
241                         ibs_op.ibs_op_data1_low = low;
242                         ibs_op.ibs_op_data1_high = high;
243                         rdmsr(MSR_AMD64_IBSOPDATA2, low, high);
244                         ibs_op.ibs_op_data2_low = low;
245                         ibs_op.ibs_op_data2_high = high;
246                         rdmsr(MSR_AMD64_IBSOPDATA3, low, high);
247                         ibs_op.ibs_op_data3_low = low;
248                         ibs_op.ibs_op_data3_high = high;
249                         rdmsr(MSR_AMD64_IBSDCLINAD, low, high);
250                         ibs_op.ibs_dc_linear_low = low;
251                         ibs_op.ibs_dc_linear_high = high;
252                         rdmsr(MSR_AMD64_IBSDCPHYSAD, low, high);
253                         ibs_op.ibs_dc_phys_low = low;
254                         ibs_op.ibs_dc_phys_high = high;
255
256                         /* reenable the IRQ */
257                         oprofile_add_ibs_sample(regs,
258                                                 (unsigned int *)&ibs_op,
259                                                 IBS_OP_BEGIN);
260                         rdmsr(MSR_AMD64_IBSOPCTL, low, high);
261                         high = 0;
262                         low &= ~IBS_OP_LOW_VALID_BIT;
263                         low |= IBS_OP_LOW_ENABLE;
264                         wrmsr(MSR_AMD64_IBSOPCTL, low, high);
265                 }
266         }
267
268         return 1;
269 }
270
271 #endif
272
273 static int op_amd_check_ctrs(struct pt_regs * const regs,
274                              struct op_msrs const * const msrs)
275 {
276         unsigned int low, high;
277         int i;
278
279         for (i = 0 ; i < NUM_COUNTERS; ++i) {
280                 if (!reset_value[i])
281                         continue;
282                 CTR_READ(low, high, msrs, i);
283                 if (CTR_OVERFLOWED(low)) {
284                         oprofile_add_sample(regs, i);
285                         CTR_WRITE(reset_value[i], msrs, i);
286                 }
287         }
288
289 #ifdef CONFIG_OPROFILE_IBS
290         op_amd_handle_ibs(regs, msrs);
291 #endif
292
293         /* See op_model_ppro.c */
294         return 1;
295 }
296
297 static void op_amd_start(struct op_msrs const * const msrs)
298 {
299         unsigned int low, high;
300         int i;
301         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
302                 if (reset_value[i]) {
303                         CTRL_READ(low, high, msrs, i);
304                         CTRL_SET_ACTIVE(low);
305                         CTRL_WRITE(low, high, msrs, i);
306                 }
307         }
308
309 #ifdef CONFIG_OPROFILE_IBS
310         if (ibs_allowed && ibs_config.fetch_enabled) {
311                 low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
312                 high = IBS_FETCH_HIGH_ENABLE;
313                 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
314         }
315
316         if (ibs_allowed && ibs_config.op_enabled) {
317                 low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF) + IBS_OP_LOW_ENABLE;
318                 high = 0;
319                 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
320         }
321 #endif
322 }
323
324
325 static void op_amd_stop(struct op_msrs const * const msrs)
326 {
327         unsigned int low, high;
328         int i;
329
330         /* Subtle: stop on all counters to avoid race with
331          * setting our pm callback */
332         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
333                 if (!reset_value[i])
334                         continue;
335                 CTRL_READ(low, high, msrs, i);
336                 CTRL_SET_INACTIVE(low);
337                 CTRL_WRITE(low, high, msrs, i);
338         }
339
340 #ifdef CONFIG_OPROFILE_IBS
341         if (ibs_allowed && ibs_config.fetch_enabled) {
342                 low = 0;                /* clear max count and enable */
343                 high = 0;
344                 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
345         }
346
347         if (ibs_allowed && ibs_config.op_enabled) {
348                 low = 0;                /* clear max count and enable */
349                 high = 0;
350                 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
351         }
352 #endif
353 }
354
355 static void op_amd_shutdown(struct op_msrs const * const msrs)
356 {
357         int i;
358
359         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
360                 if (CTR_IS_RESERVED(msrs, i))
361                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
362         }
363         for (i = 0 ; i < NUM_CONTROLS ; ++i) {
364                 if (CTRL_IS_RESERVED(msrs, i))
365                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
366         }
367 }
368
369 #ifndef CONFIG_OPROFILE_IBS
370
371 /* no IBS support */
372
373 static int op_amd_init(struct oprofile_operations *ops)
374 {
375         return 0;
376 }
377
378 static void op_amd_exit(void) {}
379
380 #else
381
382 static u8 ibs_eilvt_off;
383
384 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
385 {
386         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
387 }
388
389 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
390 {
391         setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
392 }
393
394 static int pfm_amd64_setup_eilvt(void)
395 {
396 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
397 #define IBSCTL                          0x1cc
398         struct pci_dev *cpu_cfg;
399         int nodes;
400         u32 value = 0;
401
402         /* per CPU setup */
403         on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
404
405         nodes = 0;
406         cpu_cfg = NULL;
407         do {
408                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
409                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
410                                          cpu_cfg);
411                 if (!cpu_cfg)
412                         break;
413                 ++nodes;
414                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
415                                        | IBSCTL_LVTOFFSETVAL);
416                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
417                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
418                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
419                                 "IBSCTL = 0x%08x", value);
420                         return 1;
421                 }
422         } while (1);
423
424         if (!nodes) {
425                 printk(KERN_DEBUG "No CPU node configured for IBS");
426                 return 1;
427         }
428
429 #ifdef CONFIG_NUMA
430         /* Sanity check */
431         /* Works only for 64bit with proper numa implementation. */
432         if (nodes != num_possible_nodes()) {
433                 printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
434                         "found: %d, expected %d",
435                         nodes, num_possible_nodes());
436                 return 1;
437         }
438 #endif
439         return 0;
440 }
441
442 /*
443  * initialize the APIC for the IBS interrupts
444  * if available (AMD Family10h rev B0 and later)
445  */
446 static void setup_ibs(void)
447 {
448         ibs_allowed = boot_cpu_has(X86_FEATURE_IBS);
449
450         if (!ibs_allowed)
451                 return;
452
453         if (pfm_amd64_setup_eilvt()) {
454                 ibs_allowed = 0;
455                 return;
456         }
457
458         printk(KERN_INFO "oprofile: AMD IBS detected\n");
459 }
460
461
462 /*
463  * unitialize the APIC for the IBS interrupts if needed on AMD Family10h
464  * rev B0 and later */
465 static void clear_ibs_nmi(void)
466 {
467         if (ibs_allowed)
468                 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
469 }
470
471 static int (*create_arch_files)(struct super_block * sb, struct dentry * root);
472
473 static int setup_ibs_files(struct super_block * sb, struct dentry * root)
474 {
475         char buf[12];
476         struct dentry *dir;
477         int ret = 0;
478
479         /* architecture specific files */
480         if (create_arch_files)
481                 ret = create_arch_files(sb, root);
482
483         if (ret)
484                 return ret;
485
486         if (!ibs_allowed)
487                 return ret;
488
489         /* model specific files */
490
491         /* setup some reasonable defaults */
492         ibs_config.max_cnt_fetch = 250000;
493         ibs_config.fetch_enabled = 0;
494         ibs_config.max_cnt_op = 250000;
495         ibs_config.op_enabled = 0;
496         ibs_config.dispatched_ops = 1;
497         snprintf(buf,  sizeof(buf), "ibs_fetch");
498         dir = oprofilefs_mkdir(sb, root, buf);
499         oprofilefs_create_ulong(sb, dir, "rand_enable",
500                                 &ibs_config.rand_en);
501         oprofilefs_create_ulong(sb, dir, "enable",
502                 &ibs_config.fetch_enabled);
503         oprofilefs_create_ulong(sb, dir, "max_count",
504                 &ibs_config.max_cnt_fetch);
505         snprintf(buf,  sizeof(buf), "ibs_uops");
506         dir = oprofilefs_mkdir(sb, root, buf);
507         oprofilefs_create_ulong(sb, dir, "enable",
508                 &ibs_config.op_enabled);
509         oprofilefs_create_ulong(sb, dir, "max_count",
510                 &ibs_config.max_cnt_op);
511         oprofilefs_create_ulong(sb, dir, "dispatched_ops",
512                 &ibs_config.dispatched_ops);
513
514         return 0;
515 }
516
517 static int op_amd_init(struct oprofile_operations *ops)
518 {
519         setup_ibs();
520         create_arch_files = ops->create_files;
521         ops->create_files = setup_ibs_files;
522         return 0;
523 }
524
525 static void op_amd_exit(void)
526 {
527         clear_ibs_nmi();
528 }
529
530 #endif
531
532 struct op_x86_model_spec const op_amd_spec = {
533         .init = op_amd_init,
534         .exit = op_amd_exit,
535         .num_counters = NUM_COUNTERS,
536         .num_controls = NUM_CONTROLS,
537         .fill_in_addresses = &op_amd_fill_in_addresses,
538         .setup_ctrs = &op_amd_setup_ctrs,
539         .check_ctrs = &op_amd_check_ctrs,
540         .start = &op_amd_start,
541         .stop = &op_amd_stop,
542         .shutdown = &op_amd_shutdown
543 };