d52ae8d7303de2586351d80662fd385366331ec5
[linux-2.6.git] / arch / x86 / kvm / vmx.h
1 #ifndef VMX_H
2 #define VMX_H
3
4 /*
5  * vmx.h: VMX Architecture related definitions
6  * Copyright (c) 2004, Intel Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms and conditions of the GNU General Public License,
10  * version 2, as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19  * Place - Suite 330, Boston, MA 02111-1307 USA.
20  *
21  * A few random additions are:
22  * Copyright (C) 2006 Qumranet
23  *    Avi Kivity <avi@qumranet.com>
24  *    Yaniv Kamay <yaniv@qumranet.com>
25  *
26  */
27
28 /*
29  * Definitions of Primary Processor-Based VM-Execution Controls.
30  */
31 #define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
32 #define CPU_BASED_USE_TSC_OFFSETING             0x00000008
33 #define CPU_BASED_HLT_EXITING                   0x00000080
34 #define CPU_BASED_INVLPG_EXITING                0x00000200
35 #define CPU_BASED_MWAIT_EXITING                 0x00000400
36 #define CPU_BASED_RDPMC_EXITING                 0x00000800
37 #define CPU_BASED_RDTSC_EXITING                 0x00001000
38 #define CPU_BASED_CR8_LOAD_EXITING              0x00080000
39 #define CPU_BASED_CR8_STORE_EXITING             0x00100000
40 #define CPU_BASED_TPR_SHADOW                    0x00200000
41 #define CPU_BASED_MOV_DR_EXITING                0x00800000
42 #define CPU_BASED_UNCOND_IO_EXITING             0x01000000
43 #define CPU_BASED_USE_IO_BITMAPS                0x02000000
44 #define CPU_BASED_USE_MSR_BITMAPS               0x10000000
45 #define CPU_BASED_MONITOR_EXITING               0x20000000
46 #define CPU_BASED_PAUSE_EXITING                 0x40000000
47 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
48 /*
49  * Definitions of Secondary Processor-Based VM-Execution Controls.
50  */
51 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
52 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
53
54
55 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
56 #define PIN_BASED_NMI_EXITING                   0x00000008
57 #define PIN_BASED_VIRTUAL_NMIS                  0x00000020
58
59 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
60 #define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
61
62 #define VM_ENTRY_IA32E_MODE                     0x00000200
63 #define VM_ENTRY_SMM                            0x00000400
64 #define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
65
66 /* VMCS Encodings */
67 enum vmcs_field {
68         GUEST_ES_SELECTOR               = 0x00000800,
69         GUEST_CS_SELECTOR               = 0x00000802,
70         GUEST_SS_SELECTOR               = 0x00000804,
71         GUEST_DS_SELECTOR               = 0x00000806,
72         GUEST_FS_SELECTOR               = 0x00000808,
73         GUEST_GS_SELECTOR               = 0x0000080a,
74         GUEST_LDTR_SELECTOR             = 0x0000080c,
75         GUEST_TR_SELECTOR               = 0x0000080e,
76         HOST_ES_SELECTOR                = 0x00000c00,
77         HOST_CS_SELECTOR                = 0x00000c02,
78         HOST_SS_SELECTOR                = 0x00000c04,
79         HOST_DS_SELECTOR                = 0x00000c06,
80         HOST_FS_SELECTOR                = 0x00000c08,
81         HOST_GS_SELECTOR                = 0x00000c0a,
82         HOST_TR_SELECTOR                = 0x00000c0c,
83         IO_BITMAP_A                     = 0x00002000,
84         IO_BITMAP_A_HIGH                = 0x00002001,
85         IO_BITMAP_B                     = 0x00002002,
86         IO_BITMAP_B_HIGH                = 0x00002003,
87         MSR_BITMAP                      = 0x00002004,
88         MSR_BITMAP_HIGH                 = 0x00002005,
89         VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
90         VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
91         VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
92         VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
93         VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
94         VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
95         TSC_OFFSET                      = 0x00002010,
96         TSC_OFFSET_HIGH                 = 0x00002011,
97         VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
98         VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
99         APIC_ACCESS_ADDR                = 0x00002014,
100         APIC_ACCESS_ADDR_HIGH           = 0x00002015,
101         VMCS_LINK_POINTER               = 0x00002800,
102         VMCS_LINK_POINTER_HIGH          = 0x00002801,
103         GUEST_IA32_DEBUGCTL             = 0x00002802,
104         GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
105         PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
106         CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
107         EXCEPTION_BITMAP                = 0x00004004,
108         PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
109         PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
110         CR3_TARGET_COUNT                = 0x0000400a,
111         VM_EXIT_CONTROLS                = 0x0000400c,
112         VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
113         VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
114         VM_ENTRY_CONTROLS               = 0x00004012,
115         VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
116         VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
117         VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
118         VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
119         TPR_THRESHOLD                   = 0x0000401c,
120         SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
121         VM_INSTRUCTION_ERROR            = 0x00004400,
122         VM_EXIT_REASON                  = 0x00004402,
123         VM_EXIT_INTR_INFO               = 0x00004404,
124         VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
125         IDT_VECTORING_INFO_FIELD        = 0x00004408,
126         IDT_VECTORING_ERROR_CODE        = 0x0000440a,
127         VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
128         VMX_INSTRUCTION_INFO            = 0x0000440e,
129         GUEST_ES_LIMIT                  = 0x00004800,
130         GUEST_CS_LIMIT                  = 0x00004802,
131         GUEST_SS_LIMIT                  = 0x00004804,
132         GUEST_DS_LIMIT                  = 0x00004806,
133         GUEST_FS_LIMIT                  = 0x00004808,
134         GUEST_GS_LIMIT                  = 0x0000480a,
135         GUEST_LDTR_LIMIT                = 0x0000480c,
136         GUEST_TR_LIMIT                  = 0x0000480e,
137         GUEST_GDTR_LIMIT                = 0x00004810,
138         GUEST_IDTR_LIMIT                = 0x00004812,
139         GUEST_ES_AR_BYTES               = 0x00004814,
140         GUEST_CS_AR_BYTES               = 0x00004816,
141         GUEST_SS_AR_BYTES               = 0x00004818,
142         GUEST_DS_AR_BYTES               = 0x0000481a,
143         GUEST_FS_AR_BYTES               = 0x0000481c,
144         GUEST_GS_AR_BYTES               = 0x0000481e,
145         GUEST_LDTR_AR_BYTES             = 0x00004820,
146         GUEST_TR_AR_BYTES               = 0x00004822,
147         GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
148         GUEST_ACTIVITY_STATE            = 0X00004826,
149         GUEST_SYSENTER_CS               = 0x0000482A,
150         HOST_IA32_SYSENTER_CS           = 0x00004c00,
151         CR0_GUEST_HOST_MASK             = 0x00006000,
152         CR4_GUEST_HOST_MASK             = 0x00006002,
153         CR0_READ_SHADOW                 = 0x00006004,
154         CR4_READ_SHADOW                 = 0x00006006,
155         CR3_TARGET_VALUE0               = 0x00006008,
156         CR3_TARGET_VALUE1               = 0x0000600a,
157         CR3_TARGET_VALUE2               = 0x0000600c,
158         CR3_TARGET_VALUE3               = 0x0000600e,
159         EXIT_QUALIFICATION              = 0x00006400,
160         GUEST_LINEAR_ADDRESS            = 0x0000640a,
161         GUEST_CR0                       = 0x00006800,
162         GUEST_CR3                       = 0x00006802,
163         GUEST_CR4                       = 0x00006804,
164         GUEST_ES_BASE                   = 0x00006806,
165         GUEST_CS_BASE                   = 0x00006808,
166         GUEST_SS_BASE                   = 0x0000680a,
167         GUEST_DS_BASE                   = 0x0000680c,
168         GUEST_FS_BASE                   = 0x0000680e,
169         GUEST_GS_BASE                   = 0x00006810,
170         GUEST_LDTR_BASE                 = 0x00006812,
171         GUEST_TR_BASE                   = 0x00006814,
172         GUEST_GDTR_BASE                 = 0x00006816,
173         GUEST_IDTR_BASE                 = 0x00006818,
174         GUEST_DR7                       = 0x0000681a,
175         GUEST_RSP                       = 0x0000681c,
176         GUEST_RIP                       = 0x0000681e,
177         GUEST_RFLAGS                    = 0x00006820,
178         GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
179         GUEST_SYSENTER_ESP              = 0x00006824,
180         GUEST_SYSENTER_EIP              = 0x00006826,
181         HOST_CR0                        = 0x00006c00,
182         HOST_CR3                        = 0x00006c02,
183         HOST_CR4                        = 0x00006c04,
184         HOST_FS_BASE                    = 0x00006c06,
185         HOST_GS_BASE                    = 0x00006c08,
186         HOST_TR_BASE                    = 0x00006c0a,
187         HOST_GDTR_BASE                  = 0x00006c0c,
188         HOST_IDTR_BASE                  = 0x00006c0e,
189         HOST_IA32_SYSENTER_ESP          = 0x00006c10,
190         HOST_IA32_SYSENTER_EIP          = 0x00006c12,
191         HOST_RSP                        = 0x00006c14,
192         HOST_RIP                        = 0x00006c16,
193 };
194
195 #define VMX_EXIT_REASONS_FAILED_VMENTRY         0x80000000
196
197 #define EXIT_REASON_EXCEPTION_NMI       0
198 #define EXIT_REASON_EXTERNAL_INTERRUPT  1
199 #define EXIT_REASON_TRIPLE_FAULT        2
200
201 #define EXIT_REASON_PENDING_INTERRUPT   7
202
203 #define EXIT_REASON_TASK_SWITCH         9
204 #define EXIT_REASON_CPUID               10
205 #define EXIT_REASON_HLT                 12
206 #define EXIT_REASON_INVLPG              14
207 #define EXIT_REASON_RDPMC               15
208 #define EXIT_REASON_RDTSC               16
209 #define EXIT_REASON_VMCALL              18
210 #define EXIT_REASON_VMCLEAR             19
211 #define EXIT_REASON_VMLAUNCH            20
212 #define EXIT_REASON_VMPTRLD             21
213 #define EXIT_REASON_VMPTRST             22
214 #define EXIT_REASON_VMREAD              23
215 #define EXIT_REASON_VMRESUME            24
216 #define EXIT_REASON_VMWRITE             25
217 #define EXIT_REASON_VMOFF               26
218 #define EXIT_REASON_VMON                27
219 #define EXIT_REASON_CR_ACCESS           28
220 #define EXIT_REASON_DR_ACCESS           29
221 #define EXIT_REASON_IO_INSTRUCTION      30
222 #define EXIT_REASON_MSR_READ            31
223 #define EXIT_REASON_MSR_WRITE           32
224 #define EXIT_REASON_MWAIT_INSTRUCTION   36
225 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
226 #define EXIT_REASON_APIC_ACCESS         44
227 #define EXIT_REASON_WBINVD              54
228
229 /*
230  * Interruption-information format
231  */
232 #define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
233 #define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
234 #define INTR_INFO_DELIEVER_CODE_MASK    0x800           /* 11 */
235 #define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
236
237 #define VECTORING_INFO_VECTOR_MASK              INTR_INFO_VECTOR_MASK
238 #define VECTORING_INFO_TYPE_MASK                INTR_INFO_INTR_TYPE_MASK
239 #define VECTORING_INFO_DELIEVER_CODE_MASK       INTR_INFO_DELIEVER_CODE_MASK
240 #define VECTORING_INFO_VALID_MASK               INTR_INFO_VALID_MASK
241
242 #define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
243 #define INTR_TYPE_EXCEPTION             (3 << 8) /* processor exception */
244 #define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
245
246 /*
247  * Exit Qualifications for MOV for Control Register Access
248  */
249 #define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control reg.*/
250 #define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
251 #define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose reg. */
252 #define LMSW_SOURCE_DATA_SHIFT 16
253 #define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
254 #define REG_EAX                         (0 << 8)
255 #define REG_ECX                         (1 << 8)
256 #define REG_EDX                         (2 << 8)
257 #define REG_EBX                         (3 << 8)
258 #define REG_ESP                         (4 << 8)
259 #define REG_EBP                         (5 << 8)
260 #define REG_ESI                         (6 << 8)
261 #define REG_EDI                         (7 << 8)
262 #define REG_R8                         (8 << 8)
263 #define REG_R9                         (9 << 8)
264 #define REG_R10                        (10 << 8)
265 #define REG_R11                        (11 << 8)
266 #define REG_R12                        (12 << 8)
267 #define REG_R13                        (13 << 8)
268 #define REG_R14                        (14 << 8)
269 #define REG_R15                        (15 << 8)
270
271 /*
272  * Exit Qualifications for MOV for Debug Register Access
273  */
274 #define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug reg. */
275 #define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
276 #define TYPE_MOV_TO_DR                  (0 << 4)
277 #define TYPE_MOV_FROM_DR                (1 << 4)
278 #define DEBUG_REG_ACCESS_REG            0xf00   /* 11:8, general purpose reg. */
279
280
281 /* segment AR */
282 #define SEGMENT_AR_L_MASK (1 << 13)
283
284 #define AR_TYPE_ACCESSES_MASK 1
285 #define AR_TYPE_READABLE_MASK (1 << 1)
286 #define AR_TYPE_WRITEABLE_MASK (1 << 2)
287 #define AR_TYPE_CODE_MASK (1 << 3)
288 #define AR_TYPE_MASK 0x0f
289 #define AR_TYPE_BUSY_64_TSS 11
290 #define AR_TYPE_BUSY_32_TSS 11
291 #define AR_TYPE_BUSY_16_TSS 3
292 #define AR_TYPE_LDT 2
293
294 #define AR_UNUSABLE_MASK (1 << 16)
295 #define AR_S_MASK (1 << 4)
296 #define AR_P_MASK (1 << 7)
297 #define AR_L_MASK (1 << 13)
298 #define AR_DB_MASK (1 << 14)
299 #define AR_G_MASK (1 << 15)
300 #define AR_DPL_SHIFT 5
301 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
302
303 #define AR_RESERVD_MASK 0xfffe0f00
304
305 #define MSR_IA32_VMX_BASIC                      0x480
306 #define MSR_IA32_VMX_PINBASED_CTLS              0x481
307 #define MSR_IA32_VMX_PROCBASED_CTLS             0x482
308 #define MSR_IA32_VMX_EXIT_CTLS                  0x483
309 #define MSR_IA32_VMX_ENTRY_CTLS                 0x484
310 #define MSR_IA32_VMX_MISC                       0x485
311 #define MSR_IA32_VMX_CR0_FIXED0                 0x486
312 #define MSR_IA32_VMX_CR0_FIXED1                 0x487
313 #define MSR_IA32_VMX_CR4_FIXED0                 0x488
314 #define MSR_IA32_VMX_CR4_FIXED1                 0x489
315 #define MSR_IA32_VMX_VMCS_ENUM                  0x48a
316 #define MSR_IA32_VMX_PROCBASED_CTLS2            0x48b
317
318 #define MSR_IA32_FEATURE_CONTROL                0x3a
319 #define MSR_IA32_FEATURE_CONTROL_LOCKED         0x1
320 #define MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED  0x4
321
322 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT        9
323
324 #endif