KVM: VMX: Avoid rearranging switched guest msrs while they are loaded
[linux-2.6.git] / arch / x86 / kvm / vmx.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  *
9  * Authors:
10  *   Avi Kivity   <avi@qumranet.com>
11  *   Yaniv Kamay  <yaniv@qumranet.com>
12  *
13  * This work is licensed under the terms of the GNU GPL, version 2.  See
14  * the COPYING file in the top-level directory.
15  *
16  */
17
18 #include "irq.h"
19 #include "vmx.h"
20 #include "segment_descriptor.h"
21 #include "mmu.h"
22
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/mm.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30
31 #include <asm/io.h>
32 #include <asm/desc.h>
33
34 MODULE_AUTHOR("Qumranet");
35 MODULE_LICENSE("GPL");
36
37 static int bypass_guest_pf = 1;
38 module_param(bypass_guest_pf, bool, 0);
39
40 struct vmcs {
41         u32 revision_id;
42         u32 abort;
43         char data[0];
44 };
45
46 struct vcpu_vmx {
47         struct kvm_vcpu       vcpu;
48         int                   launched;
49         u8                    fail;
50         u32                   idt_vectoring_info;
51         struct kvm_msr_entry *guest_msrs;
52         struct kvm_msr_entry *host_msrs;
53         int                   nmsrs;
54         int                   save_nmsrs;
55         int                   msr_offset_efer;
56 #ifdef CONFIG_X86_64
57         int                   msr_offset_kernel_gs_base;
58 #endif
59         struct vmcs          *vmcs;
60         struct {
61                 int           loaded;
62                 u16           fs_sel, gs_sel, ldt_sel;
63                 int           gs_ldt_reload_needed;
64                 int           fs_reload_needed;
65                 int           guest_efer_loaded;
66         } host_state;
67         struct {
68                 struct {
69                         bool pending;
70                         u8 vector;
71                         unsigned rip;
72                 } irq;
73         } rmode;
74 };
75
76 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
77 {
78         return container_of(vcpu, struct vcpu_vmx, vcpu);
79 }
80
81 static int init_rmode_tss(struct kvm *kvm);
82
83 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
84 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
85
86 static struct page *vmx_io_bitmap_a;
87 static struct page *vmx_io_bitmap_b;
88
89 static struct vmcs_config {
90         int size;
91         int order;
92         u32 revision_id;
93         u32 pin_based_exec_ctrl;
94         u32 cpu_based_exec_ctrl;
95         u32 cpu_based_2nd_exec_ctrl;
96         u32 vmexit_ctrl;
97         u32 vmentry_ctrl;
98 } vmcs_config;
99
100 #define VMX_SEGMENT_FIELD(seg)                                  \
101         [VCPU_SREG_##seg] = {                                   \
102                 .selector = GUEST_##seg##_SELECTOR,             \
103                 .base = GUEST_##seg##_BASE,                     \
104                 .limit = GUEST_##seg##_LIMIT,                   \
105                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
106         }
107
108 static struct kvm_vmx_segment_field {
109         unsigned selector;
110         unsigned base;
111         unsigned limit;
112         unsigned ar_bytes;
113 } kvm_vmx_segment_fields[] = {
114         VMX_SEGMENT_FIELD(CS),
115         VMX_SEGMENT_FIELD(DS),
116         VMX_SEGMENT_FIELD(ES),
117         VMX_SEGMENT_FIELD(FS),
118         VMX_SEGMENT_FIELD(GS),
119         VMX_SEGMENT_FIELD(SS),
120         VMX_SEGMENT_FIELD(TR),
121         VMX_SEGMENT_FIELD(LDTR),
122 };
123
124 /*
125  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
126  * away by decrementing the array size.
127  */
128 static const u32 vmx_msr_index[] = {
129 #ifdef CONFIG_X86_64
130         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
131 #endif
132         MSR_EFER, MSR_K6_STAR,
133 };
134 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
135
136 static void load_msrs(struct kvm_msr_entry *e, int n)
137 {
138         int i;
139
140         for (i = 0; i < n; ++i)
141                 wrmsrl(e[i].index, e[i].data);
142 }
143
144 static void save_msrs(struct kvm_msr_entry *e, int n)
145 {
146         int i;
147
148         for (i = 0; i < n; ++i)
149                 rdmsrl(e[i].index, e[i].data);
150 }
151
152 static inline int is_page_fault(u32 intr_info)
153 {
154         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
155                              INTR_INFO_VALID_MASK)) ==
156                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
157 }
158
159 static inline int is_no_device(u32 intr_info)
160 {
161         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
162                              INTR_INFO_VALID_MASK)) ==
163                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
164 }
165
166 static inline int is_invalid_opcode(u32 intr_info)
167 {
168         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
169                              INTR_INFO_VALID_MASK)) ==
170                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
171 }
172
173 static inline int is_external_interrupt(u32 intr_info)
174 {
175         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
176                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
177 }
178
179 static inline int cpu_has_vmx_tpr_shadow(void)
180 {
181         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
182 }
183
184 static inline int vm_need_tpr_shadow(struct kvm *kvm)
185 {
186         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
187 }
188
189 static inline int cpu_has_secondary_exec_ctrls(void)
190 {
191         return (vmcs_config.cpu_based_exec_ctrl &
192                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
193 }
194
195 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
196 {
197         return (vmcs_config.cpu_based_2nd_exec_ctrl &
198                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
199 }
200
201 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
202 {
203         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
204                 (irqchip_in_kernel(kvm)));
205 }
206
207 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
208 {
209         int i;
210
211         for (i = 0; i < vmx->nmsrs; ++i)
212                 if (vmx->guest_msrs[i].index == msr)
213                         return i;
214         return -1;
215 }
216
217 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
218 {
219         int i;
220
221         i = __find_msr_index(vmx, msr);
222         if (i >= 0)
223                 return &vmx->guest_msrs[i];
224         return NULL;
225 }
226
227 static void vmcs_clear(struct vmcs *vmcs)
228 {
229         u64 phys_addr = __pa(vmcs);
230         u8 error;
231
232         asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
233                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
234                       : "cc", "memory");
235         if (error)
236                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
237                        vmcs, phys_addr);
238 }
239
240 static void __vcpu_clear(void *arg)
241 {
242         struct vcpu_vmx *vmx = arg;
243         int cpu = raw_smp_processor_id();
244
245         if (vmx->vcpu.cpu == cpu)
246                 vmcs_clear(vmx->vmcs);
247         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
248                 per_cpu(current_vmcs, cpu) = NULL;
249         rdtscll(vmx->vcpu.arch.host_tsc);
250 }
251
252 static void vcpu_clear(struct vcpu_vmx *vmx)
253 {
254         if (vmx->vcpu.cpu == -1)
255                 return;
256         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
257         vmx->launched = 0;
258 }
259
260 static unsigned long vmcs_readl(unsigned long field)
261 {
262         unsigned long value;
263
264         asm volatile (ASM_VMX_VMREAD_RDX_RAX
265                       : "=a"(value) : "d"(field) : "cc");
266         return value;
267 }
268
269 static u16 vmcs_read16(unsigned long field)
270 {
271         return vmcs_readl(field);
272 }
273
274 static u32 vmcs_read32(unsigned long field)
275 {
276         return vmcs_readl(field);
277 }
278
279 static u64 vmcs_read64(unsigned long field)
280 {
281 #ifdef CONFIG_X86_64
282         return vmcs_readl(field);
283 #else
284         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
285 #endif
286 }
287
288 static noinline void vmwrite_error(unsigned long field, unsigned long value)
289 {
290         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
291                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
292         dump_stack();
293 }
294
295 static void vmcs_writel(unsigned long field, unsigned long value)
296 {
297         u8 error;
298
299         asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
300                        : "=q"(error) : "a"(value), "d"(field) : "cc");
301         if (unlikely(error))
302                 vmwrite_error(field, value);
303 }
304
305 static void vmcs_write16(unsigned long field, u16 value)
306 {
307         vmcs_writel(field, value);
308 }
309
310 static void vmcs_write32(unsigned long field, u32 value)
311 {
312         vmcs_writel(field, value);
313 }
314
315 static void vmcs_write64(unsigned long field, u64 value)
316 {
317 #ifdef CONFIG_X86_64
318         vmcs_writel(field, value);
319 #else
320         vmcs_writel(field, value);
321         asm volatile ("");
322         vmcs_writel(field+1, value >> 32);
323 #endif
324 }
325
326 static void vmcs_clear_bits(unsigned long field, u32 mask)
327 {
328         vmcs_writel(field, vmcs_readl(field) & ~mask);
329 }
330
331 static void vmcs_set_bits(unsigned long field, u32 mask)
332 {
333         vmcs_writel(field, vmcs_readl(field) | mask);
334 }
335
336 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
337 {
338         u32 eb;
339
340         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
341         if (!vcpu->fpu_active)
342                 eb |= 1u << NM_VECTOR;
343         if (vcpu->guest_debug.enabled)
344                 eb |= 1u << 1;
345         if (vcpu->arch.rmode.active)
346                 eb = ~0;
347         vmcs_write32(EXCEPTION_BITMAP, eb);
348 }
349
350 static void reload_tss(void)
351 {
352 #ifndef CONFIG_X86_64
353
354         /*
355          * VT restores TR but not its size.  Useless.
356          */
357         struct descriptor_table gdt;
358         struct segment_descriptor *descs;
359
360         get_gdt(&gdt);
361         descs = (void *)gdt.base;
362         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
363         load_TR_desc();
364 #endif
365 }
366
367 static void load_transition_efer(struct vcpu_vmx *vmx)
368 {
369         int efer_offset = vmx->msr_offset_efer;
370         u64 host_efer = vmx->host_msrs[efer_offset].data;
371         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
372         u64 ignore_bits;
373
374         if (efer_offset < 0)
375                 return;
376         /*
377          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
378          * outside long mode
379          */
380         ignore_bits = EFER_NX | EFER_SCE;
381 #ifdef CONFIG_X86_64
382         ignore_bits |= EFER_LMA | EFER_LME;
383         /* SCE is meaningful only in long mode on Intel */
384         if (guest_efer & EFER_LMA)
385                 ignore_bits &= ~(u64)EFER_SCE;
386 #endif
387         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
388                 return;
389
390         vmx->host_state.guest_efer_loaded = 1;
391         guest_efer &= ~ignore_bits;
392         guest_efer |= host_efer & ignore_bits;
393         wrmsrl(MSR_EFER, guest_efer);
394         vmx->vcpu.stat.efer_reload++;
395 }
396
397 static void reload_host_efer(struct vcpu_vmx *vmx)
398 {
399         if (vmx->host_state.guest_efer_loaded) {
400                 vmx->host_state.guest_efer_loaded = 0;
401                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
402         }
403 }
404
405 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
406 {
407         struct vcpu_vmx *vmx = to_vmx(vcpu);
408
409         if (vmx->host_state.loaded)
410                 return;
411
412         vmx->host_state.loaded = 1;
413         /*
414          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
415          * allow segment selectors with cpl > 0 or ti == 1.
416          */
417         vmx->host_state.ldt_sel = read_ldt();
418         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
419         vmx->host_state.fs_sel = read_fs();
420         if (!(vmx->host_state.fs_sel & 7)) {
421                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
422                 vmx->host_state.fs_reload_needed = 0;
423         } else {
424                 vmcs_write16(HOST_FS_SELECTOR, 0);
425                 vmx->host_state.fs_reload_needed = 1;
426         }
427         vmx->host_state.gs_sel = read_gs();
428         if (!(vmx->host_state.gs_sel & 7))
429                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
430         else {
431                 vmcs_write16(HOST_GS_SELECTOR, 0);
432                 vmx->host_state.gs_ldt_reload_needed = 1;
433         }
434
435 #ifdef CONFIG_X86_64
436         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
437         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
438 #else
439         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
440         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
441 #endif
442
443 #ifdef CONFIG_X86_64
444         if (is_long_mode(&vmx->vcpu))
445                 save_msrs(vmx->host_msrs +
446                           vmx->msr_offset_kernel_gs_base, 1);
447
448 #endif
449         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
450         load_transition_efer(vmx);
451 }
452
453 static void vmx_load_host_state(struct vcpu_vmx *vmx)
454 {
455         unsigned long flags;
456
457         if (!vmx->host_state.loaded)
458                 return;
459
460         ++vmx->vcpu.stat.host_state_reload;
461         vmx->host_state.loaded = 0;
462         if (vmx->host_state.fs_reload_needed)
463                 load_fs(vmx->host_state.fs_sel);
464         if (vmx->host_state.gs_ldt_reload_needed) {
465                 load_ldt(vmx->host_state.ldt_sel);
466                 /*
467                  * If we have to reload gs, we must take care to
468                  * preserve our gs base.
469                  */
470                 local_irq_save(flags);
471                 load_gs(vmx->host_state.gs_sel);
472 #ifdef CONFIG_X86_64
473                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
474 #endif
475                 local_irq_restore(flags);
476         }
477         reload_tss();
478         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
479         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
480         reload_host_efer(vmx);
481 }
482
483 /*
484  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
485  * vcpu mutex is already taken.
486  */
487 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
488 {
489         struct vcpu_vmx *vmx = to_vmx(vcpu);
490         u64 phys_addr = __pa(vmx->vmcs);
491         u64 tsc_this, delta;
492
493         if (vcpu->cpu != cpu) {
494                 vcpu_clear(vmx);
495                 kvm_migrate_apic_timer(vcpu);
496         }
497
498         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
499                 u8 error;
500
501                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
502                 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
503                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
504                               : "cc");
505                 if (error)
506                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
507                                vmx->vmcs, phys_addr);
508         }
509
510         if (vcpu->cpu != cpu) {
511                 struct descriptor_table dt;
512                 unsigned long sysenter_esp;
513
514                 vcpu->cpu = cpu;
515                 /*
516                  * Linux uses per-cpu TSS and GDT, so set these when switching
517                  * processors.
518                  */
519                 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
520                 get_gdt(&dt);
521                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
522
523                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
524                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
525
526                 /*
527                  * Make sure the time stamp counter is monotonous.
528                  */
529                 rdtscll(tsc_this);
530                 delta = vcpu->arch.host_tsc - tsc_this;
531                 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
532         }
533 }
534
535 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
536 {
537         vmx_load_host_state(to_vmx(vcpu));
538 }
539
540 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
541 {
542         if (vcpu->fpu_active)
543                 return;
544         vcpu->fpu_active = 1;
545         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
546         if (vcpu->arch.cr0 & X86_CR0_TS)
547                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
548         update_exception_bitmap(vcpu);
549 }
550
551 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
552 {
553         if (!vcpu->fpu_active)
554                 return;
555         vcpu->fpu_active = 0;
556         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
557         update_exception_bitmap(vcpu);
558 }
559
560 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
561 {
562         vcpu_clear(to_vmx(vcpu));
563 }
564
565 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
566 {
567         return vmcs_readl(GUEST_RFLAGS);
568 }
569
570 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
571 {
572         if (vcpu->arch.rmode.active)
573                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
574         vmcs_writel(GUEST_RFLAGS, rflags);
575 }
576
577 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
578 {
579         unsigned long rip;
580         u32 interruptibility;
581
582         rip = vmcs_readl(GUEST_RIP);
583         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
584         vmcs_writel(GUEST_RIP, rip);
585
586         /*
587          * We emulated an instruction, so temporary interrupt blocking
588          * should be removed, if set.
589          */
590         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
591         if (interruptibility & 3)
592                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
593                              interruptibility & ~3);
594         vcpu->arch.interrupt_window_open = 1;
595 }
596
597 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
598                                 bool has_error_code, u32 error_code)
599 {
600         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
601                      nr | INTR_TYPE_EXCEPTION
602                      | (has_error_code ? INTR_INFO_DELIEVER_CODE_MASK : 0)
603                      | INTR_INFO_VALID_MASK);
604         if (has_error_code)
605                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
606 }
607
608 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
609 {
610         struct vcpu_vmx *vmx = to_vmx(vcpu);
611
612         return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
613 }
614
615 /*
616  * Swap MSR entry in host/guest MSR entry array.
617  */
618 #ifdef CONFIG_X86_64
619 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
620 {
621         struct kvm_msr_entry tmp;
622
623         tmp = vmx->guest_msrs[to];
624         vmx->guest_msrs[to] = vmx->guest_msrs[from];
625         vmx->guest_msrs[from] = tmp;
626         tmp = vmx->host_msrs[to];
627         vmx->host_msrs[to] = vmx->host_msrs[from];
628         vmx->host_msrs[from] = tmp;
629 }
630 #endif
631
632 /*
633  * Set up the vmcs to automatically save and restore system
634  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
635  * mode, as fiddling with msrs is very expensive.
636  */
637 static void setup_msrs(struct vcpu_vmx *vmx)
638 {
639         int save_nmsrs;
640
641         vmx_load_host_state(vmx);
642         save_nmsrs = 0;
643 #ifdef CONFIG_X86_64
644         if (is_long_mode(&vmx->vcpu)) {
645                 int index;
646
647                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
648                 if (index >= 0)
649                         move_msr_up(vmx, index, save_nmsrs++);
650                 index = __find_msr_index(vmx, MSR_LSTAR);
651                 if (index >= 0)
652                         move_msr_up(vmx, index, save_nmsrs++);
653                 index = __find_msr_index(vmx, MSR_CSTAR);
654                 if (index >= 0)
655                         move_msr_up(vmx, index, save_nmsrs++);
656                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
657                 if (index >= 0)
658                         move_msr_up(vmx, index, save_nmsrs++);
659                 /*
660                  * MSR_K6_STAR is only needed on long mode guests, and only
661                  * if efer.sce is enabled.
662                  */
663                 index = __find_msr_index(vmx, MSR_K6_STAR);
664                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
665                         move_msr_up(vmx, index, save_nmsrs++);
666         }
667 #endif
668         vmx->save_nmsrs = save_nmsrs;
669
670 #ifdef CONFIG_X86_64
671         vmx->msr_offset_kernel_gs_base =
672                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
673 #endif
674         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
675 }
676
677 /*
678  * reads and returns guest's timestamp counter "register"
679  * guest_tsc = host_tsc + tsc_offset    -- 21.3
680  */
681 static u64 guest_read_tsc(void)
682 {
683         u64 host_tsc, tsc_offset;
684
685         rdtscll(host_tsc);
686         tsc_offset = vmcs_read64(TSC_OFFSET);
687         return host_tsc + tsc_offset;
688 }
689
690 /*
691  * writes 'guest_tsc' into guest's timestamp counter "register"
692  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
693  */
694 static void guest_write_tsc(u64 guest_tsc)
695 {
696         u64 host_tsc;
697
698         rdtscll(host_tsc);
699         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
700 }
701
702 /*
703  * Reads an msr value (of 'msr_index') into 'pdata'.
704  * Returns 0 on success, non-0 otherwise.
705  * Assumes vcpu_load() was already called.
706  */
707 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
708 {
709         u64 data;
710         struct kvm_msr_entry *msr;
711
712         if (!pdata) {
713                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
714                 return -EINVAL;
715         }
716
717         switch (msr_index) {
718 #ifdef CONFIG_X86_64
719         case MSR_FS_BASE:
720                 data = vmcs_readl(GUEST_FS_BASE);
721                 break;
722         case MSR_GS_BASE:
723                 data = vmcs_readl(GUEST_GS_BASE);
724                 break;
725         case MSR_EFER:
726                 return kvm_get_msr_common(vcpu, msr_index, pdata);
727 #endif
728         case MSR_IA32_TIME_STAMP_COUNTER:
729                 data = guest_read_tsc();
730                 break;
731         case MSR_IA32_SYSENTER_CS:
732                 data = vmcs_read32(GUEST_SYSENTER_CS);
733                 break;
734         case MSR_IA32_SYSENTER_EIP:
735                 data = vmcs_readl(GUEST_SYSENTER_EIP);
736                 break;
737         case MSR_IA32_SYSENTER_ESP:
738                 data = vmcs_readl(GUEST_SYSENTER_ESP);
739                 break;
740         default:
741                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
742                 if (msr) {
743                         data = msr->data;
744                         break;
745                 }
746                 return kvm_get_msr_common(vcpu, msr_index, pdata);
747         }
748
749         *pdata = data;
750         return 0;
751 }
752
753 /*
754  * Writes msr value into into the appropriate "register".
755  * Returns 0 on success, non-0 otherwise.
756  * Assumes vcpu_load() was already called.
757  */
758 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
759 {
760         struct vcpu_vmx *vmx = to_vmx(vcpu);
761         struct kvm_msr_entry *msr;
762         int ret = 0;
763
764         switch (msr_index) {
765 #ifdef CONFIG_X86_64
766         case MSR_EFER:
767                 ret = kvm_set_msr_common(vcpu, msr_index, data);
768                 if (vmx->host_state.loaded) {
769                         reload_host_efer(vmx);
770                         load_transition_efer(vmx);
771                 }
772                 break;
773         case MSR_FS_BASE:
774                 vmcs_writel(GUEST_FS_BASE, data);
775                 break;
776         case MSR_GS_BASE:
777                 vmcs_writel(GUEST_GS_BASE, data);
778                 break;
779 #endif
780         case MSR_IA32_SYSENTER_CS:
781                 vmcs_write32(GUEST_SYSENTER_CS, data);
782                 break;
783         case MSR_IA32_SYSENTER_EIP:
784                 vmcs_writel(GUEST_SYSENTER_EIP, data);
785                 break;
786         case MSR_IA32_SYSENTER_ESP:
787                 vmcs_writel(GUEST_SYSENTER_ESP, data);
788                 break;
789         case MSR_IA32_TIME_STAMP_COUNTER:
790                 guest_write_tsc(data);
791                 break;
792         default:
793                 msr = find_msr_entry(vmx, msr_index);
794                 if (msr) {
795                         msr->data = data;
796                         if (vmx->host_state.loaded)
797                                 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
798                         break;
799                 }
800                 ret = kvm_set_msr_common(vcpu, msr_index, data);
801         }
802
803         return ret;
804 }
805
806 /*
807  * Sync the rsp and rip registers into the vcpu structure.  This allows
808  * registers to be accessed by indexing vcpu->arch.regs.
809  */
810 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
811 {
812         vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
813         vcpu->arch.rip = vmcs_readl(GUEST_RIP);
814 }
815
816 /*
817  * Syncs rsp and rip back into the vmcs.  Should be called after possible
818  * modification.
819  */
820 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
821 {
822         vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
823         vmcs_writel(GUEST_RIP, vcpu->arch.rip);
824 }
825
826 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
827 {
828         unsigned long dr7 = 0x400;
829         int old_singlestep;
830
831         old_singlestep = vcpu->guest_debug.singlestep;
832
833         vcpu->guest_debug.enabled = dbg->enabled;
834         if (vcpu->guest_debug.enabled) {
835                 int i;
836
837                 dr7 |= 0x200;  /* exact */
838                 for (i = 0; i < 4; ++i) {
839                         if (!dbg->breakpoints[i].enabled)
840                                 continue;
841                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
842                         dr7 |= 2 << (i*2);    /* global enable */
843                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
844                 }
845
846                 vcpu->guest_debug.singlestep = dbg->singlestep;
847         } else
848                 vcpu->guest_debug.singlestep = 0;
849
850         if (old_singlestep && !vcpu->guest_debug.singlestep) {
851                 unsigned long flags;
852
853                 flags = vmcs_readl(GUEST_RFLAGS);
854                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
855                 vmcs_writel(GUEST_RFLAGS, flags);
856         }
857
858         update_exception_bitmap(vcpu);
859         vmcs_writel(GUEST_DR7, dr7);
860
861         return 0;
862 }
863
864 static int vmx_get_irq(struct kvm_vcpu *vcpu)
865 {
866         struct vcpu_vmx *vmx = to_vmx(vcpu);
867         u32 idtv_info_field;
868
869         idtv_info_field = vmx->idt_vectoring_info;
870         if (idtv_info_field & INTR_INFO_VALID_MASK) {
871                 if (is_external_interrupt(idtv_info_field))
872                         return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
873                 else
874                         printk(KERN_DEBUG "pending exception: not handled yet\n");
875         }
876         return -1;
877 }
878
879 static __init int cpu_has_kvm_support(void)
880 {
881         unsigned long ecx = cpuid_ecx(1);
882         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
883 }
884
885 static __init int vmx_disabled_by_bios(void)
886 {
887         u64 msr;
888
889         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
890         return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
891                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
892             == MSR_IA32_FEATURE_CONTROL_LOCKED;
893         /* locked but not enabled */
894 }
895
896 static void hardware_enable(void *garbage)
897 {
898         int cpu = raw_smp_processor_id();
899         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
900         u64 old;
901
902         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
903         if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
904                     MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
905             != (MSR_IA32_FEATURE_CONTROL_LOCKED |
906                 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
907                 /* enable and lock */
908                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
909                        MSR_IA32_FEATURE_CONTROL_LOCKED |
910                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
911         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
912         asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
913                       : "memory", "cc");
914 }
915
916 static void hardware_disable(void *garbage)
917 {
918         asm volatile (ASM_VMX_VMXOFF : : : "cc");
919 }
920
921 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
922                                       u32 msr, u32 *result)
923 {
924         u32 vmx_msr_low, vmx_msr_high;
925         u32 ctl = ctl_min | ctl_opt;
926
927         rdmsr(msr, vmx_msr_low, vmx_msr_high);
928
929         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
930         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
931
932         /* Ensure minimum (required) set of control bits are supported. */
933         if (ctl_min & ~ctl)
934                 return -EIO;
935
936         *result = ctl;
937         return 0;
938 }
939
940 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
941 {
942         u32 vmx_msr_low, vmx_msr_high;
943         u32 min, opt;
944         u32 _pin_based_exec_control = 0;
945         u32 _cpu_based_exec_control = 0;
946         u32 _cpu_based_2nd_exec_control = 0;
947         u32 _vmexit_control = 0;
948         u32 _vmentry_control = 0;
949
950         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
951         opt = 0;
952         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
953                                 &_pin_based_exec_control) < 0)
954                 return -EIO;
955
956         min = CPU_BASED_HLT_EXITING |
957 #ifdef CONFIG_X86_64
958               CPU_BASED_CR8_LOAD_EXITING |
959               CPU_BASED_CR8_STORE_EXITING |
960 #endif
961               CPU_BASED_USE_IO_BITMAPS |
962               CPU_BASED_MOV_DR_EXITING |
963               CPU_BASED_USE_TSC_OFFSETING;
964         opt = CPU_BASED_TPR_SHADOW |
965               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
966         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
967                                 &_cpu_based_exec_control) < 0)
968                 return -EIO;
969 #ifdef CONFIG_X86_64
970         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
971                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
972                                            ~CPU_BASED_CR8_STORE_EXITING;
973 #endif
974         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
975                 min = 0;
976                 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
977                         SECONDARY_EXEC_WBINVD_EXITING;
978                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
979                                         &_cpu_based_2nd_exec_control) < 0)
980                         return -EIO;
981         }
982 #ifndef CONFIG_X86_64
983         if (!(_cpu_based_2nd_exec_control &
984                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
985                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
986 #endif
987
988         min = 0;
989 #ifdef CONFIG_X86_64
990         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
991 #endif
992         opt = 0;
993         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
994                                 &_vmexit_control) < 0)
995                 return -EIO;
996
997         min = opt = 0;
998         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
999                                 &_vmentry_control) < 0)
1000                 return -EIO;
1001
1002         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1003
1004         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1005         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1006                 return -EIO;
1007
1008 #ifdef CONFIG_X86_64
1009         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1010         if (vmx_msr_high & (1u<<16))
1011                 return -EIO;
1012 #endif
1013
1014         /* Require Write-Back (WB) memory type for VMCS accesses. */
1015         if (((vmx_msr_high >> 18) & 15) != 6)
1016                 return -EIO;
1017
1018         vmcs_conf->size = vmx_msr_high & 0x1fff;
1019         vmcs_conf->order = get_order(vmcs_config.size);
1020         vmcs_conf->revision_id = vmx_msr_low;
1021
1022         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1023         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1024         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1025         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1026         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1027
1028         return 0;
1029 }
1030
1031 static struct vmcs *alloc_vmcs_cpu(int cpu)
1032 {
1033         int node = cpu_to_node(cpu);
1034         struct page *pages;
1035         struct vmcs *vmcs;
1036
1037         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1038         if (!pages)
1039                 return NULL;
1040         vmcs = page_address(pages);
1041         memset(vmcs, 0, vmcs_config.size);
1042         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1043         return vmcs;
1044 }
1045
1046 static struct vmcs *alloc_vmcs(void)
1047 {
1048         return alloc_vmcs_cpu(raw_smp_processor_id());
1049 }
1050
1051 static void free_vmcs(struct vmcs *vmcs)
1052 {
1053         free_pages((unsigned long)vmcs, vmcs_config.order);
1054 }
1055
1056 static void free_kvm_area(void)
1057 {
1058         int cpu;
1059
1060         for_each_online_cpu(cpu)
1061                 free_vmcs(per_cpu(vmxarea, cpu));
1062 }
1063
1064 static __init int alloc_kvm_area(void)
1065 {
1066         int cpu;
1067
1068         for_each_online_cpu(cpu) {
1069                 struct vmcs *vmcs;
1070
1071                 vmcs = alloc_vmcs_cpu(cpu);
1072                 if (!vmcs) {
1073                         free_kvm_area();
1074                         return -ENOMEM;
1075                 }
1076
1077                 per_cpu(vmxarea, cpu) = vmcs;
1078         }
1079         return 0;
1080 }
1081
1082 static __init int hardware_setup(void)
1083 {
1084         if (setup_vmcs_config(&vmcs_config) < 0)
1085                 return -EIO;
1086         return alloc_kvm_area();
1087 }
1088
1089 static __exit void hardware_unsetup(void)
1090 {
1091         free_kvm_area();
1092 }
1093
1094 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1095 {
1096         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1097
1098         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1099                 vmcs_write16(sf->selector, save->selector);
1100                 vmcs_writel(sf->base, save->base);
1101                 vmcs_write32(sf->limit, save->limit);
1102                 vmcs_write32(sf->ar_bytes, save->ar);
1103         } else {
1104                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1105                         << AR_DPL_SHIFT;
1106                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1107         }
1108 }
1109
1110 static void enter_pmode(struct kvm_vcpu *vcpu)
1111 {
1112         unsigned long flags;
1113
1114         vcpu->arch.rmode.active = 0;
1115
1116         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1117         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1118         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1119
1120         flags = vmcs_readl(GUEST_RFLAGS);
1121         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1122         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1123         vmcs_writel(GUEST_RFLAGS, flags);
1124
1125         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1126                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1127
1128         update_exception_bitmap(vcpu);
1129
1130         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1131         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1132         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1133         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1134
1135         vmcs_write16(GUEST_SS_SELECTOR, 0);
1136         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1137
1138         vmcs_write16(GUEST_CS_SELECTOR,
1139                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1140         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1141 }
1142
1143 static gva_t rmode_tss_base(struct kvm *kvm)
1144 {
1145         if (!kvm->arch.tss_addr) {
1146                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1147                                  kvm->memslots[0].npages - 3;
1148                 return base_gfn << PAGE_SHIFT;
1149         }
1150         return kvm->arch.tss_addr;
1151 }
1152
1153 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1154 {
1155         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1156
1157         save->selector = vmcs_read16(sf->selector);
1158         save->base = vmcs_readl(sf->base);
1159         save->limit = vmcs_read32(sf->limit);
1160         save->ar = vmcs_read32(sf->ar_bytes);
1161         vmcs_write16(sf->selector, save->base >> 4);
1162         vmcs_write32(sf->base, save->base & 0xfffff);
1163         vmcs_write32(sf->limit, 0xffff);
1164         vmcs_write32(sf->ar_bytes, 0xf3);
1165 }
1166
1167 static void enter_rmode(struct kvm_vcpu *vcpu)
1168 {
1169         unsigned long flags;
1170
1171         vcpu->arch.rmode.active = 1;
1172
1173         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1174         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1175
1176         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1177         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1178
1179         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1180         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1181
1182         flags = vmcs_readl(GUEST_RFLAGS);
1183         vcpu->arch.rmode.save_iopl
1184                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1185
1186         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1187
1188         vmcs_writel(GUEST_RFLAGS, flags);
1189         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1190         update_exception_bitmap(vcpu);
1191
1192         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1193         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1194         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1195
1196         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1197         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1198         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1199                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1200         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1201
1202         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1203         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1204         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1205         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1206
1207         kvm_mmu_reset_context(vcpu);
1208         init_rmode_tss(vcpu->kvm);
1209 }
1210
1211 #ifdef CONFIG_X86_64
1212
1213 static void enter_lmode(struct kvm_vcpu *vcpu)
1214 {
1215         u32 guest_tr_ar;
1216
1217         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1218         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1219                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1220                        __FUNCTION__);
1221                 vmcs_write32(GUEST_TR_AR_BYTES,
1222                              (guest_tr_ar & ~AR_TYPE_MASK)
1223                              | AR_TYPE_BUSY_64_TSS);
1224         }
1225
1226         vcpu->arch.shadow_efer |= EFER_LMA;
1227
1228         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1229         vmcs_write32(VM_ENTRY_CONTROLS,
1230                      vmcs_read32(VM_ENTRY_CONTROLS)
1231                      | VM_ENTRY_IA32E_MODE);
1232 }
1233
1234 static void exit_lmode(struct kvm_vcpu *vcpu)
1235 {
1236         vcpu->arch.shadow_efer &= ~EFER_LMA;
1237
1238         vmcs_write32(VM_ENTRY_CONTROLS,
1239                      vmcs_read32(VM_ENTRY_CONTROLS)
1240                      & ~VM_ENTRY_IA32E_MODE);
1241 }
1242
1243 #endif
1244
1245 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1246 {
1247         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1248         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1249 }
1250
1251 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1252 {
1253         vmx_fpu_deactivate(vcpu);
1254
1255         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1256                 enter_pmode(vcpu);
1257
1258         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1259                 enter_rmode(vcpu);
1260
1261 #ifdef CONFIG_X86_64
1262         if (vcpu->arch.shadow_efer & EFER_LME) {
1263                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1264                         enter_lmode(vcpu);
1265                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1266                         exit_lmode(vcpu);
1267         }
1268 #endif
1269
1270         vmcs_writel(CR0_READ_SHADOW, cr0);
1271         vmcs_writel(GUEST_CR0,
1272                     (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1273         vcpu->arch.cr0 = cr0;
1274
1275         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1276                 vmx_fpu_activate(vcpu);
1277 }
1278
1279 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1280 {
1281         vmcs_writel(GUEST_CR3, cr3);
1282         if (vcpu->arch.cr0 & X86_CR0_PE)
1283                 vmx_fpu_deactivate(vcpu);
1284 }
1285
1286 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1287 {
1288         vmcs_writel(CR4_READ_SHADOW, cr4);
1289         vmcs_writel(GUEST_CR4, cr4 | (vcpu->arch.rmode.active ?
1290                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1291         vcpu->arch.cr4 = cr4;
1292 }
1293
1294 #ifdef CONFIG_X86_64
1295
1296 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1297 {
1298         struct vcpu_vmx *vmx = to_vmx(vcpu);
1299         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1300
1301         vcpu->arch.shadow_efer = efer;
1302         if (efer & EFER_LMA) {
1303                 vmcs_write32(VM_ENTRY_CONTROLS,
1304                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1305                                      VM_ENTRY_IA32E_MODE);
1306                 msr->data = efer;
1307
1308         } else {
1309                 vmcs_write32(VM_ENTRY_CONTROLS,
1310                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1311                                      ~VM_ENTRY_IA32E_MODE);
1312
1313                 msr->data = efer & ~EFER_LME;
1314         }
1315         setup_msrs(vmx);
1316 }
1317
1318 #endif
1319
1320 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1321 {
1322         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1323
1324         return vmcs_readl(sf->base);
1325 }
1326
1327 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1328                             struct kvm_segment *var, int seg)
1329 {
1330         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1331         u32 ar;
1332
1333         var->base = vmcs_readl(sf->base);
1334         var->limit = vmcs_read32(sf->limit);
1335         var->selector = vmcs_read16(sf->selector);
1336         ar = vmcs_read32(sf->ar_bytes);
1337         if (ar & AR_UNUSABLE_MASK)
1338                 ar = 0;
1339         var->type = ar & 15;
1340         var->s = (ar >> 4) & 1;
1341         var->dpl = (ar >> 5) & 3;
1342         var->present = (ar >> 7) & 1;
1343         var->avl = (ar >> 12) & 1;
1344         var->l = (ar >> 13) & 1;
1345         var->db = (ar >> 14) & 1;
1346         var->g = (ar >> 15) & 1;
1347         var->unusable = (ar >> 16) & 1;
1348 }
1349
1350 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1351 {
1352         u32 ar;
1353
1354         if (var->unusable)
1355                 ar = 1 << 16;
1356         else {
1357                 ar = var->type & 15;
1358                 ar |= (var->s & 1) << 4;
1359                 ar |= (var->dpl & 3) << 5;
1360                 ar |= (var->present & 1) << 7;
1361                 ar |= (var->avl & 1) << 12;
1362                 ar |= (var->l & 1) << 13;
1363                 ar |= (var->db & 1) << 14;
1364                 ar |= (var->g & 1) << 15;
1365         }
1366         if (ar == 0) /* a 0 value means unusable */
1367                 ar = AR_UNUSABLE_MASK;
1368
1369         return ar;
1370 }
1371
1372 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1373                             struct kvm_segment *var, int seg)
1374 {
1375         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1376         u32 ar;
1377
1378         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1379                 vcpu->arch.rmode.tr.selector = var->selector;
1380                 vcpu->arch.rmode.tr.base = var->base;
1381                 vcpu->arch.rmode.tr.limit = var->limit;
1382                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1383                 return;
1384         }
1385         vmcs_writel(sf->base, var->base);
1386         vmcs_write32(sf->limit, var->limit);
1387         vmcs_write16(sf->selector, var->selector);
1388         if (vcpu->arch.rmode.active && var->s) {
1389                 /*
1390                  * Hack real-mode segments into vm86 compatibility.
1391                  */
1392                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1393                         vmcs_writel(sf->base, 0xf0000);
1394                 ar = 0xf3;
1395         } else
1396                 ar = vmx_segment_access_rights(var);
1397         vmcs_write32(sf->ar_bytes, ar);
1398 }
1399
1400 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1401 {
1402         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1403
1404         *db = (ar >> 14) & 1;
1405         *l = (ar >> 13) & 1;
1406 }
1407
1408 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1409 {
1410         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1411         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1412 }
1413
1414 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1415 {
1416         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1417         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1418 }
1419
1420 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1421 {
1422         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1423         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1424 }
1425
1426 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1427 {
1428         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1429         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1430 }
1431
1432 static int init_rmode_tss(struct kvm *kvm)
1433 {
1434         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1435         u16 data = 0;
1436         int ret = 0;
1437         int r;
1438
1439         down_read(&current->mm->mmap_sem);
1440         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1441         if (r < 0)
1442                 goto out;
1443         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1444         r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1445         if (r < 0)
1446                 goto out;
1447         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1448         if (r < 0)
1449                 goto out;
1450         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1451         if (r < 0)
1452                 goto out;
1453         data = ~0;
1454         r = kvm_write_guest_page(kvm, fn, &data,
1455                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1456                                  sizeof(u8));
1457         if (r < 0)
1458                 goto out;
1459
1460         ret = 1;
1461 out:
1462         up_read(&current->mm->mmap_sem);
1463         return ret;
1464 }
1465
1466 static void seg_setup(int seg)
1467 {
1468         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1469
1470         vmcs_write16(sf->selector, 0);
1471         vmcs_writel(sf->base, 0);
1472         vmcs_write32(sf->limit, 0xffff);
1473         vmcs_write32(sf->ar_bytes, 0x93);
1474 }
1475
1476 static int alloc_apic_access_page(struct kvm *kvm)
1477 {
1478         struct kvm_userspace_memory_region kvm_userspace_mem;
1479         int r = 0;
1480
1481         down_write(&kvm->slots_lock);
1482         if (kvm->arch.apic_access_page)
1483                 goto out;
1484         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1485         kvm_userspace_mem.flags = 0;
1486         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1487         kvm_userspace_mem.memory_size = PAGE_SIZE;
1488         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1489         if (r)
1490                 goto out;
1491
1492         down_read(&current->mm->mmap_sem);
1493         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
1494         up_read(&current->mm->mmap_sem);
1495 out:
1496         up_write(&kvm->slots_lock);
1497         return r;
1498 }
1499
1500 /*
1501  * Sets up the vmcs for emulated real mode.
1502  */
1503 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1504 {
1505         u32 host_sysenter_cs;
1506         u32 junk;
1507         unsigned long a;
1508         struct descriptor_table dt;
1509         int i;
1510         unsigned long kvm_vmx_return;
1511         u32 exec_control;
1512
1513         /* I/O */
1514         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1515         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1516
1517         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1518
1519         /* Control */
1520         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1521                 vmcs_config.pin_based_exec_ctrl);
1522
1523         exec_control = vmcs_config.cpu_based_exec_ctrl;
1524         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1525                 exec_control &= ~CPU_BASED_TPR_SHADOW;
1526 #ifdef CONFIG_X86_64
1527                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1528                                 CPU_BASED_CR8_LOAD_EXITING;
1529 #endif
1530         }
1531         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1532
1533         if (cpu_has_secondary_exec_ctrls()) {
1534                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1535                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1536                         exec_control &=
1537                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1538                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1539         }
1540
1541         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1542         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1543         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
1544
1545         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
1546         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
1547         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
1548
1549         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
1550         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1551         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1552         vmcs_write16(HOST_FS_SELECTOR, read_fs());    /* 22.2.4 */
1553         vmcs_write16(HOST_GS_SELECTOR, read_gs());    /* 22.2.4 */
1554         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1555 #ifdef CONFIG_X86_64
1556         rdmsrl(MSR_FS_BASE, a);
1557         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1558         rdmsrl(MSR_GS_BASE, a);
1559         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1560 #else
1561         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1562         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1563 #endif
1564
1565         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
1566
1567         get_idt(&dt);
1568         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
1569
1570         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1571         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1572         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1573         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1574         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1575
1576         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1577         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1578         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1579         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
1580         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1581         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
1582
1583         for (i = 0; i < NR_VMX_MSR; ++i) {
1584                 u32 index = vmx_msr_index[i];
1585                 u32 data_low, data_high;
1586                 u64 data;
1587                 int j = vmx->nmsrs;
1588
1589                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1590                         continue;
1591                 if (wrmsr_safe(index, data_low, data_high) < 0)
1592                         continue;
1593                 data = data_low | ((u64)data_high << 32);
1594                 vmx->host_msrs[j].index = index;
1595                 vmx->host_msrs[j].reserved = 0;
1596                 vmx->host_msrs[j].data = data;
1597                 vmx->guest_msrs[j] = vmx->host_msrs[j];
1598                 ++vmx->nmsrs;
1599         }
1600
1601         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1602
1603         /* 22.2.1, 20.8.1 */
1604         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1605
1606         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1607         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1608
1609
1610         return 0;
1611 }
1612
1613 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1614 {
1615         struct vcpu_vmx *vmx = to_vmx(vcpu);
1616         u64 msr;
1617         int ret;
1618
1619         if (!init_rmode_tss(vmx->vcpu.kvm)) {
1620                 ret = -ENOMEM;
1621                 goto out;
1622         }
1623
1624         vmx->vcpu.arch.rmode.active = 0;
1625
1626         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1627         set_cr8(&vmx->vcpu, 0);
1628         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1629         if (vmx->vcpu.vcpu_id == 0)
1630                 msr |= MSR_IA32_APICBASE_BSP;
1631         kvm_set_apic_base(&vmx->vcpu, msr);
1632
1633         fx_init(&vmx->vcpu);
1634
1635         /*
1636          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1637          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
1638          */
1639         if (vmx->vcpu.vcpu_id == 0) {
1640                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1641                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1642         } else {
1643                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
1644                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
1645         }
1646         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1647         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1648
1649         seg_setup(VCPU_SREG_DS);
1650         seg_setup(VCPU_SREG_ES);
1651         seg_setup(VCPU_SREG_FS);
1652         seg_setup(VCPU_SREG_GS);
1653         seg_setup(VCPU_SREG_SS);
1654
1655         vmcs_write16(GUEST_TR_SELECTOR, 0);
1656         vmcs_writel(GUEST_TR_BASE, 0);
1657         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1658         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1659
1660         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1661         vmcs_writel(GUEST_LDTR_BASE, 0);
1662         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1663         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1664
1665         vmcs_write32(GUEST_SYSENTER_CS, 0);
1666         vmcs_writel(GUEST_SYSENTER_ESP, 0);
1667         vmcs_writel(GUEST_SYSENTER_EIP, 0);
1668
1669         vmcs_writel(GUEST_RFLAGS, 0x02);
1670         if (vmx->vcpu.vcpu_id == 0)
1671                 vmcs_writel(GUEST_RIP, 0xfff0);
1672         else
1673                 vmcs_writel(GUEST_RIP, 0);
1674         vmcs_writel(GUEST_RSP, 0);
1675
1676         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1677         vmcs_writel(GUEST_DR7, 0x400);
1678
1679         vmcs_writel(GUEST_GDTR_BASE, 0);
1680         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1681
1682         vmcs_writel(GUEST_IDTR_BASE, 0);
1683         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1684
1685         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1686         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1687         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1688
1689         guest_write_tsc(0);
1690
1691         /* Special registers */
1692         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1693
1694         setup_msrs(vmx);
1695
1696         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
1697
1698         if (cpu_has_vmx_tpr_shadow()) {
1699                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1700                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1701                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1702                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
1703                 vmcs_write32(TPR_THRESHOLD, 0);
1704         }
1705
1706         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1707                 vmcs_write64(APIC_ACCESS_ADDR,
1708                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
1709
1710         vmx->vcpu.arch.cr0 = 0x60000010;
1711         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
1712         vmx_set_cr4(&vmx->vcpu, 0);
1713 #ifdef CONFIG_X86_64
1714         vmx_set_efer(&vmx->vcpu, 0);
1715 #endif
1716         vmx_fpu_activate(&vmx->vcpu);
1717         update_exception_bitmap(&vmx->vcpu);
1718
1719         return 0;
1720
1721 out:
1722         return ret;
1723 }
1724
1725 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1726 {
1727         struct vcpu_vmx *vmx = to_vmx(vcpu);
1728
1729         if (vcpu->arch.rmode.active) {
1730                 vmx->rmode.irq.pending = true;
1731                 vmx->rmode.irq.vector = irq;
1732                 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
1733                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1734                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1735                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1736                 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
1737                 return;
1738         }
1739         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1740                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1741 }
1742
1743 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1744 {
1745         int word_index = __ffs(vcpu->arch.irq_summary);
1746         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1747         int irq = word_index * BITS_PER_LONG + bit_index;
1748
1749         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1750         if (!vcpu->arch.irq_pending[word_index])
1751                 clear_bit(word_index, &vcpu->arch.irq_summary);
1752         vmx_inject_irq(vcpu, irq);
1753 }
1754
1755
1756 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1757                                        struct kvm_run *kvm_run)
1758 {
1759         u32 cpu_based_vm_exec_control;
1760
1761         vcpu->arch.interrupt_window_open =
1762                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1763                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1764
1765         if (vcpu->arch.interrupt_window_open &&
1766             vcpu->arch.irq_summary &&
1767             !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1768                 /*
1769                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1770                  */
1771                 kvm_do_inject_irq(vcpu);
1772
1773         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1774         if (!vcpu->arch.interrupt_window_open &&
1775             (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
1776                 /*
1777                  * Interrupts blocked.  Wait for unblock.
1778                  */
1779                 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1780         else
1781                 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1782         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1783 }
1784
1785 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1786 {
1787         int ret;
1788         struct kvm_userspace_memory_region tss_mem = {
1789                 .slot = 8,
1790                 .guest_phys_addr = addr,
1791                 .memory_size = PAGE_SIZE * 3,
1792                 .flags = 0,
1793         };
1794
1795         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1796         if (ret)
1797                 return ret;
1798         kvm->arch.tss_addr = addr;
1799         return 0;
1800 }
1801
1802 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1803 {
1804         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1805
1806         set_debugreg(dbg->bp[0], 0);
1807         set_debugreg(dbg->bp[1], 1);
1808         set_debugreg(dbg->bp[2], 2);
1809         set_debugreg(dbg->bp[3], 3);
1810
1811         if (dbg->singlestep) {
1812                 unsigned long flags;
1813
1814                 flags = vmcs_readl(GUEST_RFLAGS);
1815                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1816                 vmcs_writel(GUEST_RFLAGS, flags);
1817         }
1818 }
1819
1820 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1821                                   int vec, u32 err_code)
1822 {
1823         if (!vcpu->arch.rmode.active)
1824                 return 0;
1825
1826         /*
1827          * Instruction with address size override prefix opcode 0x67
1828          * Cause the #SS fault with 0 error code in VM86 mode.
1829          */
1830         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1831                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
1832                         return 1;
1833         return 0;
1834 }
1835
1836 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1837 {
1838         struct vcpu_vmx *vmx = to_vmx(vcpu);
1839         u32 intr_info, error_code;
1840         unsigned long cr2, rip;
1841         u32 vect_info;
1842         enum emulation_result er;
1843
1844         vect_info = vmx->idt_vectoring_info;
1845         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1846
1847         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1848                                                 !is_page_fault(intr_info))
1849                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1850                        "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1851
1852         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1853                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1854                 set_bit(irq, vcpu->arch.irq_pending);
1855                 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
1856         }
1857
1858         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1859                 return 1;  /* already handled by vmx_vcpu_run() */
1860
1861         if (is_no_device(intr_info)) {
1862                 vmx_fpu_activate(vcpu);
1863                 return 1;
1864         }
1865
1866         if (is_invalid_opcode(intr_info)) {
1867                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1868                 if (er != EMULATE_DONE)
1869                         kvm_queue_exception(vcpu, UD_VECTOR);
1870                 return 1;
1871         }
1872
1873         error_code = 0;
1874         rip = vmcs_readl(GUEST_RIP);
1875         if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1876                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1877         if (is_page_fault(intr_info)) {
1878                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1879                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
1880         }
1881
1882         if (vcpu->arch.rmode.active &&
1883             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1884                                                                 error_code)) {
1885                 if (vcpu->arch.halt_request) {
1886                         vcpu->arch.halt_request = 0;
1887                         return kvm_emulate_halt(vcpu);
1888                 }
1889                 return 1;
1890         }
1891
1892         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1893             (INTR_TYPE_EXCEPTION | 1)) {
1894                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1895                 return 0;
1896         }
1897         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1898         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1899         kvm_run->ex.error_code = error_code;
1900         return 0;
1901 }
1902
1903 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1904                                      struct kvm_run *kvm_run)
1905 {
1906         ++vcpu->stat.irq_exits;
1907         return 1;
1908 }
1909
1910 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1911 {
1912         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1913         return 0;
1914 }
1915
1916 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1917 {
1918         unsigned long exit_qualification;
1919         int size, down, in, string, rep;
1920         unsigned port;
1921
1922         ++vcpu->stat.io_exits;
1923         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1924         string = (exit_qualification & 16) != 0;
1925
1926         if (string) {
1927                 if (emulate_instruction(vcpu,
1928                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1929                         return 0;
1930                 return 1;
1931         }
1932
1933         size = (exit_qualification & 7) + 1;
1934         in = (exit_qualification & 8) != 0;
1935         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1936         rep = (exit_qualification & 32) != 0;
1937         port = exit_qualification >> 16;
1938
1939         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
1940 }
1941
1942 static void
1943 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1944 {
1945         /*
1946          * Patch in the VMCALL instruction:
1947          */
1948         hypercall[0] = 0x0f;
1949         hypercall[1] = 0x01;
1950         hypercall[2] = 0xc1;
1951 }
1952
1953 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1954 {
1955         unsigned long exit_qualification;
1956         int cr;
1957         int reg;
1958
1959         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1960         cr = exit_qualification & 15;
1961         reg = (exit_qualification >> 8) & 15;
1962         switch ((exit_qualification >> 4) & 3) {
1963         case 0: /* mov to cr */
1964                 switch (cr) {
1965                 case 0:
1966                         vcpu_load_rsp_rip(vcpu);
1967                         set_cr0(vcpu, vcpu->arch.regs[reg]);
1968                         skip_emulated_instruction(vcpu);
1969                         return 1;
1970                 case 3:
1971                         vcpu_load_rsp_rip(vcpu);
1972                         set_cr3(vcpu, vcpu->arch.regs[reg]);
1973                         skip_emulated_instruction(vcpu);
1974                         return 1;
1975                 case 4:
1976                         vcpu_load_rsp_rip(vcpu);
1977                         set_cr4(vcpu, vcpu->arch.regs[reg]);
1978                         skip_emulated_instruction(vcpu);
1979                         return 1;
1980                 case 8:
1981                         vcpu_load_rsp_rip(vcpu);
1982                         set_cr8(vcpu, vcpu->arch.regs[reg]);
1983                         skip_emulated_instruction(vcpu);
1984                         if (irqchip_in_kernel(vcpu->kvm))
1985                                 return 1;
1986                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1987                         return 0;
1988                 };
1989                 break;
1990         case 2: /* clts */
1991                 vcpu_load_rsp_rip(vcpu);
1992                 vmx_fpu_deactivate(vcpu);
1993                 vcpu->arch.cr0 &= ~X86_CR0_TS;
1994                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1995                 vmx_fpu_activate(vcpu);
1996                 skip_emulated_instruction(vcpu);
1997                 return 1;
1998         case 1: /*mov from cr*/
1999                 switch (cr) {
2000                 case 3:
2001                         vcpu_load_rsp_rip(vcpu);
2002                         vcpu->arch.regs[reg] = vcpu->arch.cr3;
2003                         vcpu_put_rsp_rip(vcpu);
2004                         skip_emulated_instruction(vcpu);
2005                         return 1;
2006                 case 8:
2007                         vcpu_load_rsp_rip(vcpu);
2008                         vcpu->arch.regs[reg] = get_cr8(vcpu);
2009                         vcpu_put_rsp_rip(vcpu);
2010                         skip_emulated_instruction(vcpu);
2011                         return 1;
2012                 }
2013                 break;
2014         case 3: /* lmsw */
2015                 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2016
2017                 skip_emulated_instruction(vcpu);
2018                 return 1;
2019         default:
2020                 break;
2021         }
2022         kvm_run->exit_reason = 0;
2023         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2024                (int)(exit_qualification >> 4) & 3, cr);
2025         return 0;
2026 }
2027
2028 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2029 {
2030         unsigned long exit_qualification;
2031         unsigned long val;
2032         int dr, reg;
2033
2034         /*
2035          * FIXME: this code assumes the host is debugging the guest.
2036          *        need to deal with guest debugging itself too.
2037          */
2038         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2039         dr = exit_qualification & 7;
2040         reg = (exit_qualification >> 8) & 15;
2041         vcpu_load_rsp_rip(vcpu);
2042         if (exit_qualification & 16) {
2043                 /* mov from dr */
2044                 switch (dr) {
2045                 case 6:
2046                         val = 0xffff0ff0;
2047                         break;
2048                 case 7:
2049                         val = 0x400;
2050                         break;
2051                 default:
2052                         val = 0;
2053                 }
2054                 vcpu->arch.regs[reg] = val;
2055         } else {
2056                 /* mov to dr */
2057         }
2058         vcpu_put_rsp_rip(vcpu);
2059         skip_emulated_instruction(vcpu);
2060         return 1;
2061 }
2062
2063 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2064 {
2065         kvm_emulate_cpuid(vcpu);
2066         return 1;
2067 }
2068
2069 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2070 {
2071         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2072         u64 data;
2073
2074         if (vmx_get_msr(vcpu, ecx, &data)) {
2075                 kvm_inject_gp(vcpu, 0);
2076                 return 1;
2077         }
2078
2079         /* FIXME: handling of bits 32:63 of rax, rdx */
2080         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2081         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2082         skip_emulated_instruction(vcpu);
2083         return 1;
2084 }
2085
2086 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2087 {
2088         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2089         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2090                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2091
2092         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2093                 kvm_inject_gp(vcpu, 0);
2094                 return 1;
2095         }
2096
2097         skip_emulated_instruction(vcpu);
2098         return 1;
2099 }
2100
2101 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2102                                       struct kvm_run *kvm_run)
2103 {
2104         return 1;
2105 }
2106
2107 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2108                                    struct kvm_run *kvm_run)
2109 {
2110         u32 cpu_based_vm_exec_control;
2111
2112         /* clear pending irq */
2113         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2114         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2115         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2116         /*
2117          * If the user space waits to inject interrupts, exit as soon as
2118          * possible
2119          */
2120         if (kvm_run->request_interrupt_window &&
2121             !vcpu->arch.irq_summary) {
2122                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2123                 ++vcpu->stat.irq_window_exits;
2124                 return 0;
2125         }
2126         return 1;
2127 }
2128
2129 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2130 {
2131         skip_emulated_instruction(vcpu);
2132         return kvm_emulate_halt(vcpu);
2133 }
2134
2135 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2136 {
2137         skip_emulated_instruction(vcpu);
2138         kvm_emulate_hypercall(vcpu);
2139         return 1;
2140 }
2141
2142 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2143 {
2144         skip_emulated_instruction(vcpu);
2145         /* TODO: Add support for VT-d/pass-through device */
2146         return 1;
2147 }
2148
2149 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2150 {
2151         u64 exit_qualification;
2152         enum emulation_result er;
2153         unsigned long offset;
2154
2155         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2156         offset = exit_qualification & 0xffful;
2157
2158         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2159
2160         if (er !=  EMULATE_DONE) {
2161                 printk(KERN_ERR
2162                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2163                        offset);
2164                 return -ENOTSUPP;
2165         }
2166         return 1;
2167 }
2168
2169 /*
2170  * The exit handlers return 1 if the exit was handled fully and guest execution
2171  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
2172  * to be done to userspace and return 0.
2173  */
2174 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2175                                       struct kvm_run *kvm_run) = {
2176         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
2177         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
2178         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
2179         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
2180         [EXIT_REASON_CR_ACCESS]               = handle_cr,
2181         [EXIT_REASON_DR_ACCESS]               = handle_dr,
2182         [EXIT_REASON_CPUID]                   = handle_cpuid,
2183         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
2184         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
2185         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
2186         [EXIT_REASON_HLT]                     = handle_halt,
2187         [EXIT_REASON_VMCALL]                  = handle_vmcall,
2188         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
2189         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
2190         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
2191 };
2192
2193 static const int kvm_vmx_max_exit_handlers =
2194         ARRAY_SIZE(kvm_vmx_exit_handlers);
2195
2196 /*
2197  * The guest has exited.  See if we can fix it or if we need userspace
2198  * assistance.
2199  */
2200 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2201 {
2202         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2203         struct vcpu_vmx *vmx = to_vmx(vcpu);
2204         u32 vectoring_info = vmx->idt_vectoring_info;
2205
2206         if (unlikely(vmx->fail)) {
2207                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2208                 kvm_run->fail_entry.hardware_entry_failure_reason
2209                         = vmcs_read32(VM_INSTRUCTION_ERROR);
2210                 return 0;
2211         }
2212
2213         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2214                                 exit_reason != EXIT_REASON_EXCEPTION_NMI)
2215                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2216                        "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
2217         if (exit_reason < kvm_vmx_max_exit_handlers
2218             && kvm_vmx_exit_handlers[exit_reason])
2219                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2220         else {
2221                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2222                 kvm_run->hw.hardware_exit_reason = exit_reason;
2223         }
2224         return 0;
2225 }
2226
2227 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2228 {
2229 }
2230
2231 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2232 {
2233         int max_irr, tpr;
2234
2235         if (!vm_need_tpr_shadow(vcpu->kvm))
2236                 return;
2237
2238         if (!kvm_lapic_enabled(vcpu) ||
2239             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2240                 vmcs_write32(TPR_THRESHOLD, 0);
2241                 return;
2242         }
2243
2244         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2245         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2246 }
2247
2248 static void enable_irq_window(struct kvm_vcpu *vcpu)
2249 {
2250         u32 cpu_based_vm_exec_control;
2251
2252         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2253         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2254         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2255 }
2256
2257 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2258 {
2259         struct vcpu_vmx *vmx = to_vmx(vcpu);
2260         u32 idtv_info_field, intr_info_field;
2261         int has_ext_irq, interrupt_window_open;
2262         int vector;
2263
2264         update_tpr_threshold(vcpu);
2265
2266         has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2267         intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2268         idtv_info_field = vmx->idt_vectoring_info;
2269         if (intr_info_field & INTR_INFO_VALID_MASK) {
2270                 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2271                         /* TODO: fault when IDT_Vectoring */
2272                         if (printk_ratelimit())
2273                                 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2274                 }
2275                 if (has_ext_irq)
2276                         enable_irq_window(vcpu);
2277                 return;
2278         }
2279         if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2280                 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2281                     == INTR_TYPE_EXT_INTR
2282                     && vcpu->arch.rmode.active) {
2283                         u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2284
2285                         vmx_inject_irq(vcpu, vect);
2286                         if (unlikely(has_ext_irq))
2287                                 enable_irq_window(vcpu);
2288                         return;
2289                 }
2290
2291                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2292                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2293                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2294
2295                 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2296                         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2297                                 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2298                 if (unlikely(has_ext_irq))
2299                         enable_irq_window(vcpu);
2300                 return;
2301         }
2302         if (!has_ext_irq)
2303                 return;
2304         interrupt_window_open =
2305                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2306                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2307         if (interrupt_window_open) {
2308                 vector = kvm_cpu_get_interrupt(vcpu);
2309                 vmx_inject_irq(vcpu, vector);
2310                 kvm_timer_intr_post(vcpu, vector);
2311         } else
2312                 enable_irq_window(vcpu);
2313 }
2314
2315 /*
2316  * Failure to inject an interrupt should give us the information
2317  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
2318  * when fetching the interrupt redirection bitmap in the real-mode
2319  * tss, this doesn't happen.  So we do it ourselves.
2320  */
2321 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2322 {
2323         vmx->rmode.irq.pending = 0;
2324         if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2325                 return;
2326         vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2327         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2328                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2329                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2330                 return;
2331         }
2332         vmx->idt_vectoring_info =
2333                 VECTORING_INFO_VALID_MASK
2334                 | INTR_TYPE_EXT_INTR
2335                 | vmx->rmode.irq.vector;
2336 }
2337
2338 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2339 {
2340         struct vcpu_vmx *vmx = to_vmx(vcpu);
2341         u32 intr_info;
2342
2343         /*
2344          * Loading guest fpu may have cleared host cr0.ts
2345          */
2346         vmcs_writel(HOST_CR0, read_cr0());
2347
2348         asm(
2349                 /* Store host registers */
2350 #ifdef CONFIG_X86_64
2351                 "push %%rdx; push %%rbp;"
2352                 "push %%rcx \n\t"
2353 #else
2354                 "push %%edx; push %%ebp;"
2355                 "push %%ecx \n\t"
2356 #endif
2357                 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2358                 /* Check if vmlaunch of vmresume is needed */
2359                 "cmpl $0, %c[launched](%0) \n\t"
2360                 /* Load guest registers.  Don't clobber flags. */
2361 #ifdef CONFIG_X86_64
2362                 "mov %c[cr2](%0), %%rax \n\t"
2363                 "mov %%rax, %%cr2 \n\t"
2364                 "mov %c[rax](%0), %%rax \n\t"
2365                 "mov %c[rbx](%0), %%rbx \n\t"
2366                 "mov %c[rdx](%0), %%rdx \n\t"
2367                 "mov %c[rsi](%0), %%rsi \n\t"
2368                 "mov %c[rdi](%0), %%rdi \n\t"
2369                 "mov %c[rbp](%0), %%rbp \n\t"
2370                 "mov %c[r8](%0),  %%r8  \n\t"
2371                 "mov %c[r9](%0),  %%r9  \n\t"
2372                 "mov %c[r10](%0), %%r10 \n\t"
2373                 "mov %c[r11](%0), %%r11 \n\t"
2374                 "mov %c[r12](%0), %%r12 \n\t"
2375                 "mov %c[r13](%0), %%r13 \n\t"
2376                 "mov %c[r14](%0), %%r14 \n\t"
2377                 "mov %c[r15](%0), %%r15 \n\t"
2378                 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2379 #else
2380                 "mov %c[cr2](%0), %%eax \n\t"
2381                 "mov %%eax,   %%cr2 \n\t"
2382                 "mov %c[rax](%0), %%eax \n\t"
2383                 "mov %c[rbx](%0), %%ebx \n\t"
2384                 "mov %c[rdx](%0), %%edx \n\t"
2385                 "mov %c[rsi](%0), %%esi \n\t"
2386                 "mov %c[rdi](%0), %%edi \n\t"
2387                 "mov %c[rbp](%0), %%ebp \n\t"
2388                 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2389 #endif
2390                 /* Enter guest mode */
2391                 "jne .Llaunched \n\t"
2392                 ASM_VMX_VMLAUNCH "\n\t"
2393                 "jmp .Lkvm_vmx_return \n\t"
2394                 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2395                 ".Lkvm_vmx_return: "
2396                 /* Save guest registers, load host registers, keep flags */
2397 #ifdef CONFIG_X86_64
2398                 "xchg %0,     (%%rsp) \n\t"
2399                 "mov %%rax, %c[rax](%0) \n\t"
2400                 "mov %%rbx, %c[rbx](%0) \n\t"
2401                 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2402                 "mov %%rdx, %c[rdx](%0) \n\t"
2403                 "mov %%rsi, %c[rsi](%0) \n\t"
2404                 "mov %%rdi, %c[rdi](%0) \n\t"
2405                 "mov %%rbp, %c[rbp](%0) \n\t"
2406                 "mov %%r8,  %c[r8](%0) \n\t"
2407                 "mov %%r9,  %c[r9](%0) \n\t"
2408                 "mov %%r10, %c[r10](%0) \n\t"
2409                 "mov %%r11, %c[r11](%0) \n\t"
2410                 "mov %%r12, %c[r12](%0) \n\t"
2411                 "mov %%r13, %c[r13](%0) \n\t"
2412                 "mov %%r14, %c[r14](%0) \n\t"
2413                 "mov %%r15, %c[r15](%0) \n\t"
2414                 "mov %%cr2, %%rax   \n\t"
2415                 "mov %%rax, %c[cr2](%0) \n\t"
2416
2417                 "pop  %%rbp; pop  %%rbp; pop  %%rdx \n\t"
2418 #else
2419                 "xchg %0, (%%esp) \n\t"
2420                 "mov %%eax, %c[rax](%0) \n\t"
2421                 "mov %%ebx, %c[rbx](%0) \n\t"
2422                 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2423                 "mov %%edx, %c[rdx](%0) \n\t"
2424                 "mov %%esi, %c[rsi](%0) \n\t"
2425                 "mov %%edi, %c[rdi](%0) \n\t"
2426                 "mov %%ebp, %c[rbp](%0) \n\t"
2427                 "mov %%cr2, %%eax  \n\t"
2428                 "mov %%eax, %c[cr2](%0) \n\t"
2429
2430                 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
2431 #endif
2432                 "setbe %c[fail](%0) \n\t"
2433               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2434                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2435                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
2436                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
2437                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
2438                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
2439                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
2440                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
2441                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
2442                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
2443 #ifdef CONFIG_X86_64
2444                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
2445                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
2446                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
2447                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
2448                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
2449                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
2450                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
2451                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
2452 #endif
2453                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
2454               : "cc", "memory"
2455 #ifdef CONFIG_X86_64
2456                 , "rbx", "rdi", "rsi"
2457                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2458 #else
2459                 , "ebx", "edi", "rsi"
2460 #endif
2461               );
2462
2463         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2464         if (vmx->rmode.irq.pending)
2465                 fixup_rmode_irq(vmx);
2466
2467         vcpu->arch.interrupt_window_open =
2468                 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2469
2470         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2471         vmx->launched = 1;
2472
2473         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2474
2475         /* We need to handle NMIs before interrupts are enabled */
2476         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2477                 asm("int $2");
2478 }
2479
2480 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2481 {
2482         struct vcpu_vmx *vmx = to_vmx(vcpu);
2483
2484         if (vmx->vmcs) {
2485                 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2486                 free_vmcs(vmx->vmcs);
2487                 vmx->vmcs = NULL;
2488         }
2489 }
2490
2491 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2492 {
2493         struct vcpu_vmx *vmx = to_vmx(vcpu);
2494
2495         vmx_free_vmcs(vcpu);
2496         kfree(vmx->host_msrs);
2497         kfree(vmx->guest_msrs);
2498         kvm_vcpu_uninit(vcpu);
2499         kmem_cache_free(kvm_vcpu_cache, vmx);
2500 }
2501
2502 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2503 {
2504         int err;
2505         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2506         int cpu;
2507
2508         if (!vmx)
2509                 return ERR_PTR(-ENOMEM);
2510
2511         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2512         if (err)
2513                 goto free_vcpu;
2514
2515         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2516         if (!vmx->guest_msrs) {
2517                 err = -ENOMEM;
2518                 goto uninit_vcpu;
2519         }
2520
2521         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2522         if (!vmx->host_msrs)
2523                 goto free_guest_msrs;
2524
2525         vmx->vmcs = alloc_vmcs();
2526         if (!vmx->vmcs)
2527                 goto free_msrs;
2528
2529         vmcs_clear(vmx->vmcs);
2530
2531         cpu = get_cpu();
2532         vmx_vcpu_load(&vmx->vcpu, cpu);
2533         err = vmx_vcpu_setup(vmx);
2534         vmx_vcpu_put(&vmx->vcpu);
2535         put_cpu();
2536         if (err)
2537                 goto free_vmcs;
2538         if (vm_need_virtualize_apic_accesses(kvm))
2539                 if (alloc_apic_access_page(kvm) != 0)
2540                         goto free_vmcs;
2541
2542         return &vmx->vcpu;
2543
2544 free_vmcs:
2545         free_vmcs(vmx->vmcs);
2546 free_msrs:
2547         kfree(vmx->host_msrs);
2548 free_guest_msrs:
2549         kfree(vmx->guest_msrs);
2550 uninit_vcpu:
2551         kvm_vcpu_uninit(&vmx->vcpu);
2552 free_vcpu:
2553         kmem_cache_free(kvm_vcpu_cache, vmx);
2554         return ERR_PTR(err);
2555 }
2556
2557 static void __init vmx_check_processor_compat(void *rtn)
2558 {
2559         struct vmcs_config vmcs_conf;
2560
2561         *(int *)rtn = 0;
2562         if (setup_vmcs_config(&vmcs_conf) < 0)
2563                 *(int *)rtn = -EIO;
2564         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2565                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2566                                 smp_processor_id());
2567                 *(int *)rtn = -EIO;
2568         }
2569 }
2570
2571 static struct kvm_x86_ops vmx_x86_ops = {
2572         .cpu_has_kvm_support = cpu_has_kvm_support,
2573         .disabled_by_bios = vmx_disabled_by_bios,
2574         .hardware_setup = hardware_setup,
2575         .hardware_unsetup = hardware_unsetup,
2576         .check_processor_compatibility = vmx_check_processor_compat,
2577         .hardware_enable = hardware_enable,
2578         .hardware_disable = hardware_disable,
2579         .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
2580
2581         .vcpu_create = vmx_create_vcpu,
2582         .vcpu_free = vmx_free_vcpu,
2583         .vcpu_reset = vmx_vcpu_reset,
2584
2585         .prepare_guest_switch = vmx_save_host_state,
2586         .vcpu_load = vmx_vcpu_load,
2587         .vcpu_put = vmx_vcpu_put,
2588         .vcpu_decache = vmx_vcpu_decache,
2589
2590         .set_guest_debug = set_guest_debug,
2591         .guest_debug_pre = kvm_guest_debug_pre,
2592         .get_msr = vmx_get_msr,
2593         .set_msr = vmx_set_msr,
2594         .get_segment_base = vmx_get_segment_base,
2595         .get_segment = vmx_get_segment,
2596         .set_segment = vmx_set_segment,
2597         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2598         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2599         .set_cr0 = vmx_set_cr0,
2600         .set_cr3 = vmx_set_cr3,
2601         .set_cr4 = vmx_set_cr4,
2602 #ifdef CONFIG_X86_64
2603         .set_efer = vmx_set_efer,
2604 #endif
2605         .get_idt = vmx_get_idt,
2606         .set_idt = vmx_set_idt,
2607         .get_gdt = vmx_get_gdt,
2608         .set_gdt = vmx_set_gdt,
2609         .cache_regs = vcpu_load_rsp_rip,
2610         .decache_regs = vcpu_put_rsp_rip,
2611         .get_rflags = vmx_get_rflags,
2612         .set_rflags = vmx_set_rflags,
2613
2614         .tlb_flush = vmx_flush_tlb,
2615
2616         .run = vmx_vcpu_run,
2617         .handle_exit = kvm_handle_exit,
2618         .skip_emulated_instruction = skip_emulated_instruction,
2619         .patch_hypercall = vmx_patch_hypercall,
2620         .get_irq = vmx_get_irq,
2621         .set_irq = vmx_inject_irq,
2622         .queue_exception = vmx_queue_exception,
2623         .exception_injected = vmx_exception_injected,
2624         .inject_pending_irq = vmx_intr_assist,
2625         .inject_pending_vectors = do_interrupt_requests,
2626
2627         .set_tss_addr = vmx_set_tss_addr,
2628 };
2629
2630 static int __init vmx_init(void)
2631 {
2632         void *iova;
2633         int r;
2634
2635         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2636         if (!vmx_io_bitmap_a)
2637                 return -ENOMEM;
2638
2639         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2640         if (!vmx_io_bitmap_b) {
2641                 r = -ENOMEM;
2642                 goto out;
2643         }
2644
2645         /*
2646          * Allow direct access to the PC debug port (it is often used for I/O
2647          * delays, but the vmexits simply slow things down).
2648          */
2649         iova = kmap(vmx_io_bitmap_a);
2650         memset(iova, 0xff, PAGE_SIZE);
2651         clear_bit(0x80, iova);
2652         kunmap(vmx_io_bitmap_a);
2653
2654         iova = kmap(vmx_io_bitmap_b);
2655         memset(iova, 0xff, PAGE_SIZE);
2656         kunmap(vmx_io_bitmap_b);
2657
2658         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2659         if (r)
2660                 goto out1;
2661
2662         if (bypass_guest_pf)
2663                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2664
2665         return 0;
2666
2667 out1:
2668         __free_page(vmx_io_bitmap_b);
2669 out:
2670         __free_page(vmx_io_bitmap_a);
2671         return r;
2672 }
2673
2674 static void __exit vmx_exit(void)
2675 {
2676         __free_page(vmx_io_bitmap_b);
2677         __free_page(vmx_io_bitmap_a);
2678
2679         kvm_exit();
2680 }
2681
2682 module_init(vmx_init)
2683 module_exit(vmx_exit)