KVM: VMX: Enable Virtual Processor Identification (VPID)
[linux-2.6.git] / arch / x86 / kvm / vmx.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  *
9  * Authors:
10  *   Avi Kivity   <avi@qumranet.com>
11  *   Yaniv Kamay  <yaniv@qumranet.com>
12  *
13  * This work is licensed under the terms of the GNU GPL, version 2.  See
14  * the COPYING file in the top-level directory.
15  *
16  */
17
18 #include "irq.h"
19 #include "vmx.h"
20 #include "segment_descriptor.h"
21 #include "mmu.h"
22
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/mm.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30
31 #include <asm/io.h>
32 #include <asm/desc.h>
33
34 MODULE_AUTHOR("Qumranet");
35 MODULE_LICENSE("GPL");
36
37 static int bypass_guest_pf = 1;
38 module_param(bypass_guest_pf, bool, 0);
39
40 static int enable_vpid = 1;
41 module_param(enable_vpid, bool, 0);
42
43 struct vmcs {
44         u32 revision_id;
45         u32 abort;
46         char data[0];
47 };
48
49 struct vcpu_vmx {
50         struct kvm_vcpu       vcpu;
51         int                   launched;
52         u8                    fail;
53         u32                   idt_vectoring_info;
54         struct kvm_msr_entry *guest_msrs;
55         struct kvm_msr_entry *host_msrs;
56         int                   nmsrs;
57         int                   save_nmsrs;
58         int                   msr_offset_efer;
59 #ifdef CONFIG_X86_64
60         int                   msr_offset_kernel_gs_base;
61 #endif
62         struct vmcs          *vmcs;
63         struct {
64                 int           loaded;
65                 u16           fs_sel, gs_sel, ldt_sel;
66                 int           gs_ldt_reload_needed;
67                 int           fs_reload_needed;
68                 int           guest_efer_loaded;
69         } host_state;
70         struct {
71                 struct {
72                         bool pending;
73                         u8 vector;
74                         unsigned rip;
75                 } irq;
76         } rmode;
77         int vpid;
78 };
79
80 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
81 {
82         return container_of(vcpu, struct vcpu_vmx, vcpu);
83 }
84
85 static int init_rmode_tss(struct kvm *kvm);
86
87 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
88 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
89
90 static struct page *vmx_io_bitmap_a;
91 static struct page *vmx_io_bitmap_b;
92
93 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
94 static DEFINE_SPINLOCK(vmx_vpid_lock);
95
96 static struct vmcs_config {
97         int size;
98         int order;
99         u32 revision_id;
100         u32 pin_based_exec_ctrl;
101         u32 cpu_based_exec_ctrl;
102         u32 cpu_based_2nd_exec_ctrl;
103         u32 vmexit_ctrl;
104         u32 vmentry_ctrl;
105 } vmcs_config;
106
107 #define VMX_SEGMENT_FIELD(seg)                                  \
108         [VCPU_SREG_##seg] = {                                   \
109                 .selector = GUEST_##seg##_SELECTOR,             \
110                 .base = GUEST_##seg##_BASE,                     \
111                 .limit = GUEST_##seg##_LIMIT,                   \
112                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
113         }
114
115 static struct kvm_vmx_segment_field {
116         unsigned selector;
117         unsigned base;
118         unsigned limit;
119         unsigned ar_bytes;
120 } kvm_vmx_segment_fields[] = {
121         VMX_SEGMENT_FIELD(CS),
122         VMX_SEGMENT_FIELD(DS),
123         VMX_SEGMENT_FIELD(ES),
124         VMX_SEGMENT_FIELD(FS),
125         VMX_SEGMENT_FIELD(GS),
126         VMX_SEGMENT_FIELD(SS),
127         VMX_SEGMENT_FIELD(TR),
128         VMX_SEGMENT_FIELD(LDTR),
129 };
130
131 /*
132  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
133  * away by decrementing the array size.
134  */
135 static const u32 vmx_msr_index[] = {
136 #ifdef CONFIG_X86_64
137         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
138 #endif
139         MSR_EFER, MSR_K6_STAR,
140 };
141 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
142
143 static void load_msrs(struct kvm_msr_entry *e, int n)
144 {
145         int i;
146
147         for (i = 0; i < n; ++i)
148                 wrmsrl(e[i].index, e[i].data);
149 }
150
151 static void save_msrs(struct kvm_msr_entry *e, int n)
152 {
153         int i;
154
155         for (i = 0; i < n; ++i)
156                 rdmsrl(e[i].index, e[i].data);
157 }
158
159 static inline int is_page_fault(u32 intr_info)
160 {
161         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
162                              INTR_INFO_VALID_MASK)) ==
163                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
164 }
165
166 static inline int is_no_device(u32 intr_info)
167 {
168         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
169                              INTR_INFO_VALID_MASK)) ==
170                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
171 }
172
173 static inline int is_invalid_opcode(u32 intr_info)
174 {
175         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
176                              INTR_INFO_VALID_MASK)) ==
177                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
178 }
179
180 static inline int is_external_interrupt(u32 intr_info)
181 {
182         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
183                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
184 }
185
186 static inline int cpu_has_vmx_tpr_shadow(void)
187 {
188         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
189 }
190
191 static inline int vm_need_tpr_shadow(struct kvm *kvm)
192 {
193         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
194 }
195
196 static inline int cpu_has_secondary_exec_ctrls(void)
197 {
198         return (vmcs_config.cpu_based_exec_ctrl &
199                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
200 }
201
202 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
203 {
204         return (vmcs_config.cpu_based_2nd_exec_ctrl &
205                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
206 }
207
208 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
209 {
210         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
211                 (irqchip_in_kernel(kvm)));
212 }
213
214 static inline int cpu_has_vmx_vpid(void)
215 {
216         return (vmcs_config.cpu_based_2nd_exec_ctrl &
217                 SECONDARY_EXEC_ENABLE_VPID);
218 }
219
220 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
221 {
222         int i;
223
224         for (i = 0; i < vmx->nmsrs; ++i)
225                 if (vmx->guest_msrs[i].index == msr)
226                         return i;
227         return -1;
228 }
229
230 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
231 {
232     struct {
233         u64 vpid : 16;
234         u64 rsvd : 48;
235         u64 gva;
236     } operand = { vpid, 0, gva };
237
238     asm volatile (ASM_VMX_INVVPID
239                   /* CF==1 or ZF==1 --> rc = -1 */
240                   "; ja 1f ; ud2 ; 1:"
241                   : : "a"(&operand), "c"(ext) : "cc", "memory");
242 }
243
244 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
245 {
246         int i;
247
248         i = __find_msr_index(vmx, msr);
249         if (i >= 0)
250                 return &vmx->guest_msrs[i];
251         return NULL;
252 }
253
254 static void vmcs_clear(struct vmcs *vmcs)
255 {
256         u64 phys_addr = __pa(vmcs);
257         u8 error;
258
259         asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
260                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
261                       : "cc", "memory");
262         if (error)
263                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
264                        vmcs, phys_addr);
265 }
266
267 static void __vcpu_clear(void *arg)
268 {
269         struct vcpu_vmx *vmx = arg;
270         int cpu = raw_smp_processor_id();
271
272         if (vmx->vcpu.cpu == cpu)
273                 vmcs_clear(vmx->vmcs);
274         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
275                 per_cpu(current_vmcs, cpu) = NULL;
276         rdtscll(vmx->vcpu.arch.host_tsc);
277 }
278
279 static void vcpu_clear(struct vcpu_vmx *vmx)
280 {
281         if (vmx->vcpu.cpu == -1)
282                 return;
283         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
284         vmx->launched = 0;
285 }
286
287 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
288 {
289         if (vmx->vpid == 0)
290                 return;
291
292         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
293 }
294
295 static unsigned long vmcs_readl(unsigned long field)
296 {
297         unsigned long value;
298
299         asm volatile (ASM_VMX_VMREAD_RDX_RAX
300                       : "=a"(value) : "d"(field) : "cc");
301         return value;
302 }
303
304 static u16 vmcs_read16(unsigned long field)
305 {
306         return vmcs_readl(field);
307 }
308
309 static u32 vmcs_read32(unsigned long field)
310 {
311         return vmcs_readl(field);
312 }
313
314 static u64 vmcs_read64(unsigned long field)
315 {
316 #ifdef CONFIG_X86_64
317         return vmcs_readl(field);
318 #else
319         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
320 #endif
321 }
322
323 static noinline void vmwrite_error(unsigned long field, unsigned long value)
324 {
325         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
326                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
327         dump_stack();
328 }
329
330 static void vmcs_writel(unsigned long field, unsigned long value)
331 {
332         u8 error;
333
334         asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
335                        : "=q"(error) : "a"(value), "d"(field) : "cc");
336         if (unlikely(error))
337                 vmwrite_error(field, value);
338 }
339
340 static void vmcs_write16(unsigned long field, u16 value)
341 {
342         vmcs_writel(field, value);
343 }
344
345 static void vmcs_write32(unsigned long field, u32 value)
346 {
347         vmcs_writel(field, value);
348 }
349
350 static void vmcs_write64(unsigned long field, u64 value)
351 {
352 #ifdef CONFIG_X86_64
353         vmcs_writel(field, value);
354 #else
355         vmcs_writel(field, value);
356         asm volatile ("");
357         vmcs_writel(field+1, value >> 32);
358 #endif
359 }
360
361 static void vmcs_clear_bits(unsigned long field, u32 mask)
362 {
363         vmcs_writel(field, vmcs_readl(field) & ~mask);
364 }
365
366 static void vmcs_set_bits(unsigned long field, u32 mask)
367 {
368         vmcs_writel(field, vmcs_readl(field) | mask);
369 }
370
371 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
372 {
373         u32 eb;
374
375         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
376         if (!vcpu->fpu_active)
377                 eb |= 1u << NM_VECTOR;
378         if (vcpu->guest_debug.enabled)
379                 eb |= 1u << 1;
380         if (vcpu->arch.rmode.active)
381                 eb = ~0;
382         vmcs_write32(EXCEPTION_BITMAP, eb);
383 }
384
385 static void reload_tss(void)
386 {
387         /*
388          * VT restores TR but not its size.  Useless.
389          */
390         struct descriptor_table gdt;
391         struct segment_descriptor *descs;
392
393         get_gdt(&gdt);
394         descs = (void *)gdt.base;
395         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
396         load_TR_desc();
397 }
398
399 static void load_transition_efer(struct vcpu_vmx *vmx)
400 {
401         int efer_offset = vmx->msr_offset_efer;
402         u64 host_efer = vmx->host_msrs[efer_offset].data;
403         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
404         u64 ignore_bits;
405
406         if (efer_offset < 0)
407                 return;
408         /*
409          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
410          * outside long mode
411          */
412         ignore_bits = EFER_NX | EFER_SCE;
413 #ifdef CONFIG_X86_64
414         ignore_bits |= EFER_LMA | EFER_LME;
415         /* SCE is meaningful only in long mode on Intel */
416         if (guest_efer & EFER_LMA)
417                 ignore_bits &= ~(u64)EFER_SCE;
418 #endif
419         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
420                 return;
421
422         vmx->host_state.guest_efer_loaded = 1;
423         guest_efer &= ~ignore_bits;
424         guest_efer |= host_efer & ignore_bits;
425         wrmsrl(MSR_EFER, guest_efer);
426         vmx->vcpu.stat.efer_reload++;
427 }
428
429 static void reload_host_efer(struct vcpu_vmx *vmx)
430 {
431         if (vmx->host_state.guest_efer_loaded) {
432                 vmx->host_state.guest_efer_loaded = 0;
433                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
434         }
435 }
436
437 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
438 {
439         struct vcpu_vmx *vmx = to_vmx(vcpu);
440
441         if (vmx->host_state.loaded)
442                 return;
443
444         vmx->host_state.loaded = 1;
445         /*
446          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
447          * allow segment selectors with cpl > 0 or ti == 1.
448          */
449         vmx->host_state.ldt_sel = read_ldt();
450         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
451         vmx->host_state.fs_sel = read_fs();
452         if (!(vmx->host_state.fs_sel & 7)) {
453                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
454                 vmx->host_state.fs_reload_needed = 0;
455         } else {
456                 vmcs_write16(HOST_FS_SELECTOR, 0);
457                 vmx->host_state.fs_reload_needed = 1;
458         }
459         vmx->host_state.gs_sel = read_gs();
460         if (!(vmx->host_state.gs_sel & 7))
461                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
462         else {
463                 vmcs_write16(HOST_GS_SELECTOR, 0);
464                 vmx->host_state.gs_ldt_reload_needed = 1;
465         }
466
467 #ifdef CONFIG_X86_64
468         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
469         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
470 #else
471         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
472         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
473 #endif
474
475 #ifdef CONFIG_X86_64
476         if (is_long_mode(&vmx->vcpu))
477                 save_msrs(vmx->host_msrs +
478                           vmx->msr_offset_kernel_gs_base, 1);
479
480 #endif
481         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
482         load_transition_efer(vmx);
483 }
484
485 static void vmx_load_host_state(struct vcpu_vmx *vmx)
486 {
487         unsigned long flags;
488
489         if (!vmx->host_state.loaded)
490                 return;
491
492         ++vmx->vcpu.stat.host_state_reload;
493         vmx->host_state.loaded = 0;
494         if (vmx->host_state.fs_reload_needed)
495                 load_fs(vmx->host_state.fs_sel);
496         if (vmx->host_state.gs_ldt_reload_needed) {
497                 load_ldt(vmx->host_state.ldt_sel);
498                 /*
499                  * If we have to reload gs, we must take care to
500                  * preserve our gs base.
501                  */
502                 local_irq_save(flags);
503                 load_gs(vmx->host_state.gs_sel);
504 #ifdef CONFIG_X86_64
505                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
506 #endif
507                 local_irq_restore(flags);
508         }
509         reload_tss();
510         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
511         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
512         reload_host_efer(vmx);
513 }
514
515 /*
516  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
517  * vcpu mutex is already taken.
518  */
519 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
520 {
521         struct vcpu_vmx *vmx = to_vmx(vcpu);
522         u64 phys_addr = __pa(vmx->vmcs);
523         u64 tsc_this, delta;
524
525         if (vcpu->cpu != cpu) {
526                 vcpu_clear(vmx);
527                 kvm_migrate_apic_timer(vcpu);
528                 vpid_sync_vcpu_all(vmx);
529         }
530
531         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
532                 u8 error;
533
534                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
535                 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
536                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
537                               : "cc");
538                 if (error)
539                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
540                                vmx->vmcs, phys_addr);
541         }
542
543         if (vcpu->cpu != cpu) {
544                 struct descriptor_table dt;
545                 unsigned long sysenter_esp;
546
547                 vcpu->cpu = cpu;
548                 /*
549                  * Linux uses per-cpu TSS and GDT, so set these when switching
550                  * processors.
551                  */
552                 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
553                 get_gdt(&dt);
554                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
555
556                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
557                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
558
559                 /*
560                  * Make sure the time stamp counter is monotonous.
561                  */
562                 rdtscll(tsc_this);
563                 delta = vcpu->arch.host_tsc - tsc_this;
564                 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
565         }
566 }
567
568 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
569 {
570         vmx_load_host_state(to_vmx(vcpu));
571 }
572
573 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
574 {
575         if (vcpu->fpu_active)
576                 return;
577         vcpu->fpu_active = 1;
578         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
579         if (vcpu->arch.cr0 & X86_CR0_TS)
580                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
581         update_exception_bitmap(vcpu);
582 }
583
584 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
585 {
586         if (!vcpu->fpu_active)
587                 return;
588         vcpu->fpu_active = 0;
589         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
590         update_exception_bitmap(vcpu);
591 }
592
593 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
594 {
595         vcpu_clear(to_vmx(vcpu));
596 }
597
598 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
599 {
600         return vmcs_readl(GUEST_RFLAGS);
601 }
602
603 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
604 {
605         if (vcpu->arch.rmode.active)
606                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
607         vmcs_writel(GUEST_RFLAGS, rflags);
608 }
609
610 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
611 {
612         unsigned long rip;
613         u32 interruptibility;
614
615         rip = vmcs_readl(GUEST_RIP);
616         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
617         vmcs_writel(GUEST_RIP, rip);
618
619         /*
620          * We emulated an instruction, so temporary interrupt blocking
621          * should be removed, if set.
622          */
623         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
624         if (interruptibility & 3)
625                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
626                              interruptibility & ~3);
627         vcpu->arch.interrupt_window_open = 1;
628 }
629
630 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
631                                 bool has_error_code, u32 error_code)
632 {
633         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
634                      nr | INTR_TYPE_EXCEPTION
635                      | (has_error_code ? INTR_INFO_DELIEVER_CODE_MASK : 0)
636                      | INTR_INFO_VALID_MASK);
637         if (has_error_code)
638                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
639 }
640
641 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
642 {
643         struct vcpu_vmx *vmx = to_vmx(vcpu);
644
645         return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
646 }
647
648 /*
649  * Swap MSR entry in host/guest MSR entry array.
650  */
651 #ifdef CONFIG_X86_64
652 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
653 {
654         struct kvm_msr_entry tmp;
655
656         tmp = vmx->guest_msrs[to];
657         vmx->guest_msrs[to] = vmx->guest_msrs[from];
658         vmx->guest_msrs[from] = tmp;
659         tmp = vmx->host_msrs[to];
660         vmx->host_msrs[to] = vmx->host_msrs[from];
661         vmx->host_msrs[from] = tmp;
662 }
663 #endif
664
665 /*
666  * Set up the vmcs to automatically save and restore system
667  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
668  * mode, as fiddling with msrs is very expensive.
669  */
670 static void setup_msrs(struct vcpu_vmx *vmx)
671 {
672         int save_nmsrs;
673
674         vmx_load_host_state(vmx);
675         save_nmsrs = 0;
676 #ifdef CONFIG_X86_64
677         if (is_long_mode(&vmx->vcpu)) {
678                 int index;
679
680                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
681                 if (index >= 0)
682                         move_msr_up(vmx, index, save_nmsrs++);
683                 index = __find_msr_index(vmx, MSR_LSTAR);
684                 if (index >= 0)
685                         move_msr_up(vmx, index, save_nmsrs++);
686                 index = __find_msr_index(vmx, MSR_CSTAR);
687                 if (index >= 0)
688                         move_msr_up(vmx, index, save_nmsrs++);
689                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
690                 if (index >= 0)
691                         move_msr_up(vmx, index, save_nmsrs++);
692                 /*
693                  * MSR_K6_STAR is only needed on long mode guests, and only
694                  * if efer.sce is enabled.
695                  */
696                 index = __find_msr_index(vmx, MSR_K6_STAR);
697                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
698                         move_msr_up(vmx, index, save_nmsrs++);
699         }
700 #endif
701         vmx->save_nmsrs = save_nmsrs;
702
703 #ifdef CONFIG_X86_64
704         vmx->msr_offset_kernel_gs_base =
705                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
706 #endif
707         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
708 }
709
710 /*
711  * reads and returns guest's timestamp counter "register"
712  * guest_tsc = host_tsc + tsc_offset    -- 21.3
713  */
714 static u64 guest_read_tsc(void)
715 {
716         u64 host_tsc, tsc_offset;
717
718         rdtscll(host_tsc);
719         tsc_offset = vmcs_read64(TSC_OFFSET);
720         return host_tsc + tsc_offset;
721 }
722
723 /*
724  * writes 'guest_tsc' into guest's timestamp counter "register"
725  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
726  */
727 static void guest_write_tsc(u64 guest_tsc)
728 {
729         u64 host_tsc;
730
731         rdtscll(host_tsc);
732         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
733 }
734
735 /*
736  * Reads an msr value (of 'msr_index') into 'pdata'.
737  * Returns 0 on success, non-0 otherwise.
738  * Assumes vcpu_load() was already called.
739  */
740 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
741 {
742         u64 data;
743         struct kvm_msr_entry *msr;
744
745         if (!pdata) {
746                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
747                 return -EINVAL;
748         }
749
750         switch (msr_index) {
751 #ifdef CONFIG_X86_64
752         case MSR_FS_BASE:
753                 data = vmcs_readl(GUEST_FS_BASE);
754                 break;
755         case MSR_GS_BASE:
756                 data = vmcs_readl(GUEST_GS_BASE);
757                 break;
758         case MSR_EFER:
759                 return kvm_get_msr_common(vcpu, msr_index, pdata);
760 #endif
761         case MSR_IA32_TIME_STAMP_COUNTER:
762                 data = guest_read_tsc();
763                 break;
764         case MSR_IA32_SYSENTER_CS:
765                 data = vmcs_read32(GUEST_SYSENTER_CS);
766                 break;
767         case MSR_IA32_SYSENTER_EIP:
768                 data = vmcs_readl(GUEST_SYSENTER_EIP);
769                 break;
770         case MSR_IA32_SYSENTER_ESP:
771                 data = vmcs_readl(GUEST_SYSENTER_ESP);
772                 break;
773         default:
774                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
775                 if (msr) {
776                         data = msr->data;
777                         break;
778                 }
779                 return kvm_get_msr_common(vcpu, msr_index, pdata);
780         }
781
782         *pdata = data;
783         return 0;
784 }
785
786 /*
787  * Writes msr value into into the appropriate "register".
788  * Returns 0 on success, non-0 otherwise.
789  * Assumes vcpu_load() was already called.
790  */
791 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
792 {
793         struct vcpu_vmx *vmx = to_vmx(vcpu);
794         struct kvm_msr_entry *msr;
795         int ret = 0;
796
797         switch (msr_index) {
798 #ifdef CONFIG_X86_64
799         case MSR_EFER:
800                 ret = kvm_set_msr_common(vcpu, msr_index, data);
801                 if (vmx->host_state.loaded) {
802                         reload_host_efer(vmx);
803                         load_transition_efer(vmx);
804                 }
805                 break;
806         case MSR_FS_BASE:
807                 vmcs_writel(GUEST_FS_BASE, data);
808                 break;
809         case MSR_GS_BASE:
810                 vmcs_writel(GUEST_GS_BASE, data);
811                 break;
812 #endif
813         case MSR_IA32_SYSENTER_CS:
814                 vmcs_write32(GUEST_SYSENTER_CS, data);
815                 break;
816         case MSR_IA32_SYSENTER_EIP:
817                 vmcs_writel(GUEST_SYSENTER_EIP, data);
818                 break;
819         case MSR_IA32_SYSENTER_ESP:
820                 vmcs_writel(GUEST_SYSENTER_ESP, data);
821                 break;
822         case MSR_IA32_TIME_STAMP_COUNTER:
823                 guest_write_tsc(data);
824                 break;
825         default:
826                 msr = find_msr_entry(vmx, msr_index);
827                 if (msr) {
828                         msr->data = data;
829                         if (vmx->host_state.loaded)
830                                 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
831                         break;
832                 }
833                 ret = kvm_set_msr_common(vcpu, msr_index, data);
834         }
835
836         return ret;
837 }
838
839 /*
840  * Sync the rsp and rip registers into the vcpu structure.  This allows
841  * registers to be accessed by indexing vcpu->arch.regs.
842  */
843 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
844 {
845         vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
846         vcpu->arch.rip = vmcs_readl(GUEST_RIP);
847 }
848
849 /*
850  * Syncs rsp and rip back into the vmcs.  Should be called after possible
851  * modification.
852  */
853 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
854 {
855         vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
856         vmcs_writel(GUEST_RIP, vcpu->arch.rip);
857 }
858
859 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
860 {
861         unsigned long dr7 = 0x400;
862         int old_singlestep;
863
864         old_singlestep = vcpu->guest_debug.singlestep;
865
866         vcpu->guest_debug.enabled = dbg->enabled;
867         if (vcpu->guest_debug.enabled) {
868                 int i;
869
870                 dr7 |= 0x200;  /* exact */
871                 for (i = 0; i < 4; ++i) {
872                         if (!dbg->breakpoints[i].enabled)
873                                 continue;
874                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
875                         dr7 |= 2 << (i*2);    /* global enable */
876                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
877                 }
878
879                 vcpu->guest_debug.singlestep = dbg->singlestep;
880         } else
881                 vcpu->guest_debug.singlestep = 0;
882
883         if (old_singlestep && !vcpu->guest_debug.singlestep) {
884                 unsigned long flags;
885
886                 flags = vmcs_readl(GUEST_RFLAGS);
887                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
888                 vmcs_writel(GUEST_RFLAGS, flags);
889         }
890
891         update_exception_bitmap(vcpu);
892         vmcs_writel(GUEST_DR7, dr7);
893
894         return 0;
895 }
896
897 static int vmx_get_irq(struct kvm_vcpu *vcpu)
898 {
899         struct vcpu_vmx *vmx = to_vmx(vcpu);
900         u32 idtv_info_field;
901
902         idtv_info_field = vmx->idt_vectoring_info;
903         if (idtv_info_field & INTR_INFO_VALID_MASK) {
904                 if (is_external_interrupt(idtv_info_field))
905                         return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
906                 else
907                         printk(KERN_DEBUG "pending exception: not handled yet\n");
908         }
909         return -1;
910 }
911
912 static __init int cpu_has_kvm_support(void)
913 {
914         unsigned long ecx = cpuid_ecx(1);
915         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
916 }
917
918 static __init int vmx_disabled_by_bios(void)
919 {
920         u64 msr;
921
922         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
923         return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
924                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
925             == MSR_IA32_FEATURE_CONTROL_LOCKED;
926         /* locked but not enabled */
927 }
928
929 static void hardware_enable(void *garbage)
930 {
931         int cpu = raw_smp_processor_id();
932         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
933         u64 old;
934
935         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
936         if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
937                     MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
938             != (MSR_IA32_FEATURE_CONTROL_LOCKED |
939                 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
940                 /* enable and lock */
941                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
942                        MSR_IA32_FEATURE_CONTROL_LOCKED |
943                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
944         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
945         asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
946                       : "memory", "cc");
947 }
948
949 static void hardware_disable(void *garbage)
950 {
951         asm volatile (ASM_VMX_VMXOFF : : : "cc");
952 }
953
954 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
955                                       u32 msr, u32 *result)
956 {
957         u32 vmx_msr_low, vmx_msr_high;
958         u32 ctl = ctl_min | ctl_opt;
959
960         rdmsr(msr, vmx_msr_low, vmx_msr_high);
961
962         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
963         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
964
965         /* Ensure minimum (required) set of control bits are supported. */
966         if (ctl_min & ~ctl)
967                 return -EIO;
968
969         *result = ctl;
970         return 0;
971 }
972
973 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
974 {
975         u32 vmx_msr_low, vmx_msr_high;
976         u32 min, opt;
977         u32 _pin_based_exec_control = 0;
978         u32 _cpu_based_exec_control = 0;
979         u32 _cpu_based_2nd_exec_control = 0;
980         u32 _vmexit_control = 0;
981         u32 _vmentry_control = 0;
982
983         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
984         opt = 0;
985         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
986                                 &_pin_based_exec_control) < 0)
987                 return -EIO;
988
989         min = CPU_BASED_HLT_EXITING |
990 #ifdef CONFIG_X86_64
991               CPU_BASED_CR8_LOAD_EXITING |
992               CPU_BASED_CR8_STORE_EXITING |
993 #endif
994               CPU_BASED_USE_IO_BITMAPS |
995               CPU_BASED_MOV_DR_EXITING |
996               CPU_BASED_USE_TSC_OFFSETING;
997         opt = CPU_BASED_TPR_SHADOW |
998               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
999         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1000                                 &_cpu_based_exec_control) < 0)
1001                 return -EIO;
1002 #ifdef CONFIG_X86_64
1003         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1004                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1005                                            ~CPU_BASED_CR8_STORE_EXITING;
1006 #endif
1007         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1008                 min = 0;
1009                 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1010                         SECONDARY_EXEC_WBINVD_EXITING |
1011                         SECONDARY_EXEC_ENABLE_VPID;
1012                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
1013                                         &_cpu_based_2nd_exec_control) < 0)
1014                         return -EIO;
1015         }
1016 #ifndef CONFIG_X86_64
1017         if (!(_cpu_based_2nd_exec_control &
1018                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1019                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1020 #endif
1021
1022         min = 0;
1023 #ifdef CONFIG_X86_64
1024         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1025 #endif
1026         opt = 0;
1027         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1028                                 &_vmexit_control) < 0)
1029                 return -EIO;
1030
1031         min = opt = 0;
1032         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1033                                 &_vmentry_control) < 0)
1034                 return -EIO;
1035
1036         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1037
1038         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1039         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1040                 return -EIO;
1041
1042 #ifdef CONFIG_X86_64
1043         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1044         if (vmx_msr_high & (1u<<16))
1045                 return -EIO;
1046 #endif
1047
1048         /* Require Write-Back (WB) memory type for VMCS accesses. */
1049         if (((vmx_msr_high >> 18) & 15) != 6)
1050                 return -EIO;
1051
1052         vmcs_conf->size = vmx_msr_high & 0x1fff;
1053         vmcs_conf->order = get_order(vmcs_config.size);
1054         vmcs_conf->revision_id = vmx_msr_low;
1055
1056         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1057         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1058         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1059         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1060         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1061
1062         return 0;
1063 }
1064
1065 static struct vmcs *alloc_vmcs_cpu(int cpu)
1066 {
1067         int node = cpu_to_node(cpu);
1068         struct page *pages;
1069         struct vmcs *vmcs;
1070
1071         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1072         if (!pages)
1073                 return NULL;
1074         vmcs = page_address(pages);
1075         memset(vmcs, 0, vmcs_config.size);
1076         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1077         return vmcs;
1078 }
1079
1080 static struct vmcs *alloc_vmcs(void)
1081 {
1082         return alloc_vmcs_cpu(raw_smp_processor_id());
1083 }
1084
1085 static void free_vmcs(struct vmcs *vmcs)
1086 {
1087         free_pages((unsigned long)vmcs, vmcs_config.order);
1088 }
1089
1090 static void free_kvm_area(void)
1091 {
1092         int cpu;
1093
1094         for_each_online_cpu(cpu)
1095                 free_vmcs(per_cpu(vmxarea, cpu));
1096 }
1097
1098 static __init int alloc_kvm_area(void)
1099 {
1100         int cpu;
1101
1102         for_each_online_cpu(cpu) {
1103                 struct vmcs *vmcs;
1104
1105                 vmcs = alloc_vmcs_cpu(cpu);
1106                 if (!vmcs) {
1107                         free_kvm_area();
1108                         return -ENOMEM;
1109                 }
1110
1111                 per_cpu(vmxarea, cpu) = vmcs;
1112         }
1113         return 0;
1114 }
1115
1116 static __init int hardware_setup(void)
1117 {
1118         if (setup_vmcs_config(&vmcs_config) < 0)
1119                 return -EIO;
1120         return alloc_kvm_area();
1121 }
1122
1123 static __exit void hardware_unsetup(void)
1124 {
1125         free_kvm_area();
1126 }
1127
1128 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1129 {
1130         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1131
1132         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1133                 vmcs_write16(sf->selector, save->selector);
1134                 vmcs_writel(sf->base, save->base);
1135                 vmcs_write32(sf->limit, save->limit);
1136                 vmcs_write32(sf->ar_bytes, save->ar);
1137         } else {
1138                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1139                         << AR_DPL_SHIFT;
1140                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1141         }
1142 }
1143
1144 static void enter_pmode(struct kvm_vcpu *vcpu)
1145 {
1146         unsigned long flags;
1147
1148         vcpu->arch.rmode.active = 0;
1149
1150         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1151         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1152         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1153
1154         flags = vmcs_readl(GUEST_RFLAGS);
1155         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1156         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1157         vmcs_writel(GUEST_RFLAGS, flags);
1158
1159         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1160                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1161
1162         update_exception_bitmap(vcpu);
1163
1164         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1165         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1166         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1167         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1168
1169         vmcs_write16(GUEST_SS_SELECTOR, 0);
1170         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1171
1172         vmcs_write16(GUEST_CS_SELECTOR,
1173                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1174         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1175 }
1176
1177 static gva_t rmode_tss_base(struct kvm *kvm)
1178 {
1179         if (!kvm->arch.tss_addr) {
1180                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1181                                  kvm->memslots[0].npages - 3;
1182                 return base_gfn << PAGE_SHIFT;
1183         }
1184         return kvm->arch.tss_addr;
1185 }
1186
1187 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1188 {
1189         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1190
1191         save->selector = vmcs_read16(sf->selector);
1192         save->base = vmcs_readl(sf->base);
1193         save->limit = vmcs_read32(sf->limit);
1194         save->ar = vmcs_read32(sf->ar_bytes);
1195         vmcs_write16(sf->selector, save->base >> 4);
1196         vmcs_write32(sf->base, save->base & 0xfffff);
1197         vmcs_write32(sf->limit, 0xffff);
1198         vmcs_write32(sf->ar_bytes, 0xf3);
1199 }
1200
1201 static void enter_rmode(struct kvm_vcpu *vcpu)
1202 {
1203         unsigned long flags;
1204
1205         vcpu->arch.rmode.active = 1;
1206
1207         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1208         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1209
1210         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1211         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1212
1213         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1214         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1215
1216         flags = vmcs_readl(GUEST_RFLAGS);
1217         vcpu->arch.rmode.save_iopl
1218                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1219
1220         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1221
1222         vmcs_writel(GUEST_RFLAGS, flags);
1223         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1224         update_exception_bitmap(vcpu);
1225
1226         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1227         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1228         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1229
1230         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1231         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1232         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1233                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1234         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1235
1236         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1237         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1238         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1239         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1240
1241         kvm_mmu_reset_context(vcpu);
1242         init_rmode_tss(vcpu->kvm);
1243 }
1244
1245 #ifdef CONFIG_X86_64
1246
1247 static void enter_lmode(struct kvm_vcpu *vcpu)
1248 {
1249         u32 guest_tr_ar;
1250
1251         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1252         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1253                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1254                        __FUNCTION__);
1255                 vmcs_write32(GUEST_TR_AR_BYTES,
1256                              (guest_tr_ar & ~AR_TYPE_MASK)
1257                              | AR_TYPE_BUSY_64_TSS);
1258         }
1259
1260         vcpu->arch.shadow_efer |= EFER_LMA;
1261
1262         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1263         vmcs_write32(VM_ENTRY_CONTROLS,
1264                      vmcs_read32(VM_ENTRY_CONTROLS)
1265                      | VM_ENTRY_IA32E_MODE);
1266 }
1267
1268 static void exit_lmode(struct kvm_vcpu *vcpu)
1269 {
1270         vcpu->arch.shadow_efer &= ~EFER_LMA;
1271
1272         vmcs_write32(VM_ENTRY_CONTROLS,
1273                      vmcs_read32(VM_ENTRY_CONTROLS)
1274                      & ~VM_ENTRY_IA32E_MODE);
1275 }
1276
1277 #endif
1278
1279 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1280 {
1281         vpid_sync_vcpu_all(to_vmx(vcpu));
1282 }
1283
1284 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1285 {
1286         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1287         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1288 }
1289
1290 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1291 {
1292         vmx_fpu_deactivate(vcpu);
1293
1294         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1295                 enter_pmode(vcpu);
1296
1297         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1298                 enter_rmode(vcpu);
1299
1300 #ifdef CONFIG_X86_64
1301         if (vcpu->arch.shadow_efer & EFER_LME) {
1302                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1303                         enter_lmode(vcpu);
1304                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1305                         exit_lmode(vcpu);
1306         }
1307 #endif
1308
1309         vmcs_writel(CR0_READ_SHADOW, cr0);
1310         vmcs_writel(GUEST_CR0,
1311                     (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1312         vcpu->arch.cr0 = cr0;
1313
1314         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1315                 vmx_fpu_activate(vcpu);
1316 }
1317
1318 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1319 {
1320         vmx_flush_tlb(vcpu);
1321         vmcs_writel(GUEST_CR3, cr3);
1322         if (vcpu->arch.cr0 & X86_CR0_PE)
1323                 vmx_fpu_deactivate(vcpu);
1324 }
1325
1326 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1327 {
1328         vmcs_writel(CR4_READ_SHADOW, cr4);
1329         vmcs_writel(GUEST_CR4, cr4 | (vcpu->arch.rmode.active ?
1330                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1331         vcpu->arch.cr4 = cr4;
1332 }
1333
1334 #ifdef CONFIG_X86_64
1335
1336 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1337 {
1338         struct vcpu_vmx *vmx = to_vmx(vcpu);
1339         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1340
1341         vcpu->arch.shadow_efer = efer;
1342         if (efer & EFER_LMA) {
1343                 vmcs_write32(VM_ENTRY_CONTROLS,
1344                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1345                                      VM_ENTRY_IA32E_MODE);
1346                 msr->data = efer;
1347
1348         } else {
1349                 vmcs_write32(VM_ENTRY_CONTROLS,
1350                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1351                                      ~VM_ENTRY_IA32E_MODE);
1352
1353                 msr->data = efer & ~EFER_LME;
1354         }
1355         setup_msrs(vmx);
1356 }
1357
1358 #endif
1359
1360 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1361 {
1362         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1363
1364         return vmcs_readl(sf->base);
1365 }
1366
1367 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1368                             struct kvm_segment *var, int seg)
1369 {
1370         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1371         u32 ar;
1372
1373         var->base = vmcs_readl(sf->base);
1374         var->limit = vmcs_read32(sf->limit);
1375         var->selector = vmcs_read16(sf->selector);
1376         ar = vmcs_read32(sf->ar_bytes);
1377         if (ar & AR_UNUSABLE_MASK)
1378                 ar = 0;
1379         var->type = ar & 15;
1380         var->s = (ar >> 4) & 1;
1381         var->dpl = (ar >> 5) & 3;
1382         var->present = (ar >> 7) & 1;
1383         var->avl = (ar >> 12) & 1;
1384         var->l = (ar >> 13) & 1;
1385         var->db = (ar >> 14) & 1;
1386         var->g = (ar >> 15) & 1;
1387         var->unusable = (ar >> 16) & 1;
1388 }
1389
1390 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1391 {
1392         u32 ar;
1393
1394         if (var->unusable)
1395                 ar = 1 << 16;
1396         else {
1397                 ar = var->type & 15;
1398                 ar |= (var->s & 1) << 4;
1399                 ar |= (var->dpl & 3) << 5;
1400                 ar |= (var->present & 1) << 7;
1401                 ar |= (var->avl & 1) << 12;
1402                 ar |= (var->l & 1) << 13;
1403                 ar |= (var->db & 1) << 14;
1404                 ar |= (var->g & 1) << 15;
1405         }
1406         if (ar == 0) /* a 0 value means unusable */
1407                 ar = AR_UNUSABLE_MASK;
1408
1409         return ar;
1410 }
1411
1412 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1413                             struct kvm_segment *var, int seg)
1414 {
1415         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1416         u32 ar;
1417
1418         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1419                 vcpu->arch.rmode.tr.selector = var->selector;
1420                 vcpu->arch.rmode.tr.base = var->base;
1421                 vcpu->arch.rmode.tr.limit = var->limit;
1422                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1423                 return;
1424         }
1425         vmcs_writel(sf->base, var->base);
1426         vmcs_write32(sf->limit, var->limit);
1427         vmcs_write16(sf->selector, var->selector);
1428         if (vcpu->arch.rmode.active && var->s) {
1429                 /*
1430                  * Hack real-mode segments into vm86 compatibility.
1431                  */
1432                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1433                         vmcs_writel(sf->base, 0xf0000);
1434                 ar = 0xf3;
1435         } else
1436                 ar = vmx_segment_access_rights(var);
1437         vmcs_write32(sf->ar_bytes, ar);
1438 }
1439
1440 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1441 {
1442         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1443
1444         *db = (ar >> 14) & 1;
1445         *l = (ar >> 13) & 1;
1446 }
1447
1448 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1449 {
1450         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1451         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1452 }
1453
1454 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1455 {
1456         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1457         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1458 }
1459
1460 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1461 {
1462         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1463         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1464 }
1465
1466 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1467 {
1468         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1469         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1470 }
1471
1472 static int init_rmode_tss(struct kvm *kvm)
1473 {
1474         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1475         u16 data = 0;
1476         int ret = 0;
1477         int r;
1478
1479         down_read(&kvm->slots_lock);
1480         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1481         if (r < 0)
1482                 goto out;
1483         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1484         r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1485         if (r < 0)
1486                 goto out;
1487         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1488         if (r < 0)
1489                 goto out;
1490         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1491         if (r < 0)
1492                 goto out;
1493         data = ~0;
1494         r = kvm_write_guest_page(kvm, fn, &data,
1495                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1496                                  sizeof(u8));
1497         if (r < 0)
1498                 goto out;
1499
1500         ret = 1;
1501 out:
1502         up_read(&kvm->slots_lock);
1503         return ret;
1504 }
1505
1506 static void seg_setup(int seg)
1507 {
1508         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1509
1510         vmcs_write16(sf->selector, 0);
1511         vmcs_writel(sf->base, 0);
1512         vmcs_write32(sf->limit, 0xffff);
1513         vmcs_write32(sf->ar_bytes, 0x93);
1514 }
1515
1516 static int alloc_apic_access_page(struct kvm *kvm)
1517 {
1518         struct kvm_userspace_memory_region kvm_userspace_mem;
1519         int r = 0;
1520
1521         down_write(&kvm->slots_lock);
1522         if (kvm->arch.apic_access_page)
1523                 goto out;
1524         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1525         kvm_userspace_mem.flags = 0;
1526         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1527         kvm_userspace_mem.memory_size = PAGE_SIZE;
1528         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1529         if (r)
1530                 goto out;
1531
1532         down_read(&current->mm->mmap_sem);
1533         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
1534         up_read(&current->mm->mmap_sem);
1535 out:
1536         up_write(&kvm->slots_lock);
1537         return r;
1538 }
1539
1540 static void allocate_vpid(struct vcpu_vmx *vmx)
1541 {
1542         int vpid;
1543
1544         vmx->vpid = 0;
1545         if (!enable_vpid || !cpu_has_vmx_vpid())
1546                 return;
1547         spin_lock(&vmx_vpid_lock);
1548         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
1549         if (vpid < VMX_NR_VPIDS) {
1550                 vmx->vpid = vpid;
1551                 __set_bit(vpid, vmx_vpid_bitmap);
1552         }
1553         spin_unlock(&vmx_vpid_lock);
1554 }
1555
1556 /*
1557  * Sets up the vmcs for emulated real mode.
1558  */
1559 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1560 {
1561         u32 host_sysenter_cs;
1562         u32 junk;
1563         unsigned long a;
1564         struct descriptor_table dt;
1565         int i;
1566         unsigned long kvm_vmx_return;
1567         u32 exec_control;
1568
1569         /* I/O */
1570         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1571         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1572
1573         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1574
1575         /* Control */
1576         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1577                 vmcs_config.pin_based_exec_ctrl);
1578
1579         exec_control = vmcs_config.cpu_based_exec_ctrl;
1580         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1581                 exec_control &= ~CPU_BASED_TPR_SHADOW;
1582 #ifdef CONFIG_X86_64
1583                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1584                                 CPU_BASED_CR8_LOAD_EXITING;
1585 #endif
1586         }
1587         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1588
1589         if (cpu_has_secondary_exec_ctrls()) {
1590                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1591                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1592                         exec_control &=
1593                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1594                 if (vmx->vpid == 0)
1595                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
1596                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1597         }
1598
1599         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1600         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1601         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
1602
1603         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
1604         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
1605         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
1606
1607         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
1608         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1609         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1610         vmcs_write16(HOST_FS_SELECTOR, read_fs());    /* 22.2.4 */
1611         vmcs_write16(HOST_GS_SELECTOR, read_gs());    /* 22.2.4 */
1612         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1613 #ifdef CONFIG_X86_64
1614         rdmsrl(MSR_FS_BASE, a);
1615         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1616         rdmsrl(MSR_GS_BASE, a);
1617         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1618 #else
1619         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1620         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1621 #endif
1622
1623         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
1624
1625         get_idt(&dt);
1626         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
1627
1628         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1629         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1630         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1631         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1632         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1633
1634         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1635         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1636         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1637         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
1638         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1639         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
1640
1641         for (i = 0; i < NR_VMX_MSR; ++i) {
1642                 u32 index = vmx_msr_index[i];
1643                 u32 data_low, data_high;
1644                 u64 data;
1645                 int j = vmx->nmsrs;
1646
1647                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1648                         continue;
1649                 if (wrmsr_safe(index, data_low, data_high) < 0)
1650                         continue;
1651                 data = data_low | ((u64)data_high << 32);
1652                 vmx->host_msrs[j].index = index;
1653                 vmx->host_msrs[j].reserved = 0;
1654                 vmx->host_msrs[j].data = data;
1655                 vmx->guest_msrs[j] = vmx->host_msrs[j];
1656                 ++vmx->nmsrs;
1657         }
1658
1659         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1660
1661         /* 22.2.1, 20.8.1 */
1662         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1663
1664         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1665         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1666
1667
1668         return 0;
1669 }
1670
1671 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1672 {
1673         struct vcpu_vmx *vmx = to_vmx(vcpu);
1674         u64 msr;
1675         int ret;
1676
1677         if (!init_rmode_tss(vmx->vcpu.kvm)) {
1678                 ret = -ENOMEM;
1679                 goto out;
1680         }
1681
1682         vmx->vcpu.arch.rmode.active = 0;
1683
1684         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1685         set_cr8(&vmx->vcpu, 0);
1686         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1687         if (vmx->vcpu.vcpu_id == 0)
1688                 msr |= MSR_IA32_APICBASE_BSP;
1689         kvm_set_apic_base(&vmx->vcpu, msr);
1690
1691         fx_init(&vmx->vcpu);
1692
1693         /*
1694          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1695          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
1696          */
1697         if (vmx->vcpu.vcpu_id == 0) {
1698                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1699                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1700         } else {
1701                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
1702                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
1703         }
1704         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1705         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1706
1707         seg_setup(VCPU_SREG_DS);
1708         seg_setup(VCPU_SREG_ES);
1709         seg_setup(VCPU_SREG_FS);
1710         seg_setup(VCPU_SREG_GS);
1711         seg_setup(VCPU_SREG_SS);
1712
1713         vmcs_write16(GUEST_TR_SELECTOR, 0);
1714         vmcs_writel(GUEST_TR_BASE, 0);
1715         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1716         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1717
1718         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1719         vmcs_writel(GUEST_LDTR_BASE, 0);
1720         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1721         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1722
1723         vmcs_write32(GUEST_SYSENTER_CS, 0);
1724         vmcs_writel(GUEST_SYSENTER_ESP, 0);
1725         vmcs_writel(GUEST_SYSENTER_EIP, 0);
1726
1727         vmcs_writel(GUEST_RFLAGS, 0x02);
1728         if (vmx->vcpu.vcpu_id == 0)
1729                 vmcs_writel(GUEST_RIP, 0xfff0);
1730         else
1731                 vmcs_writel(GUEST_RIP, 0);
1732         vmcs_writel(GUEST_RSP, 0);
1733
1734         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1735         vmcs_writel(GUEST_DR7, 0x400);
1736
1737         vmcs_writel(GUEST_GDTR_BASE, 0);
1738         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1739
1740         vmcs_writel(GUEST_IDTR_BASE, 0);
1741         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1742
1743         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1744         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1745         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1746
1747         guest_write_tsc(0);
1748
1749         /* Special registers */
1750         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1751
1752         setup_msrs(vmx);
1753
1754         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
1755
1756         if (cpu_has_vmx_tpr_shadow()) {
1757                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1758                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1759                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1760                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
1761                 vmcs_write32(TPR_THRESHOLD, 0);
1762         }
1763
1764         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1765                 vmcs_write64(APIC_ACCESS_ADDR,
1766                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
1767
1768         if (vmx->vpid != 0)
1769                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
1770
1771         vmx->vcpu.arch.cr0 = 0x60000010;
1772         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
1773         vmx_set_cr4(&vmx->vcpu, 0);
1774 #ifdef CONFIG_X86_64
1775         vmx_set_efer(&vmx->vcpu, 0);
1776 #endif
1777         vmx_fpu_activate(&vmx->vcpu);
1778         update_exception_bitmap(&vmx->vcpu);
1779
1780         vpid_sync_vcpu_all(vmx);
1781
1782         return 0;
1783
1784 out:
1785         return ret;
1786 }
1787
1788 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1789 {
1790         struct vcpu_vmx *vmx = to_vmx(vcpu);
1791
1792         if (vcpu->arch.rmode.active) {
1793                 vmx->rmode.irq.pending = true;
1794                 vmx->rmode.irq.vector = irq;
1795                 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
1796                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1797                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1798                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1799                 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
1800                 return;
1801         }
1802         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1803                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1804 }
1805
1806 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1807 {
1808         int word_index = __ffs(vcpu->arch.irq_summary);
1809         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1810         int irq = word_index * BITS_PER_LONG + bit_index;
1811
1812         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1813         if (!vcpu->arch.irq_pending[word_index])
1814                 clear_bit(word_index, &vcpu->arch.irq_summary);
1815         vmx_inject_irq(vcpu, irq);
1816 }
1817
1818
1819 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1820                                        struct kvm_run *kvm_run)
1821 {
1822         u32 cpu_based_vm_exec_control;
1823
1824         vcpu->arch.interrupt_window_open =
1825                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1826                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1827
1828         if (vcpu->arch.interrupt_window_open &&
1829             vcpu->arch.irq_summary &&
1830             !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1831                 /*
1832                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1833                  */
1834                 kvm_do_inject_irq(vcpu);
1835
1836         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1837         if (!vcpu->arch.interrupt_window_open &&
1838             (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
1839                 /*
1840                  * Interrupts blocked.  Wait for unblock.
1841                  */
1842                 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1843         else
1844                 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1845         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1846 }
1847
1848 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1849 {
1850         int ret;
1851         struct kvm_userspace_memory_region tss_mem = {
1852                 .slot = 8,
1853                 .guest_phys_addr = addr,
1854                 .memory_size = PAGE_SIZE * 3,
1855                 .flags = 0,
1856         };
1857
1858         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1859         if (ret)
1860                 return ret;
1861         kvm->arch.tss_addr = addr;
1862         return 0;
1863 }
1864
1865 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1866 {
1867         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1868
1869         set_debugreg(dbg->bp[0], 0);
1870         set_debugreg(dbg->bp[1], 1);
1871         set_debugreg(dbg->bp[2], 2);
1872         set_debugreg(dbg->bp[3], 3);
1873
1874         if (dbg->singlestep) {
1875                 unsigned long flags;
1876
1877                 flags = vmcs_readl(GUEST_RFLAGS);
1878                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1879                 vmcs_writel(GUEST_RFLAGS, flags);
1880         }
1881 }
1882
1883 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1884                                   int vec, u32 err_code)
1885 {
1886         if (!vcpu->arch.rmode.active)
1887                 return 0;
1888
1889         /*
1890          * Instruction with address size override prefix opcode 0x67
1891          * Cause the #SS fault with 0 error code in VM86 mode.
1892          */
1893         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1894                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
1895                         return 1;
1896         return 0;
1897 }
1898
1899 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1900 {
1901         struct vcpu_vmx *vmx = to_vmx(vcpu);
1902         u32 intr_info, error_code;
1903         unsigned long cr2, rip;
1904         u32 vect_info;
1905         enum emulation_result er;
1906
1907         vect_info = vmx->idt_vectoring_info;
1908         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1909
1910         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1911                                                 !is_page_fault(intr_info))
1912                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1913                        "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1914
1915         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1916                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1917                 set_bit(irq, vcpu->arch.irq_pending);
1918                 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
1919         }
1920
1921         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1922                 return 1;  /* already handled by vmx_vcpu_run() */
1923
1924         if (is_no_device(intr_info)) {
1925                 vmx_fpu_activate(vcpu);
1926                 return 1;
1927         }
1928
1929         if (is_invalid_opcode(intr_info)) {
1930                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1931                 if (er != EMULATE_DONE)
1932                         kvm_queue_exception(vcpu, UD_VECTOR);
1933                 return 1;
1934         }
1935
1936         error_code = 0;
1937         rip = vmcs_readl(GUEST_RIP);
1938         if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1939                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1940         if (is_page_fault(intr_info)) {
1941                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1942                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
1943         }
1944
1945         if (vcpu->arch.rmode.active &&
1946             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1947                                                                 error_code)) {
1948                 if (vcpu->arch.halt_request) {
1949                         vcpu->arch.halt_request = 0;
1950                         return kvm_emulate_halt(vcpu);
1951                 }
1952                 return 1;
1953         }
1954
1955         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1956             (INTR_TYPE_EXCEPTION | 1)) {
1957                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1958                 return 0;
1959         }
1960         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1961         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1962         kvm_run->ex.error_code = error_code;
1963         return 0;
1964 }
1965
1966 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1967                                      struct kvm_run *kvm_run)
1968 {
1969         ++vcpu->stat.irq_exits;
1970         return 1;
1971 }
1972
1973 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1974 {
1975         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1976         return 0;
1977 }
1978
1979 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1980 {
1981         unsigned long exit_qualification;
1982         int size, down, in, string, rep;
1983         unsigned port;
1984
1985         ++vcpu->stat.io_exits;
1986         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1987         string = (exit_qualification & 16) != 0;
1988
1989         if (string) {
1990                 if (emulate_instruction(vcpu,
1991                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1992                         return 0;
1993                 return 1;
1994         }
1995
1996         size = (exit_qualification & 7) + 1;
1997         in = (exit_qualification & 8) != 0;
1998         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1999         rep = (exit_qualification & 32) != 0;
2000         port = exit_qualification >> 16;
2001
2002         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2003 }
2004
2005 static void
2006 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2007 {
2008         /*
2009          * Patch in the VMCALL instruction:
2010          */
2011         hypercall[0] = 0x0f;
2012         hypercall[1] = 0x01;
2013         hypercall[2] = 0xc1;
2014 }
2015
2016 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2017 {
2018         unsigned long exit_qualification;
2019         int cr;
2020         int reg;
2021
2022         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2023         cr = exit_qualification & 15;
2024         reg = (exit_qualification >> 8) & 15;
2025         switch ((exit_qualification >> 4) & 3) {
2026         case 0: /* mov to cr */
2027                 switch (cr) {
2028                 case 0:
2029                         vcpu_load_rsp_rip(vcpu);
2030                         set_cr0(vcpu, vcpu->arch.regs[reg]);
2031                         skip_emulated_instruction(vcpu);
2032                         return 1;
2033                 case 3:
2034                         vcpu_load_rsp_rip(vcpu);
2035                         set_cr3(vcpu, vcpu->arch.regs[reg]);
2036                         skip_emulated_instruction(vcpu);
2037                         return 1;
2038                 case 4:
2039                         vcpu_load_rsp_rip(vcpu);
2040                         set_cr4(vcpu, vcpu->arch.regs[reg]);
2041                         skip_emulated_instruction(vcpu);
2042                         return 1;
2043                 case 8:
2044                         vcpu_load_rsp_rip(vcpu);
2045                         set_cr8(vcpu, vcpu->arch.regs[reg]);
2046                         skip_emulated_instruction(vcpu);
2047                         if (irqchip_in_kernel(vcpu->kvm))
2048                                 return 1;
2049                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2050                         return 0;
2051                 };
2052                 break;
2053         case 2: /* clts */
2054                 vcpu_load_rsp_rip(vcpu);
2055                 vmx_fpu_deactivate(vcpu);
2056                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2057                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2058                 vmx_fpu_activate(vcpu);
2059                 skip_emulated_instruction(vcpu);
2060                 return 1;
2061         case 1: /*mov from cr*/
2062                 switch (cr) {
2063                 case 3:
2064                         vcpu_load_rsp_rip(vcpu);
2065                         vcpu->arch.regs[reg] = vcpu->arch.cr3;
2066                         vcpu_put_rsp_rip(vcpu);
2067                         skip_emulated_instruction(vcpu);
2068                         return 1;
2069                 case 8:
2070                         vcpu_load_rsp_rip(vcpu);
2071                         vcpu->arch.regs[reg] = get_cr8(vcpu);
2072                         vcpu_put_rsp_rip(vcpu);
2073                         skip_emulated_instruction(vcpu);
2074                         return 1;
2075                 }
2076                 break;
2077         case 3: /* lmsw */
2078                 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2079
2080                 skip_emulated_instruction(vcpu);
2081                 return 1;
2082         default:
2083                 break;
2084         }
2085         kvm_run->exit_reason = 0;
2086         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2087                (int)(exit_qualification >> 4) & 3, cr);
2088         return 0;
2089 }
2090
2091 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2092 {
2093         unsigned long exit_qualification;
2094         unsigned long val;
2095         int dr, reg;
2096
2097         /*
2098          * FIXME: this code assumes the host is debugging the guest.
2099          *        need to deal with guest debugging itself too.
2100          */
2101         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2102         dr = exit_qualification & 7;
2103         reg = (exit_qualification >> 8) & 15;
2104         vcpu_load_rsp_rip(vcpu);
2105         if (exit_qualification & 16) {
2106                 /* mov from dr */
2107                 switch (dr) {
2108                 case 6:
2109                         val = 0xffff0ff0;
2110                         break;
2111                 case 7:
2112                         val = 0x400;
2113                         break;
2114                 default:
2115                         val = 0;
2116                 }
2117                 vcpu->arch.regs[reg] = val;
2118         } else {
2119                 /* mov to dr */
2120         }
2121         vcpu_put_rsp_rip(vcpu);
2122         skip_emulated_instruction(vcpu);
2123         return 1;
2124 }
2125
2126 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2127 {
2128         kvm_emulate_cpuid(vcpu);
2129         return 1;
2130 }
2131
2132 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2133 {
2134         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2135         u64 data;
2136
2137         if (vmx_get_msr(vcpu, ecx, &data)) {
2138                 kvm_inject_gp(vcpu, 0);
2139                 return 1;
2140         }
2141
2142         /* FIXME: handling of bits 32:63 of rax, rdx */
2143         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2144         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2145         skip_emulated_instruction(vcpu);
2146         return 1;
2147 }
2148
2149 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2150 {
2151         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2152         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2153                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2154
2155         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2156                 kvm_inject_gp(vcpu, 0);
2157                 return 1;
2158         }
2159
2160         skip_emulated_instruction(vcpu);
2161         return 1;
2162 }
2163
2164 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2165                                       struct kvm_run *kvm_run)
2166 {
2167         return 1;
2168 }
2169
2170 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2171                                    struct kvm_run *kvm_run)
2172 {
2173         u32 cpu_based_vm_exec_control;
2174
2175         /* clear pending irq */
2176         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2177         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2178         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2179         /*
2180          * If the user space waits to inject interrupts, exit as soon as
2181          * possible
2182          */
2183         if (kvm_run->request_interrupt_window &&
2184             !vcpu->arch.irq_summary) {
2185                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2186                 ++vcpu->stat.irq_window_exits;
2187                 return 0;
2188         }
2189         return 1;
2190 }
2191
2192 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2193 {
2194         skip_emulated_instruction(vcpu);
2195         return kvm_emulate_halt(vcpu);
2196 }
2197
2198 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2199 {
2200         skip_emulated_instruction(vcpu);
2201         kvm_emulate_hypercall(vcpu);
2202         return 1;
2203 }
2204
2205 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2206 {
2207         skip_emulated_instruction(vcpu);
2208         /* TODO: Add support for VT-d/pass-through device */
2209         return 1;
2210 }
2211
2212 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2213 {
2214         u64 exit_qualification;
2215         enum emulation_result er;
2216         unsigned long offset;
2217
2218         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2219         offset = exit_qualification & 0xffful;
2220
2221         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2222
2223         if (er !=  EMULATE_DONE) {
2224                 printk(KERN_ERR
2225                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2226                        offset);
2227                 return -ENOTSUPP;
2228         }
2229         return 1;
2230 }
2231
2232 /*
2233  * The exit handlers return 1 if the exit was handled fully and guest execution
2234  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
2235  * to be done to userspace and return 0.
2236  */
2237 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2238                                       struct kvm_run *kvm_run) = {
2239         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
2240         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
2241         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
2242         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
2243         [EXIT_REASON_CR_ACCESS]               = handle_cr,
2244         [EXIT_REASON_DR_ACCESS]               = handle_dr,
2245         [EXIT_REASON_CPUID]                   = handle_cpuid,
2246         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
2247         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
2248         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
2249         [EXIT_REASON_HLT]                     = handle_halt,
2250         [EXIT_REASON_VMCALL]                  = handle_vmcall,
2251         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
2252         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
2253         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
2254 };
2255
2256 static const int kvm_vmx_max_exit_handlers =
2257         ARRAY_SIZE(kvm_vmx_exit_handlers);
2258
2259 /*
2260  * The guest has exited.  See if we can fix it or if we need userspace
2261  * assistance.
2262  */
2263 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2264 {
2265         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2266         struct vcpu_vmx *vmx = to_vmx(vcpu);
2267         u32 vectoring_info = vmx->idt_vectoring_info;
2268
2269         if (unlikely(vmx->fail)) {
2270                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2271                 kvm_run->fail_entry.hardware_entry_failure_reason
2272                         = vmcs_read32(VM_INSTRUCTION_ERROR);
2273                 return 0;
2274         }
2275
2276         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2277                                 exit_reason != EXIT_REASON_EXCEPTION_NMI)
2278                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2279                        "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
2280         if (exit_reason < kvm_vmx_max_exit_handlers
2281             && kvm_vmx_exit_handlers[exit_reason])
2282                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2283         else {
2284                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2285                 kvm_run->hw.hardware_exit_reason = exit_reason;
2286         }
2287         return 0;
2288 }
2289
2290 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2291 {
2292         int max_irr, tpr;
2293
2294         if (!vm_need_tpr_shadow(vcpu->kvm))
2295                 return;
2296
2297         if (!kvm_lapic_enabled(vcpu) ||
2298             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2299                 vmcs_write32(TPR_THRESHOLD, 0);
2300                 return;
2301         }
2302
2303         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2304         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2305 }
2306
2307 static void enable_irq_window(struct kvm_vcpu *vcpu)
2308 {
2309         u32 cpu_based_vm_exec_control;
2310
2311         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2312         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2313         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2314 }
2315
2316 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2317 {
2318         struct vcpu_vmx *vmx = to_vmx(vcpu);
2319         u32 idtv_info_field, intr_info_field;
2320         int has_ext_irq, interrupt_window_open;
2321         int vector;
2322
2323         update_tpr_threshold(vcpu);
2324
2325         has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2326         intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2327         idtv_info_field = vmx->idt_vectoring_info;
2328         if (intr_info_field & INTR_INFO_VALID_MASK) {
2329                 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2330                         /* TODO: fault when IDT_Vectoring */
2331                         if (printk_ratelimit())
2332                                 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2333                 }
2334                 if (has_ext_irq)
2335                         enable_irq_window(vcpu);
2336                 return;
2337         }
2338         if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2339                 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2340                     == INTR_TYPE_EXT_INTR
2341                     && vcpu->arch.rmode.active) {
2342                         u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2343
2344                         vmx_inject_irq(vcpu, vect);
2345                         if (unlikely(has_ext_irq))
2346                                 enable_irq_window(vcpu);
2347                         return;
2348                 }
2349
2350                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2351                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2352                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2353
2354                 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2355                         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2356                                 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2357                 if (unlikely(has_ext_irq))
2358                         enable_irq_window(vcpu);
2359                 return;
2360         }
2361         if (!has_ext_irq)
2362                 return;
2363         interrupt_window_open =
2364                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2365                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2366         if (interrupt_window_open) {
2367                 vector = kvm_cpu_get_interrupt(vcpu);
2368                 vmx_inject_irq(vcpu, vector);
2369                 kvm_timer_intr_post(vcpu, vector);
2370         } else
2371                 enable_irq_window(vcpu);
2372 }
2373
2374 /*
2375  * Failure to inject an interrupt should give us the information
2376  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
2377  * when fetching the interrupt redirection bitmap in the real-mode
2378  * tss, this doesn't happen.  So we do it ourselves.
2379  */
2380 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2381 {
2382         vmx->rmode.irq.pending = 0;
2383         if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2384                 return;
2385         vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2386         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2387                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2388                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2389                 return;
2390         }
2391         vmx->idt_vectoring_info =
2392                 VECTORING_INFO_VALID_MASK
2393                 | INTR_TYPE_EXT_INTR
2394                 | vmx->rmode.irq.vector;
2395 }
2396
2397 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2398 {
2399         struct vcpu_vmx *vmx = to_vmx(vcpu);
2400         u32 intr_info;
2401
2402         /*
2403          * Loading guest fpu may have cleared host cr0.ts
2404          */
2405         vmcs_writel(HOST_CR0, read_cr0());
2406
2407         asm(
2408                 /* Store host registers */
2409 #ifdef CONFIG_X86_64
2410                 "push %%rdx; push %%rbp;"
2411                 "push %%rcx \n\t"
2412 #else
2413                 "push %%edx; push %%ebp;"
2414                 "push %%ecx \n\t"
2415 #endif
2416                 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2417                 /* Check if vmlaunch of vmresume is needed */
2418                 "cmpl $0, %c[launched](%0) \n\t"
2419                 /* Load guest registers.  Don't clobber flags. */
2420 #ifdef CONFIG_X86_64
2421                 "mov %c[cr2](%0), %%rax \n\t"
2422                 "mov %%rax, %%cr2 \n\t"
2423                 "mov %c[rax](%0), %%rax \n\t"
2424                 "mov %c[rbx](%0), %%rbx \n\t"
2425                 "mov %c[rdx](%0), %%rdx \n\t"
2426                 "mov %c[rsi](%0), %%rsi \n\t"
2427                 "mov %c[rdi](%0), %%rdi \n\t"
2428                 "mov %c[rbp](%0), %%rbp \n\t"
2429                 "mov %c[r8](%0),  %%r8  \n\t"
2430                 "mov %c[r9](%0),  %%r9  \n\t"
2431                 "mov %c[r10](%0), %%r10 \n\t"
2432                 "mov %c[r11](%0), %%r11 \n\t"
2433                 "mov %c[r12](%0), %%r12 \n\t"
2434                 "mov %c[r13](%0), %%r13 \n\t"
2435                 "mov %c[r14](%0), %%r14 \n\t"
2436                 "mov %c[r15](%0), %%r15 \n\t"
2437                 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2438 #else
2439                 "mov %c[cr2](%0), %%eax \n\t"
2440                 "mov %%eax,   %%cr2 \n\t"
2441                 "mov %c[rax](%0), %%eax \n\t"
2442                 "mov %c[rbx](%0), %%ebx \n\t"
2443                 "mov %c[rdx](%0), %%edx \n\t"
2444                 "mov %c[rsi](%0), %%esi \n\t"
2445                 "mov %c[rdi](%0), %%edi \n\t"
2446                 "mov %c[rbp](%0), %%ebp \n\t"
2447                 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2448 #endif
2449                 /* Enter guest mode */
2450                 "jne .Llaunched \n\t"
2451                 ASM_VMX_VMLAUNCH "\n\t"
2452                 "jmp .Lkvm_vmx_return \n\t"
2453                 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2454                 ".Lkvm_vmx_return: "
2455                 /* Save guest registers, load host registers, keep flags */
2456 #ifdef CONFIG_X86_64
2457                 "xchg %0,     (%%rsp) \n\t"
2458                 "mov %%rax, %c[rax](%0) \n\t"
2459                 "mov %%rbx, %c[rbx](%0) \n\t"
2460                 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2461                 "mov %%rdx, %c[rdx](%0) \n\t"
2462                 "mov %%rsi, %c[rsi](%0) \n\t"
2463                 "mov %%rdi, %c[rdi](%0) \n\t"
2464                 "mov %%rbp, %c[rbp](%0) \n\t"
2465                 "mov %%r8,  %c[r8](%0) \n\t"
2466                 "mov %%r9,  %c[r9](%0) \n\t"
2467                 "mov %%r10, %c[r10](%0) \n\t"
2468                 "mov %%r11, %c[r11](%0) \n\t"
2469                 "mov %%r12, %c[r12](%0) \n\t"
2470                 "mov %%r13, %c[r13](%0) \n\t"
2471                 "mov %%r14, %c[r14](%0) \n\t"
2472                 "mov %%r15, %c[r15](%0) \n\t"
2473                 "mov %%cr2, %%rax   \n\t"
2474                 "mov %%rax, %c[cr2](%0) \n\t"
2475
2476                 "pop  %%rbp; pop  %%rbp; pop  %%rdx \n\t"
2477 #else
2478                 "xchg %0, (%%esp) \n\t"
2479                 "mov %%eax, %c[rax](%0) \n\t"
2480                 "mov %%ebx, %c[rbx](%0) \n\t"
2481                 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2482                 "mov %%edx, %c[rdx](%0) \n\t"
2483                 "mov %%esi, %c[rsi](%0) \n\t"
2484                 "mov %%edi, %c[rdi](%0) \n\t"
2485                 "mov %%ebp, %c[rbp](%0) \n\t"
2486                 "mov %%cr2, %%eax  \n\t"
2487                 "mov %%eax, %c[cr2](%0) \n\t"
2488
2489                 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
2490 #endif
2491                 "setbe %c[fail](%0) \n\t"
2492               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2493                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2494                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
2495                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
2496                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
2497                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
2498                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
2499                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
2500                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
2501                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
2502 #ifdef CONFIG_X86_64
2503                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
2504                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
2505                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
2506                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
2507                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
2508                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
2509                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
2510                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
2511 #endif
2512                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
2513               : "cc", "memory"
2514 #ifdef CONFIG_X86_64
2515                 , "rbx", "rdi", "rsi"
2516                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2517 #else
2518                 , "ebx", "edi", "rsi"
2519 #endif
2520               );
2521
2522         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2523         if (vmx->rmode.irq.pending)
2524                 fixup_rmode_irq(vmx);
2525
2526         vcpu->arch.interrupt_window_open =
2527                 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2528
2529         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2530         vmx->launched = 1;
2531
2532         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2533
2534         /* We need to handle NMIs before interrupts are enabled */
2535         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2536                 asm("int $2");
2537 }
2538
2539 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2540 {
2541         struct vcpu_vmx *vmx = to_vmx(vcpu);
2542
2543         if (vmx->vmcs) {
2544                 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2545                 free_vmcs(vmx->vmcs);
2546                 vmx->vmcs = NULL;
2547         }
2548 }
2549
2550 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2551 {
2552         struct vcpu_vmx *vmx = to_vmx(vcpu);
2553
2554         spin_lock(&vmx_vpid_lock);
2555         if (vmx->vpid != 0)
2556                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2557         spin_unlock(&vmx_vpid_lock);
2558         vmx_free_vmcs(vcpu);
2559         kfree(vmx->host_msrs);
2560         kfree(vmx->guest_msrs);
2561         kvm_vcpu_uninit(vcpu);
2562         kmem_cache_free(kvm_vcpu_cache, vmx);
2563 }
2564
2565 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2566 {
2567         int err;
2568         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2569         int cpu;
2570
2571         if (!vmx)
2572                 return ERR_PTR(-ENOMEM);
2573
2574         allocate_vpid(vmx);
2575
2576         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2577         if (err)
2578                 goto free_vcpu;
2579
2580         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2581         if (!vmx->guest_msrs) {
2582                 err = -ENOMEM;
2583                 goto uninit_vcpu;
2584         }
2585
2586         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2587         if (!vmx->host_msrs)
2588                 goto free_guest_msrs;
2589
2590         vmx->vmcs = alloc_vmcs();
2591         if (!vmx->vmcs)
2592                 goto free_msrs;
2593
2594         vmcs_clear(vmx->vmcs);
2595
2596         cpu = get_cpu();
2597         vmx_vcpu_load(&vmx->vcpu, cpu);
2598         err = vmx_vcpu_setup(vmx);
2599         vmx_vcpu_put(&vmx->vcpu);
2600         put_cpu();
2601         if (err)
2602                 goto free_vmcs;
2603         if (vm_need_virtualize_apic_accesses(kvm))
2604                 if (alloc_apic_access_page(kvm) != 0)
2605                         goto free_vmcs;
2606
2607         return &vmx->vcpu;
2608
2609 free_vmcs:
2610         free_vmcs(vmx->vmcs);
2611 free_msrs:
2612         kfree(vmx->host_msrs);
2613 free_guest_msrs:
2614         kfree(vmx->guest_msrs);
2615 uninit_vcpu:
2616         kvm_vcpu_uninit(&vmx->vcpu);
2617 free_vcpu:
2618         kmem_cache_free(kvm_vcpu_cache, vmx);
2619         return ERR_PTR(err);
2620 }
2621
2622 static void __init vmx_check_processor_compat(void *rtn)
2623 {
2624         struct vmcs_config vmcs_conf;
2625
2626         *(int *)rtn = 0;
2627         if (setup_vmcs_config(&vmcs_conf) < 0)
2628                 *(int *)rtn = -EIO;
2629         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2630                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2631                                 smp_processor_id());
2632                 *(int *)rtn = -EIO;
2633         }
2634 }
2635
2636 static struct kvm_x86_ops vmx_x86_ops = {
2637         .cpu_has_kvm_support = cpu_has_kvm_support,
2638         .disabled_by_bios = vmx_disabled_by_bios,
2639         .hardware_setup = hardware_setup,
2640         .hardware_unsetup = hardware_unsetup,
2641         .check_processor_compatibility = vmx_check_processor_compat,
2642         .hardware_enable = hardware_enable,
2643         .hardware_disable = hardware_disable,
2644         .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
2645
2646         .vcpu_create = vmx_create_vcpu,
2647         .vcpu_free = vmx_free_vcpu,
2648         .vcpu_reset = vmx_vcpu_reset,
2649
2650         .prepare_guest_switch = vmx_save_host_state,
2651         .vcpu_load = vmx_vcpu_load,
2652         .vcpu_put = vmx_vcpu_put,
2653         .vcpu_decache = vmx_vcpu_decache,
2654
2655         .set_guest_debug = set_guest_debug,
2656         .guest_debug_pre = kvm_guest_debug_pre,
2657         .get_msr = vmx_get_msr,
2658         .set_msr = vmx_set_msr,
2659         .get_segment_base = vmx_get_segment_base,
2660         .get_segment = vmx_get_segment,
2661         .set_segment = vmx_set_segment,
2662         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2663         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2664         .set_cr0 = vmx_set_cr0,
2665         .set_cr3 = vmx_set_cr3,
2666         .set_cr4 = vmx_set_cr4,
2667 #ifdef CONFIG_X86_64
2668         .set_efer = vmx_set_efer,
2669 #endif
2670         .get_idt = vmx_get_idt,
2671         .set_idt = vmx_set_idt,
2672         .get_gdt = vmx_get_gdt,
2673         .set_gdt = vmx_set_gdt,
2674         .cache_regs = vcpu_load_rsp_rip,
2675         .decache_regs = vcpu_put_rsp_rip,
2676         .get_rflags = vmx_get_rflags,
2677         .set_rflags = vmx_set_rflags,
2678
2679         .tlb_flush = vmx_flush_tlb,
2680
2681         .run = vmx_vcpu_run,
2682         .handle_exit = kvm_handle_exit,
2683         .skip_emulated_instruction = skip_emulated_instruction,
2684         .patch_hypercall = vmx_patch_hypercall,
2685         .get_irq = vmx_get_irq,
2686         .set_irq = vmx_inject_irq,
2687         .queue_exception = vmx_queue_exception,
2688         .exception_injected = vmx_exception_injected,
2689         .inject_pending_irq = vmx_intr_assist,
2690         .inject_pending_vectors = do_interrupt_requests,
2691
2692         .set_tss_addr = vmx_set_tss_addr,
2693 };
2694
2695 static int __init vmx_init(void)
2696 {
2697         void *iova;
2698         int r;
2699
2700         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2701         if (!vmx_io_bitmap_a)
2702                 return -ENOMEM;
2703
2704         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2705         if (!vmx_io_bitmap_b) {
2706                 r = -ENOMEM;
2707                 goto out;
2708         }
2709
2710         /*
2711          * Allow direct access to the PC debug port (it is often used for I/O
2712          * delays, but the vmexits simply slow things down).
2713          */
2714         iova = kmap(vmx_io_bitmap_a);
2715         memset(iova, 0xff, PAGE_SIZE);
2716         clear_bit(0x80, iova);
2717         kunmap(vmx_io_bitmap_a);
2718
2719         iova = kmap(vmx_io_bitmap_b);
2720         memset(iova, 0xff, PAGE_SIZE);
2721         kunmap(vmx_io_bitmap_b);
2722
2723         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
2724
2725         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2726         if (r)
2727                 goto out1;
2728
2729         if (bypass_guest_pf)
2730                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2731
2732         return 0;
2733
2734 out1:
2735         __free_page(vmx_io_bitmap_b);
2736 out:
2737         __free_page(vmx_io_bitmap_a);
2738         return r;
2739 }
2740
2741 static void __exit vmx_exit(void)
2742 {
2743         __free_page(vmx_io_bitmap_b);
2744         __free_page(vmx_io_bitmap_a);
2745
2746         kvm_exit();
2747 }
2748
2749 module_init(vmx_init)
2750 module_exit(vmx_exit)