KVM: Introduce kvm_memory_slot::arch and move lpage_info into it
[linux-2.6.git] / arch / x86 / kvm / mmu.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * MMU support
8  *
9  * Copyright (C) 2006 Qumranet, Inc.
10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11  *
12  * Authors:
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Avi Kivity   <avi@qumranet.com>
15  *
16  * This work is licensed under the terms of the GNU GPL, version 2.  See
17  * the COPYING file in the top-level directory.
18  *
19  */
20
21 #include "irq.h"
22 #include "mmu.h"
23 #include "x86.h"
24 #include "kvm_cache_regs.h"
25
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
29 #include <linux/mm.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
38
39 #include <asm/page.h>
40 #include <asm/cmpxchg.h>
41 #include <asm/io.h>
42 #include <asm/vmx.h>
43
44 /*
45  * When setting this variable to true it enables Two-Dimensional-Paging
46  * where the hardware walks 2 page tables:
47  * 1. the guest-virtual to guest-physical
48  * 2. while doing 1. it walks guest-physical to host-physical
49  * If the hardware supports that we don't need to do shadow paging.
50  */
51 bool tdp_enabled = false;
52
53 enum {
54         AUDIT_PRE_PAGE_FAULT,
55         AUDIT_POST_PAGE_FAULT,
56         AUDIT_PRE_PTE_WRITE,
57         AUDIT_POST_PTE_WRITE,
58         AUDIT_PRE_SYNC,
59         AUDIT_POST_SYNC
60 };
61
62 #undef MMU_DEBUG
63
64 #ifdef MMU_DEBUG
65
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
68
69 #else
70
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
73
74 #endif
75
76 #ifdef MMU_DEBUG
77 static bool dbg = 0;
78 module_param(dbg, bool, 0644);
79 #endif
80
81 #ifndef MMU_DEBUG
82 #define ASSERT(x) do { } while (0)
83 #else
84 #define ASSERT(x)                                                       \
85         if (!(x)) {                                                     \
86                 printk(KERN_WARNING "assertion failed %s:%d: %s\n",     \
87                        __FILE__, __LINE__, #x);                         \
88         }
89 #endif
90
91 #define PTE_PREFETCH_NUM                8
92
93 #define PT_FIRST_AVAIL_BITS_SHIFT 9
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
95
96 #define PT64_LEVEL_BITS 9
97
98 #define PT64_LEVEL_SHIFT(level) \
99                 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
100
101 #define PT64_INDEX(address, level)\
102         (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
103
104
105 #define PT32_LEVEL_BITS 10
106
107 #define PT32_LEVEL_SHIFT(level) \
108                 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
109
110 #define PT32_LVL_OFFSET_MASK(level) \
111         (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112                                                 * PT32_LEVEL_BITS))) - 1))
113
114 #define PT32_INDEX(address, level)\
115         (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
116
117
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123                                                 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125         (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126                                                 * PT64_LEVEL_BITS))) - 1))
127
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133                                             * PT32_LEVEL_BITS))) - 1))
134
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
136                         | PT64_NX_MASK)
137
138 #define PTE_LIST_EXT 4
139
140 #define ACC_EXEC_MASK    1
141 #define ACC_WRITE_MASK   PT_WRITABLE_MASK
142 #define ACC_USER_MASK    PT_USER_MASK
143 #define ACC_ALL          (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
144
145 #include <trace/events/kvm.h>
146
147 #define CREATE_TRACE_POINTS
148 #include "mmutrace.h"
149
150 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
151
152 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153
154 struct pte_list_desc {
155         u64 *sptes[PTE_LIST_EXT];
156         struct pte_list_desc *more;
157 };
158
159 struct kvm_shadow_walk_iterator {
160         u64 addr;
161         hpa_t shadow_addr;
162         u64 *sptep;
163         int level;
164         unsigned index;
165 };
166
167 #define for_each_shadow_entry(_vcpu, _addr, _walker)    \
168         for (shadow_walk_init(&(_walker), _vcpu, _addr);        \
169              shadow_walk_okay(&(_walker));                      \
170              shadow_walk_next(&(_walker)))
171
172 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte)     \
173         for (shadow_walk_init(&(_walker), _vcpu, _addr);                \
174              shadow_walk_okay(&(_walker)) &&                            \
175                 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; });  \
176              __shadow_walk_next(&(_walker), spte))
177
178 static struct kmem_cache *pte_list_desc_cache;
179 static struct kmem_cache *mmu_page_header_cache;
180 static struct percpu_counter kvm_total_used_mmu_pages;
181
182 static u64 __read_mostly shadow_nx_mask;
183 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
184 static u64 __read_mostly shadow_user_mask;
185 static u64 __read_mostly shadow_accessed_mask;
186 static u64 __read_mostly shadow_dirty_mask;
187 static u64 __read_mostly shadow_mmio_mask;
188
189 static void mmu_spte_set(u64 *sptep, u64 spte);
190
191 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
192 {
193         shadow_mmio_mask = mmio_mask;
194 }
195 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
196
197 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
198 {
199         access &= ACC_WRITE_MASK | ACC_USER_MASK;
200
201         trace_mark_mmio_spte(sptep, gfn, access);
202         mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
203 }
204
205 static bool is_mmio_spte(u64 spte)
206 {
207         return (spte & shadow_mmio_mask) == shadow_mmio_mask;
208 }
209
210 static gfn_t get_mmio_spte_gfn(u64 spte)
211 {
212         return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
213 }
214
215 static unsigned get_mmio_spte_access(u64 spte)
216 {
217         return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
218 }
219
220 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
221 {
222         if (unlikely(is_noslot_pfn(pfn))) {
223                 mark_mmio_spte(sptep, gfn, access);
224                 return true;
225         }
226
227         return false;
228 }
229
230 static inline u64 rsvd_bits(int s, int e)
231 {
232         return ((1ULL << (e - s + 1)) - 1) << s;
233 }
234
235 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
236                 u64 dirty_mask, u64 nx_mask, u64 x_mask)
237 {
238         shadow_user_mask = user_mask;
239         shadow_accessed_mask = accessed_mask;
240         shadow_dirty_mask = dirty_mask;
241         shadow_nx_mask = nx_mask;
242         shadow_x_mask = x_mask;
243 }
244 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
245
246 static int is_cpuid_PSE36(void)
247 {
248         return 1;
249 }
250
251 static int is_nx(struct kvm_vcpu *vcpu)
252 {
253         return vcpu->arch.efer & EFER_NX;
254 }
255
256 static int is_shadow_present_pte(u64 pte)
257 {
258         return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
259 }
260
261 static int is_large_pte(u64 pte)
262 {
263         return pte & PT_PAGE_SIZE_MASK;
264 }
265
266 static int is_dirty_gpte(unsigned long pte)
267 {
268         return pte & PT_DIRTY_MASK;
269 }
270
271 static int is_rmap_spte(u64 pte)
272 {
273         return is_shadow_present_pte(pte);
274 }
275
276 static int is_last_spte(u64 pte, int level)
277 {
278         if (level == PT_PAGE_TABLE_LEVEL)
279                 return 1;
280         if (is_large_pte(pte))
281                 return 1;
282         return 0;
283 }
284
285 static pfn_t spte_to_pfn(u64 pte)
286 {
287         return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
288 }
289
290 static gfn_t pse36_gfn_delta(u32 gpte)
291 {
292         int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
293
294         return (gpte & PT32_DIR_PSE36_MASK) << shift;
295 }
296
297 #ifdef CONFIG_X86_64
298 static void __set_spte(u64 *sptep, u64 spte)
299 {
300         *sptep = spte;
301 }
302
303 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
304 {
305         *sptep = spte;
306 }
307
308 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
309 {
310         return xchg(sptep, spte);
311 }
312
313 static u64 __get_spte_lockless(u64 *sptep)
314 {
315         return ACCESS_ONCE(*sptep);
316 }
317
318 static bool __check_direct_spte_mmio_pf(u64 spte)
319 {
320         /* It is valid if the spte is zapped. */
321         return spte == 0ull;
322 }
323 #else
324 union split_spte {
325         struct {
326                 u32 spte_low;
327                 u32 spte_high;
328         };
329         u64 spte;
330 };
331
332 static void count_spte_clear(u64 *sptep, u64 spte)
333 {
334         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
335
336         if (is_shadow_present_pte(spte))
337                 return;
338
339         /* Ensure the spte is completely set before we increase the count */
340         smp_wmb();
341         sp->clear_spte_count++;
342 }
343
344 static void __set_spte(u64 *sptep, u64 spte)
345 {
346         union split_spte *ssptep, sspte;
347
348         ssptep = (union split_spte *)sptep;
349         sspte = (union split_spte)spte;
350
351         ssptep->spte_high = sspte.spte_high;
352
353         /*
354          * If we map the spte from nonpresent to present, We should store
355          * the high bits firstly, then set present bit, so cpu can not
356          * fetch this spte while we are setting the spte.
357          */
358         smp_wmb();
359
360         ssptep->spte_low = sspte.spte_low;
361 }
362
363 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
364 {
365         union split_spte *ssptep, sspte;
366
367         ssptep = (union split_spte *)sptep;
368         sspte = (union split_spte)spte;
369
370         ssptep->spte_low = sspte.spte_low;
371
372         /*
373          * If we map the spte from present to nonpresent, we should clear
374          * present bit firstly to avoid vcpu fetch the old high bits.
375          */
376         smp_wmb();
377
378         ssptep->spte_high = sspte.spte_high;
379         count_spte_clear(sptep, spte);
380 }
381
382 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
383 {
384         union split_spte *ssptep, sspte, orig;
385
386         ssptep = (union split_spte *)sptep;
387         sspte = (union split_spte)spte;
388
389         /* xchg acts as a barrier before the setting of the high bits */
390         orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
391         orig.spte_high = ssptep->spte_high;
392         ssptep->spte_high = sspte.spte_high;
393         count_spte_clear(sptep, spte);
394
395         return orig.spte;
396 }
397
398 /*
399  * The idea using the light way get the spte on x86_32 guest is from
400  * gup_get_pte(arch/x86/mm/gup.c).
401  * The difference is we can not catch the spte tlb flush if we leave
402  * guest mode, so we emulate it by increase clear_spte_count when spte
403  * is cleared.
404  */
405 static u64 __get_spte_lockless(u64 *sptep)
406 {
407         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
408         union split_spte spte, *orig = (union split_spte *)sptep;
409         int count;
410
411 retry:
412         count = sp->clear_spte_count;
413         smp_rmb();
414
415         spte.spte_low = orig->spte_low;
416         smp_rmb();
417
418         spte.spte_high = orig->spte_high;
419         smp_rmb();
420
421         if (unlikely(spte.spte_low != orig->spte_low ||
422               count != sp->clear_spte_count))
423                 goto retry;
424
425         return spte.spte;
426 }
427
428 static bool __check_direct_spte_mmio_pf(u64 spte)
429 {
430         union split_spte sspte = (union split_spte)spte;
431         u32 high_mmio_mask = shadow_mmio_mask >> 32;
432
433         /* It is valid if the spte is zapped. */
434         if (spte == 0ull)
435                 return true;
436
437         /* It is valid if the spte is being zapped. */
438         if (sspte.spte_low == 0ull &&
439             (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
440                 return true;
441
442         return false;
443 }
444 #endif
445
446 static bool spte_has_volatile_bits(u64 spte)
447 {
448         if (!shadow_accessed_mask)
449                 return false;
450
451         if (!is_shadow_present_pte(spte))
452                 return false;
453
454         if ((spte & shadow_accessed_mask) &&
455               (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
456                 return false;
457
458         return true;
459 }
460
461 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
462 {
463         return (old_spte & bit_mask) && !(new_spte & bit_mask);
464 }
465
466 /* Rules for using mmu_spte_set:
467  * Set the sptep from nonpresent to present.
468  * Note: the sptep being assigned *must* be either not present
469  * or in a state where the hardware will not attempt to update
470  * the spte.
471  */
472 static void mmu_spte_set(u64 *sptep, u64 new_spte)
473 {
474         WARN_ON(is_shadow_present_pte(*sptep));
475         __set_spte(sptep, new_spte);
476 }
477
478 /* Rules for using mmu_spte_update:
479  * Update the state bits, it means the mapped pfn is not changged.
480  */
481 static void mmu_spte_update(u64 *sptep, u64 new_spte)
482 {
483         u64 mask, old_spte = *sptep;
484
485         WARN_ON(!is_rmap_spte(new_spte));
486
487         if (!is_shadow_present_pte(old_spte))
488                 return mmu_spte_set(sptep, new_spte);
489
490         new_spte |= old_spte & shadow_dirty_mask;
491
492         mask = shadow_accessed_mask;
493         if (is_writable_pte(old_spte))
494                 mask |= shadow_dirty_mask;
495
496         if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask)
497                 __update_clear_spte_fast(sptep, new_spte);
498         else
499                 old_spte = __update_clear_spte_slow(sptep, new_spte);
500
501         if (!shadow_accessed_mask)
502                 return;
503
504         if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
505                 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
506         if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
507                 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
508 }
509
510 /*
511  * Rules for using mmu_spte_clear_track_bits:
512  * It sets the sptep from present to nonpresent, and track the
513  * state bits, it is used to clear the last level sptep.
514  */
515 static int mmu_spte_clear_track_bits(u64 *sptep)
516 {
517         pfn_t pfn;
518         u64 old_spte = *sptep;
519
520         if (!spte_has_volatile_bits(old_spte))
521                 __update_clear_spte_fast(sptep, 0ull);
522         else
523                 old_spte = __update_clear_spte_slow(sptep, 0ull);
524
525         if (!is_rmap_spte(old_spte))
526                 return 0;
527
528         pfn = spte_to_pfn(old_spte);
529         if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
530                 kvm_set_pfn_accessed(pfn);
531         if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
532                 kvm_set_pfn_dirty(pfn);
533         return 1;
534 }
535
536 /*
537  * Rules for using mmu_spte_clear_no_track:
538  * Directly clear spte without caring the state bits of sptep,
539  * it is used to set the upper level spte.
540  */
541 static void mmu_spte_clear_no_track(u64 *sptep)
542 {
543         __update_clear_spte_fast(sptep, 0ull);
544 }
545
546 static u64 mmu_spte_get_lockless(u64 *sptep)
547 {
548         return __get_spte_lockless(sptep);
549 }
550
551 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
552 {
553         rcu_read_lock();
554         atomic_inc(&vcpu->kvm->arch.reader_counter);
555
556         /* Increase the counter before walking shadow page table */
557         smp_mb__after_atomic_inc();
558 }
559
560 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
561 {
562         /* Decrease the counter after walking shadow page table finished */
563         smp_mb__before_atomic_dec();
564         atomic_dec(&vcpu->kvm->arch.reader_counter);
565         rcu_read_unlock();
566 }
567
568 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
569                                   struct kmem_cache *base_cache, int min)
570 {
571         void *obj;
572
573         if (cache->nobjs >= min)
574                 return 0;
575         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
576                 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
577                 if (!obj)
578                         return -ENOMEM;
579                 cache->objects[cache->nobjs++] = obj;
580         }
581         return 0;
582 }
583
584 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
585 {
586         return cache->nobjs;
587 }
588
589 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
590                                   struct kmem_cache *cache)
591 {
592         while (mc->nobjs)
593                 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
594 }
595
596 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
597                                        int min)
598 {
599         void *page;
600
601         if (cache->nobjs >= min)
602                 return 0;
603         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
604                 page = (void *)__get_free_page(GFP_KERNEL);
605                 if (!page)
606                         return -ENOMEM;
607                 cache->objects[cache->nobjs++] = page;
608         }
609         return 0;
610 }
611
612 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
613 {
614         while (mc->nobjs)
615                 free_page((unsigned long)mc->objects[--mc->nobjs]);
616 }
617
618 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
619 {
620         int r;
621
622         r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
623                                    pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
624         if (r)
625                 goto out;
626         r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
627         if (r)
628                 goto out;
629         r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
630                                    mmu_page_header_cache, 4);
631 out:
632         return r;
633 }
634
635 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
636 {
637         mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
638                                 pte_list_desc_cache);
639         mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
640         mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
641                                 mmu_page_header_cache);
642 }
643
644 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
645                                     size_t size)
646 {
647         void *p;
648
649         BUG_ON(!mc->nobjs);
650         p = mc->objects[--mc->nobjs];
651         return p;
652 }
653
654 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
655 {
656         return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache,
657                                       sizeof(struct pte_list_desc));
658 }
659
660 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
661 {
662         kmem_cache_free(pte_list_desc_cache, pte_list_desc);
663 }
664
665 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
666 {
667         if (!sp->role.direct)
668                 return sp->gfns[index];
669
670         return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
671 }
672
673 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
674 {
675         if (sp->role.direct)
676                 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
677         else
678                 sp->gfns[index] = gfn;
679 }
680
681 /*
682  * Return the pointer to the large page information for a given gfn,
683  * handling slots that are not large page aligned.
684  */
685 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
686                                               struct kvm_memory_slot *slot,
687                                               int level)
688 {
689         unsigned long idx;
690
691         idx = gfn_to_index(gfn, slot->base_gfn, level);
692         return &slot->arch.lpage_info[level - 2][idx];
693 }
694
695 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
696 {
697         struct kvm_memory_slot *slot;
698         struct kvm_lpage_info *linfo;
699         int i;
700
701         slot = gfn_to_memslot(kvm, gfn);
702         for (i = PT_DIRECTORY_LEVEL;
703              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
704                 linfo = lpage_info_slot(gfn, slot, i);
705                 linfo->write_count += 1;
706         }
707         kvm->arch.indirect_shadow_pages++;
708 }
709
710 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
711 {
712         struct kvm_memory_slot *slot;
713         struct kvm_lpage_info *linfo;
714         int i;
715
716         slot = gfn_to_memslot(kvm, gfn);
717         for (i = PT_DIRECTORY_LEVEL;
718              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
719                 linfo = lpage_info_slot(gfn, slot, i);
720                 linfo->write_count -= 1;
721                 WARN_ON(linfo->write_count < 0);
722         }
723         kvm->arch.indirect_shadow_pages--;
724 }
725
726 static int has_wrprotected_page(struct kvm *kvm,
727                                 gfn_t gfn,
728                                 int level)
729 {
730         struct kvm_memory_slot *slot;
731         struct kvm_lpage_info *linfo;
732
733         slot = gfn_to_memslot(kvm, gfn);
734         if (slot) {
735                 linfo = lpage_info_slot(gfn, slot, level);
736                 return linfo->write_count;
737         }
738
739         return 1;
740 }
741
742 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
743 {
744         unsigned long page_size;
745         int i, ret = 0;
746
747         page_size = kvm_host_page_size(kvm, gfn);
748
749         for (i = PT_PAGE_TABLE_LEVEL;
750              i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
751                 if (page_size >= KVM_HPAGE_SIZE(i))
752                         ret = i;
753                 else
754                         break;
755         }
756
757         return ret;
758 }
759
760 static struct kvm_memory_slot *
761 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
762                             bool no_dirty_log)
763 {
764         struct kvm_memory_slot *slot;
765
766         slot = gfn_to_memslot(vcpu->kvm, gfn);
767         if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
768               (no_dirty_log && slot->dirty_bitmap))
769                 slot = NULL;
770
771         return slot;
772 }
773
774 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
775 {
776         return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
777 }
778
779 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
780 {
781         int host_level, level, max_level;
782
783         host_level = host_mapping_level(vcpu->kvm, large_gfn);
784
785         if (host_level == PT_PAGE_TABLE_LEVEL)
786                 return host_level;
787
788         max_level = kvm_x86_ops->get_lpage_level() < host_level ?
789                 kvm_x86_ops->get_lpage_level() : host_level;
790
791         for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
792                 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
793                         break;
794
795         return level - 1;
796 }
797
798 /*
799  * Pte mapping structures:
800  *
801  * If pte_list bit zero is zero, then pte_list point to the spte.
802  *
803  * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
804  * pte_list_desc containing more mappings.
805  *
806  * Returns the number of pte entries before the spte was added or zero if
807  * the spte was not added.
808  *
809  */
810 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
811                         unsigned long *pte_list)
812 {
813         struct pte_list_desc *desc;
814         int i, count = 0;
815
816         if (!*pte_list) {
817                 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
818                 *pte_list = (unsigned long)spte;
819         } else if (!(*pte_list & 1)) {
820                 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
821                 desc = mmu_alloc_pte_list_desc(vcpu);
822                 desc->sptes[0] = (u64 *)*pte_list;
823                 desc->sptes[1] = spte;
824                 *pte_list = (unsigned long)desc | 1;
825                 ++count;
826         } else {
827                 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
828                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
829                 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
830                         desc = desc->more;
831                         count += PTE_LIST_EXT;
832                 }
833                 if (desc->sptes[PTE_LIST_EXT-1]) {
834                         desc->more = mmu_alloc_pte_list_desc(vcpu);
835                         desc = desc->more;
836                 }
837                 for (i = 0; desc->sptes[i]; ++i)
838                         ++count;
839                 desc->sptes[i] = spte;
840         }
841         return count;
842 }
843
844 static u64 *pte_list_next(unsigned long *pte_list, u64 *spte)
845 {
846         struct pte_list_desc *desc;
847         u64 *prev_spte;
848         int i;
849
850         if (!*pte_list)
851                 return NULL;
852         else if (!(*pte_list & 1)) {
853                 if (!spte)
854                         return (u64 *)*pte_list;
855                 return NULL;
856         }
857         desc = (struct pte_list_desc *)(*pte_list & ~1ul);
858         prev_spte = NULL;
859         while (desc) {
860                 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
861                         if (prev_spte == spte)
862                                 return desc->sptes[i];
863                         prev_spte = desc->sptes[i];
864                 }
865                 desc = desc->more;
866         }
867         return NULL;
868 }
869
870 static void
871 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
872                            int i, struct pte_list_desc *prev_desc)
873 {
874         int j;
875
876         for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
877                 ;
878         desc->sptes[i] = desc->sptes[j];
879         desc->sptes[j] = NULL;
880         if (j != 0)
881                 return;
882         if (!prev_desc && !desc->more)
883                 *pte_list = (unsigned long)desc->sptes[0];
884         else
885                 if (prev_desc)
886                         prev_desc->more = desc->more;
887                 else
888                         *pte_list = (unsigned long)desc->more | 1;
889         mmu_free_pte_list_desc(desc);
890 }
891
892 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
893 {
894         struct pte_list_desc *desc;
895         struct pte_list_desc *prev_desc;
896         int i;
897
898         if (!*pte_list) {
899                 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
900                 BUG();
901         } else if (!(*pte_list & 1)) {
902                 rmap_printk("pte_list_remove:  %p 1->0\n", spte);
903                 if ((u64 *)*pte_list != spte) {
904                         printk(KERN_ERR "pte_list_remove:  %p 1->BUG\n", spte);
905                         BUG();
906                 }
907                 *pte_list = 0;
908         } else {
909                 rmap_printk("pte_list_remove:  %p many->many\n", spte);
910                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
911                 prev_desc = NULL;
912                 while (desc) {
913                         for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
914                                 if (desc->sptes[i] == spte) {
915                                         pte_list_desc_remove_entry(pte_list,
916                                                                desc, i,
917                                                                prev_desc);
918                                         return;
919                                 }
920                         prev_desc = desc;
921                         desc = desc->more;
922                 }
923                 pr_err("pte_list_remove: %p many->many\n", spte);
924                 BUG();
925         }
926 }
927
928 typedef void (*pte_list_walk_fn) (u64 *spte);
929 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
930 {
931         struct pte_list_desc *desc;
932         int i;
933
934         if (!*pte_list)
935                 return;
936
937         if (!(*pte_list & 1))
938                 return fn((u64 *)*pte_list);
939
940         desc = (struct pte_list_desc *)(*pte_list & ~1ul);
941         while (desc) {
942                 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
943                         fn(desc->sptes[i]);
944                 desc = desc->more;
945         }
946 }
947
948 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
949                                     struct kvm_memory_slot *slot)
950 {
951         struct kvm_lpage_info *linfo;
952
953         if (likely(level == PT_PAGE_TABLE_LEVEL))
954                 return &slot->rmap[gfn - slot->base_gfn];
955
956         linfo = lpage_info_slot(gfn, slot, level);
957         return &linfo->rmap_pde;
958 }
959
960 /*
961  * Take gfn and return the reverse mapping to it.
962  */
963 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
964 {
965         struct kvm_memory_slot *slot;
966
967         slot = gfn_to_memslot(kvm, gfn);
968         return __gfn_to_rmap(gfn, level, slot);
969 }
970
971 static bool rmap_can_add(struct kvm_vcpu *vcpu)
972 {
973         struct kvm_mmu_memory_cache *cache;
974
975         cache = &vcpu->arch.mmu_pte_list_desc_cache;
976         return mmu_memory_cache_free_objects(cache);
977 }
978
979 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
980 {
981         struct kvm_mmu_page *sp;
982         unsigned long *rmapp;
983
984         sp = page_header(__pa(spte));
985         kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
986         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
987         return pte_list_add(vcpu, spte, rmapp);
988 }
989
990 static u64 *rmap_next(unsigned long *rmapp, u64 *spte)
991 {
992         return pte_list_next(rmapp, spte);
993 }
994
995 static void rmap_remove(struct kvm *kvm, u64 *spte)
996 {
997         struct kvm_mmu_page *sp;
998         gfn_t gfn;
999         unsigned long *rmapp;
1000
1001         sp = page_header(__pa(spte));
1002         gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1003         rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1004         pte_list_remove(spte, rmapp);
1005 }
1006
1007 static void drop_spte(struct kvm *kvm, u64 *sptep)
1008 {
1009         if (mmu_spte_clear_track_bits(sptep))
1010                 rmap_remove(kvm, sptep);
1011 }
1012
1013 int kvm_mmu_rmap_write_protect(struct kvm *kvm, u64 gfn,
1014                                struct kvm_memory_slot *slot)
1015 {
1016         unsigned long *rmapp;
1017         u64 *spte;
1018         int i, write_protected = 0;
1019
1020         rmapp = __gfn_to_rmap(gfn, PT_PAGE_TABLE_LEVEL, slot);
1021         spte = rmap_next(rmapp, NULL);
1022         while (spte) {
1023                 BUG_ON(!(*spte & PT_PRESENT_MASK));
1024                 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
1025                 if (is_writable_pte(*spte)) {
1026                         mmu_spte_update(spte, *spte & ~PT_WRITABLE_MASK);
1027                         write_protected = 1;
1028                 }
1029                 spte = rmap_next(rmapp, spte);
1030         }
1031
1032         /* check for huge page mappings */
1033         for (i = PT_DIRECTORY_LEVEL;
1034              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1035                 rmapp = __gfn_to_rmap(gfn, i, slot);
1036                 spte = rmap_next(rmapp, NULL);
1037                 while (spte) {
1038                         BUG_ON(!(*spte & PT_PRESENT_MASK));
1039                         BUG_ON(!is_large_pte(*spte));
1040                         pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
1041                         if (is_writable_pte(*spte)) {
1042                                 drop_spte(kvm, spte);
1043                                 --kvm->stat.lpages;
1044                                 spte = NULL;
1045                                 write_protected = 1;
1046                         }
1047                         spte = rmap_next(rmapp, spte);
1048                 }
1049         }
1050
1051         return write_protected;
1052 }
1053
1054 static int rmap_write_protect(struct kvm *kvm, u64 gfn)
1055 {
1056         struct kvm_memory_slot *slot;
1057
1058         slot = gfn_to_memslot(kvm, gfn);
1059         return kvm_mmu_rmap_write_protect(kvm, gfn, slot);
1060 }
1061
1062 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1063                            unsigned long data)
1064 {
1065         u64 *spte;
1066         int need_tlb_flush = 0;
1067
1068         while ((spte = rmap_next(rmapp, NULL))) {
1069                 BUG_ON(!(*spte & PT_PRESENT_MASK));
1070                 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
1071                 drop_spte(kvm, spte);
1072                 need_tlb_flush = 1;
1073         }
1074         return need_tlb_flush;
1075 }
1076
1077 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1078                              unsigned long data)
1079 {
1080         int need_flush = 0;
1081         u64 *spte, new_spte;
1082         pte_t *ptep = (pte_t *)data;
1083         pfn_t new_pfn;
1084
1085         WARN_ON(pte_huge(*ptep));
1086         new_pfn = pte_pfn(*ptep);
1087         spte = rmap_next(rmapp, NULL);
1088         while (spte) {
1089                 BUG_ON(!is_shadow_present_pte(*spte));
1090                 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
1091                 need_flush = 1;
1092                 if (pte_write(*ptep)) {
1093                         drop_spte(kvm, spte);
1094                         spte = rmap_next(rmapp, NULL);
1095                 } else {
1096                         new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
1097                         new_spte |= (u64)new_pfn << PAGE_SHIFT;
1098
1099                         new_spte &= ~PT_WRITABLE_MASK;
1100                         new_spte &= ~SPTE_HOST_WRITEABLE;
1101                         new_spte &= ~shadow_accessed_mask;
1102                         mmu_spte_clear_track_bits(spte);
1103                         mmu_spte_set(spte, new_spte);
1104                         spte = rmap_next(rmapp, spte);
1105                 }
1106         }
1107         if (need_flush)
1108                 kvm_flush_remote_tlbs(kvm);
1109
1110         return 0;
1111 }
1112
1113 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1114                           unsigned long data,
1115                           int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1116                                          unsigned long data))
1117 {
1118         int j;
1119         int ret;
1120         int retval = 0;
1121         struct kvm_memslots *slots;
1122         struct kvm_memory_slot *memslot;
1123
1124         slots = kvm_memslots(kvm);
1125
1126         kvm_for_each_memslot(memslot, slots) {
1127                 unsigned long start = memslot->userspace_addr;
1128                 unsigned long end;
1129
1130                 end = start + (memslot->npages << PAGE_SHIFT);
1131                 if (hva >= start && hva < end) {
1132                         gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
1133                         gfn_t gfn = memslot->base_gfn + gfn_offset;
1134
1135                         ret = handler(kvm, &memslot->rmap[gfn_offset], data);
1136
1137                         for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
1138                                 struct kvm_lpage_info *linfo;
1139
1140                                 linfo = lpage_info_slot(gfn, memslot,
1141                                                         PT_DIRECTORY_LEVEL + j);
1142                                 ret |= handler(kvm, &linfo->rmap_pde, data);
1143                         }
1144                         trace_kvm_age_page(hva, memslot, ret);
1145                         retval |= ret;
1146                 }
1147         }
1148
1149         return retval;
1150 }
1151
1152 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1153 {
1154         return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1155 }
1156
1157 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1158 {
1159         kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1160 }
1161
1162 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1163                          unsigned long data)
1164 {
1165         u64 *spte;
1166         int young = 0;
1167
1168         /*
1169          * Emulate the accessed bit for EPT, by checking if this page has
1170          * an EPT mapping, and clearing it if it does. On the next access,
1171          * a new EPT mapping will be established.
1172          * This has some overhead, but not as much as the cost of swapping
1173          * out actively used pages or breaking up actively used hugepages.
1174          */
1175         if (!shadow_accessed_mask)
1176                 return kvm_unmap_rmapp(kvm, rmapp, data);
1177
1178         spte = rmap_next(rmapp, NULL);
1179         while (spte) {
1180                 int _young;
1181                 u64 _spte = *spte;
1182                 BUG_ON(!(_spte & PT_PRESENT_MASK));
1183                 _young = _spte & PT_ACCESSED_MASK;
1184                 if (_young) {
1185                         young = 1;
1186                         clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
1187                 }
1188                 spte = rmap_next(rmapp, spte);
1189         }
1190         return young;
1191 }
1192
1193 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1194                               unsigned long data)
1195 {
1196         u64 *spte;
1197         int young = 0;
1198
1199         /*
1200          * If there's no access bit in the secondary pte set by the
1201          * hardware it's up to gup-fast/gup to set the access bit in
1202          * the primary pte or in the page structure.
1203          */
1204         if (!shadow_accessed_mask)
1205                 goto out;
1206
1207         spte = rmap_next(rmapp, NULL);
1208         while (spte) {
1209                 u64 _spte = *spte;
1210                 BUG_ON(!(_spte & PT_PRESENT_MASK));
1211                 young = _spte & PT_ACCESSED_MASK;
1212                 if (young) {
1213                         young = 1;
1214                         break;
1215                 }
1216                 spte = rmap_next(rmapp, spte);
1217         }
1218 out:
1219         return young;
1220 }
1221
1222 #define RMAP_RECYCLE_THRESHOLD 1000
1223
1224 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1225 {
1226         unsigned long *rmapp;
1227         struct kvm_mmu_page *sp;
1228
1229         sp = page_header(__pa(spte));
1230
1231         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1232
1233         kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
1234         kvm_flush_remote_tlbs(vcpu->kvm);
1235 }
1236
1237 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1238 {
1239         return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
1240 }
1241
1242 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1243 {
1244         return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1245 }
1246
1247 #ifdef MMU_DEBUG
1248 static int is_empty_shadow_page(u64 *spt)
1249 {
1250         u64 *pos;
1251         u64 *end;
1252
1253         for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1254                 if (is_shadow_present_pte(*pos)) {
1255                         printk(KERN_ERR "%s: %p %llx\n", __func__,
1256                                pos, *pos);
1257                         return 0;
1258                 }
1259         return 1;
1260 }
1261 #endif
1262
1263 /*
1264  * This value is the sum of all of the kvm instances's
1265  * kvm->arch.n_used_mmu_pages values.  We need a global,
1266  * aggregate version in order to make the slab shrinker
1267  * faster
1268  */
1269 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1270 {
1271         kvm->arch.n_used_mmu_pages += nr;
1272         percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1273 }
1274
1275 /*
1276  * Remove the sp from shadow page cache, after call it,
1277  * we can not find this sp from the cache, and the shadow
1278  * page table is still valid.
1279  * It should be under the protection of mmu lock.
1280  */
1281 static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp)
1282 {
1283         ASSERT(is_empty_shadow_page(sp->spt));
1284         hlist_del(&sp->hash_link);
1285         if (!sp->role.direct)
1286                 free_page((unsigned long)sp->gfns);
1287 }
1288
1289 /*
1290  * Free the shadow page table and the sp, we can do it
1291  * out of the protection of mmu lock.
1292  */
1293 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1294 {
1295         list_del(&sp->link);
1296         free_page((unsigned long)sp->spt);
1297         kmem_cache_free(mmu_page_header_cache, sp);
1298 }
1299
1300 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1301 {
1302         return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1303 }
1304
1305 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1306                                     struct kvm_mmu_page *sp, u64 *parent_pte)
1307 {
1308         if (!parent_pte)
1309                 return;
1310
1311         pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1312 }
1313
1314 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1315                                        u64 *parent_pte)
1316 {
1317         pte_list_remove(parent_pte, &sp->parent_ptes);
1318 }
1319
1320 static void drop_parent_pte(struct kvm_mmu_page *sp,
1321                             u64 *parent_pte)
1322 {
1323         mmu_page_remove_parent_pte(sp, parent_pte);
1324         mmu_spte_clear_no_track(parent_pte);
1325 }
1326
1327 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1328                                                u64 *parent_pte, int direct)
1329 {
1330         struct kvm_mmu_page *sp;
1331         sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache,
1332                                         sizeof *sp);
1333         sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
1334         if (!direct)
1335                 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
1336                                                   PAGE_SIZE);
1337         set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1338         list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1339         bitmap_zero(sp->slot_bitmap, KVM_MEM_SLOTS_NUM);
1340         sp->parent_ptes = 0;
1341         mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1342         kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1343         return sp;
1344 }
1345
1346 static void mark_unsync(u64 *spte);
1347 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1348 {
1349         pte_list_walk(&sp->parent_ptes, mark_unsync);
1350 }
1351
1352 static void mark_unsync(u64 *spte)
1353 {
1354         struct kvm_mmu_page *sp;
1355         unsigned int index;
1356
1357         sp = page_header(__pa(spte));
1358         index = spte - sp->spt;
1359         if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1360                 return;
1361         if (sp->unsync_children++)
1362                 return;
1363         kvm_mmu_mark_parents_unsync(sp);
1364 }
1365
1366 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1367                                struct kvm_mmu_page *sp)
1368 {
1369         return 1;
1370 }
1371
1372 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1373 {
1374 }
1375
1376 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1377                                  struct kvm_mmu_page *sp, u64 *spte,
1378                                  const void *pte)
1379 {
1380         WARN_ON(1);
1381 }
1382
1383 #define KVM_PAGE_ARRAY_NR 16
1384
1385 struct kvm_mmu_pages {
1386         struct mmu_page_and_offset {
1387                 struct kvm_mmu_page *sp;
1388                 unsigned int idx;
1389         } page[KVM_PAGE_ARRAY_NR];
1390         unsigned int nr;
1391 };
1392
1393 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1394                          int idx)
1395 {
1396         int i;
1397
1398         if (sp->unsync)
1399                 for (i=0; i < pvec->nr; i++)
1400                         if (pvec->page[i].sp == sp)
1401                                 return 0;
1402
1403         pvec->page[pvec->nr].sp = sp;
1404         pvec->page[pvec->nr].idx = idx;
1405         pvec->nr++;
1406         return (pvec->nr == KVM_PAGE_ARRAY_NR);
1407 }
1408
1409 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1410                            struct kvm_mmu_pages *pvec)
1411 {
1412         int i, ret, nr_unsync_leaf = 0;
1413
1414         for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1415                 struct kvm_mmu_page *child;
1416                 u64 ent = sp->spt[i];
1417
1418                 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1419                         goto clear_child_bitmap;
1420
1421                 child = page_header(ent & PT64_BASE_ADDR_MASK);
1422
1423                 if (child->unsync_children) {
1424                         if (mmu_pages_add(pvec, child, i))
1425                                 return -ENOSPC;
1426
1427                         ret = __mmu_unsync_walk(child, pvec);
1428                         if (!ret)
1429                                 goto clear_child_bitmap;
1430                         else if (ret > 0)
1431                                 nr_unsync_leaf += ret;
1432                         else
1433                                 return ret;
1434                 } else if (child->unsync) {
1435                         nr_unsync_leaf++;
1436                         if (mmu_pages_add(pvec, child, i))
1437                                 return -ENOSPC;
1438                 } else
1439                          goto clear_child_bitmap;
1440
1441                 continue;
1442
1443 clear_child_bitmap:
1444                 __clear_bit(i, sp->unsync_child_bitmap);
1445                 sp->unsync_children--;
1446                 WARN_ON((int)sp->unsync_children < 0);
1447         }
1448
1449
1450         return nr_unsync_leaf;
1451 }
1452
1453 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1454                            struct kvm_mmu_pages *pvec)
1455 {
1456         if (!sp->unsync_children)
1457                 return 0;
1458
1459         mmu_pages_add(pvec, sp, 0);
1460         return __mmu_unsync_walk(sp, pvec);
1461 }
1462
1463 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1464 {
1465         WARN_ON(!sp->unsync);
1466         trace_kvm_mmu_sync_page(sp);
1467         sp->unsync = 0;
1468         --kvm->stat.mmu_unsync;
1469 }
1470
1471 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1472                                     struct list_head *invalid_list);
1473 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1474                                     struct list_head *invalid_list);
1475
1476 #define for_each_gfn_sp(kvm, sp, gfn, pos)                              \
1477   hlist_for_each_entry(sp, pos,                                         \
1478    &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
1479         if ((sp)->gfn != (gfn)) {} else
1480
1481 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos)               \
1482   hlist_for_each_entry(sp, pos,                                         \
1483    &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
1484                 if ((sp)->gfn != (gfn) || (sp)->role.direct ||          \
1485                         (sp)->role.invalid) {} else
1486
1487 /* @sp->gfn should be write-protected at the call site */
1488 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1489                            struct list_head *invalid_list, bool clear_unsync)
1490 {
1491         if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1492                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1493                 return 1;
1494         }
1495
1496         if (clear_unsync)
1497                 kvm_unlink_unsync_page(vcpu->kvm, sp);
1498
1499         if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1500                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1501                 return 1;
1502         }
1503
1504         kvm_mmu_flush_tlb(vcpu);
1505         return 0;
1506 }
1507
1508 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1509                                    struct kvm_mmu_page *sp)
1510 {
1511         LIST_HEAD(invalid_list);
1512         int ret;
1513
1514         ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1515         if (ret)
1516                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1517
1518         return ret;
1519 }
1520
1521 #ifdef CONFIG_KVM_MMU_AUDIT
1522 #include "mmu_audit.c"
1523 #else
1524 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1525 static void mmu_audit_disable(void) { }
1526 #endif
1527
1528 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1529                          struct list_head *invalid_list)
1530 {
1531         return __kvm_sync_page(vcpu, sp, invalid_list, true);
1532 }
1533
1534 /* @gfn should be write-protected at the call site */
1535 static void kvm_sync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
1536 {
1537         struct kvm_mmu_page *s;
1538         struct hlist_node *node;
1539         LIST_HEAD(invalid_list);
1540         bool flush = false;
1541
1542         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1543                 if (!s->unsync)
1544                         continue;
1545
1546                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1547                 kvm_unlink_unsync_page(vcpu->kvm, s);
1548                 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1549                         (vcpu->arch.mmu.sync_page(vcpu, s))) {
1550                         kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1551                         continue;
1552                 }
1553                 flush = true;
1554         }
1555
1556         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1557         if (flush)
1558                 kvm_mmu_flush_tlb(vcpu);
1559 }
1560
1561 struct mmu_page_path {
1562         struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1563         unsigned int idx[PT64_ROOT_LEVEL-1];
1564 };
1565
1566 #define for_each_sp(pvec, sp, parents, i)                       \
1567                 for (i = mmu_pages_next(&pvec, &parents, -1),   \
1568                         sp = pvec.page[i].sp;                   \
1569                         i < pvec.nr && ({ sp = pvec.page[i].sp; 1;});   \
1570                         i = mmu_pages_next(&pvec, &parents, i))
1571
1572 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1573                           struct mmu_page_path *parents,
1574                           int i)
1575 {
1576         int n;
1577
1578         for (n = i+1; n < pvec->nr; n++) {
1579                 struct kvm_mmu_page *sp = pvec->page[n].sp;
1580
1581                 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1582                         parents->idx[0] = pvec->page[n].idx;
1583                         return n;
1584                 }
1585
1586                 parents->parent[sp->role.level-2] = sp;
1587                 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1588         }
1589
1590         return n;
1591 }
1592
1593 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1594 {
1595         struct kvm_mmu_page *sp;
1596         unsigned int level = 0;
1597
1598         do {
1599                 unsigned int idx = parents->idx[level];
1600
1601                 sp = parents->parent[level];
1602                 if (!sp)
1603                         return;
1604
1605                 --sp->unsync_children;
1606                 WARN_ON((int)sp->unsync_children < 0);
1607                 __clear_bit(idx, sp->unsync_child_bitmap);
1608                 level++;
1609         } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1610 }
1611
1612 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1613                                struct mmu_page_path *parents,
1614                                struct kvm_mmu_pages *pvec)
1615 {
1616         parents->parent[parent->role.level-1] = NULL;
1617         pvec->nr = 0;
1618 }
1619
1620 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1621                               struct kvm_mmu_page *parent)
1622 {
1623         int i;
1624         struct kvm_mmu_page *sp;
1625         struct mmu_page_path parents;
1626         struct kvm_mmu_pages pages;
1627         LIST_HEAD(invalid_list);
1628
1629         kvm_mmu_pages_init(parent, &parents, &pages);
1630         while (mmu_unsync_walk(parent, &pages)) {
1631                 int protected = 0;
1632
1633                 for_each_sp(pages, sp, parents, i)
1634                         protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1635
1636                 if (protected)
1637                         kvm_flush_remote_tlbs(vcpu->kvm);
1638
1639                 for_each_sp(pages, sp, parents, i) {
1640                         kvm_sync_page(vcpu, sp, &invalid_list);
1641                         mmu_pages_clear_parents(&parents);
1642                 }
1643                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1644                 cond_resched_lock(&vcpu->kvm->mmu_lock);
1645                 kvm_mmu_pages_init(parent, &parents, &pages);
1646         }
1647 }
1648
1649 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1650 {
1651         int i;
1652
1653         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1654                 sp->spt[i] = 0ull;
1655 }
1656
1657 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1658 {
1659         sp->write_flooding_count = 0;
1660 }
1661
1662 static void clear_sp_write_flooding_count(u64 *spte)
1663 {
1664         struct kvm_mmu_page *sp =  page_header(__pa(spte));
1665
1666         __clear_sp_write_flooding_count(sp);
1667 }
1668
1669 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1670                                              gfn_t gfn,
1671                                              gva_t gaddr,
1672                                              unsigned level,
1673                                              int direct,
1674                                              unsigned access,
1675                                              u64 *parent_pte)
1676 {
1677         union kvm_mmu_page_role role;
1678         unsigned quadrant;
1679         struct kvm_mmu_page *sp;
1680         struct hlist_node *node;
1681         bool need_sync = false;
1682
1683         role = vcpu->arch.mmu.base_role;
1684         role.level = level;
1685         role.direct = direct;
1686         if (role.direct)
1687                 role.cr4_pae = 0;
1688         role.access = access;
1689         if (!vcpu->arch.mmu.direct_map
1690             && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1691                 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1692                 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1693                 role.quadrant = quadrant;
1694         }
1695         for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1696                 if (!need_sync && sp->unsync)
1697                         need_sync = true;
1698
1699                 if (sp->role.word != role.word)
1700                         continue;
1701
1702                 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1703                         break;
1704
1705                 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1706                 if (sp->unsync_children) {
1707                         kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1708                         kvm_mmu_mark_parents_unsync(sp);
1709                 } else if (sp->unsync)
1710                         kvm_mmu_mark_parents_unsync(sp);
1711
1712                 __clear_sp_write_flooding_count(sp);
1713                 trace_kvm_mmu_get_page(sp, false);
1714                 return sp;
1715         }
1716         ++vcpu->kvm->stat.mmu_cache_miss;
1717         sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1718         if (!sp)
1719                 return sp;
1720         sp->gfn = gfn;
1721         sp->role = role;
1722         hlist_add_head(&sp->hash_link,
1723                 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1724         if (!direct) {
1725                 if (rmap_write_protect(vcpu->kvm, gfn))
1726                         kvm_flush_remote_tlbs(vcpu->kvm);
1727                 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1728                         kvm_sync_pages(vcpu, gfn);
1729
1730                 account_shadowed(vcpu->kvm, gfn);
1731         }
1732         init_shadow_page_table(sp);
1733         trace_kvm_mmu_get_page(sp, true);
1734         return sp;
1735 }
1736
1737 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1738                              struct kvm_vcpu *vcpu, u64 addr)
1739 {
1740         iterator->addr = addr;
1741         iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1742         iterator->level = vcpu->arch.mmu.shadow_root_level;
1743
1744         if (iterator->level == PT64_ROOT_LEVEL &&
1745             vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1746             !vcpu->arch.mmu.direct_map)
1747                 --iterator->level;
1748
1749         if (iterator->level == PT32E_ROOT_LEVEL) {
1750                 iterator->shadow_addr
1751                         = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1752                 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1753                 --iterator->level;
1754                 if (!iterator->shadow_addr)
1755                         iterator->level = 0;
1756         }
1757 }
1758
1759 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1760 {
1761         if (iterator->level < PT_PAGE_TABLE_LEVEL)
1762                 return false;
1763
1764         iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1765         iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1766         return true;
1767 }
1768
1769 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1770                                u64 spte)
1771 {
1772         if (is_last_spte(spte, iterator->level)) {
1773                 iterator->level = 0;
1774                 return;
1775         }
1776
1777         iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1778         --iterator->level;
1779 }
1780
1781 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1782 {
1783         return __shadow_walk_next(iterator, *iterator->sptep);
1784 }
1785
1786 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1787 {
1788         u64 spte;
1789
1790         spte = __pa(sp->spt)
1791                 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1792                 | PT_WRITABLE_MASK | PT_USER_MASK;
1793         mmu_spte_set(sptep, spte);
1794 }
1795
1796 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1797 {
1798         if (is_large_pte(*sptep)) {
1799                 drop_spte(vcpu->kvm, sptep);
1800                 --vcpu->kvm->stat.lpages;
1801                 kvm_flush_remote_tlbs(vcpu->kvm);
1802         }
1803 }
1804
1805 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1806                                    unsigned direct_access)
1807 {
1808         if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1809                 struct kvm_mmu_page *child;
1810
1811                 /*
1812                  * For the direct sp, if the guest pte's dirty bit
1813                  * changed form clean to dirty, it will corrupt the
1814                  * sp's access: allow writable in the read-only sp,
1815                  * so we should update the spte at this point to get
1816                  * a new sp with the correct access.
1817                  */
1818                 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1819                 if (child->role.access == direct_access)
1820                         return;
1821
1822                 drop_parent_pte(child, sptep);
1823                 kvm_flush_remote_tlbs(vcpu->kvm);
1824         }
1825 }
1826
1827 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1828                              u64 *spte)
1829 {
1830         u64 pte;
1831         struct kvm_mmu_page *child;
1832
1833         pte = *spte;
1834         if (is_shadow_present_pte(pte)) {
1835                 if (is_last_spte(pte, sp->role.level)) {
1836                         drop_spte(kvm, spte);
1837                         if (is_large_pte(pte))
1838                                 --kvm->stat.lpages;
1839                 } else {
1840                         child = page_header(pte & PT64_BASE_ADDR_MASK);
1841                         drop_parent_pte(child, spte);
1842                 }
1843                 return true;
1844         }
1845
1846         if (is_mmio_spte(pte))
1847                 mmu_spte_clear_no_track(spte);
1848
1849         return false;
1850 }
1851
1852 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
1853                                          struct kvm_mmu_page *sp)
1854 {
1855         unsigned i;
1856
1857         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1858                 mmu_page_zap_pte(kvm, sp, sp->spt + i);
1859 }
1860
1861 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
1862 {
1863         mmu_page_remove_parent_pte(sp, parent_pte);
1864 }
1865
1866 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
1867 {
1868         u64 *parent_pte;
1869
1870         while ((parent_pte = pte_list_next(&sp->parent_ptes, NULL)))
1871                 drop_parent_pte(sp, parent_pte);
1872 }
1873
1874 static int mmu_zap_unsync_children(struct kvm *kvm,
1875                                    struct kvm_mmu_page *parent,
1876                                    struct list_head *invalid_list)
1877 {
1878         int i, zapped = 0;
1879         struct mmu_page_path parents;
1880         struct kvm_mmu_pages pages;
1881
1882         if (parent->role.level == PT_PAGE_TABLE_LEVEL)
1883                 return 0;
1884
1885         kvm_mmu_pages_init(parent, &parents, &pages);
1886         while (mmu_unsync_walk(parent, &pages)) {
1887                 struct kvm_mmu_page *sp;
1888
1889                 for_each_sp(pages, sp, parents, i) {
1890                         kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
1891                         mmu_pages_clear_parents(&parents);
1892                         zapped++;
1893                 }
1894                 kvm_mmu_pages_init(parent, &parents, &pages);
1895         }
1896
1897         return zapped;
1898 }
1899
1900 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1901                                     struct list_head *invalid_list)
1902 {
1903         int ret;
1904
1905         trace_kvm_mmu_prepare_zap_page(sp);
1906         ++kvm->stat.mmu_shadow_zapped;
1907         ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
1908         kvm_mmu_page_unlink_children(kvm, sp);
1909         kvm_mmu_unlink_parents(kvm, sp);
1910         if (!sp->role.invalid && !sp->role.direct)
1911                 unaccount_shadowed(kvm, sp->gfn);
1912         if (sp->unsync)
1913                 kvm_unlink_unsync_page(kvm, sp);
1914         if (!sp->root_count) {
1915                 /* Count self */
1916                 ret++;
1917                 list_move(&sp->link, invalid_list);
1918                 kvm_mod_used_mmu_pages(kvm, -1);
1919         } else {
1920                 list_move(&sp->link, &kvm->arch.active_mmu_pages);
1921                 kvm_reload_remote_mmus(kvm);
1922         }
1923
1924         sp->role.invalid = 1;
1925         return ret;
1926 }
1927
1928 static void kvm_mmu_isolate_pages(struct list_head *invalid_list)
1929 {
1930         struct kvm_mmu_page *sp;
1931
1932         list_for_each_entry(sp, invalid_list, link)
1933                 kvm_mmu_isolate_page(sp);
1934 }
1935
1936 static void free_pages_rcu(struct rcu_head *head)
1937 {
1938         struct kvm_mmu_page *next, *sp;
1939
1940         sp = container_of(head, struct kvm_mmu_page, rcu);
1941         while (sp) {
1942                 if (!list_empty(&sp->link))
1943                         next = list_first_entry(&sp->link,
1944                                       struct kvm_mmu_page, link);
1945                 else
1946                         next = NULL;
1947                 kvm_mmu_free_page(sp);
1948                 sp = next;
1949         }
1950 }
1951
1952 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1953                                     struct list_head *invalid_list)
1954 {
1955         struct kvm_mmu_page *sp;
1956
1957         if (list_empty(invalid_list))
1958                 return;
1959
1960         kvm_flush_remote_tlbs(kvm);
1961
1962         if (atomic_read(&kvm->arch.reader_counter)) {
1963                 kvm_mmu_isolate_pages(invalid_list);
1964                 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1965                 list_del_init(invalid_list);
1966
1967                 trace_kvm_mmu_delay_free_pages(sp);
1968                 call_rcu(&sp->rcu, free_pages_rcu);
1969                 return;
1970         }
1971
1972         do {
1973                 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1974                 WARN_ON(!sp->role.invalid || sp->root_count);
1975                 kvm_mmu_isolate_page(sp);
1976                 kvm_mmu_free_page(sp);
1977         } while (!list_empty(invalid_list));
1978
1979 }
1980
1981 /*
1982  * Changing the number of mmu pages allocated to the vm
1983  * Note: if goal_nr_mmu_pages is too small, you will get dead lock
1984  */
1985 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
1986 {
1987         LIST_HEAD(invalid_list);
1988         /*
1989          * If we set the number of mmu pages to be smaller be than the
1990          * number of actived pages , we must to free some mmu pages before we
1991          * change the value
1992          */
1993
1994         if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
1995                 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
1996                         !list_empty(&kvm->arch.active_mmu_pages)) {
1997                         struct kvm_mmu_page *page;
1998
1999                         page = container_of(kvm->arch.active_mmu_pages.prev,
2000                                             struct kvm_mmu_page, link);
2001                         kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
2002                 }
2003                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2004                 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2005         }
2006
2007         kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2008 }
2009
2010 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2011 {
2012         struct kvm_mmu_page *sp;
2013         struct hlist_node *node;
2014         LIST_HEAD(invalid_list);
2015         int r;
2016
2017         pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2018         r = 0;
2019         spin_lock(&kvm->mmu_lock);
2020         for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
2021                 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2022                          sp->role.word);
2023                 r = 1;
2024                 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2025         }
2026         kvm_mmu_commit_zap_page(kvm, &invalid_list);
2027         spin_unlock(&kvm->mmu_lock);
2028
2029         return r;
2030 }
2031 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2032
2033 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
2034 {
2035         int slot = memslot_id(kvm, gfn);
2036         struct kvm_mmu_page *sp = page_header(__pa(pte));
2037
2038         __set_bit(slot, sp->slot_bitmap);
2039 }
2040
2041 /*
2042  * The function is based on mtrr_type_lookup() in
2043  * arch/x86/kernel/cpu/mtrr/generic.c
2044  */
2045 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2046                          u64 start, u64 end)
2047 {
2048         int i;
2049         u64 base, mask;
2050         u8 prev_match, curr_match;
2051         int num_var_ranges = KVM_NR_VAR_MTRR;
2052
2053         if (!mtrr_state->enabled)
2054                 return 0xFF;
2055
2056         /* Make end inclusive end, instead of exclusive */
2057         end--;
2058
2059         /* Look in fixed ranges. Just return the type as per start */
2060         if (mtrr_state->have_fixed && (start < 0x100000)) {
2061                 int idx;
2062
2063                 if (start < 0x80000) {
2064                         idx = 0;
2065                         idx += (start >> 16);
2066                         return mtrr_state->fixed_ranges[idx];
2067                 } else if (start < 0xC0000) {
2068                         idx = 1 * 8;
2069                         idx += ((start - 0x80000) >> 14);
2070                         return mtrr_state->fixed_ranges[idx];
2071                 } else if (start < 0x1000000) {
2072                         idx = 3 * 8;
2073                         idx += ((start - 0xC0000) >> 12);
2074                         return mtrr_state->fixed_ranges[idx];
2075                 }
2076         }
2077
2078         /*
2079          * Look in variable ranges
2080          * Look of multiple ranges matching this address and pick type
2081          * as per MTRR precedence
2082          */
2083         if (!(mtrr_state->enabled & 2))
2084                 return mtrr_state->def_type;
2085
2086         prev_match = 0xFF;
2087         for (i = 0; i < num_var_ranges; ++i) {
2088                 unsigned short start_state, end_state;
2089
2090                 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2091                         continue;
2092
2093                 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2094                        (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2095                 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2096                        (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2097
2098                 start_state = ((start & mask) == (base & mask));
2099                 end_state = ((end & mask) == (base & mask));
2100                 if (start_state != end_state)
2101                         return 0xFE;
2102
2103                 if ((start & mask) != (base & mask))
2104                         continue;
2105
2106                 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2107                 if (prev_match == 0xFF) {
2108                         prev_match = curr_match;
2109                         continue;
2110                 }
2111
2112                 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2113                     curr_match == MTRR_TYPE_UNCACHABLE)
2114                         return MTRR_TYPE_UNCACHABLE;
2115
2116                 if ((prev_match == MTRR_TYPE_WRBACK &&
2117                      curr_match == MTRR_TYPE_WRTHROUGH) ||
2118                     (prev_match == MTRR_TYPE_WRTHROUGH &&
2119                      curr_match == MTRR_TYPE_WRBACK)) {
2120                         prev_match = MTRR_TYPE_WRTHROUGH;
2121                         curr_match = MTRR_TYPE_WRTHROUGH;
2122                 }
2123
2124                 if (prev_match != curr_match)
2125                         return MTRR_TYPE_UNCACHABLE;
2126         }
2127
2128         if (prev_match != 0xFF)
2129                 return prev_match;
2130
2131         return mtrr_state->def_type;
2132 }
2133
2134 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2135 {
2136         u8 mtrr;
2137
2138         mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2139                              (gfn << PAGE_SHIFT) + PAGE_SIZE);
2140         if (mtrr == 0xfe || mtrr == 0xff)
2141                 mtrr = MTRR_TYPE_WRBACK;
2142         return mtrr;
2143 }
2144 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2145
2146 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2147 {
2148         trace_kvm_mmu_unsync_page(sp);
2149         ++vcpu->kvm->stat.mmu_unsync;
2150         sp->unsync = 1;
2151
2152         kvm_mmu_mark_parents_unsync(sp);
2153 }
2154
2155 static void kvm_unsync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
2156 {
2157         struct kvm_mmu_page *s;
2158         struct hlist_node *node;
2159
2160         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2161                 if (s->unsync)
2162                         continue;
2163                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2164                 __kvm_unsync_page(vcpu, s);
2165         }
2166 }
2167
2168 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2169                                   bool can_unsync)
2170 {
2171         struct kvm_mmu_page *s;
2172         struct hlist_node *node;
2173         bool need_unsync = false;
2174
2175         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2176                 if (!can_unsync)
2177                         return 1;
2178
2179                 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2180                         return 1;
2181
2182                 if (!need_unsync && !s->unsync) {
2183                         need_unsync = true;
2184                 }
2185         }
2186         if (need_unsync)
2187                 kvm_unsync_pages(vcpu, gfn);
2188         return 0;
2189 }
2190
2191 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2192                     unsigned pte_access, int user_fault,
2193                     int write_fault, int level,
2194                     gfn_t gfn, pfn_t pfn, bool speculative,
2195                     bool can_unsync, bool host_writable)
2196 {
2197         u64 spte, entry = *sptep;
2198         int ret = 0;
2199
2200         if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2201                 return 0;
2202
2203         spte = PT_PRESENT_MASK;
2204         if (!speculative)
2205                 spte |= shadow_accessed_mask;
2206
2207         if (pte_access & ACC_EXEC_MASK)
2208                 spte |= shadow_x_mask;
2209         else
2210                 spte |= shadow_nx_mask;
2211         if (pte_access & ACC_USER_MASK)
2212                 spte |= shadow_user_mask;
2213         if (level > PT_PAGE_TABLE_LEVEL)
2214                 spte |= PT_PAGE_SIZE_MASK;
2215         if (tdp_enabled)
2216                 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2217                         kvm_is_mmio_pfn(pfn));
2218
2219         if (host_writable)
2220                 spte |= SPTE_HOST_WRITEABLE;
2221         else
2222                 pte_access &= ~ACC_WRITE_MASK;
2223
2224         spte |= (u64)pfn << PAGE_SHIFT;
2225
2226         if ((pte_access & ACC_WRITE_MASK)
2227             || (!vcpu->arch.mmu.direct_map && write_fault
2228                 && !is_write_protection(vcpu) && !user_fault)) {
2229
2230                 if (level > PT_PAGE_TABLE_LEVEL &&
2231                     has_wrprotected_page(vcpu->kvm, gfn, level)) {
2232                         ret = 1;
2233                         drop_spte(vcpu->kvm, sptep);
2234                         goto done;
2235                 }
2236
2237                 spte |= PT_WRITABLE_MASK;
2238
2239                 if (!vcpu->arch.mmu.direct_map
2240                     && !(pte_access & ACC_WRITE_MASK)) {
2241                         spte &= ~PT_USER_MASK;
2242                         /*
2243                          * If we converted a user page to a kernel page,
2244                          * so that the kernel can write to it when cr0.wp=0,
2245                          * then we should prevent the kernel from executing it
2246                          * if SMEP is enabled.
2247                          */
2248                         if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
2249                                 spte |= PT64_NX_MASK;
2250                 }
2251
2252                 /*
2253                  * Optimization: for pte sync, if spte was writable the hash
2254                  * lookup is unnecessary (and expensive). Write protection
2255                  * is responsibility of mmu_get_page / kvm_sync_page.
2256                  * Same reasoning can be applied to dirty page accounting.
2257                  */
2258                 if (!can_unsync && is_writable_pte(*sptep))
2259                         goto set_pte;
2260
2261                 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2262                         pgprintk("%s: found shadow page for %llx, marking ro\n",
2263                                  __func__, gfn);
2264                         ret = 1;
2265                         pte_access &= ~ACC_WRITE_MASK;
2266                         if (is_writable_pte(spte))
2267                                 spte &= ~PT_WRITABLE_MASK;
2268                 }
2269         }
2270
2271         if (pte_access & ACC_WRITE_MASK)
2272                 mark_page_dirty(vcpu->kvm, gfn);
2273
2274 set_pte:
2275         mmu_spte_update(sptep, spte);
2276         /*
2277          * If we overwrite a writable spte with a read-only one we
2278          * should flush remote TLBs. Otherwise rmap_write_protect
2279          * will find a read-only spte, even though the writable spte
2280          * might be cached on a CPU's TLB.
2281          */
2282         if (is_writable_pte(entry) && !is_writable_pte(*sptep))
2283                 kvm_flush_remote_tlbs(vcpu->kvm);
2284 done:
2285         return ret;
2286 }
2287
2288 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2289                          unsigned pt_access, unsigned pte_access,
2290                          int user_fault, int write_fault,
2291                          int *emulate, int level, gfn_t gfn,
2292                          pfn_t pfn, bool speculative,
2293                          bool host_writable)
2294 {
2295         int was_rmapped = 0;
2296         int rmap_count;
2297
2298         pgprintk("%s: spte %llx access %x write_fault %d"
2299                  " user_fault %d gfn %llx\n",
2300                  __func__, *sptep, pt_access,
2301                  write_fault, user_fault, gfn);
2302
2303         if (is_rmap_spte(*sptep)) {
2304                 /*
2305                  * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2306                  * the parent of the now unreachable PTE.
2307                  */
2308                 if (level > PT_PAGE_TABLE_LEVEL &&
2309                     !is_large_pte(*sptep)) {
2310                         struct kvm_mmu_page *child;
2311                         u64 pte = *sptep;
2312
2313                         child = page_header(pte & PT64_BASE_ADDR_MASK);
2314                         drop_parent_pte(child, sptep);
2315                         kvm_flush_remote_tlbs(vcpu->kvm);
2316                 } else if (pfn != spte_to_pfn(*sptep)) {
2317                         pgprintk("hfn old %llx new %llx\n",
2318                                  spte_to_pfn(*sptep), pfn);
2319                         drop_spte(vcpu->kvm, sptep);
2320                         kvm_flush_remote_tlbs(vcpu->kvm);
2321                 } else
2322                         was_rmapped = 1;
2323         }
2324
2325         if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
2326                       level, gfn, pfn, speculative, true,
2327                       host_writable)) {
2328                 if (write_fault)
2329                         *emulate = 1;
2330                 kvm_mmu_flush_tlb(vcpu);
2331         }
2332
2333         if (unlikely(is_mmio_spte(*sptep) && emulate))
2334                 *emulate = 1;
2335
2336         pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2337         pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2338                  is_large_pte(*sptep)? "2MB" : "4kB",
2339                  *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2340                  *sptep, sptep);
2341         if (!was_rmapped && is_large_pte(*sptep))
2342                 ++vcpu->kvm->stat.lpages;
2343
2344         if (is_shadow_present_pte(*sptep)) {
2345                 page_header_update_slot(vcpu->kvm, sptep, gfn);
2346                 if (!was_rmapped) {
2347                         rmap_count = rmap_add(vcpu, sptep, gfn);
2348                         if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2349                                 rmap_recycle(vcpu, sptep, gfn);
2350                 }
2351         }
2352         kvm_release_pfn_clean(pfn);
2353 }
2354
2355 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2356 {
2357 }
2358
2359 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2360                                      bool no_dirty_log)
2361 {
2362         struct kvm_memory_slot *slot;
2363         unsigned long hva;
2364
2365         slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2366         if (!slot) {
2367                 get_page(fault_page);
2368                 return page_to_pfn(fault_page);
2369         }
2370
2371         hva = gfn_to_hva_memslot(slot, gfn);
2372
2373         return hva_to_pfn_atomic(vcpu->kvm, hva);
2374 }
2375
2376 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2377                                     struct kvm_mmu_page *sp,
2378                                     u64 *start, u64 *end)
2379 {
2380         struct page *pages[PTE_PREFETCH_NUM];
2381         unsigned access = sp->role.access;
2382         int i, ret;
2383         gfn_t gfn;
2384
2385         gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2386         if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2387                 return -1;
2388
2389         ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2390         if (ret <= 0)
2391                 return -1;
2392
2393         for (i = 0; i < ret; i++, gfn++, start++)
2394                 mmu_set_spte(vcpu, start, ACC_ALL,
2395                              access, 0, 0, NULL,
2396                              sp->role.level, gfn,
2397                              page_to_pfn(pages[i]), true, true);
2398
2399         return 0;
2400 }
2401
2402 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2403                                   struct kvm_mmu_page *sp, u64 *sptep)
2404 {
2405         u64 *spte, *start = NULL;
2406         int i;
2407
2408         WARN_ON(!sp->role.direct);
2409
2410         i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2411         spte = sp->spt + i;
2412
2413         for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2414                 if (is_shadow_present_pte(*spte) || spte == sptep) {
2415                         if (!start)
2416                                 continue;
2417                         if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2418                                 break;
2419                         start = NULL;
2420                 } else if (!start)
2421                         start = spte;
2422         }
2423 }
2424
2425 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2426 {
2427         struct kvm_mmu_page *sp;
2428
2429         /*
2430          * Since it's no accessed bit on EPT, it's no way to
2431          * distinguish between actually accessed translations
2432          * and prefetched, so disable pte prefetch if EPT is
2433          * enabled.
2434          */
2435         if (!shadow_accessed_mask)
2436                 return;
2437
2438         sp = page_header(__pa(sptep));
2439         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2440                 return;
2441
2442         __direct_pte_prefetch(vcpu, sp, sptep);
2443 }
2444
2445 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2446                         int map_writable, int level, gfn_t gfn, pfn_t pfn,
2447                         bool prefault)
2448 {
2449         struct kvm_shadow_walk_iterator iterator;
2450         struct kvm_mmu_page *sp;
2451         int emulate = 0;
2452         gfn_t pseudo_gfn;
2453
2454         for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2455                 if (iterator.level == level) {
2456                         unsigned pte_access = ACC_ALL;
2457
2458                         mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
2459                                      0, write, &emulate,
2460                                      level, gfn, pfn, prefault, map_writable);
2461                         direct_pte_prefetch(vcpu, iterator.sptep);
2462                         ++vcpu->stat.pf_fixed;
2463                         break;
2464                 }
2465
2466                 if (!is_shadow_present_pte(*iterator.sptep)) {
2467                         u64 base_addr = iterator.addr;
2468
2469                         base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2470                         pseudo_gfn = base_addr >> PAGE_SHIFT;
2471                         sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2472                                               iterator.level - 1,
2473                                               1, ACC_ALL, iterator.sptep);
2474                         if (!sp) {
2475                                 pgprintk("nonpaging_map: ENOMEM\n");
2476                                 kvm_release_pfn_clean(pfn);
2477                                 return -ENOMEM;
2478                         }
2479
2480                         mmu_spte_set(iterator.sptep,
2481                                      __pa(sp->spt)
2482                                      | PT_PRESENT_MASK | PT_WRITABLE_MASK
2483                                      | shadow_user_mask | shadow_x_mask
2484                                      | shadow_accessed_mask);
2485                 }
2486         }
2487         return emulate;
2488 }
2489
2490 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2491 {
2492         siginfo_t info;
2493
2494         info.si_signo   = SIGBUS;
2495         info.si_errno   = 0;
2496         info.si_code    = BUS_MCEERR_AR;
2497         info.si_addr    = (void __user *)address;
2498         info.si_addr_lsb = PAGE_SHIFT;
2499
2500         send_sig_info(SIGBUS, &info, tsk);
2501 }
2502
2503 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2504 {
2505         kvm_release_pfn_clean(pfn);
2506         if (is_hwpoison_pfn(pfn)) {
2507                 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2508                 return 0;
2509         }
2510
2511         return -EFAULT;
2512 }
2513
2514 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2515                                         gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2516 {
2517         pfn_t pfn = *pfnp;
2518         gfn_t gfn = *gfnp;
2519         int level = *levelp;
2520
2521         /*
2522          * Check if it's a transparent hugepage. If this would be an
2523          * hugetlbfs page, level wouldn't be set to
2524          * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2525          * here.
2526          */
2527         if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2528             level == PT_PAGE_TABLE_LEVEL &&
2529             PageTransCompound(pfn_to_page(pfn)) &&
2530             !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2531                 unsigned long mask;
2532                 /*
2533                  * mmu_notifier_retry was successful and we hold the
2534                  * mmu_lock here, so the pmd can't become splitting
2535                  * from under us, and in turn
2536                  * __split_huge_page_refcount() can't run from under
2537                  * us and we can safely transfer the refcount from
2538                  * PG_tail to PG_head as we switch the pfn to tail to
2539                  * head.
2540                  */
2541                 *levelp = level = PT_DIRECTORY_LEVEL;
2542                 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2543                 VM_BUG_ON((gfn & mask) != (pfn & mask));
2544                 if (pfn & mask) {
2545                         gfn &= ~mask;
2546                         *gfnp = gfn;
2547                         kvm_release_pfn_clean(pfn);
2548                         pfn &= ~mask;
2549                         if (!get_page_unless_zero(pfn_to_page(pfn)))
2550                                 BUG();
2551                         *pfnp = pfn;
2552                 }
2553         }
2554 }
2555
2556 static bool mmu_invalid_pfn(pfn_t pfn)
2557 {
2558         return unlikely(is_invalid_pfn(pfn));
2559 }
2560
2561 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2562                                 pfn_t pfn, unsigned access, int *ret_val)
2563 {
2564         bool ret = true;
2565
2566         /* The pfn is invalid, report the error! */
2567         if (unlikely(is_invalid_pfn(pfn))) {
2568                 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2569                 goto exit;
2570         }
2571
2572         if (unlikely(is_noslot_pfn(pfn)))
2573                 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2574
2575         ret = false;
2576 exit:
2577         return ret;
2578 }
2579
2580 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2581                          gva_t gva, pfn_t *pfn, bool write, bool *writable);
2582
2583 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn,
2584                          bool prefault)
2585 {
2586         int r;
2587         int level;
2588         int force_pt_level;
2589         pfn_t pfn;
2590         unsigned long mmu_seq;
2591         bool map_writable;
2592
2593         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2594         if (likely(!force_pt_level)) {
2595                 level = mapping_level(vcpu, gfn);
2596                 /*
2597                  * This path builds a PAE pagetable - so we can map
2598                  * 2mb pages at maximum. Therefore check if the level
2599                  * is larger than that.
2600                  */
2601                 if (level > PT_DIRECTORY_LEVEL)
2602                         level = PT_DIRECTORY_LEVEL;
2603
2604                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2605         } else
2606                 level = PT_PAGE_TABLE_LEVEL;
2607
2608         mmu_seq = vcpu->kvm->mmu_notifier_seq;
2609         smp_rmb();
2610
2611         if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2612                 return 0;
2613
2614         if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2615                 return r;
2616
2617         spin_lock(&vcpu->kvm->mmu_lock);
2618         if (mmu_notifier_retry(vcpu, mmu_seq))
2619                 goto out_unlock;
2620         kvm_mmu_free_some_pages(vcpu);
2621         if (likely(!force_pt_level))
2622                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2623         r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2624                          prefault);
2625         spin_unlock(&vcpu->kvm->mmu_lock);
2626
2627
2628         return r;
2629
2630 out_unlock:
2631         spin_unlock(&vcpu->kvm->mmu_lock);
2632         kvm_release_pfn_clean(pfn);
2633         return 0;
2634 }
2635
2636
2637 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2638 {
2639         int i;
2640         struct kvm_mmu_page *sp;
2641         LIST_HEAD(invalid_list);
2642
2643         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2644                 return;
2645         spin_lock(&vcpu->kvm->mmu_lock);
2646         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2647             (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2648              vcpu->arch.mmu.direct_map)) {
2649                 hpa_t root = vcpu->arch.mmu.root_hpa;
2650
2651                 sp = page_header(root);
2652                 --sp->root_count;
2653                 if (!sp->root_count && sp->role.invalid) {
2654                         kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2655                         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2656                 }
2657                 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2658                 spin_unlock(&vcpu->kvm->mmu_lock);
2659                 return;
2660         }
2661         for (i = 0; i < 4; ++i) {
2662                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2663
2664                 if (root) {
2665                         root &= PT64_BASE_ADDR_MASK;
2666                         sp = page_header(root);
2667                         --sp->root_count;
2668                         if (!sp->root_count && sp->role.invalid)
2669                                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2670                                                          &invalid_list);
2671                 }
2672                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2673         }
2674         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2675         spin_unlock(&vcpu->kvm->mmu_lock);
2676         vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2677 }
2678
2679 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2680 {
2681         int ret = 0;
2682
2683         if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2684                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2685                 ret = 1;
2686         }
2687
2688         return ret;
2689 }
2690
2691 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2692 {
2693         struct kvm_mmu_page *sp;
2694         unsigned i;
2695
2696         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2697                 spin_lock(&vcpu->kvm->mmu_lock);
2698                 kvm_mmu_free_some_pages(vcpu);
2699                 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2700                                       1, ACC_ALL, NULL);
2701                 ++sp->root_count;
2702                 spin_unlock(&vcpu->kvm->mmu_lock);
2703                 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2704         } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2705                 for (i = 0; i < 4; ++i) {
2706                         hpa_t root = vcpu->arch.mmu.pae_root[i];
2707
2708                         ASSERT(!VALID_PAGE(root));
2709                         spin_lock(&vcpu->kvm->mmu_lock);
2710                         kvm_mmu_free_some_pages(vcpu);
2711                         sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2712                                               i << 30,
2713                                               PT32_ROOT_LEVEL, 1, ACC_ALL,
2714                                               NULL);
2715                         root = __pa(sp->spt);
2716                         ++sp->root_count;
2717                         spin_unlock(&vcpu->kvm->mmu_lock);
2718                         vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2719                 }
2720                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2721         } else
2722                 BUG();
2723
2724         return 0;
2725 }
2726
2727 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2728 {
2729         struct kvm_mmu_page *sp;
2730         u64 pdptr, pm_mask;
2731         gfn_t root_gfn;
2732         int i;
2733
2734         root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2735
2736         if (mmu_check_root(vcpu, root_gfn))
2737                 return 1;
2738
2739         /*
2740          * Do we shadow a long mode page table? If so we need to
2741          * write-protect the guests page table root.
2742          */
2743         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2744                 hpa_t root = vcpu->arch.mmu.root_hpa;
2745
2746                 ASSERT(!VALID_PAGE(root));
2747
2748                 spin_lock(&vcpu->kvm->mmu_lock);
2749                 kvm_mmu_free_some_pages(vcpu);
2750                 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2751                                       0, ACC_ALL, NULL);
2752                 root = __pa(sp->spt);
2753                 ++sp->root_count;
2754                 spin_unlock(&vcpu->kvm->mmu_lock);
2755                 vcpu->arch.mmu.root_hpa = root;
2756                 return 0;
2757         }
2758
2759         /*
2760          * We shadow a 32 bit page table. This may be a legacy 2-level
2761          * or a PAE 3-level page table. In either case we need to be aware that
2762          * the shadow page table may be a PAE or a long mode page table.
2763          */
2764         pm_mask = PT_PRESENT_MASK;
2765         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2766                 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2767
2768         for (i = 0; i < 4; ++i) {
2769                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2770
2771                 ASSERT(!VALID_PAGE(root));
2772                 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2773                         pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
2774                         if (!is_present_gpte(pdptr)) {
2775                                 vcpu->arch.mmu.pae_root[i] = 0;
2776                                 continue;
2777                         }
2778                         root_gfn = pdptr >> PAGE_SHIFT;
2779                         if (mmu_check_root(vcpu, root_gfn))
2780                                 return 1;
2781                 }
2782                 spin_lock(&vcpu->kvm->mmu_lock);
2783                 kvm_mmu_free_some_pages(vcpu);
2784                 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
2785                                       PT32_ROOT_LEVEL, 0,
2786                                       ACC_ALL, NULL);
2787                 root = __pa(sp->spt);
2788                 ++sp->root_count;
2789                 spin_unlock(&vcpu->kvm->mmu_lock);
2790
2791                 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
2792         }
2793         vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2794
2795         /*
2796          * If we shadow a 32 bit page table with a long mode page
2797          * table we enter this path.
2798          */
2799         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2800                 if (vcpu->arch.mmu.lm_root == NULL) {
2801                         /*
2802                          * The additional page necessary for this is only
2803                          * allocated on demand.
2804                          */
2805
2806                         u64 *lm_root;
2807
2808                         lm_root = (void*)get_zeroed_page(GFP_KERNEL);
2809                         if (lm_root == NULL)
2810                                 return 1;
2811
2812                         lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
2813
2814                         vcpu->arch.mmu.lm_root = lm_root;
2815                 }
2816
2817                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
2818         }
2819
2820         return 0;
2821 }
2822
2823 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2824 {
2825         if (vcpu->arch.mmu.direct_map)
2826                 return mmu_alloc_direct_roots(vcpu);
2827         else
2828                 return mmu_alloc_shadow_roots(vcpu);
2829 }
2830
2831 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2832 {
2833         int i;
2834         struct kvm_mmu_page *sp;
2835
2836         if (vcpu->arch.mmu.direct_map)
2837                 return;
2838
2839         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2840                 return;
2841
2842         vcpu_clear_mmio_info(vcpu, ~0ul);
2843         kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
2844         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2845                 hpa_t root = vcpu->arch.mmu.root_hpa;
2846                 sp = page_header(root);
2847                 mmu_sync_children(vcpu, sp);
2848                 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2849                 return;
2850         }
2851         for (i = 0; i < 4; ++i) {
2852                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2853
2854                 if (root && VALID_PAGE(root)) {
2855                         root &= PT64_BASE_ADDR_MASK;
2856                         sp = page_header(root);
2857                         mmu_sync_children(vcpu, sp);
2858                 }
2859         }
2860         kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2861 }
2862
2863 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2864 {
2865         spin_lock(&vcpu->kvm->mmu_lock);
2866         mmu_sync_roots(vcpu);
2867         spin_unlock(&vcpu->kvm->mmu_lock);
2868 }
2869
2870 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2871                                   u32 access, struct x86_exception *exception)
2872 {
2873         if (exception)
2874                 exception->error_code = 0;
2875         return vaddr;
2876 }
2877
2878 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
2879                                          u32 access,
2880                                          struct x86_exception *exception)
2881 {
2882         if (exception)
2883                 exception->error_code = 0;
2884         return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
2885 }
2886
2887 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2888 {
2889         if (direct)
2890                 return vcpu_match_mmio_gpa(vcpu, addr);
2891
2892         return vcpu_match_mmio_gva(vcpu, addr);
2893 }
2894
2895
2896 /*
2897  * On direct hosts, the last spte is only allows two states
2898  * for mmio page fault:
2899  *   - It is the mmio spte
2900  *   - It is zapped or it is being zapped.
2901  *
2902  * This function completely checks the spte when the last spte
2903  * is not the mmio spte.
2904  */
2905 static bool check_direct_spte_mmio_pf(u64 spte)
2906 {
2907         return __check_direct_spte_mmio_pf(spte);
2908 }
2909
2910 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
2911 {
2912         struct kvm_shadow_walk_iterator iterator;
2913         u64 spte = 0ull;
2914
2915         walk_shadow_page_lockless_begin(vcpu);
2916         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
2917                 if (!is_shadow_present_pte(spte))
2918                         break;
2919         walk_shadow_page_lockless_end(vcpu);
2920
2921         return spte;
2922 }
2923
2924 /*
2925  * If it is a real mmio page fault, return 1 and emulat the instruction
2926  * directly, return 0 to let CPU fault again on the address, -1 is
2927  * returned if bug is detected.
2928  */
2929 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2930 {
2931         u64 spte;
2932
2933         if (quickly_check_mmio_pf(vcpu, addr, direct))
2934                 return 1;
2935
2936         spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
2937
2938         if (is_mmio_spte(spte)) {
2939                 gfn_t gfn = get_mmio_spte_gfn(spte);
2940                 unsigned access = get_mmio_spte_access(spte);
2941
2942                 if (direct)
2943                         addr = 0;
2944
2945                 trace_handle_mmio_page_fault(addr, gfn, access);
2946                 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
2947                 return 1;
2948         }
2949
2950         /*
2951          * It's ok if the gva is remapped by other cpus on shadow guest,
2952          * it's a BUG if the gfn is not a mmio page.
2953          */
2954         if (direct && !check_direct_spte_mmio_pf(spte))
2955                 return -1;
2956
2957         /*
2958          * If the page table is zapped by other cpus, let CPU fault again on
2959          * the address.
2960          */
2961         return 0;
2962 }
2963 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
2964
2965 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
2966                                   u32 error_code, bool direct)
2967 {
2968         int ret;
2969
2970         ret = handle_mmio_page_fault_common(vcpu, addr, direct);
2971         WARN_ON(ret < 0);
2972         return ret;
2973 }
2974
2975 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
2976                                 u32 error_code, bool prefault)
2977 {
2978         gfn_t gfn;
2979         int r;
2980
2981         pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
2982
2983         if (unlikely(error_code & PFERR_RSVD_MASK))
2984                 return handle_mmio_page_fault(vcpu, gva, error_code, true);
2985
2986         r = mmu_topup_memory_caches(vcpu);
2987         if (r)
2988                 return r;
2989
2990         ASSERT(vcpu);
2991         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2992
2993         gfn = gva >> PAGE_SHIFT;
2994
2995         return nonpaging_map(vcpu, gva & PAGE_MASK,
2996                              error_code & PFERR_WRITE_MASK, gfn, prefault);
2997 }
2998
2999 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3000 {
3001         struct kvm_arch_async_pf arch;
3002
3003         arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3004         arch.gfn = gfn;
3005         arch.direct_map = vcpu->arch.mmu.direct_map;
3006         arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3007
3008         return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3009 }
3010
3011 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3012 {
3013         if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3014                      kvm_event_needs_reinjection(vcpu)))
3015                 return false;
3016
3017         return kvm_x86_ops->interrupt_allowed(vcpu);
3018 }
3019
3020 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3021                          gva_t gva, pfn_t *pfn, bool write, bool *writable)
3022 {
3023         bool async;
3024
3025         *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3026
3027         if (!async)
3028                 return false; /* *pfn has correct page already */
3029
3030         put_page(pfn_to_page(*pfn));
3031
3032         if (!prefault && can_do_async_pf(vcpu)) {
3033                 trace_kvm_try_async_get_page(gva, gfn);
3034                 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3035                         trace_kvm_async_pf_doublefault(gva, gfn);
3036                         kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3037                         return true;
3038                 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3039                         return true;
3040         }
3041
3042         *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3043
3044         return false;
3045 }
3046
3047 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3048                           bool prefault)
3049 {
3050         pfn_t pfn;
3051         int r;
3052         int level;
3053         int force_pt_level;
3054         gfn_t gfn = gpa >> PAGE_SHIFT;
3055         unsigned long mmu_seq;
3056         int write = error_code & PFERR_WRITE_MASK;
3057         bool map_writable;
3058
3059         ASSERT(vcpu);
3060         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3061
3062         if (unlikely(error_code & PFERR_RSVD_MASK))
3063                 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3064
3065         r = mmu_topup_memory_caches(vcpu);
3066         if (r)
3067                 return r;
3068
3069         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3070         if (likely(!force_pt_level)) {
3071                 level = mapping_level(vcpu, gfn);
3072                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3073         } else
3074                 level = PT_PAGE_TABLE_LEVEL;
3075
3076         mmu_seq = vcpu->kvm->mmu_notifier_seq;
3077         smp_rmb();
3078
3079         if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3080                 return 0;
3081
3082         if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3083                 return r;
3084
3085         spin_lock(&vcpu->kvm->mmu_lock);
3086         if (mmu_notifier_retry(vcpu, mmu_seq))
3087                 goto out_unlock;
3088         kvm_mmu_free_some_pages(vcpu);
3089         if (likely(!force_pt_level))
3090                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3091         r = __direct_map(vcpu, gpa, write, map_writable,
3092                          level, gfn, pfn, prefault);
3093         spin_unlock(&vcpu->kvm->mmu_lock);
3094
3095         return r;
3096
3097 out_unlock:
3098         spin_unlock(&vcpu->kvm->mmu_lock);
3099         kvm_release_pfn_clean(pfn);
3100         return 0;
3101 }
3102
3103 static void nonpaging_free(struct kvm_vcpu *vcpu)
3104 {
3105         mmu_free_roots(vcpu);
3106 }
3107
3108 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3109                                   struct kvm_mmu *context)
3110 {
3111         context->new_cr3 = nonpaging_new_cr3;
3112         context->page_fault = nonpaging_page_fault;
3113         context->gva_to_gpa = nonpaging_gva_to_gpa;
3114         context->free = nonpaging_free;
3115         context->sync_page = nonpaging_sync_page;
3116         context->invlpg = nonpaging_invlpg;
3117         context->update_pte = nonpaging_update_pte;
3118         context->root_level = 0;
3119         context->shadow_root_level = PT32E_ROOT_LEVEL;
3120         context->root_hpa = INVALID_PAGE;
3121         context->direct_map = true;
3122         context->nx = false;
3123         return 0;
3124 }
3125
3126 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3127 {
3128         ++vcpu->stat.tlb_flush;
3129         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3130 }
3131
3132 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3133 {
3134         pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3135         mmu_free_roots(vcpu);
3136 }
3137
3138 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3139 {
3140         return kvm_read_cr3(vcpu);
3141 }
3142
3143 static void inject_page_fault(struct kvm_vcpu *vcpu,
3144                               struct x86_exception *fault)
3145 {
3146         vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3147 }
3148
3149 static void paging_free(struct kvm_vcpu *vcpu)
3150 {
3151         nonpaging_free(vcpu);
3152 }
3153
3154 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3155 {
3156         int bit7;
3157
3158         bit7 = (gpte >> 7) & 1;
3159         return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
3160 }
3161
3162 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3163                            int *nr_present)
3164 {
3165         if (unlikely(is_mmio_spte(*sptep))) {
3166                 if (gfn != get_mmio_spte_gfn(*sptep)) {
3167                         mmu_spte_clear_no_track(sptep);
3168                         return true;
3169                 }
3170
3171                 (*nr_present)++;
3172                 mark_mmio_spte(sptep, gfn, access);
3173                 return true;
3174         }
3175
3176         return false;
3177 }
3178
3179 #define PTTYPE 64
3180 #include "paging_tmpl.h"
3181 #undef PTTYPE
3182
3183 #define PTTYPE 32
3184 #include "paging_tmpl.h"
3185 #undef PTTYPE
3186
3187 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3188                                   struct kvm_mmu *context,
3189                                   int level)
3190 {
3191         int maxphyaddr = cpuid_maxphyaddr(vcpu);
3192         u64 exb_bit_rsvd = 0;
3193
3194         if (!context->nx)
3195                 exb_bit_rsvd = rsvd_bits(63, 63);
3196         switch (level) {
3197         case PT32_ROOT_LEVEL:
3198                 /* no rsvd bits for 2 level 4K page table entries */
3199                 context->rsvd_bits_mask[0][1] = 0;
3200                 context->rsvd_bits_mask[0][0] = 0;
3201                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3202
3203                 if (!is_pse(vcpu)) {
3204                         context->rsvd_bits_mask[1][1] = 0;
3205                         break;
3206                 }
3207
3208                 if (is_cpuid_PSE36())
3209                         /* 36bits PSE 4MB page */
3210                         context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3211                 else
3212                         /* 32 bits PSE 4MB page */
3213                         context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3214                 break;
3215         case PT32E_ROOT_LEVEL:
3216                 context->rsvd_bits_mask[0][2] =
3217                         rsvd_bits(maxphyaddr, 63) |
3218                         rsvd_bits(7, 8) | rsvd_bits(1, 2);      /* PDPTE */
3219                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3220                         rsvd_bits(maxphyaddr, 62);      /* PDE */
3221                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3222                         rsvd_bits(maxphyaddr, 62);      /* PTE */
3223                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3224                         rsvd_bits(maxphyaddr, 62) |
3225                         rsvd_bits(13, 20);              /* large page */
3226                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3227                 break;
3228         case PT64_ROOT_LEVEL:
3229                 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3230                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3231                 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3232                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3233                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3234                         rsvd_bits(maxphyaddr, 51);
3235                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3236                         rsvd_bits(maxphyaddr, 51);
3237                 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3238                 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3239                         rsvd_bits(maxphyaddr, 51) |
3240                         rsvd_bits(13, 29);
3241                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3242                         rsvd_bits(maxphyaddr, 51) |
3243                         rsvd_bits(13, 20);              /* large page */
3244                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3245                 break;
3246         }
3247 }
3248
3249 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3250                                         struct kvm_mmu *context,
3251                                         int level)
3252 {
3253         context->nx = is_nx(vcpu);
3254
3255         reset_rsvds_bits_mask(vcpu, context, level);
3256
3257         ASSERT(is_pae(vcpu));
3258         context->new_cr3 = paging_new_cr3;
3259         context->page_fault = paging64_page_fault;
3260         context->gva_to_gpa = paging64_gva_to_gpa;
3261         context->sync_page = paging64_sync_page;
3262         context->invlpg = paging64_invlpg;
3263         context->update_pte = paging64_update_pte;
3264         context->free = paging_free;
3265         context->root_level = level;
3266         context->shadow_root_level = level;
3267         context->root_hpa = INVALID_PAGE;
3268         context->direct_map = false;
3269         return 0;
3270 }
3271
3272 static int paging64_init_context(struct kvm_vcpu *vcpu,
3273                                  struct kvm_mmu *context)
3274 {
3275         return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3276 }
3277
3278 static int paging32_init_context(struct kvm_vcpu *vcpu,
3279                                  struct kvm_mmu *context)
3280 {
3281         context->nx = false;
3282
3283         reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3284
3285         context->new_cr3 = paging_new_cr3;
3286         context->page_fault = paging32_page_fault;
3287         context->gva_to_gpa = paging32_gva_to_gpa;
3288         context->free = paging_free;
3289         context->sync_page = paging32_sync_page;
3290         context->invlpg = paging32_invlpg;
3291         context->update_pte = paging32_update_pte;
3292         context->root_level = PT32_ROOT_LEVEL;
3293         context->shadow_root_level = PT32E_ROOT_LEVEL;
3294         context->root_hpa = INVALID_PAGE;
3295         context->direct_map = false;
3296         return 0;
3297 }
3298
3299 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3300                                   struct kvm_mmu *context)
3301 {
3302         return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3303 }
3304
3305 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3306 {
3307         struct kvm_mmu *context = vcpu->arch.walk_mmu;
3308
3309         context->base_role.word = 0;
3310         context->new_cr3 = nonpaging_new_cr3;
3311         context->page_fault = tdp_page_fault;
3312         context->free = nonpaging_free;
3313         context->sync_page = nonpaging_sync_page;
3314         context->invlpg = nonpaging_invlpg;
3315         context->update_pte = nonpaging_update_pte;
3316         context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3317         context->root_hpa = INVALID_PAGE;
3318         context->direct_map = true;
3319         context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3320         context->get_cr3 = get_cr3;
3321         context->get_pdptr = kvm_pdptr_read;
3322         context->inject_page_fault = kvm_inject_page_fault;
3323
3324         if (!is_paging(vcpu)) {
3325                 context->nx = false;
3326                 context->gva_to_gpa = nonpaging_gva_to_gpa;
3327                 context->root_level = 0;
3328         } else if (is_long_mode(vcpu)) {
3329                 context->nx = is_nx(vcpu);
3330                 reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL);
3331                 context->gva_to_gpa = paging64_gva_to_gpa;
3332                 context->root_level = PT64_ROOT_LEVEL;
3333         } else if (is_pae(vcpu)) {
3334                 context->nx = is_nx(vcpu);
3335                 reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL);
3336                 context->gva_to_gpa = paging64_gva_to_gpa;
3337                 context->root_level = PT32E_ROOT_LEVEL;
3338         } else {
3339                 context->nx = false;
3340                 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3341                 context->gva_to_gpa = paging32_gva_to_gpa;
3342                 context->root_level = PT32_ROOT_LEVEL;
3343         }
3344
3345         return 0;
3346 }
3347
3348 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3349 {
3350         int r;
3351         bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3352         ASSERT(vcpu);
3353         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3354
3355         if (!is_paging(vcpu))
3356                 r = nonpaging_init_context(vcpu, context);
3357         else if (is_long_mode(vcpu))
3358                 r = paging64_init_context(vcpu, context);
3359         else if (is_pae(vcpu))
3360                 r = paging32E_init_context(vcpu, context);
3361         else
3362                 r = paging32_init_context(vcpu, context);
3363
3364         vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3365         vcpu->arch.mmu.base_role.cr0_wp  = is_write_protection(vcpu);
3366         vcpu->arch.mmu.base_role.smep_andnot_wp
3367                 = smep && !is_write_protection(vcpu);
3368
3369         return r;
3370 }
3371 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3372
3373 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3374 {
3375         int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3376
3377         vcpu->arch.walk_mmu->set_cr3           = kvm_x86_ops->set_cr3;
3378         vcpu->arch.walk_mmu->get_cr3           = get_cr3;
3379         vcpu->arch.walk_mmu->get_pdptr         = kvm_pdptr_read;
3380         vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3381
3382         return r;
3383 }
3384
3385 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3386 {
3387         struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3388
3389         g_context->get_cr3           = get_cr3;
3390         g_context->get_pdptr         = kvm_pdptr_read;
3391         g_context->inject_page_fault = kvm_inject_page_fault;
3392
3393         /*
3394          * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3395          * translation of l2_gpa to l1_gpa addresses is done using the
3396          * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3397          * functions between mmu and nested_mmu are swapped.
3398          */
3399         if (!is_paging(vcpu)) {
3400                 g_context->nx = false;
3401                 g_context->root_level = 0;
3402                 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3403         } else if (is_long_mode(vcpu)) {
3404                 g_context->nx = is_nx(vcpu);
3405                 reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL);
3406                 g_context->root_level = PT64_ROOT_LEVEL;
3407                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3408         } else if (is_pae(vcpu)) {
3409                 g_context->nx = is_nx(vcpu);
3410                 reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL);
3411                 g_context->root_level = PT32E_ROOT_LEVEL;
3412                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3413         } else {
3414                 g_context->nx = false;
3415                 reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL);
3416                 g_context->root_level = PT32_ROOT_LEVEL;
3417                 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3418         }
3419
3420         return 0;
3421 }
3422
3423 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3424 {
3425         if (mmu_is_nested(vcpu))
3426                 return init_kvm_nested_mmu(vcpu);
3427         else if (tdp_enabled)
3428                 return init_kvm_tdp_mmu(vcpu);
3429         else
3430                 return init_kvm_softmmu(vcpu);
3431 }
3432
3433 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3434 {
3435         ASSERT(vcpu);
3436         if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3437                 /* mmu.free() should set root_hpa = INVALID_PAGE */
3438                 vcpu->arch.mmu.free(vcpu);
3439 }
3440
3441 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3442 {
3443         destroy_kvm_mmu(vcpu);
3444         return init_kvm_mmu(vcpu);
3445 }
3446 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3447
3448 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3449 {
3450         int r;
3451
3452         r = mmu_topup_memory_caches(vcpu);
3453         if (r)
3454                 goto out;
3455         r = mmu_alloc_roots(vcpu);
3456         spin_lock(&vcpu->kvm->mmu_lock);
3457         mmu_sync_roots(vcpu);
3458         spin_unlock(&vcpu->kvm->mmu_lock);
3459         if (r)
3460                 goto out;
3461         /* set_cr3() should ensure TLB has been flushed */
3462         vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3463 out:
3464         return r;
3465 }
3466 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3467
3468 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3469 {
3470         mmu_free_roots(vcpu);
3471 }
3472 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3473
3474 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3475                                   struct kvm_mmu_page *sp, u64 *spte,
3476                                   const void *new)
3477 {
3478         if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3479                 ++vcpu->kvm->stat.mmu_pde_zapped;
3480                 return;
3481         }
3482
3483         ++vcpu->kvm->stat.mmu_pte_updated;
3484         vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3485 }
3486
3487 static bool need_remote_flush(u64 old, u64 new)
3488 {
3489         if (!is_shadow_present_pte(old))
3490                 return false;
3491         if (!is_shadow_present_pte(new))
3492                 return true;
3493         if ((old ^ new) & PT64_BASE_ADDR_MASK)
3494                 return true;
3495         old ^= PT64_NX_MASK;
3496         new ^= PT64_NX_MASK;
3497         return (old & ~new & PT64_PERM_MASK) != 0;
3498 }
3499
3500 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3501                                     bool remote_flush, bool local_flush)
3502 {
3503         if (zap_page)
3504                 return;
3505
3506         if (remote_flush)
3507                 kvm_flush_remote_tlbs(vcpu->kvm);
3508         else if (local_flush)
3509                 kvm_mmu_flush_tlb(vcpu);
3510 }
3511
3512 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3513                                     const u8 *new, int *bytes)
3514 {
3515         u64 gentry;
3516         int r;
3517
3518         /*
3519          * Assume that the pte write on a page table of the same type
3520          * as the current vcpu paging mode since we update the sptes only
3521          * when they have the same mode.
3522          */
3523         if (is_pae(vcpu) && *bytes == 4) {
3524                 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3525                 *gpa &= ~(gpa_t)7;
3526                 *bytes = 8;
3527                 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, min(*bytes, 8));
3528                 if (r)
3529                         gentry = 0;
3530                 new = (const u8 *)&gentry;
3531         }
3532
3533         switch (*bytes) {
3534         case 4:
3535                 gentry = *(const u32 *)new;
3536                 break;
3537         case 8:
3538                 gentry = *(const u64 *)new;
3539                 break;
3540         default:
3541                 gentry = 0;
3542                 break;
3543         }
3544
3545         return gentry;
3546 }
3547
3548 /*
3549  * If we're seeing too many writes to a page, it may no longer be a page table,
3550  * or we may be forking, in which case it is better to unmap the page.
3551  */
3552 static bool detect_write_flooding(struct kvm_mmu_page *sp)
3553 {
3554         /*
3555          * Skip write-flooding detected for the sp whose level is 1, because
3556          * it can become unsync, then the guest page is not write-protected.
3557          */
3558         if (sp->role.level == 1)
3559                 return false;
3560
3561         return ++sp->write_flooding_count >= 3;
3562 }
3563
3564 /*
3565  * Misaligned accesses are too much trouble to fix up; also, they usually
3566  * indicate a page is not used as a page table.
3567  */
3568 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3569                                     int bytes)
3570 {
3571         unsigned offset, pte_size, misaligned;
3572
3573         pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3574                  gpa, bytes, sp->role.word);
3575
3576         offset = offset_in_page(gpa);
3577         pte_size = sp->role.cr4_pae ? 8 : 4;
3578
3579         /*
3580          * Sometimes, the OS only writes the last one bytes to update status
3581          * bits, for example, in linux, andb instruction is used in clear_bit().
3582          */
3583         if (!(offset & (pte_size - 1)) && bytes == 1)
3584                 return false;
3585
3586         misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3587         misaligned |= bytes < 4;
3588
3589         return misaligned;
3590 }
3591
3592 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
3593 {
3594         unsigned page_offset, quadrant;
3595         u64 *spte;
3596         int level;
3597
3598         page_offset = offset_in_page(gpa);
3599         level = sp->role.level;
3600         *nspte = 1;
3601         if (!sp->role.cr4_pae) {
3602                 page_offset <<= 1;      /* 32->64 */
3603                 /*
3604                  * A 32-bit pde maps 4MB while the shadow pdes map
3605                  * only 2MB.  So we need to double the offset again
3606                  * and zap two pdes instead of one.
3607                  */
3608                 if (level == PT32_ROOT_LEVEL) {
3609                         page_offset &= ~7; /* kill rounding error */
3610                         page_offset <<= 1;
3611                         *nspte = 2;
3612                 }
3613                 quadrant = page_offset >> PAGE_SHIFT;
3614                 page_offset &= ~PAGE_MASK;
3615                 if (quadrant != sp->role.quadrant)
3616                         return NULL;
3617         }
3618
3619         spte = &sp->spt[page_offset / sizeof(*spte)];
3620         return spte;
3621 }
3622
3623 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3624                        const u8 *new, int bytes)
3625 {
3626         gfn_t gfn = gpa >> PAGE_SHIFT;
3627         union kvm_mmu_page_role mask = { .word = 0 };
3628         struct kvm_mmu_page *sp;
3629         struct hlist_node *node;
3630         LIST_HEAD(invalid_list);
3631         u64 entry, gentry, *spte;
3632         int npte;
3633         bool remote_flush, local_flush, zap_page;
3634
3635         /*
3636          * If we don't have indirect shadow pages, it means no page is
3637          * write-protected, so we can exit simply.
3638          */
3639         if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3640                 return;
3641
3642         zap_page = remote_flush = local_flush = false;
3643
3644         pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3645
3646         gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
3647
3648         /*
3649          * No need to care whether allocation memory is successful
3650          * or not since pte prefetch is skiped if it does not have
3651          * enough objects in the cache.
3652          */
3653         mmu_topup_memory_caches(vcpu);
3654
3655         spin_lock(&vcpu->kvm->mmu_lock);
3656         ++vcpu->kvm->stat.mmu_pte_write;
3657         kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3658
3659         mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3660         for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3661                 if (detect_write_misaligned(sp, gpa, bytes) ||
3662                       detect_write_flooding(sp)) {
3663                         zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3664                                                      &invalid_list);
3665                         ++vcpu->kvm->stat.mmu_flooded;
3666                         continue;
3667                 }
3668
3669                 spte = get_written_sptes(sp, gpa, &npte);
3670                 if (!spte)
3671                         continue;
3672
3673                 local_flush = true;
3674                 while (npte--) {
3675                         entry = *spte;
3676                         mmu_page_zap_pte(vcpu->kvm, sp, spte);
3677                         if (gentry &&
3678                               !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3679                               & mask.word) && rmap_can_add(vcpu))
3680                                 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3681                         if (!remote_flush && need_remote_flush(entry, *spte))
3682                                 remote_flush = true;
3683                         ++spte;
3684                 }
3685         }
3686         mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3687         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3688         kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3689         spin_unlock(&vcpu->kvm->mmu_lock);
3690 }
3691
3692 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3693 {
3694         gpa_t gpa;
3695         int r;
3696
3697         if (vcpu->arch.mmu.direct_map)
3698                 return 0;
3699
3700         gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
3701
3702         r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3703
3704         return r;
3705 }
3706 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
3707
3708 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
3709 {
3710         LIST_HEAD(invalid_list);
3711
3712         while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3713                !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
3714                 struct kvm_mmu_page *sp;
3715
3716                 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
3717                                   struct kvm_mmu_page, link);
3718                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3719                 ++vcpu->kvm->stat.mmu_recycled;
3720         }
3721         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3722 }
3723
3724 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
3725 {
3726         if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
3727                 return vcpu_match_mmio_gpa(vcpu, addr);
3728
3729         return vcpu_match_mmio_gva(vcpu, addr);
3730 }
3731
3732 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
3733                        void *insn, int insn_len)
3734 {
3735         int r, emulation_type = EMULTYPE_RETRY;
3736         enum emulation_result er;
3737
3738         r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3739         if (r < 0)
3740                 goto out;
3741
3742         if (!r) {
3743                 r = 1;
3744                 goto out;
3745         }
3746
3747         if (is_mmio_page_fault(vcpu, cr2))
3748                 emulation_type = 0;
3749
3750         er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
3751
3752         switch (er) {
3753         case EMULATE_DONE:
3754                 return 1;
3755         case EMULATE_DO_MMIO:
3756                 ++vcpu->stat.mmio_exits;
3757                 /* fall through */
3758         case EMULATE_FAIL:
3759                 return 0;
3760         default:
3761                 BUG();
3762         }
3763 out:
3764         return r;
3765 }
3766 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
3767
3768 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
3769 {
3770         vcpu->arch.mmu.invlpg(vcpu, gva);
3771         kvm_mmu_flush_tlb(vcpu);
3772         ++vcpu->stat.invlpg;
3773 }
3774 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
3775
3776 void kvm_enable_tdp(void)
3777 {
3778         tdp_enabled = true;
3779 }
3780 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
3781
3782 void kvm_disable_tdp(void)
3783 {
3784         tdp_enabled = false;
3785 }
3786 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
3787
3788 static void free_mmu_pages(struct kvm_vcpu *vcpu)
3789 {
3790         free_page((unsigned long)vcpu->arch.mmu.pae_root);
3791         if (vcpu->arch.mmu.lm_root != NULL)
3792                 free_page((unsigned long)vcpu->arch.mmu.lm_root);
3793 }
3794
3795 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
3796 {
3797         struct page *page;
3798         int i;
3799
3800         ASSERT(vcpu);
3801
3802         /*
3803          * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3804          * Therefore we need to allocate shadow page tables in the first
3805          * 4GB of memory, which happens to fit the DMA32 zone.
3806          */
3807         page = alloc_page(GFP_KERNEL | __GFP_DMA32);
3808         if (!page)
3809                 return -ENOMEM;
3810
3811         vcpu->arch.mmu.pae_root = page_address(page);
3812         for (i = 0; i < 4; ++i)
3813                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3814
3815         return 0;
3816 }
3817
3818 int kvm_mmu_create(struct kvm_vcpu *vcpu)
3819 {
3820         ASSERT(vcpu);
3821
3822         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
3823         vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3824         vcpu->arch.mmu.translate_gpa = translate_gpa;
3825         vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
3826
3827         return alloc_mmu_pages(vcpu);
3828 }
3829
3830 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
3831 {
3832         ASSERT(vcpu);
3833         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3834
3835         return init_kvm_mmu(vcpu);
3836 }
3837
3838 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
3839 {
3840         struct kvm_mmu_page *sp;
3841
3842         list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
3843                 int i;
3844                 u64 *pt;
3845
3846                 if (!test_bit(slot, sp->slot_bitmap))
3847                         continue;
3848
3849                 pt = sp->spt;
3850                 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3851                         if (!is_shadow_present_pte(pt[i]) ||
3852                               !is_last_spte(pt[i], sp->role.level))
3853                                 continue;
3854
3855                         if (is_large_pte(pt[i])) {
3856                                 drop_spte(kvm, &pt[i]);
3857                                 --kvm->stat.lpages;
3858                                 continue;
3859                         }
3860
3861                         /* avoid RMW */
3862                         if (is_writable_pte(pt[i]))
3863                                 mmu_spte_update(&pt[i],
3864                                                 pt[i] & ~PT_WRITABLE_MASK);
3865                 }
3866         }
3867         kvm_flush_remote_tlbs(kvm);
3868 }
3869
3870 void kvm_mmu_zap_all(struct kvm *kvm)
3871 {
3872         struct kvm_mmu_page *sp, *node;
3873         LIST_HEAD(invalid_list);
3874
3875         spin_lock(&kvm->mmu_lock);
3876 restart:
3877         list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
3878                 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3879                         goto restart;
3880
3881         kvm_mmu_commit_zap_page(kvm, &invalid_list);
3882         spin_unlock(&kvm->mmu_lock);
3883 }
3884
3885 static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3886                                                 struct list_head *invalid_list)
3887 {
3888         struct kvm_mmu_page *page;
3889
3890         page = container_of(kvm->arch.active_mmu_pages.prev,
3891                             struct kvm_mmu_page, link);
3892         kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3893 }
3894
3895 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
3896 {
3897         struct kvm *kvm;
3898         struct kvm *kvm_freed = NULL;
3899         int nr_to_scan = sc->nr_to_scan;
3900
3901         if (nr_to_scan == 0)
3902                 goto out;
3903
3904         raw_spin_lock(&kvm_lock);
3905
3906         list_for_each_entry(kvm, &vm_list, vm_list) {
3907                 int idx;
3908                 LIST_HEAD(invalid_list);
3909
3910                 idx = srcu_read_lock(&kvm->srcu);
3911                 spin_lock(&kvm->mmu_lock);
3912                 if (!kvm_freed && nr_to_scan > 0 &&
3913                     kvm->arch.n_used_mmu_pages > 0) {
3914                         kvm_mmu_remove_some_alloc_mmu_pages(kvm,
3915                                                             &invalid_list);
3916                         kvm_freed = kvm;
3917                 }
3918                 nr_to_scan--;
3919
3920                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3921                 spin_unlock(&kvm->mmu_lock);
3922                 srcu_read_unlock(&kvm->srcu, idx);
3923         }
3924         if (kvm_freed)
3925                 list_move_tail(&kvm_freed->vm_list, &vm_list);
3926
3927         raw_spin_unlock(&kvm_lock);
3928
3929 out:
3930         return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3931 }
3932
3933 static struct shrinker mmu_shrinker = {
3934         .shrink = mmu_shrink,
3935         .seeks = DEFAULT_SEEKS * 10,
3936 };
3937
3938 static void mmu_destroy_caches(void)
3939 {
3940         if (pte_list_desc_cache)
3941                 kmem_cache_destroy(pte_list_desc_cache);
3942         if (mmu_page_header_cache)
3943                 kmem_cache_destroy(mmu_page_header_cache);
3944 }
3945
3946 int kvm_mmu_module_init(void)
3947 {
3948         pte_list_desc_cache = kmem_cache_create("pte_list_desc",
3949                                             sizeof(struct pte_list_desc),
3950                                             0, 0, NULL);
3951         if (!pte_list_desc_cache)
3952                 goto nomem;
3953
3954         mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3955                                                   sizeof(struct kvm_mmu_page),
3956                                                   0, 0, NULL);
3957         if (!mmu_page_header_cache)
3958                 goto nomem;
3959
3960         if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
3961                 goto nomem;
3962
3963         register_shrinker(&mmu_shrinker);
3964
3965         return 0;
3966
3967 nomem:
3968         mmu_destroy_caches();
3969         return -ENOMEM;
3970 }
3971
3972 /*
3973  * Caculate mmu pages needed for kvm.
3974  */
3975 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3976 {
3977         unsigned int nr_mmu_pages;
3978         unsigned int  nr_pages = 0;
3979         struct kvm_memslots *slots;
3980         struct kvm_memory_slot *memslot;
3981
3982         slots = kvm_memslots(kvm);
3983
3984         kvm_for_each_memslot(memslot, slots)
3985                 nr_pages += memslot->npages;
3986
3987         nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3988         nr_mmu_pages = max(nr_mmu_pages,
3989                         (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3990
3991         return nr_mmu_pages;
3992 }
3993
3994 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3995 {
3996         struct kvm_shadow_walk_iterator iterator;
3997         u64 spte;
3998         int nr_sptes = 0;
3999
4000         walk_shadow_page_lockless_begin(vcpu);
4001         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4002                 sptes[iterator.level-1] = spte;
4003                 nr_sptes++;
4004                 if (!is_shadow_present_pte(spte))
4005                         break;
4006         }
4007         walk_shadow_page_lockless_end(vcpu);
4008
4009         return nr_sptes;
4010 }
4011 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4012
4013 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4014 {
4015         ASSERT(vcpu);
4016
4017         destroy_kvm_mmu(vcpu);
4018         free_mmu_pages(vcpu);
4019         mmu_free_memory_caches(vcpu);
4020 }
4021
4022 void kvm_mmu_module_exit(void)
4023 {
4024         mmu_destroy_caches();
4025         percpu_counter_destroy(&kvm_total_used_mmu_pages);
4026         unregister_shrinker(&mmu_shrinker);
4027         mmu_audit_disable();
4028 }