KVM: kvm_io_device: extend in_range() to manage len and write attribute
[linux-2.6.git] / arch / x86 / kvm / i8259.c
1 /*
2  * 8259 interrupt controller emulation
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  * Copyright (c) 2007 Intel Corporation
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  * Authors:
25  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
26  *   Port from Qemu.
27  */
28 #include <linux/mm.h>
29 #include "irq.h"
30
31 #include <linux/kvm_host.h>
32
33 /*
34  * set irq level. If an edge is detected, then the IRR is set to 1
35  */
36 static inline void pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
37 {
38         int mask;
39         mask = 1 << irq;
40         if (s->elcr & mask)     /* level triggered */
41                 if (level) {
42                         s->irr |= mask;
43                         s->last_irr |= mask;
44                 } else {
45                         s->irr &= ~mask;
46                         s->last_irr &= ~mask;
47                 }
48         else    /* edge triggered */
49                 if (level) {
50                         if ((s->last_irr & mask) == 0)
51                                 s->irr |= mask;
52                         s->last_irr |= mask;
53                 } else
54                         s->last_irr &= ~mask;
55 }
56
57 /*
58  * return the highest priority found in mask (highest = smallest
59  * number). Return 8 if no irq
60  */
61 static inline int get_priority(struct kvm_kpic_state *s, int mask)
62 {
63         int priority;
64         if (mask == 0)
65                 return 8;
66         priority = 0;
67         while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
68                 priority++;
69         return priority;
70 }
71
72 /*
73  * return the pic wanted interrupt. return -1 if none
74  */
75 static int pic_get_irq(struct kvm_kpic_state *s)
76 {
77         int mask, cur_priority, priority;
78
79         mask = s->irr & ~s->imr;
80         priority = get_priority(s, mask);
81         if (priority == 8)
82                 return -1;
83         /*
84          * compute current priority. If special fully nested mode on the
85          * master, the IRQ coming from the slave is not taken into account
86          * for the priority computation.
87          */
88         mask = s->isr;
89         if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
90                 mask &= ~(1 << 2);
91         cur_priority = get_priority(s, mask);
92         if (priority < cur_priority)
93                 /*
94                  * higher priority found: an irq should be generated
95                  */
96                 return (priority + s->priority_add) & 7;
97         else
98                 return -1;
99 }
100
101 /*
102  * raise irq to CPU if necessary. must be called every time the active
103  * irq may change
104  */
105 static void pic_update_irq(struct kvm_pic *s)
106 {
107         int irq2, irq;
108
109         irq2 = pic_get_irq(&s->pics[1]);
110         if (irq2 >= 0) {
111                 /*
112                  * if irq request by slave pic, signal master PIC
113                  */
114                 pic_set_irq1(&s->pics[0], 2, 1);
115                 pic_set_irq1(&s->pics[0], 2, 0);
116         }
117         irq = pic_get_irq(&s->pics[0]);
118         if (irq >= 0)
119                 s->irq_request(s->irq_request_opaque, 1);
120         else
121                 s->irq_request(s->irq_request_opaque, 0);
122 }
123
124 void kvm_pic_update_irq(struct kvm_pic *s)
125 {
126         pic_update_irq(s);
127 }
128
129 void kvm_pic_set_irq(void *opaque, int irq, int level)
130 {
131         struct kvm_pic *s = opaque;
132
133         pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
134         pic_update_irq(s);
135 }
136
137 /*
138  * acknowledge interrupt 'irq'
139  */
140 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
141 {
142         if (s->auto_eoi) {
143                 if (s->rotate_on_auto_eoi)
144                         s->priority_add = (irq + 1) & 7;
145         } else
146                 s->isr |= (1 << irq);
147         /*
148          * We don't clear a level sensitive interrupt here
149          */
150         if (!(s->elcr & (1 << irq)))
151                 s->irr &= ~(1 << irq);
152 }
153
154 int kvm_pic_read_irq(struct kvm_pic *s)
155 {
156         int irq, irq2, intno;
157
158         irq = pic_get_irq(&s->pics[0]);
159         if (irq >= 0) {
160                 pic_intack(&s->pics[0], irq);
161                 if (irq == 2) {
162                         irq2 = pic_get_irq(&s->pics[1]);
163                         if (irq2 >= 0)
164                                 pic_intack(&s->pics[1], irq2);
165                         else
166                                 /*
167                                  * spurious IRQ on slave controller
168                                  */
169                                 irq2 = 7;
170                         intno = s->pics[1].irq_base + irq2;
171                         irq = irq2 + 8;
172                 } else
173                         intno = s->pics[0].irq_base + irq;
174         } else {
175                 /*
176                  * spurious IRQ on host controller
177                  */
178                 irq = 7;
179                 intno = s->pics[0].irq_base + irq;
180         }
181         pic_update_irq(s);
182
183         return intno;
184 }
185
186 void kvm_pic_reset(struct kvm_kpic_state *s)
187 {
188         s->last_irr = 0;
189         s->irr = 0;
190         s->imr = 0;
191         s->isr = 0;
192         s->priority_add = 0;
193         s->irq_base = 0;
194         s->read_reg_select = 0;
195         s->poll = 0;
196         s->special_mask = 0;
197         s->init_state = 0;
198         s->auto_eoi = 0;
199         s->rotate_on_auto_eoi = 0;
200         s->special_fully_nested_mode = 0;
201         s->init4 = 0;
202 }
203
204 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
205 {
206         struct kvm_kpic_state *s = opaque;
207         int priority, cmd, irq;
208
209         addr &= 1;
210         if (addr == 0) {
211                 if (val & 0x10) {
212                         kvm_pic_reset(s);       /* init */
213                         /*
214                          * deassert a pending interrupt
215                          */
216                         s->pics_state->irq_request(s->pics_state->
217                                                    irq_request_opaque, 0);
218                         s->init_state = 1;
219                         s->init4 = val & 1;
220                         if (val & 0x02)
221                                 printk(KERN_ERR "single mode not supported");
222                         if (val & 0x08)
223                                 printk(KERN_ERR
224                                        "level sensitive irq not supported");
225                 } else if (val & 0x08) {
226                         if (val & 0x04)
227                                 s->poll = 1;
228                         if (val & 0x02)
229                                 s->read_reg_select = val & 1;
230                         if (val & 0x40)
231                                 s->special_mask = (val >> 5) & 1;
232                 } else {
233                         cmd = val >> 5;
234                         switch (cmd) {
235                         case 0:
236                         case 4:
237                                 s->rotate_on_auto_eoi = cmd >> 2;
238                                 break;
239                         case 1: /* end of interrupt */
240                         case 5:
241                                 priority = get_priority(s, s->isr);
242                                 if (priority != 8) {
243                                         irq = (priority + s->priority_add) & 7;
244                                         s->isr &= ~(1 << irq);
245                                         if (cmd == 5)
246                                                 s->priority_add = (irq + 1) & 7;
247                                         pic_update_irq(s->pics_state);
248                                 }
249                                 break;
250                         case 3:
251                                 irq = val & 7;
252                                 s->isr &= ~(1 << irq);
253                                 pic_update_irq(s->pics_state);
254                                 break;
255                         case 6:
256                                 s->priority_add = (val + 1) & 7;
257                                 pic_update_irq(s->pics_state);
258                                 break;
259                         case 7:
260                                 irq = val & 7;
261                                 s->isr &= ~(1 << irq);
262                                 s->priority_add = (irq + 1) & 7;
263                                 pic_update_irq(s->pics_state);
264                                 break;
265                         default:
266                                 break;  /* no operation */
267                         }
268                 }
269         } else
270                 switch (s->init_state) {
271                 case 0:         /* normal mode */
272                         s->imr = val;
273                         pic_update_irq(s->pics_state);
274                         break;
275                 case 1:
276                         s->irq_base = val & 0xf8;
277                         s->init_state = 2;
278                         break;
279                 case 2:
280                         if (s->init4)
281                                 s->init_state = 3;
282                         else
283                                 s->init_state = 0;
284                         break;
285                 case 3:
286                         s->special_fully_nested_mode = (val >> 4) & 1;
287                         s->auto_eoi = (val >> 1) & 1;
288                         s->init_state = 0;
289                         break;
290                 }
291 }
292
293 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
294 {
295         int ret;
296
297         ret = pic_get_irq(s);
298         if (ret >= 0) {
299                 if (addr1 >> 7) {
300                         s->pics_state->pics[0].isr &= ~(1 << 2);
301                         s->pics_state->pics[0].irr &= ~(1 << 2);
302                 }
303                 s->irr &= ~(1 << ret);
304                 s->isr &= ~(1 << ret);
305                 if (addr1 >> 7 || ret != 2)
306                         pic_update_irq(s->pics_state);
307         } else {
308                 ret = 0x07;
309                 pic_update_irq(s->pics_state);
310         }
311
312         return ret;
313 }
314
315 static u32 pic_ioport_read(void *opaque, u32 addr1)
316 {
317         struct kvm_kpic_state *s = opaque;
318         unsigned int addr;
319         int ret;
320
321         addr = addr1;
322         addr &= 1;
323         if (s->poll) {
324                 ret = pic_poll_read(s, addr1);
325                 s->poll = 0;
326         } else
327                 if (addr == 0)
328                         if (s->read_reg_select)
329                                 ret = s->isr;
330                         else
331                                 ret = s->irr;
332                 else
333                         ret = s->imr;
334         return ret;
335 }
336
337 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
338 {
339         struct kvm_kpic_state *s = opaque;
340         s->elcr = val & s->elcr_mask;
341 }
342
343 static u32 elcr_ioport_read(void *opaque, u32 addr1)
344 {
345         struct kvm_kpic_state *s = opaque;
346         return s->elcr;
347 }
348
349 static int picdev_in_range(struct kvm_io_device *this, gpa_t addr,
350                            int len, int is_write)
351 {
352         switch (addr) {
353         case 0x20:
354         case 0x21:
355         case 0xa0:
356         case 0xa1:
357         case 0x4d0:
358         case 0x4d1:
359                 return 1;
360         default:
361                 return 0;
362         }
363 }
364
365 static void picdev_write(struct kvm_io_device *this,
366                          gpa_t addr, int len, const void *val)
367 {
368         struct kvm_pic *s = this->private;
369         unsigned char data = *(unsigned char *)val;
370
371         if (len != 1) {
372                 if (printk_ratelimit())
373                         printk(KERN_ERR "PIC: non byte write\n");
374                 return;
375         }
376         switch (addr) {
377         case 0x20:
378         case 0x21:
379         case 0xa0:
380         case 0xa1:
381                 pic_ioport_write(&s->pics[addr >> 7], addr, data);
382                 break;
383         case 0x4d0:
384         case 0x4d1:
385                 elcr_ioport_write(&s->pics[addr & 1], addr, data);
386                 break;
387         }
388 }
389
390 static void picdev_read(struct kvm_io_device *this,
391                         gpa_t addr, int len, void *val)
392 {
393         struct kvm_pic *s = this->private;
394         unsigned char data = 0;
395
396         if (len != 1) {
397                 if (printk_ratelimit())
398                         printk(KERN_ERR "PIC: non byte read\n");
399                 return;
400         }
401         switch (addr) {
402         case 0x20:
403         case 0x21:
404         case 0xa0:
405         case 0xa1:
406                 data = pic_ioport_read(&s->pics[addr >> 7], addr);
407                 break;
408         case 0x4d0:
409         case 0x4d1:
410                 data = elcr_ioport_read(&s->pics[addr & 1], addr);
411                 break;
412         }
413         *(unsigned char *)val = data;
414 }
415
416 /*
417  * callback when PIC0 irq status changed
418  */
419 static void pic_irq_request(void *opaque, int level)
420 {
421         struct kvm *kvm = opaque;
422         struct kvm_vcpu *vcpu = kvm->vcpus[0];
423
424         pic_irqchip(kvm)->output = level;
425         if (vcpu)
426                 kvm_vcpu_kick(vcpu);
427 }
428
429 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
430 {
431         struct kvm_pic *s;
432         s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
433         if (!s)
434                 return NULL;
435         s->pics[0].elcr_mask = 0xf8;
436         s->pics[1].elcr_mask = 0xde;
437         s->irq_request = pic_irq_request;
438         s->irq_request_opaque = kvm;
439         s->pics[0].pics_state = s;
440         s->pics[1].pics_state = s;
441
442         /*
443          * Initialize PIO device
444          */
445         s->dev.read = picdev_read;
446         s->dev.write = picdev_write;
447         s->dev.in_range = picdev_in_range;
448         s->dev.private = s;
449         kvm_io_bus_register_dev(&kvm->pio_bus, &s->dev);
450         return s;
451 }