Change pci_raw_ops to pci_raw_read/write
[linux-2.6.git] / arch / x86 / kernel / quirks.c
1 /*
2  * This file contains work-arounds for x86 and x86_64 platform bugs.
3  */
4 #include <linux/pci.h>
5 #include <linux/irq.h>
6
7 #include <asm/hpet.h>
8
9 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
10
11 static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
12 {
13         u8 config, rev;
14         u32 word;
15
16         /* BIOS may enable hardware IRQ balancing for
17          * E7520/E7320/E7525(revision ID 0x9 and below)
18          * based platforms.
19          * Disable SW irqbalance/affinity on those platforms.
20          */
21         pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
22         if (rev > 0x9)
23                 return;
24
25         /* enable access to config space*/
26         pci_read_config_byte(dev, 0xf4, &config);
27         pci_write_config_byte(dev, 0xf4, config|0x2);
28
29         /* read xTPR register */
30         raw_pci_read(0, 0, 0x40, 0x4c, 2, &word);
31
32         if (!(word & (1 << 13))) {
33                 dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
34                         "disabling irq balancing and affinity\n");
35 #ifdef CONFIG_IRQBALANCE
36                 irqbalance_disable("");
37 #endif
38                 noirqdebug_setup("");
39 #ifdef CONFIG_PROC_FS
40                 no_irq_affinity = 1;
41 #endif
42         }
43
44         /* put back the original value for config space*/
45         if (!(config & 0x2))
46                 pci_write_config_byte(dev, 0xf4, config);
47 }
48 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
49                         quirk_intel_irqbalance);
50 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
51                         quirk_intel_irqbalance);
52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
53                         quirk_intel_irqbalance);
54 #endif
55
56 #if defined(CONFIG_HPET_TIMER)
57 unsigned long force_hpet_address;
58
59 static enum {
60         NONE_FORCE_HPET_RESUME,
61         OLD_ICH_FORCE_HPET_RESUME,
62         ICH_FORCE_HPET_RESUME,
63         VT8237_FORCE_HPET_RESUME,
64         NVIDIA_FORCE_HPET_RESUME,
65 } force_hpet_resume_type;
66
67 static void __iomem *rcba_base;
68
69 static void ich_force_hpet_resume(void)
70 {
71         u32 val;
72
73         if (!force_hpet_address)
74                 return;
75
76         if (rcba_base == NULL)
77                 BUG();
78
79         /* read the Function Disable register, dword mode only */
80         val = readl(rcba_base + 0x3404);
81         if (!(val & 0x80)) {
82                 /* HPET disabled in HPTC. Trying to enable */
83                 writel(val | 0x80, rcba_base + 0x3404);
84         }
85
86         val = readl(rcba_base + 0x3404);
87         if (!(val & 0x80))
88                 BUG();
89         else
90                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
91
92         return;
93 }
94
95 static void ich_force_enable_hpet(struct pci_dev *dev)
96 {
97         u32 val;
98         u32 uninitialized_var(rcba);
99         int err = 0;
100
101         if (hpet_address || force_hpet_address)
102                 return;
103
104         pci_read_config_dword(dev, 0xF0, &rcba);
105         rcba &= 0xFFFFC000;
106         if (rcba == 0) {
107                 dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
108                         "cannot force enable HPET\n");
109                 return;
110         }
111
112         /* use bits 31:14, 16 kB aligned */
113         rcba_base = ioremap_nocache(rcba, 0x4000);
114         if (rcba_base == NULL) {
115                 dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
116                         "cannot force enable HPET\n");
117                 return;
118         }
119
120         /* read the Function Disable register, dword mode only */
121         val = readl(rcba_base + 0x3404);
122
123         if (val & 0x80) {
124                 /* HPET is enabled in HPTC. Just not reported by BIOS */
125                 val = val & 0x3;
126                 force_hpet_address = 0xFED00000 | (val << 12);
127                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
128                         "0x%lx\n", force_hpet_address);
129                 iounmap(rcba_base);
130                 return;
131         }
132
133         /* HPET disabled in HPTC. Trying to enable */
134         writel(val | 0x80, rcba_base + 0x3404);
135
136         val = readl(rcba_base + 0x3404);
137         if (!(val & 0x80)) {
138                 err = 1;
139         } else {
140                 val = val & 0x3;
141                 force_hpet_address = 0xFED00000 | (val << 12);
142         }
143
144         if (err) {
145                 force_hpet_address = 0;
146                 iounmap(rcba_base);
147                 dev_printk(KERN_DEBUG, &dev->dev,
148                         "Failed to force enable HPET\n");
149         } else {
150                 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
151                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
152                         "0x%lx\n", force_hpet_address);
153         }
154 }
155
156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
157                          ich_force_enable_hpet);
158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
159                          ich_force_enable_hpet);
160 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
161                          ich_force_enable_hpet);
162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
163                          ich_force_enable_hpet);
164 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
165                          ich_force_enable_hpet);
166 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
167                          ich_force_enable_hpet);
168 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
169                          ich_force_enable_hpet);
170
171
172 static struct pci_dev *cached_dev;
173
174 static void old_ich_force_hpet_resume(void)
175 {
176         u32 val;
177         u32 uninitialized_var(gen_cntl);
178
179         if (!force_hpet_address || !cached_dev)
180                 return;
181
182         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
183         gen_cntl &= (~(0x7 << 15));
184         gen_cntl |= (0x4 << 15);
185
186         pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
187         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
188         val = gen_cntl >> 15;
189         val &= 0x7;
190         if (val == 0x4)
191                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
192         else
193                 BUG();
194 }
195
196 static void old_ich_force_enable_hpet(struct pci_dev *dev)
197 {
198         u32 val;
199         u32 uninitialized_var(gen_cntl);
200
201         if (hpet_address || force_hpet_address)
202                 return;
203
204         pci_read_config_dword(dev, 0xD0, &gen_cntl);
205         /*
206          * Bit 17 is HPET enable bit.
207          * Bit 16:15 control the HPET base address.
208          */
209         val = gen_cntl >> 15;
210         val &= 0x7;
211         if (val & 0x4) {
212                 val &= 0x3;
213                 force_hpet_address = 0xFED00000 | (val << 12);
214                 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
215                         force_hpet_address);
216                 return;
217         }
218
219         /*
220          * HPET is disabled. Trying enabling at FED00000 and check
221          * whether it sticks
222          */
223         gen_cntl &= (~(0x7 << 15));
224         gen_cntl |= (0x4 << 15);
225         pci_write_config_dword(dev, 0xD0, gen_cntl);
226
227         pci_read_config_dword(dev, 0xD0, &gen_cntl);
228
229         val = gen_cntl >> 15;
230         val &= 0x7;
231         if (val & 0x4) {
232                 /* HPET is enabled in HPTC. Just not reported by BIOS */
233                 val &= 0x3;
234                 force_hpet_address = 0xFED00000 | (val << 12);
235                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
236                         "0x%lx\n", force_hpet_address);
237                 cached_dev = dev;
238                 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
239                 return;
240         }
241
242         dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
243 }
244
245 /*
246  * Undocumented chipset features. Make sure that the user enforced
247  * this.
248  */
249 static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
250 {
251         if (hpet_force_user)
252                 old_ich_force_enable_hpet(dev);
253 }
254
255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
256                          old_ich_force_enable_hpet_user);
257 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
258                          old_ich_force_enable_hpet_user);
259 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
260                          old_ich_force_enable_hpet_user);
261 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
262                          old_ich_force_enable_hpet_user);
263 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
264                          old_ich_force_enable_hpet);
265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
266                          old_ich_force_enable_hpet);
267
268
269 static void vt8237_force_hpet_resume(void)
270 {
271         u32 val;
272
273         if (!force_hpet_address || !cached_dev)
274                 return;
275
276         val = 0xfed00000 | 0x80;
277         pci_write_config_dword(cached_dev, 0x68, val);
278
279         pci_read_config_dword(cached_dev, 0x68, &val);
280         if (val & 0x80)
281                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
282         else
283                 BUG();
284 }
285
286 static void vt8237_force_enable_hpet(struct pci_dev *dev)
287 {
288         u32 uninitialized_var(val);
289
290         if (!hpet_force_user || hpet_address || force_hpet_address)
291                 return;
292
293         pci_read_config_dword(dev, 0x68, &val);
294         /*
295          * Bit 7 is HPET enable bit.
296          * Bit 31:10 is HPET base address (contrary to what datasheet claims)
297          */
298         if (val & 0x80) {
299                 force_hpet_address = (val & ~0x3ff);
300                 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
301                         force_hpet_address);
302                 return;
303         }
304
305         /*
306          * HPET is disabled. Trying enabling at FED00000 and check
307          * whether it sticks
308          */
309         val = 0xfed00000 | 0x80;
310         pci_write_config_dword(dev, 0x68, val);
311
312         pci_read_config_dword(dev, 0x68, &val);
313         if (val & 0x80) {
314                 force_hpet_address = (val & ~0x3ff);
315                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
316                         "0x%lx\n", force_hpet_address);
317                 cached_dev = dev;
318                 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
319                 return;
320         }
321
322         dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
323 }
324
325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
326                          vt8237_force_enable_hpet);
327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
328                          vt8237_force_enable_hpet);
329
330 /*
331  * Undocumented chipset feature taken from LinuxBIOS.
332  */
333 static void nvidia_force_hpet_resume(void)
334 {
335         pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
336         printk(KERN_DEBUG "Force enabled HPET at resume\n");
337 }
338
339 static void nvidia_force_enable_hpet(struct pci_dev *dev)
340 {
341         u32 uninitialized_var(val);
342
343         if (!hpet_force_user || hpet_address || force_hpet_address)
344                 return;
345
346         pci_write_config_dword(dev, 0x44, 0xfed00001);
347         pci_read_config_dword(dev, 0x44, &val);
348         force_hpet_address = val & 0xfffffffe;
349         force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
350         dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
351                 force_hpet_address);
352         cached_dev = dev;
353         return;
354 }
355
356 /* ISA Bridges */
357 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
358                         nvidia_force_enable_hpet);
359 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
360                         nvidia_force_enable_hpet);
361
362 /* LPC bridges */
363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
364                         nvidia_force_enable_hpet);
365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
366                         nvidia_force_enable_hpet);
367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
368                         nvidia_force_enable_hpet);
369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
370                         nvidia_force_enable_hpet);
371 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
372                         nvidia_force_enable_hpet);
373 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
374                         nvidia_force_enable_hpet);
375 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
376                         nvidia_force_enable_hpet);
377 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
378                         nvidia_force_enable_hpet);
379
380 void force_hpet_resume(void)
381 {
382         switch (force_hpet_resume_type) {
383         case ICH_FORCE_HPET_RESUME:
384                 ich_force_hpet_resume();
385                 return;
386         case OLD_ICH_FORCE_HPET_RESUME:
387                 old_ich_force_hpet_resume();
388                 return;
389         case VT8237_FORCE_HPET_RESUME:
390                 vt8237_force_hpet_resume();
391                 return;
392         case NVIDIA_FORCE_HPET_RESUME:
393                 nvidia_force_hpet_resume();
394                 return;
395         default:
396                 break;
397         }
398 }
399
400 #endif