Merge branch 'x86-mm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6.git] / arch / x86 / kernel / process.c
1 #include <linux/errno.h>
2 #include <linux/kernel.h>
3 #include <linux/mm.h>
4 #include <linux/smp.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
9 #include <linux/pm.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <trace/power.h>
13 #include <asm/system.h>
14 #include <asm/apic.h>
15 #include <asm/syscalls.h>
16 #include <asm/idle.h>
17 #include <asm/uaccess.h>
18 #include <asm/i387.h>
19
20 unsigned long idle_halt;
21 EXPORT_SYMBOL(idle_halt);
22 unsigned long idle_nomwait;
23 EXPORT_SYMBOL(idle_nomwait);
24
25 struct kmem_cache *task_xstate_cachep;
26
27 DEFINE_TRACE(power_start);
28 DEFINE_TRACE(power_end);
29
30 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
31 {
32         *dst = *src;
33         if (src->thread.xstate) {
34                 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
35                                                       GFP_KERNEL);
36                 if (!dst->thread.xstate)
37                         return -ENOMEM;
38                 WARN_ON((unsigned long)dst->thread.xstate & 15);
39                 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
40         }
41         return 0;
42 }
43
44 void free_thread_xstate(struct task_struct *tsk)
45 {
46         if (tsk->thread.xstate) {
47                 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
48                 tsk->thread.xstate = NULL;
49         }
50 }
51
52 void free_thread_info(struct thread_info *ti)
53 {
54         free_thread_xstate(ti->task);
55         free_pages((unsigned long)ti, get_order(THREAD_SIZE));
56 }
57
58 void arch_task_cache_init(void)
59 {
60         task_xstate_cachep =
61                 kmem_cache_create("task_xstate", xstate_size,
62                                   __alignof__(union thread_xstate),
63                                   SLAB_PANIC, NULL);
64 }
65
66 /*
67  * Free current thread data structures etc..
68  */
69 void exit_thread(void)
70 {
71         struct task_struct *me = current;
72         struct thread_struct *t = &me->thread;
73         unsigned long *bp = t->io_bitmap_ptr;
74
75         if (bp) {
76                 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
77
78                 t->io_bitmap_ptr = NULL;
79                 clear_thread_flag(TIF_IO_BITMAP);
80                 /*
81                  * Careful, clear this in the TSS too:
82                  */
83                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
84                 t->io_bitmap_max = 0;
85                 put_cpu();
86                 kfree(bp);
87         }
88
89         ds_exit_thread(current);
90 }
91
92 void flush_thread(void)
93 {
94         struct task_struct *tsk = current;
95
96 #ifdef CONFIG_X86_64
97         if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
98                 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
99                 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
100                         clear_tsk_thread_flag(tsk, TIF_IA32);
101                 } else {
102                         set_tsk_thread_flag(tsk, TIF_IA32);
103                         current_thread_info()->status |= TS_COMPAT;
104                 }
105         }
106 #endif
107
108         clear_tsk_thread_flag(tsk, TIF_DEBUG);
109
110         tsk->thread.debugreg0 = 0;
111         tsk->thread.debugreg1 = 0;
112         tsk->thread.debugreg2 = 0;
113         tsk->thread.debugreg3 = 0;
114         tsk->thread.debugreg6 = 0;
115         tsk->thread.debugreg7 = 0;
116         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
117         /*
118          * Forget coprocessor state..
119          */
120         tsk->fpu_counter = 0;
121         clear_fpu(tsk);
122         clear_used_math();
123 }
124
125 static void hard_disable_TSC(void)
126 {
127         write_cr4(read_cr4() | X86_CR4_TSD);
128 }
129
130 void disable_TSC(void)
131 {
132         preempt_disable();
133         if (!test_and_set_thread_flag(TIF_NOTSC))
134                 /*
135                  * Must flip the CPU state synchronously with
136                  * TIF_NOTSC in the current running context.
137                  */
138                 hard_disable_TSC();
139         preempt_enable();
140 }
141
142 static void hard_enable_TSC(void)
143 {
144         write_cr4(read_cr4() & ~X86_CR4_TSD);
145 }
146
147 static void enable_TSC(void)
148 {
149         preempt_disable();
150         if (test_and_clear_thread_flag(TIF_NOTSC))
151                 /*
152                  * Must flip the CPU state synchronously with
153                  * TIF_NOTSC in the current running context.
154                  */
155                 hard_enable_TSC();
156         preempt_enable();
157 }
158
159 int get_tsc_mode(unsigned long adr)
160 {
161         unsigned int val;
162
163         if (test_thread_flag(TIF_NOTSC))
164                 val = PR_TSC_SIGSEGV;
165         else
166                 val = PR_TSC_ENABLE;
167
168         return put_user(val, (unsigned int __user *)adr);
169 }
170
171 int set_tsc_mode(unsigned int val)
172 {
173         if (val == PR_TSC_SIGSEGV)
174                 disable_TSC();
175         else if (val == PR_TSC_ENABLE)
176                 enable_TSC();
177         else
178                 return -EINVAL;
179
180         return 0;
181 }
182
183 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
184                       struct tss_struct *tss)
185 {
186         struct thread_struct *prev, *next;
187
188         prev = &prev_p->thread;
189         next = &next_p->thread;
190
191         if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
192             test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
193                 ds_switch_to(prev_p, next_p);
194         else if (next->debugctlmsr != prev->debugctlmsr)
195                 update_debugctlmsr(next->debugctlmsr);
196
197         if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
198                 set_debugreg(next->debugreg0, 0);
199                 set_debugreg(next->debugreg1, 1);
200                 set_debugreg(next->debugreg2, 2);
201                 set_debugreg(next->debugreg3, 3);
202                 /* no 4 and 5 */
203                 set_debugreg(next->debugreg6, 6);
204                 set_debugreg(next->debugreg7, 7);
205         }
206
207         if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
208             test_tsk_thread_flag(next_p, TIF_NOTSC)) {
209                 /* prev and next are different */
210                 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
211                         hard_disable_TSC();
212                 else
213                         hard_enable_TSC();
214         }
215
216         if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
217                 /*
218                  * Copy the relevant range of the IO bitmap.
219                  * Normally this is 128 bytes or less:
220                  */
221                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
222                        max(prev->io_bitmap_max, next->io_bitmap_max));
223         } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
224                 /*
225                  * Clear any possible leftover bits:
226                  */
227                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
228         }
229 }
230
231 int sys_fork(struct pt_regs *regs)
232 {
233         return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
234 }
235
236 /*
237  * This is trivial, and on the face of it looks like it
238  * could equally well be done in user mode.
239  *
240  * Not so, for quite unobvious reasons - register pressure.
241  * In user mode vfork() cannot have a stack frame, and if
242  * done by calling the "clone()" system call directly, you
243  * do not have enough call-clobbered registers to hold all
244  * the information you need.
245  */
246 int sys_vfork(struct pt_regs *regs)
247 {
248         return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
249                        NULL, NULL);
250 }
251
252
253 /*
254  * Idle related variables and functions
255  */
256 unsigned long boot_option_idle_override = 0;
257 EXPORT_SYMBOL(boot_option_idle_override);
258
259 /*
260  * Powermanagement idle function, if any..
261  */
262 void (*pm_idle)(void);
263 EXPORT_SYMBOL(pm_idle);
264
265 #ifdef CONFIG_X86_32
266 /*
267  * This halt magic was a workaround for ancient floppy DMA
268  * wreckage. It should be safe to remove.
269  */
270 static int hlt_counter;
271 void disable_hlt(void)
272 {
273         hlt_counter++;
274 }
275 EXPORT_SYMBOL(disable_hlt);
276
277 void enable_hlt(void)
278 {
279         hlt_counter--;
280 }
281 EXPORT_SYMBOL(enable_hlt);
282
283 static inline int hlt_use_halt(void)
284 {
285         return (!hlt_counter && boot_cpu_data.hlt_works_ok);
286 }
287 #else
288 static inline int hlt_use_halt(void)
289 {
290         return 1;
291 }
292 #endif
293
294 /*
295  * We use this if we don't have any better
296  * idle routine..
297  */
298 void default_idle(void)
299 {
300         if (hlt_use_halt()) {
301                 struct power_trace it;
302
303                 trace_power_start(&it, POWER_CSTATE, 1);
304                 current_thread_info()->status &= ~TS_POLLING;
305                 /*
306                  * TS_POLLING-cleared state must be visible before we
307                  * test NEED_RESCHED:
308                  */
309                 smp_mb();
310
311                 if (!need_resched())
312                         safe_halt();    /* enables interrupts racelessly */
313                 else
314                         local_irq_enable();
315                 current_thread_info()->status |= TS_POLLING;
316                 trace_power_end(&it);
317         } else {
318                 local_irq_enable();
319                 /* loop is done by the caller */
320                 cpu_relax();
321         }
322 }
323 #ifdef CONFIG_APM_MODULE
324 EXPORT_SYMBOL(default_idle);
325 #endif
326
327 void stop_this_cpu(void *dummy)
328 {
329         local_irq_disable();
330         /*
331          * Remove this CPU:
332          */
333         set_cpu_online(smp_processor_id(), false);
334         disable_local_APIC();
335
336         for (;;) {
337                 if (hlt_works(smp_processor_id()))
338                         halt();
339         }
340 }
341
342 static void do_nothing(void *unused)
343 {
344 }
345
346 /*
347  * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
348  * pm_idle and update to new pm_idle value. Required while changing pm_idle
349  * handler on SMP systems.
350  *
351  * Caller must have changed pm_idle to the new value before the call. Old
352  * pm_idle value will not be used by any CPU after the return of this function.
353  */
354 void cpu_idle_wait(void)
355 {
356         smp_mb();
357         /* kick all the CPUs so that they exit out of pm_idle */
358         smp_call_function(do_nothing, NULL, 1);
359 }
360 EXPORT_SYMBOL_GPL(cpu_idle_wait);
361
362 /*
363  * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
364  * which can obviate IPI to trigger checking of need_resched.
365  * We execute MONITOR against need_resched and enter optimized wait state
366  * through MWAIT. Whenever someone changes need_resched, we would be woken
367  * up from MWAIT (without an IPI).
368  *
369  * New with Core Duo processors, MWAIT can take some hints based on CPU
370  * capability.
371  */
372 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
373 {
374         struct power_trace it;
375
376         trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
377         if (!need_resched()) {
378                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
379                         clflush((void *)&current_thread_info()->flags);
380
381                 __monitor((void *)&current_thread_info()->flags, 0, 0);
382                 smp_mb();
383                 if (!need_resched())
384                         __mwait(ax, cx);
385         }
386         trace_power_end(&it);
387 }
388
389 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
390 static void mwait_idle(void)
391 {
392         struct power_trace it;
393         if (!need_resched()) {
394                 trace_power_start(&it, POWER_CSTATE, 1);
395                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
396                         clflush((void *)&current_thread_info()->flags);
397
398                 __monitor((void *)&current_thread_info()->flags, 0, 0);
399                 smp_mb();
400                 if (!need_resched())
401                         __sti_mwait(0, 0);
402                 else
403                         local_irq_enable();
404                 trace_power_end(&it);
405         } else
406                 local_irq_enable();
407 }
408
409 /*
410  * On SMP it's slightly faster (but much more power-consuming!)
411  * to poll the ->work.need_resched flag instead of waiting for the
412  * cross-CPU IPI to arrive. Use this option with caution.
413  */
414 static void poll_idle(void)
415 {
416         struct power_trace it;
417
418         trace_power_start(&it, POWER_CSTATE, 0);
419         local_irq_enable();
420         while (!need_resched())
421                 cpu_relax();
422         trace_power_end(&it);
423 }
424
425 /*
426  * mwait selection logic:
427  *
428  * It depends on the CPU. For AMD CPUs that support MWAIT this is
429  * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
430  * then depend on a clock divisor and current Pstate of the core. If
431  * all cores of a processor are in halt state (C1) the processor can
432  * enter the C1E (C1 enhanced) state. If mwait is used this will never
433  * happen.
434  *
435  * idle=mwait overrides this decision and forces the usage of mwait.
436  */
437 static int __cpuinitdata force_mwait;
438
439 #define MWAIT_INFO                      0x05
440 #define MWAIT_ECX_EXTENDED_INFO         0x01
441 #define MWAIT_EDX_C1                    0xf0
442
443 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
444 {
445         u32 eax, ebx, ecx, edx;
446
447         if (force_mwait)
448                 return 1;
449
450         if (c->cpuid_level < MWAIT_INFO)
451                 return 0;
452
453         cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
454         /* Check, whether EDX has extended info about MWAIT */
455         if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
456                 return 1;
457
458         /*
459          * edx enumeratios MONITOR/MWAIT extensions. Check, whether
460          * C1  supports MWAIT
461          */
462         return (edx & MWAIT_EDX_C1);
463 }
464
465 /*
466  * Check for AMD CPUs, which have potentially C1E support
467  */
468 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
469 {
470         if (c->x86_vendor != X86_VENDOR_AMD)
471                 return 0;
472
473         if (c->x86 < 0x0F)
474                 return 0;
475
476         /* Family 0x0f models < rev F do not have C1E */
477         if (c->x86 == 0x0f && c->x86_model < 0x40)
478                 return 0;
479
480         return 1;
481 }
482
483 static cpumask_var_t c1e_mask;
484 static int c1e_detected;
485
486 void c1e_remove_cpu(int cpu)
487 {
488         if (c1e_mask != NULL)
489                 cpumask_clear_cpu(cpu, c1e_mask);
490 }
491
492 /*
493  * C1E aware idle routine. We check for C1E active in the interrupt
494  * pending message MSR. If we detect C1E, then we handle it the same
495  * way as C3 power states (local apic timer and TSC stop)
496  */
497 static void c1e_idle(void)
498 {
499         if (need_resched())
500                 return;
501
502         if (!c1e_detected) {
503                 u32 lo, hi;
504
505                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
506                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
507                         c1e_detected = 1;
508                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
509                                 mark_tsc_unstable("TSC halt in AMD C1E");
510                         printk(KERN_INFO "System has AMD C1E enabled\n");
511                         set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
512                 }
513         }
514
515         if (c1e_detected) {
516                 int cpu = smp_processor_id();
517
518                 if (!cpumask_test_cpu(cpu, c1e_mask)) {
519                         cpumask_set_cpu(cpu, c1e_mask);
520                         /*
521                          * Force broadcast so ACPI can not interfere. Needs
522                          * to run with interrupts enabled as it uses
523                          * smp_function_call.
524                          */
525                         local_irq_enable();
526                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
527                                            &cpu);
528                         printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
529                                cpu);
530                         local_irq_disable();
531                 }
532                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
533
534                 default_idle();
535
536                 /*
537                  * The switch back from broadcast mode needs to be
538                  * called with interrupts disabled.
539                  */
540                  local_irq_disable();
541                  clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
542                  local_irq_enable();
543         } else
544                 default_idle();
545 }
546
547 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
548 {
549 #ifdef CONFIG_SMP
550         if (pm_idle == poll_idle && smp_num_siblings > 1) {
551                 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
552                         " performance may degrade.\n");
553         }
554 #endif
555         if (pm_idle)
556                 return;
557
558         if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
559                 /*
560                  * One CPU supports mwait => All CPUs supports mwait
561                  */
562                 printk(KERN_INFO "using mwait in idle threads.\n");
563                 pm_idle = mwait_idle;
564         } else if (check_c1e_idle(c)) {
565                 printk(KERN_INFO "using C1E aware idle routine\n");
566                 pm_idle = c1e_idle;
567         } else
568                 pm_idle = default_idle;
569 }
570
571 void __init init_c1e_mask(void)
572 {
573         /* If we're using c1e_idle, we need to allocate c1e_mask. */
574         if (pm_idle == c1e_idle) {
575                 alloc_cpumask_var(&c1e_mask, GFP_KERNEL);
576                 cpumask_clear(c1e_mask);
577         }
578 }
579
580 static int __init idle_setup(char *str)
581 {
582         if (!str)
583                 return -EINVAL;
584
585         if (!strcmp(str, "poll")) {
586                 printk("using polling idle threads.\n");
587                 pm_idle = poll_idle;
588         } else if (!strcmp(str, "mwait"))
589                 force_mwait = 1;
590         else if (!strcmp(str, "halt")) {
591                 /*
592                  * When the boot option of idle=halt is added, halt is
593                  * forced to be used for CPU idle. In such case CPU C2/C3
594                  * won't be used again.
595                  * To continue to load the CPU idle driver, don't touch
596                  * the boot_option_idle_override.
597                  */
598                 pm_idle = default_idle;
599                 idle_halt = 1;
600                 return 0;
601         } else if (!strcmp(str, "nomwait")) {
602                 /*
603                  * If the boot option of "idle=nomwait" is added,
604                  * it means that mwait will be disabled for CPU C2/C3
605                  * states. In such case it won't touch the variable
606                  * of boot_option_idle_override.
607                  */
608                 idle_nomwait = 1;
609                 return 0;
610         } else
611                 return -1;
612
613         boot_option_idle_override = 1;
614         return 0;
615 }
616 early_param("idle", idle_setup);
617
618 unsigned long arch_align_stack(unsigned long sp)
619 {
620         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
621                 sp -= get_random_int() % 8192;
622         return sp & ~0xf;
623 }
624
625 unsigned long arch_randomize_brk(struct mm_struct *mm)
626 {
627         unsigned long range_end = mm->brk + 0x02000000;
628         return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
629 }
630