arch/x86/kernel/pci-calgary_64.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright IBM Corporation, 2006-2007
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/crash_dump.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <linux/scatterlist.h>
  39 #include <linux/iommu-helper.h>
  40
  41 #include <asm/iommu.h>
  42 #include <asm/calgary.h>
  43 #include <asm/tce.h>
  44 #include <asm/pci-direct.h>
  45 #include <asm/system.h>
  46 #include <asm/dma.h>
  47 #include <asm/rio.h>
  48 #include <asm/bios_ebda.h>
  49
  50 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  51 int use_calgary __read_mostly = 1;
  52 #else
  53 int use_calgary __read_mostly = 0;
  54 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  55
  56 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  57 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  58
  59 /* register offsets inside the host bridge space */
  60 #define CALGARY_CONFIG_REG      0x0108
  61 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  62 #define PHB_PLSSR_OFFSET        0x0120
  63 #define PHB_CONFIG_RW_OFFSET    0x0160
  64 #define PHB_IOBASE_BAR_LOW      0x0170
  65 #define PHB_IOBASE_BAR_HIGH     0x0180
  66 #define PHB_MEM_1_LOW           0x0190
  67 #define PHB_MEM_1_HIGH          0x01A0
  68 #define PHB_IO_ADDR_SIZE        0x01B0
  69 #define PHB_MEM_1_SIZE          0x01C0
  70 #define PHB_MEM_ST_OFFSET       0x01D0
  71 #define PHB_AER_OFFSET          0x0200
  72 #define PHB_CONFIG_0_HIGH       0x0220
  73 #define PHB_CONFIG_0_LOW        0x0230
  74 #define PHB_CONFIG_0_END        0x0240
  75 #define PHB_MEM_2_LOW           0x02B0
  76 #define PHB_MEM_2_HIGH          0x02C0
  77 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  78 #define PHB_MEM_2_SIZE_LOW      0x02E0
  79 #define PHB_DOSHOLE_OFFSET      0x08E0
  80
  81 /* CalIOC2 specific */
  82 #define PHB_SAVIOR_L2           0x0DB0
  83 #define PHB_PAGE_MIG_CTRL       0x0DA8
  84 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  85 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  86
  87 /* PHB_CONFIG_RW */
  88 #define PHB_TCE_ENABLE          0x20000000
  89 #define PHB_SLOT_DISABLE        0x1C000000
  90 #define PHB_DAC_DISABLE         0x01000000
  91 #define PHB_MEM2_ENABLE         0x00400000
  92 #define PHB_MCSR_ENABLE         0x00100000
  93 /* TAR (Table Address Register) */
  94 #define TAR_SW_BITS             0x0000ffffffff800fUL
  95 #define TAR_VALID               0x0000000000000008UL
  96 /* CSR (Channel/DMA Status Register) */
  97 #define CSR_AGENT_MASK          0xffe0ffff
  98 /* CCR (Calgary Configuration Register) */
  99 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
 100 /* PMCR/PMDR (Page Migration Control/Debug Registers */
 101 #define PMR_SOFTSTOP            0x80000000
 102 #define PMR_SOFTSTOPFAULT       0x40000000
 103 #define PMR_HARDSTOP            0x20000000
 104
 105 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
 106 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
 107 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
 108 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
 109 #define PHBS_PER_CALGARY        4
 110
 111 /* register offsets in Calgary's internal register space */
 112 static const unsigned long tar_offsets[] = {
 113         0x0580 /* TAR0 */,
 114         0x0588 /* TAR1 */,
 115         0x0590 /* TAR2 */,
 116         0x0598 /* TAR3 */
 117 };
 118
 119 static const unsigned long split_queue_offsets[] = {
 120         0x4870 /* SPLIT QUEUE 0 */,
 121         0x5870 /* SPLIT QUEUE 1 */,
 122         0x6870 /* SPLIT QUEUE 2 */,
 123         0x7870 /* SPLIT QUEUE 3 */
 124 };
 125
 126 static const unsigned long phb_offsets[] = {
 127         0x8000 /* PHB0 */,
 128         0x9000 /* PHB1 */,
 129         0xA000 /* PHB2 */,
 130         0xB000 /* PHB3 */
 131 };
 132
 133 /* PHB debug registers */
 134
 135 static const unsigned long phb_debug_offsets[] = {
 136         0x4000  /* PHB 0 DEBUG */,
 137         0x5000  /* PHB 1 DEBUG */,
 138         0x6000  /* PHB 2 DEBUG */,
 139         0x7000  /* PHB 3 DEBUG */
 140 };
 141
 142 /*
 143  * STUFF register for each debug PHB,
 144  * byte 1 = start bus number, byte 2 = end bus number
 145  */
 146
 147 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 148
 149 #define EMERGENCY_PAGES 32 /* = 128KB */
 150
 151 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 152 static int translate_empty_slots __read_mostly = 0;
 153 static int calgary_detected __read_mostly = 0;
 154
 155 static struct rio_table_hdr     *rio_table_hdr __initdata;
 156 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 157 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 158
 159 struct calgary_bus_info {
 160         void *tce_space;
 161         unsigned char translation_disabled;
 162         signed char phbid;
 163         void __iomem *bbar;
 164 };
 165
 166 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 167 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 168 static void calgary_dump_error_regs(struct iommu_table *tbl);
 169 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 170 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 171 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 172 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
 173 static void get_tce_space_from_tar(void);
 174
 175 static struct cal_chipset_ops calgary_chip_ops = {
 176         .handle_quirks = calgary_handle_quirks,
 177         .tce_cache_blast = calgary_tce_cache_blast,
 178         .dump_error_regs = calgary_dump_error_regs
 179 };
 180
 181 static struct cal_chipset_ops calioc2_chip_ops = {
 182         .handle_quirks = calioc2_handle_quirks,
 183         .tce_cache_blast = calioc2_tce_cache_blast,
 184         .dump_error_regs = calioc2_dump_error_regs
 185 };
 186
 187 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 188
 189 /* enable this to stress test the chip's TCE cache */
 190 #ifdef CONFIG_IOMMU_DEBUG
 191 static int debugging = 1;
 192
 193 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 194         int expected, unsigned long start, unsigned long end)
 195 {
 196         unsigned long idx = start;
 197
 198         BUG_ON(start >= end);
 199
 200         while (idx < end) {
 201                 if (!!test_bit(idx, bitmap) != expected)
 202                         return idx;
 203                 ++idx;
 204         }
 205
 206         /* all bits have the expected value */
 207         return ~0UL;
 208 }
 209 #else /* debugging is disabled */
 210 static int debugging;
 211
 212 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 213         int expected, unsigned long start, unsigned long end)
 214 {
 215         return ~0UL;
 216 }
 217
 218 #endif /* CONFIG_IOMMU_DEBUG */
 219
 220 static inline int translation_enabled(struct iommu_table *tbl)
 221 {
 222         /* only PHBs with translation enabled have an IOMMU table */
 223         return (tbl != NULL);
 224 }
 225
 226 static void iommu_range_reserve(struct iommu_table *tbl,
 227         unsigned long start_addr, unsigned int npages)
 228 {
 229         unsigned long index;
 230         unsigned long end;
 231         unsigned long badbit;
 232         unsigned long flags;
 233
 234         index = start_addr >> PAGE_SHIFT;
 235
 236         /* bail out if we're asked to reserve a region we don't cover */
 237         if (index >= tbl->it_size)
 238                 return;
 239
 240         end = index + npages;
 241         if (end > tbl->it_size) /* don't go off the table */
 242                 end = tbl->it_size;
 243
 244         spin_lock_irqsave(&tbl->it_lock, flags);
 245
 246         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 247         if (badbit != ~0UL) {
 248                 if (printk_ratelimit())
 249                         printk(KERN_ERR "Calgary: entry already allocated at "
 250                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 251                                badbit, tbl, start_addr, npages);
 252         }
 253
 254         iommu_area_reserve(tbl->it_map, index, npages);
 255
 256         spin_unlock_irqrestore(&tbl->it_lock, flags);
 257 }
 258
 259 static unsigned long iommu_range_alloc(struct device *dev,
 260                                        struct iommu_table *tbl,
 261                                        unsigned int npages)
 262 {
 263         unsigned long flags;
 264         unsigned long offset;
 265         unsigned long boundary_size;
 266
 267         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 268                               PAGE_SIZE) >> PAGE_SHIFT;
 269
 270         BUG_ON(npages == 0);
 271
 272         spin_lock_irqsave(&tbl->it_lock, flags);
 273
 274         offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
 275                                   npages, 0, boundary_size, 0);
 276         if (offset == ~0UL) {
 277                 tbl->chip_ops->tce_cache_blast(tbl);
 278
 279                 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
 280                                           npages, 0, boundary_size, 0);
 281                 if (offset == ~0UL) {
 282                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 283                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 284                         if (panic_on_overflow)
 285                                 panic("Calgary: fix the allocator.\n");
 286                         else
 287                                 return bad_dma_address;
 288                 }
 289         }
 290
 291         tbl->it_hint = offset + npages;
 292         BUG_ON(tbl->it_hint > tbl->it_size);
 293
 294         spin_unlock_irqrestore(&tbl->it_lock, flags);
 295
 296         return offset;
 297 }
 298
 299 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
 300                               void *vaddr, unsigned int npages, int direction)
 301 {
 302         unsigned long entry;
 303         dma_addr_t ret = bad_dma_address;
 304
 305         entry = iommu_range_alloc(dev, tbl, npages);
 306
 307         if (unlikely(entry == bad_dma_address))
 308                 goto error;
 309
 310         /* set the return dma address */
 311         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 312
 313         /* put the TCEs in the HW table */
 314         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 315                   direction);
 316
 317         return ret;
 318
 319 error:
 320         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 321                "iommu %p\n", npages, tbl);
 322         return bad_dma_address;
 323 }
 324
 325 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 326         unsigned int npages)
 327 {
 328         unsigned long entry;
 329         unsigned long badbit;
 330         unsigned long badend;
 331         unsigned long flags;
 332
 333         /* were we called with bad_dma_address? */
 334         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
 335         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
 336                 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
 337                        "address 0x%Lx\n", dma_addr);
 338                 return;
 339         }
 340
 341         entry = dma_addr >> PAGE_SHIFT;
 342
 343         BUG_ON(entry + npages > tbl->it_size);
 344
 345         tce_free(tbl, entry, npages);
 346
 347         spin_lock_irqsave(&tbl->it_lock, flags);
 348
 349         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 350         if (badbit != ~0UL) {
 351                 if (printk_ratelimit())
 352                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 353                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 354                                badbit, tbl, dma_addr, entry, npages);
 355         }
 356
 357         iommu_area_free(tbl->it_map, entry, npages);
 358
 359         spin_unlock_irqrestore(&tbl->it_lock, flags);
 360 }
 361
 362 static inline struct iommu_table *find_iommu_table(struct device *dev)
 363 {
 364         struct pci_dev *pdev;
 365         struct pci_bus *pbus;
 366         struct iommu_table *tbl;
 367
 368         pdev = to_pci_dev(dev);
 369
 370         pbus = pdev->bus;
 371
 372         /* is the device behind a bridge? Look for the root bus */
 373         while (pbus->parent)
 374                 pbus = pbus->parent;
 375
 376         tbl = pci_iommu(pbus);
 377
 378         BUG_ON(tbl && (tbl->it_busno != pbus->number));
 379
 380         return tbl;
 381 }
 382
 383 static void calgary_unmap_sg(struct device *dev,
 384         struct scatterlist *sglist, int nelems, int direction)
 385 {
 386         struct iommu_table *tbl = find_iommu_table(dev);
 387         struct scatterlist *s;
 388         int i;
 389
 390         if (!translation_enabled(tbl))
 391                 return;
 392
 393         for_each_sg(sglist, s, nelems, i) {
 394                 unsigned int npages;
 395                 dma_addr_t dma = s->dma_address;
 396                 unsigned int dmalen = s->dma_length;
 397
 398                 if (dmalen == 0)
 399                         break;
 400
 401                 npages = iommu_num_pages(dma, dmalen, PAGE_SIZE);
 402                 iommu_free(tbl, dma, npages);
 403         }
 404 }
 405
 406 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 407         int nelems, int direction)
 408 {
 409         struct iommu_table *tbl = find_iommu_table(dev);
 410         struct scatterlist *s;
 411         unsigned long vaddr;
 412         unsigned int npages;
 413         unsigned long entry;
 414         int i;
 415
 416         for_each_sg(sg, s, nelems, i) {
 417                 BUG_ON(!sg_page(s));
 418
 419                 vaddr = (unsigned long) sg_virt(s);
 420                 npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE);
 421
 422                 entry = iommu_range_alloc(dev, tbl, npages);
 423                 if (entry == bad_dma_address) {
 424                         /* makes sure unmap knows to stop */
 425                         s->dma_length = 0;
 426                         goto error;
 427                 }
 428
 429                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 430
 431                 /* insert into HW table */
 432                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 433                           direction);
 434
 435                 s->dma_length = s->length;
 436         }
 437
 438         return nelems;
 439 error:
 440         calgary_unmap_sg(dev, sg, nelems, direction);
 441         for_each_sg(sg, s, nelems, i) {
 442                 sg->dma_address = bad_dma_address;
 443                 sg->dma_length = 0;
 444         }
 445         return 0;
 446 }
 447
 448 static dma_addr_t calgary_map_page(struct device *dev, struct page *page,
 449                                    unsigned long offset, size_t size,
 450                                    enum dma_data_direction dir,
 451                                    struct dma_attrs *attrs)
 452 {
 453         void *vaddr = page_address(page) + offset;
 454         unsigned long uaddr;
 455         unsigned int npages;
 456         struct iommu_table *tbl = find_iommu_table(dev);
 457
 458         uaddr = (unsigned long)vaddr;
 459         npages = iommu_num_pages(uaddr, size, PAGE_SIZE);
 460
 461         return iommu_alloc(dev, tbl, vaddr, npages, dir);
 462 }
 463
 464 static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr,
 465                                size_t size, enum dma_data_direction dir,
 466                                struct dma_attrs *attrs)
 467 {
 468         struct iommu_table *tbl = find_iommu_table(dev);
 469         unsigned int npages;
 470
 471         npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
 472         iommu_free(tbl, dma_addr, npages);
 473 }
 474
 475 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 476         dma_addr_t *dma_handle, gfp_t flag)
 477 {
 478         void *ret = NULL;
 479         dma_addr_t mapping;
 480         unsigned int npages, order;
 481         struct iommu_table *tbl = find_iommu_table(dev);
 482
 483         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 484         npages = size >> PAGE_SHIFT;
 485         order = get_order(size);
 486
 487         flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
 488
 489         /* alloc enough pages (and possibly more) */
 490         ret = (void *)__get_free_pages(flag, order);
 491         if (!ret)
 492                 goto error;
 493         memset(ret, 0, size);
 494
 495         /* set up tces to cover the allocated range */
 496         mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
 497         if (mapping == bad_dma_address)
 498                 goto free;
 499         *dma_handle = mapping;
 500         return ret;
 501 free:
 502         free_pages((unsigned long)ret, get_order(size));
 503         ret = NULL;
 504 error:
 505         return ret;
 506 }
 507
 508 static void calgary_free_coherent(struct device *dev, size_t size,
 509                                   void *vaddr, dma_addr_t dma_handle)
 510 {
 511         unsigned int npages;
 512         struct iommu_table *tbl = find_iommu_table(dev);
 513
 514         size = PAGE_ALIGN(size);
 515         npages = size >> PAGE_SHIFT;
 516
 517         iommu_free(tbl, dma_handle, npages);
 518         free_pages((unsigned long)vaddr, get_order(size));
 519 }
 520
 521 static struct dma_mapping_ops calgary_dma_ops = {
 522         .alloc_coherent = calgary_alloc_coherent,
 523         .free_coherent = calgary_free_coherent,
 524         .map_sg = calgary_map_sg,
 525         .unmap_sg = calgary_unmap_sg,
 526         .map_page = calgary_map_page,
 527         .unmap_page = calgary_unmap_page,
 528 };
 529
 530 static inline void __iomem * busno_to_bbar(unsigned char num)
 531 {
 532         return bus_info[num].bbar;
 533 }
 534
 535 static inline int busno_to_phbid(unsigned char num)
 536 {
 537         return bus_info[num].phbid;
 538 }
 539
 540 static inline unsigned long split_queue_offset(unsigned char num)
 541 {
 542         size_t idx = busno_to_phbid(num);
 543
 544         return split_queue_offsets[idx];
 545 }
 546
 547 static inline unsigned long tar_offset(unsigned char num)
 548 {
 549         size_t idx = busno_to_phbid(num);
 550
 551         return tar_offsets[idx];
 552 }
 553
 554 static inline unsigned long phb_offset(unsigned char num)
 555 {
 556         size_t idx = busno_to_phbid(num);
 557
 558         return phb_offsets[idx];
 559 }
 560
 561 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 562 {
 563         unsigned long target = ((unsigned long)bar) | offset;
 564         return (void __iomem*)target;
 565 }
 566
 567 static inline int is_calioc2(unsigned short device)
 568 {
 569         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 570 }
 571
 572 static inline int is_calgary(unsigned short device)
 573 {
 574         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 575 }
 576
 577 static inline int is_cal_pci_dev(unsigned short device)
 578 {
 579         return (is_calgary(device) || is_calioc2(device));
 580 }
 581
 582 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 583 {
 584         u64 val;
 585         u32 aer;
 586         int i = 0;
 587         void __iomem *bbar = tbl->bbar;
 588         void __iomem *target;
 589
 590         /* disable arbitration on the bus */
 591         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 592         aer = readl(target);
 593         writel(0, target);
 594
 595         /* read plssr to ensure it got there */
 596         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 597         val = readl(target);
 598
 599         /* poll split queues until all DMA activity is done */
 600         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 601         do {
 602                 val = readq(target);
 603                 i++;
 604         } while ((val & 0xff) != 0xff && i < 100);
 605         if (i == 100)
 606                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 607                        "continuing anyway\n");
 608
 609         /* invalidate TCE cache */
 610         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 611         writeq(tbl->tar_val, target);
 612
 613         /* enable arbitration */
 614         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 615         writel(aer, target);
 616         (void)readl(target); /* flush */
 617 }
 618
 619 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 620 {
 621         void __iomem *bbar = tbl->bbar;
 622         void __iomem *target;
 623         u64 val64;
 624         u32 val;
 625         int i = 0;
 626         int count = 1;
 627         unsigned char bus = tbl->it_busno;
 628
 629 begin:
 630         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 631                "sequence - count %d\n", bus, count);
 632
 633         /* 1. using the Page Migration Control reg set SoftStop */
 634         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 635         val = be32_to_cpu(readl(target));
 636         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 637         val |= PMR_SOFTSTOP;
 638         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 639         writel(cpu_to_be32(val), target);
 640
 641         /* 2. poll split queues until all DMA activity is done */
 642         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 643         target = calgary_reg(bbar, split_queue_offset(bus));
 644         do {
 645                 val64 = readq(target);
 646                 i++;
 647         } while ((val64 & 0xff) != 0xff && i < 100);
 648         if (i == 100)
 649                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
 650                        "continuing anyway\n");
 651
 652         /* 3. poll Page Migration DEBUG for SoftStopFault */
 653         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 654         val = be32_to_cpu(readl(target));
 655         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 656
 657         /* 4. if SoftStopFault - goto (1) */
 658         if (val & PMR_SOFTSTOPFAULT) {
 659                 if (++count < 100)
 660                         goto begin;
 661                 else {
 662                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
 663                                "aborting TCE cache flush sequence!\n");
 664                         return; /* pray for the best */
 665                 }
 666         }
 667
 668         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 669         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 670         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 671         val = be32_to_cpu(readl(target));
 672         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 673         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 674         val = be32_to_cpu(readl(target));
 675         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 676
 677         /* 6. invalidate TCE cache */
 678         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 679         target = calgary_reg(bbar, tar_offset(bus));
 680         writeq(tbl->tar_val, target);
 681
 682         /* 7. Re-read PMCR */
 683         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 684         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 685         val = be32_to_cpu(readl(target));
 686         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 687
 688         /* 8. Remove HardStop */
 689         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 690         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 691         val = 0;
 692         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 693         writel(cpu_to_be32(val), target);
 694         val = be32_to_cpu(readl(target));
 695         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 696 }
 697
 698 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 699         u64 limit)
 700 {
 701         unsigned int numpages;
 702
 703         limit = limit | 0xfffff;
 704         limit++;
 705
 706         numpages = ((limit - start) >> PAGE_SHIFT);
 707         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 708 }
 709
 710 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 711 {
 712         void __iomem *target;
 713         u64 low, high, sizelow;
 714         u64 start, limit;
 715         struct iommu_table *tbl = pci_iommu(dev->bus);
 716         unsigned char busnum = dev->bus->number;
 717         void __iomem *bbar = tbl->bbar;
 718
 719         /* peripheral MEM_1 region */
 720         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 721         low = be32_to_cpu(readl(target));
 722         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 723         high = be32_to_cpu(readl(target));
 724         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 725         sizelow = be32_to_cpu(readl(target));
 726
 727         start = (high << 32) | low;
 728         limit = sizelow;
 729
 730         calgary_reserve_mem_region(dev, start, limit);
 731 }
 732
 733 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 734 {
 735         void __iomem *target;
 736         u32 val32;
 737         u64 low, high, sizelow, sizehigh;
 738         u64 start, limit;
 739         struct iommu_table *tbl = pci_iommu(dev->bus);
 740         unsigned char busnum = dev->bus->number;
 741         void __iomem *bbar = tbl->bbar;
 742
 743         /* is it enabled? */
 744         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 745         val32 = be32_to_cpu(readl(target));
 746         if (!(val32 & PHB_MEM2_ENABLE))
 747                 return;
 748
 749         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 750         low = be32_to_cpu(readl(target));
 751         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 752         high = be32_to_cpu(readl(target));
 753         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 754         sizelow = be32_to_cpu(readl(target));
 755         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 756         sizehigh = be32_to_cpu(readl(target));
 757
 758         start = (high << 32) | low;
 759         limit = (sizehigh << 32) | sizelow;
 760
 761         calgary_reserve_mem_region(dev, start, limit);
 762 }
 763
 764 /*
 765  * some regions of the IO address space do not get translated, so we
 766  * must not give devices IO addresses in those regions. The regions
 767  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 768  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 769  * later.
 770  */
 771 static void __init calgary_reserve_regions(struct pci_dev *dev)
 772 {
 773         unsigned int npages;
 774         u64 start;
 775         struct iommu_table *tbl = pci_iommu(dev->bus);
 776
 777         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 778         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
 779
 780         /* avoid the BIOS/VGA first 640KB-1MB region */
 781         /* for CalIOC2 - avoid the entire first MB */
 782         if (is_calgary(dev->device)) {
 783                 start = (640 * 1024);
 784                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 785         } else { /* calioc2 */
 786                 start = 0;
 787                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 788         }
 789         iommu_range_reserve(tbl, start, npages);
 790
 791         /* reserve the two PCI peripheral memory regions in IO space */
 792         calgary_reserve_peripheral_mem_1(dev);
 793         calgary_reserve_peripheral_mem_2(dev);
 794 }
 795
 796 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 797 {
 798         u64 val64;
 799         u64 table_phys;
 800         void __iomem *target;
 801         int ret;
 802         struct iommu_table *tbl;
 803
 804         /* build TCE tables for each PHB */
 805         ret = build_tce_table(dev, bbar);
 806         if (ret)
 807                 return ret;
 808
 809         tbl = pci_iommu(dev->bus);
 810         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 811
 812         if (is_kdump_kernel())
 813                 calgary_init_bitmap_from_tce_table(tbl);
 814         else
 815                 tce_free(tbl, 0, tbl->it_size);
 816
 817         if (is_calgary(dev->device))
 818                 tbl->chip_ops = &calgary_chip_ops;
 819         else if (is_calioc2(dev->device))
 820                 tbl->chip_ops = &calioc2_chip_ops;
 821         else
 822                 BUG();
 823
 824         calgary_reserve_regions(dev);
 825
 826         /* set TARs for each PHB */
 827         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 828         val64 = be64_to_cpu(readq(target));
 829
 830         /* zero out all TAR bits under sw control */
 831         val64 &= ~TAR_SW_BITS;
 832         table_phys = (u64)__pa(tbl->it_base);
 833
 834         val64 |= table_phys;
 835
 836         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 837         val64 |= (u64) specified_table_size;
 838
 839         tbl->tar_val = cpu_to_be64(val64);
 840
 841         writeq(tbl->tar_val, target);
 842         readq(target); /* flush */
 843
 844         return 0;
 845 }
 846
 847 static void __init calgary_free_bus(struct pci_dev *dev)
 848 {
 849         u64 val64;
 850         struct iommu_table *tbl = pci_iommu(dev->bus);
 851         void __iomem *target;
 852         unsigned int bitmapsz;
 853
 854         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 855         val64 = be64_to_cpu(readq(target));
 856         val64 &= ~TAR_SW_BITS;
 857         writeq(cpu_to_be64(val64), target);
 858         readq(target); /* flush */
 859
 860         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 861         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 862         tbl->it_map = NULL;
 863
 864         kfree(tbl);
 865
 866         set_pci_iommu(dev->bus, NULL);
 867
 868         /* Can't free bootmem allocated memory after system is up :-( */
 869         bus_info[dev->bus->number].tce_space = NULL;
 870 }
 871
 872 static void calgary_dump_error_regs(struct iommu_table *tbl)
 873 {
 874         void __iomem *bbar = tbl->bbar;
 875         void __iomem *target;
 876         u32 csr, plssr;
 877
 878         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 879         csr = be32_to_cpu(readl(target));
 880
 881         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 882         plssr = be32_to_cpu(readl(target));
 883
 884         /* If no error, the agent ID in the CSR is not valid */
 885         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
 886                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
 887 }
 888
 889 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 890 {
 891         void __iomem *bbar = tbl->bbar;
 892         u32 csr, csmr, plssr, mck, rcstat;
 893         void __iomem *target;
 894         unsigned long phboff = phb_offset(tbl->it_busno);
 895         unsigned long erroff;
 896         u32 errregs[7];
 897         int i;
 898
 899         /* dump CSR */
 900         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 901         csr = be32_to_cpu(readl(target));
 902         /* dump PLSSR */
 903         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 904         plssr = be32_to_cpu(readl(target));
 905         /* dump CSMR */
 906         target = calgary_reg(bbar, phboff | 0x290);
 907         csmr = be32_to_cpu(readl(target));
 908         /* dump mck */
 909         target = calgary_reg(bbar, phboff | 0x800);
 910         mck = be32_to_cpu(readl(target));
 911
 912         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
 913                tbl->it_busno);
 914
 915         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 916                csr, plssr, csmr, mck);
 917
 918         /* dump rest of error regs */
 919         printk(KERN_EMERG "Calgary: ");
 920         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 921                 /* err regs are at 0x810 - 0x870 */
 922                 erroff = (0x810 + (i * 0x10));
 923                 target = calgary_reg(bbar, phboff | erroff);
 924                 errregs[i] = be32_to_cpu(readl(target));
 925                 printk("0x%08x@0x%lx ", errregs[i], erroff);
 926         }
 927         printk("\n");
 928
 929         /* root complex status */
 930         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 931         rcstat = be32_to_cpu(readl(target));
 932         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 933                PHB_ROOT_COMPLEX_STATUS);
 934 }
 935
 936 static void calgary_watchdog(unsigned long data)
 937 {
 938         struct pci_dev *dev = (struct pci_dev *)data;
 939         struct iommu_table *tbl = pci_iommu(dev->bus);
 940         void __iomem *bbar = tbl->bbar;
 941         u32 val32;
 942         void __iomem *target;
 943
 944         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 945         val32 = be32_to_cpu(readl(target));
 946
 947         /* If no error, the agent ID in the CSR is not valid */
 948         if (val32 & CSR_AGENT_MASK) {
 949                 tbl->chip_ops->dump_error_regs(tbl);
 950
 951                 /* reset error */
 952                 writel(0, target);
 953
 954                 /* Disable bus that caused the error */
 955                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 956                                      PHB_CONFIG_RW_OFFSET);
 957                 val32 = be32_to_cpu(readl(target));
 958                 val32 |= PHB_SLOT_DISABLE;
 959                 writel(cpu_to_be32(val32), target);
 960                 readl(target); /* flush */
 961         } else {
 962                 /* Reset the timer */
 963                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 964         }
 965 }
 966
 967 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 968         unsigned char busnum, unsigned long timeout)
 969 {
 970         u64 val64;
 971         void __iomem *target;
 972         unsigned int phb_shift = ~0; /* silence gcc */
 973         u64 mask;
 974
 975         switch (busno_to_phbid(busnum)) {
 976         case 0: phb_shift = (63 - 19);
 977                 break;
 978         case 1: phb_shift = (63 - 23);
 979                 break;
 980         case 2: phb_shift = (63 - 27);
 981                 break;
 982         case 3: phb_shift = (63 - 35);
 983                 break;
 984         default:
 985                 BUG_ON(busno_to_phbid(busnum));
 986         }
 987
 988         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
 989         val64 = be64_to_cpu(readq(target));
 990
 991         /* zero out this PHB's timer bits */
 992         mask = ~(0xFUL << phb_shift);
 993         val64 &= mask;
 994         val64 |= (timeout << phb_shift);
 995         writeq(cpu_to_be64(val64), target);
 996         readq(target); /* flush */
 997 }
 998
 999 static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1000 {
1001         unsigned char busnum = dev->bus->number;
1002         void __iomem *bbar = tbl->bbar;
1003         void __iomem *target;
1004         u32 val;
1005
1006         /*
1007          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1008          */
1009         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1010         val = cpu_to_be32(readl(target));
1011         val |= 0x00800000;
1012         writel(cpu_to_be32(val), target);
1013 }
1014
1015 static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1016 {
1017         unsigned char busnum = dev->bus->number;
1018
1019         /*
1020          * Give split completion a longer timeout on bus 1 for aic94xx
1021          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1022          */
1023         if (is_calgary(dev->device) && (busnum == 1))
1024                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1025                                                      CCR_2SEC_TIMEOUT);
1026 }
1027
1028 static void __init calgary_enable_translation(struct pci_dev *dev)
1029 {
1030         u32 val32;
1031         unsigned char busnum;
1032         void __iomem *target;
1033         void __iomem *bbar;
1034         struct iommu_table *tbl;
1035
1036         busnum = dev->bus->number;
1037         tbl = pci_iommu(dev->bus);
1038         bbar = tbl->bbar;
1039
1040         /* enable TCE in PHB Config Register */
1041         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1042         val32 = be32_to_cpu(readl(target));
1043         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1044
1045         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1046                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1047                "Calgary" : "CalIOC2", busnum);
1048         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1049                "bus.\n");
1050
1051         writel(cpu_to_be32(val32), target);
1052         readl(target); /* flush */
1053
1054         init_timer(&tbl->watchdog_timer);
1055         tbl->watchdog_timer.function = &calgary_watchdog;
1056         tbl->watchdog_timer.data = (unsigned long)dev;
1057         mod_timer(&tbl->watchdog_timer, jiffies);
1058 }
1059
1060 static void __init calgary_disable_translation(struct pci_dev *dev)
1061 {
1062         u32 val32;
1063         unsigned char busnum;
1064         void __iomem *target;
1065         void __iomem *bbar;
1066         struct iommu_table *tbl;
1067
1068         busnum = dev->bus->number;
1069         tbl = pci_iommu(dev->bus);
1070         bbar = tbl->bbar;
1071
1072         /* disable TCE in PHB Config Register */
1073         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1074         val32 = be32_to_cpu(readl(target));
1075         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1076
1077         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1078         writel(cpu_to_be32(val32), target);
1079         readl(target); /* flush */
1080
1081         del_timer_sync(&tbl->watchdog_timer);
1082 }
1083
1084 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1085 {
1086         pci_dev_get(dev);
1087         set_pci_iommu(dev->bus, NULL);
1088
1089         /* is the device behind a bridge? */
1090         if (dev->bus->parent)
1091                 dev->bus->parent->self = dev;
1092         else
1093                 dev->bus->self = dev;
1094 }
1095
1096 static int __init calgary_init_one(struct pci_dev *dev)
1097 {
1098         void __iomem *bbar;
1099         struct iommu_table *tbl;
1100         int ret;
1101
1102         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1103
1104         bbar = busno_to_bbar(dev->bus->number);
1105         ret = calgary_setup_tar(dev, bbar);
1106         if (ret)
1107                 goto done;
1108
1109         pci_dev_get(dev);
1110
1111         if (dev->bus->parent) {
1112                 if (dev->bus->parent->self)
1113                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1114                                "bus->parent->self!\n", dev);
1115                 dev->bus->parent->self = dev;
1116         } else
1117                 dev->bus->self = dev;
1118
1119         tbl = pci_iommu(dev->bus);
1120         tbl->chip_ops->handle_quirks(tbl, dev);
1121
1122         calgary_enable_translation(dev);
1123
1124         return 0;
1125
1126 done:
1127         return ret;
1128 }
1129
1130 static int __init calgary_locate_bbars(void)
1131 {
1132         int ret;
1133         int rioidx, phb, bus;
1134         void __iomem *bbar;
1135         void __iomem *target;
1136         unsigned long offset;
1137         u8 start_bus, end_bus;
1138         u32 val;
1139
1140         ret = -ENODATA;
1141         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1142                 struct rio_detail *rio = rio_devs[rioidx];
1143
1144                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1145                         continue;
1146
1147                 /* map entire 1MB of Calgary config space */
1148                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1149                 if (!bbar)
1150                         goto error;
1151
1152                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1153                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1154                         target = calgary_reg(bbar, offset);
1155
1156                         val = be32_to_cpu(readl(target));
1157
1158                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1159                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1160
1161                         if (end_bus) {
1162                                 for (bus = start_bus; bus <= end_bus; bus++) {
1163                                         bus_info[bus].bbar = bbar;
1164                                         bus_info[bus].phbid = phb;
1165                                 }
1166                         } else {
1167                                 bus_info[start_bus].bbar = bbar;
1168                                 bus_info[start_bus].phbid = phb;
1169                         }
1170                 }
1171         }
1172
1173         return 0;
1174
1175 error:
1176         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1177         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1178                 if (bus_info[bus].bbar)
1179                         iounmap(bus_info[bus].bbar);
1180
1181         return ret;
1182 }
1183
1184 static int __init calgary_init(void)
1185 {
1186         int ret;
1187         struct pci_dev *dev = NULL;
1188         struct calgary_bus_info *info;
1189
1190         ret = calgary_locate_bbars();
1191         if (ret)
1192                 return ret;
1193
1194         /* Purely for kdump kernel case */
1195         if (is_kdump_kernel())
1196                 get_tce_space_from_tar();
1197
1198         do {
1199                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1200                 if (!dev)
1201                         break;
1202                 if (!is_cal_pci_dev(dev->device))
1203                         continue;
1204
1205                 info = &bus_info[dev->bus->number];
1206                 if (info->translation_disabled) {
1207                         calgary_init_one_nontraslated(dev);
1208                         continue;
1209                 }
1210
1211                 if (!info->tce_space && !translate_empty_slots)
1212                         continue;
1213
1214                 ret = calgary_init_one(dev);
1215                 if (ret)
1216                         goto error;
1217         } while (1);
1218
1219         dev = NULL;
1220         for_each_pci_dev(dev) {
1221                 struct iommu_table *tbl;
1222
1223                 tbl = find_iommu_table(&dev->dev);
1224
1225                 if (translation_enabled(tbl))
1226                         dev->dev.archdata.dma_ops = &calgary_dma_ops;
1227         }
1228
1229         return ret;
1230
1231 error:
1232         do {
1233                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1234                 if (!dev)
1235                         break;
1236                 if (!is_cal_pci_dev(dev->device))
1237                         continue;
1238
1239                 info = &bus_info[dev->bus->number];
1240                 if (info->translation_disabled) {
1241                         pci_dev_put(dev);
1242                         continue;
1243                 }
1244                 if (!info->tce_space && !translate_empty_slots)
1245                         continue;
1246
1247                 calgary_disable_translation(dev);
1248                 calgary_free_bus(dev);
1249                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1250                 dev->dev.archdata.dma_ops = NULL;
1251         } while (1);
1252
1253         return ret;
1254 }
1255
1256 static inline int __init determine_tce_table_size(u64 ram)
1257 {
1258         int ret;
1259
1260         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1261                 return specified_table_size;
1262
1263         /*
1264          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1265          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1266          * larger table size has twice as many entries, so shift the
1267          * max ram address by 13 to divide by 8K and then look at the
1268          * order of the result to choose between 0-7.
1269          */
1270         ret = get_order(ram >> 13);
1271         if (ret > TCE_TABLE_SIZE_8M)
1272                 ret = TCE_TABLE_SIZE_8M;
1273
1274         return ret;
1275 }
1276
1277 static int __init build_detail_arrays(void)
1278 {
1279         unsigned long ptr;
1280         unsigned numnodes, i;
1281         int scal_detail_size, rio_detail_size;
1282
1283         numnodes = rio_table_hdr->num_scal_dev;
1284         if (numnodes > MAX_NUMNODES){
1285                 printk(KERN_WARNING
1286                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1287                         "but system has %d nodes.\n",
1288                         MAX_NUMNODES, numnodes);
1289                 return -ENODEV;
1290         }
1291
1292         switch (rio_table_hdr->version){
1293         case 2:
1294                 scal_detail_size = 11;
1295                 rio_detail_size = 13;
1296                 break;
1297         case 3:
1298                 scal_detail_size = 12;
1299                 rio_detail_size = 15;
1300                 break;
1301         default:
1302                 printk(KERN_WARNING
1303                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1304                        rio_table_hdr->version);
1305                 return -EPROTO;
1306         }
1307
1308         ptr = ((unsigned long)rio_table_hdr) + 3;
1309         for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1310                 scal_devs[i] = (struct scal_detail *)ptr;
1311
1312         for (i = 0; i < rio_table_hdr->num_rio_dev;
1313                     i++, ptr += rio_detail_size)
1314                 rio_devs[i] = (struct rio_detail *)ptr;
1315
1316         return 0;
1317 }
1318
1319 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1320 {
1321         int dev;
1322         u32 val;
1323
1324         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1325                 /*
1326                  * FIXME: properly scan for devices accross the
1327                  * PCI-to-PCI bridge on every CalIOC2 port.
1328                  */
1329                 return 1;
1330         }
1331
1332         for (dev = 1; dev < 8; dev++) {
1333                 val = read_pci_config(bus, dev, 0, 0);
1334                 if (val != 0xffffffff)
1335                         break;
1336         }
1337         return (val != 0xffffffff);
1338 }
1339
1340 /*
1341  * calgary_init_bitmap_from_tce_table():
1342  * Funtion for kdump case. In the second/kdump kernel initialize
1343  * the bitmap based on the tce table entries obtained from first kernel
1344  */
1345 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1346 {
1347         u64 *tp;
1348         unsigned int index;
1349         tp = ((u64 *)tbl->it_base);
1350         for (index = 0 ; index < tbl->it_size; index++) {
1351                 if (*tp != 0x0)
1352                         set_bit(index, tbl->it_map);
1353                 tp++;
1354         }
1355 }
1356
1357 /*
1358  * get_tce_space_from_tar():
1359  * Function for kdump case. Get the tce tables from first kernel
1360  * by reading the contents of the base adress register of calgary iommu
1361  */
1362 static void __init get_tce_space_from_tar(void)
1363 {
1364         int bus;
1365         void __iomem *target;
1366         unsigned long tce_space;
1367
1368         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1369                 struct calgary_bus_info *info = &bus_info[bus];
1370                 unsigned short pci_device;
1371                 u32 val;
1372
1373                 val = read_pci_config(bus, 0, 0, 0);
1374                 pci_device = (val & 0xFFFF0000) >> 16;
1375
1376                 if (!is_cal_pci_dev(pci_device))
1377                         continue;
1378                 if (info->translation_disabled)
1379                         continue;
1380
1381                 if (calgary_bus_has_devices(bus, pci_device) ||
1382                                                 translate_empty_slots) {
1383                         target = calgary_reg(bus_info[bus].bbar,
1384                                                 tar_offset(bus));
1385                         tce_space = be64_to_cpu(readq(target));
1386                         tce_space = tce_space & TAR_SW_BITS;
1387
1388                         tce_space = tce_space & (~specified_table_size);
1389                         info->tce_space = (u64 *)__va(tce_space);
1390                 }
1391         }
1392         return;
1393 }
1394
1395 void __init detect_calgary(void)
1396 {
1397         int bus;
1398         void *tbl;
1399         int calgary_found = 0;
1400         unsigned long ptr;
1401         unsigned int offset, prev_offset;
1402         int ret;
1403
1404         /*
1405          * if the user specified iommu=off or iommu=soft or we found
1406          * another HW IOMMU already, bail out.
1407          */
1408         if (swiotlb || no_iommu || iommu_detected)
1409                 return;
1410
1411         if (!use_calgary)
1412                 return;
1413
1414         if (!early_pci_allowed())
1415                 return;
1416
1417         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1418
1419         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1420
1421         rio_table_hdr = NULL;
1422         prev_offset = 0;
1423         offset = 0x180;
1424         /*
1425          * The next offset is stored in the 1st word.
1426          * Only parse up until the offset increases:
1427          */
1428         while (offset > prev_offset) {
1429                 /* The block id is stored in the 2nd word */
1430                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1431                         /* set the pointer past the offset & block id */
1432                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1433                         break;
1434                 }
1435                 prev_offset = offset;
1436                 offset = *((unsigned short *)(ptr + offset));
1437         }
1438         if (!rio_table_hdr) {
1439                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1440                        "in EBDA - bailing!\n");
1441                 return;
1442         }
1443
1444         ret = build_detail_arrays();
1445         if (ret) {
1446                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1447                 return;
1448         }
1449
1450         specified_table_size = determine_tce_table_size((is_kdump_kernel() ?
1451                                         saved_max_pfn : max_pfn) * PAGE_SIZE);
1452
1453         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1454                 struct calgary_bus_info *info = &bus_info[bus];
1455                 unsigned short pci_device;
1456                 u32 val;
1457
1458                 val = read_pci_config(bus, 0, 0, 0);
1459                 pci_device = (val & 0xFFFF0000) >> 16;
1460
1461                 if (!is_cal_pci_dev(pci_device))
1462                         continue;
1463
1464                 if (info->translation_disabled)
1465                         continue;
1466
1467                 if (calgary_bus_has_devices(bus, pci_device) ||
1468                     translate_empty_slots) {
1469                         /*
1470                          * If it is kdump kernel, find and use tce tables
1471                          * from first kernel, else allocate tce tables here
1472                          */
1473                         if (!is_kdump_kernel()) {
1474                                 tbl = alloc_tce_table();
1475                                 if (!tbl)
1476                                         goto cleanup;
1477                                 info->tce_space = tbl;
1478                         }
1479                         calgary_found = 1;
1480                 }
1481         }
1482
1483         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1484                calgary_found ? "found" : "not found");
1485
1486         if (calgary_found) {
1487                 iommu_detected = 1;
1488                 calgary_detected = 1;
1489                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1490                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1491                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1492                        debugging ? "enabled" : "disabled");
1493
1494                 /* swiotlb for devices that aren't behind the Calgary. */
1495                 if (max_pfn > MAX_DMA32_PFN)
1496                         swiotlb = 1;
1497         }
1498         return;
1499
1500 cleanup:
1501         for (--bus; bus >= 0; --bus) {
1502                 struct calgary_bus_info *info = &bus_info[bus];
1503
1504                 if (info->tce_space)
1505                         free_tce_table(info->tce_space);
1506         }
1507 }
1508
1509 int __init calgary_iommu_init(void)
1510 {
1511         int ret;
1512
1513         if (no_iommu || (swiotlb && !calgary_detected))
1514                 return -ENODEV;
1515
1516         if (!calgary_detected)
1517                 return -ENODEV;
1518
1519         /* ok, we're trying to use Calgary - let's roll */
1520         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1521
1522         ret = calgary_init();
1523         if (ret) {
1524                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1525                        "falling back to no_iommu\n", ret);
1526                 return ret;
1527         }
1528
1529         force_iommu = 1;
1530         bad_dma_address = 0x0;
1531         /* dma_ops is set to swiotlb or nommu */
1532         if (!dma_ops)
1533                 dma_ops = &nommu_dma_ops;
1534
1535         return 0;
1536 }
1537
1538 static int __init calgary_parse_options(char *p)
1539 {
1540         unsigned int bridge;
1541         size_t len;
1542         char* endp;
1543
1544         while (*p) {
1545                 if (!strncmp(p, "64k", 3))
1546                         specified_table_size = TCE_TABLE_SIZE_64K;
1547                 else if (!strncmp(p, "128k", 4))
1548                         specified_table_size = TCE_TABLE_SIZE_128K;
1549                 else if (!strncmp(p, "256k", 4))
1550                         specified_table_size = TCE_TABLE_SIZE_256K;
1551                 else if (!strncmp(p, "512k", 4))
1552                         specified_table_size = TCE_TABLE_SIZE_512K;
1553                 else if (!strncmp(p, "1M", 2))
1554                         specified_table_size = TCE_TABLE_SIZE_1M;
1555                 else if (!strncmp(p, "2M", 2))
1556                         specified_table_size = TCE_TABLE_SIZE_2M;
1557                 else if (!strncmp(p, "4M", 2))
1558                         specified_table_size = TCE_TABLE_SIZE_4M;
1559                 else if (!strncmp(p, "8M", 2))
1560                         specified_table_size = TCE_TABLE_SIZE_8M;
1561
1562                 len = strlen("translate_empty_slots");
1563                 if (!strncmp(p, "translate_empty_slots", len))
1564                         translate_empty_slots = 1;
1565
1566                 len = strlen("disable");
1567                 if (!strncmp(p, "disable", len)) {
1568                         p += len;
1569                         if (*p == '=')
1570                                 ++p;
1571                         if (*p == '\0')
1572                                 break;
1573                         bridge = simple_strtoul(p, &endp, 0);
1574                         if (p == endp)
1575                                 break;
1576
1577                         if (bridge < MAX_PHB_BUS_NUM) {
1578                                 printk(KERN_INFO "Calgary: disabling "
1579                                        "translation for PHB %#x\n", bridge);
1580                                 bus_info[bridge].translation_disabled = 1;
1581                         }
1582                 }
1583
1584                 p = strpbrk(p, ",");
1585                 if (!p)
1586                         break;
1587
1588                 p++; /* skip ',' */
1589         }
1590         return 1;
1591 }
1592 __setup("calgary=", calgary_parse_options);
1593
1594 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1595 {
1596         struct iommu_table *tbl;
1597         unsigned int npages;
1598         int i;
1599
1600         tbl = pci_iommu(dev->bus);
1601
1602         for (i = 0; i < 4; i++) {
1603                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1604
1605                 /* Don't give out TCEs that map MEM resources */
1606                 if (!(r->flags & IORESOURCE_MEM))
1607                         continue;
1608
1609                 /* 0-based? we reserve the whole 1st MB anyway */
1610                 if (!r->start)
1611                         continue;
1612
1613                 /* cover the whole region */
1614                 npages = (r->end - r->start) >> PAGE_SHIFT;
1615                 npages++;
1616
1617                 iommu_range_reserve(tbl, r->start, npages);
1618         }
1619 }
1620
1621 static int __init calgary_fixup_tce_spaces(void)
1622 {
1623         struct pci_dev *dev = NULL;
1624         struct calgary_bus_info *info;
1625
1626         if (no_iommu || swiotlb || !calgary_detected)
1627                 return -ENODEV;
1628
1629         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1630
1631         do {
1632                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1633                 if (!dev)
1634                         break;
1635                 if (!is_cal_pci_dev(dev->device))
1636                         continue;
1637
1638                 info = &bus_info[dev->bus->number];
1639                 if (info->translation_disabled)
1640                         continue;
1641
1642                 if (!info->tce_space)
1643                         continue;
1644
1645                 calgary_fixup_one_tce_space(dev);
1646
1647         } while (1);
1648
1649         return 0;
1650 }
1651
1652 /*
1653  * We need to be call after pcibios_assign_resources (fs_initcall level)
1654  * and before device_initcall.
1655  */
1656 rootfs_initcall(calgary_fixup_tce_spaces);