Merge branch 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6.git] / arch / x86 / include / asm / msr.h
1 #ifndef _ASM_X86_MSR_H
2 #define _ASM_X86_MSR_H
3
4 #include <asm/msr-index.h>
5
6 #ifdef __KERNEL__
7 #ifndef __ASSEMBLY__
8
9 #include <linux/types.h>
10 #include <asm/asm.h>
11 #include <asm/errno.h>
12 #include <asm/cpumask.h>
13
14 struct msr {
15         union {
16                 struct {
17                         u32 l;
18                         u32 h;
19                 };
20                 u64 q;
21         };
22 };
23
24 static inline unsigned long long native_read_tscp(unsigned int *aux)
25 {
26         unsigned long low, high;
27         asm volatile(".byte 0x0f,0x01,0xf9"
28                      : "=a" (low), "=d" (high), "=c" (*aux));
29         return low | ((u64)high << 32);
30 }
31
32 /*
33  * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
34  * constraint has different meanings. For i386, "A" means exactly
35  * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
36  * it means rax *or* rdx.
37  */
38 #ifdef CONFIG_X86_64
39 #define DECLARE_ARGS(val, low, high)    unsigned low, high
40 #define EAX_EDX_VAL(val, low, high)     ((low) | ((u64)(high) << 32))
41 #define EAX_EDX_ARGS(val, low, high)    "a" (low), "d" (high)
42 #define EAX_EDX_RET(val, low, high)     "=a" (low), "=d" (high)
43 #else
44 #define DECLARE_ARGS(val, low, high)    unsigned long long val
45 #define EAX_EDX_VAL(val, low, high)     (val)
46 #define EAX_EDX_ARGS(val, low, high)    "A" (val)
47 #define EAX_EDX_RET(val, low, high)     "=A" (val)
48 #endif
49
50 static inline unsigned long long native_read_msr(unsigned int msr)
51 {
52         DECLARE_ARGS(val, low, high);
53
54         asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr));
55         return EAX_EDX_VAL(val, low, high);
56 }
57
58 static inline unsigned long long native_read_msr_safe(unsigned int msr,
59                                                       int *err)
60 {
61         DECLARE_ARGS(val, low, high);
62
63         asm volatile("2: rdmsr ; xor %[err],%[err]\n"
64                      "1:\n\t"
65                      ".section .fixup,\"ax\"\n\t"
66                      "3:  mov %[fault],%[err] ; jmp 1b\n\t"
67                      ".previous\n\t"
68                      _ASM_EXTABLE(2b, 3b)
69                      : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
70                      : "c" (msr), [fault] "i" (-EFAULT));
71         return EAX_EDX_VAL(val, low, high);
72 }
73
74 static inline unsigned long long native_read_msr_amd_safe(unsigned int msr,
75                                                       int *err)
76 {
77         DECLARE_ARGS(val, low, high);
78
79         asm volatile("2: rdmsr ; xor %0,%0\n"
80                      "1:\n\t"
81                      ".section .fixup,\"ax\"\n\t"
82                      "3:  mov %3,%0 ; jmp 1b\n\t"
83                      ".previous\n\t"
84                      _ASM_EXTABLE(2b, 3b)
85                      : "=r" (*err), EAX_EDX_RET(val, low, high)
86                      : "c" (msr), "D" (0x9c5a203a), "i" (-EFAULT));
87         return EAX_EDX_VAL(val, low, high);
88 }
89
90 static inline void native_write_msr(unsigned int msr,
91                                     unsigned low, unsigned high)
92 {
93         asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory");
94 }
95
96 /* Can be uninlined because referenced by paravirt */
97 notrace static inline int native_write_msr_safe(unsigned int msr,
98                                         unsigned low, unsigned high)
99 {
100         int err;
101         asm volatile("2: wrmsr ; xor %[err],%[err]\n"
102                      "1:\n\t"
103                      ".section .fixup,\"ax\"\n\t"
104                      "3:  mov %[fault],%[err] ; jmp 1b\n\t"
105                      ".previous\n\t"
106                      _ASM_EXTABLE(2b, 3b)
107                      : [err] "=a" (err)
108                      : "c" (msr), "0" (low), "d" (high),
109                        [fault] "i" (-EFAULT)
110                      : "memory");
111         return err;
112 }
113
114 extern unsigned long long native_read_tsc(void);
115
116 static __always_inline unsigned long long __native_read_tsc(void)
117 {
118         DECLARE_ARGS(val, low, high);
119
120         asm volatile("rdtsc" : EAX_EDX_RET(val, low, high));
121
122         return EAX_EDX_VAL(val, low, high);
123 }
124
125 static inline unsigned long long native_read_pmc(int counter)
126 {
127         DECLARE_ARGS(val, low, high);
128
129         asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
130         return EAX_EDX_VAL(val, low, high);
131 }
132
133 #ifdef CONFIG_PARAVIRT
134 #include <asm/paravirt.h>
135 #else
136 #include <linux/errno.h>
137 /*
138  * Access to machine-specific registers (available on 586 and better only)
139  * Note: the rd* operations modify the parameters directly (without using
140  * pointer indirection), this allows gcc to optimize better
141  */
142
143 #define rdmsr(msr, val1, val2)                                  \
144 do {                                                            \
145         u64 __val = native_read_msr((msr));                     \
146         (val1) = (u32)__val;                                    \
147         (val2) = (u32)(__val >> 32);                            \
148 } while (0)
149
150 static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
151 {
152         native_write_msr(msr, low, high);
153 }
154
155 #define rdmsrl(msr, val)                        \
156         ((val) = native_read_msr((msr)))
157
158 #define wrmsrl(msr, val)                                                \
159         native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32))
160
161 /* wrmsr with exception handling */
162 static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high)
163 {
164         return native_write_msr_safe(msr, low, high);
165 }
166
167 /* rdmsr with exception handling */
168 #define rdmsr_safe(msr, p1, p2)                                 \
169 ({                                                              \
170         int __err;                                              \
171         u64 __val = native_read_msr_safe((msr), &__err);        \
172         (*p1) = (u32)__val;                                     \
173         (*p2) = (u32)(__val >> 32);                             \
174         __err;                                                  \
175 })
176
177 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
178 {
179         int err;
180
181         *p = native_read_msr_safe(msr, &err);
182         return err;
183 }
184 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
185 {
186         int err;
187
188         *p = native_read_msr_amd_safe(msr, &err);
189         return err;
190 }
191
192 #define rdtscl(low)                                             \
193         ((low) = (u32)__native_read_tsc())
194
195 #define rdtscll(val)                                            \
196         ((val) = __native_read_tsc())
197
198 #define rdpmc(counter, low, high)                       \
199 do {                                                    \
200         u64 _l = native_read_pmc((counter));            \
201         (low)  = (u32)_l;                               \
202         (high) = (u32)(_l >> 32);                       \
203 } while (0)
204
205 #define rdtscp(low, high, aux)                                  \
206 do {                                                            \
207         unsigned long long _val = native_read_tscp(&(aux));     \
208         (low) = (u32)_val;                                      \
209         (high) = (u32)(_val >> 32);                             \
210 } while (0)
211
212 #define rdtscpll(val, aux) (val) = native_read_tscp(&(aux))
213
214 #endif  /* !CONFIG_PARAVIRT */
215
216
217 #define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val),         \
218                                              (u32)((val) >> 32))
219
220 #define write_tsc(val1, val2) wrmsr(0x10, (val1), (val2))
221
222 #define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0)
223
224 #ifdef CONFIG_SMP
225 int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
226 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
227 void rdmsr_on_cpus(const cpumask_t *mask, u32 msr_no, struct msr *msrs);
228 void wrmsr_on_cpus(const cpumask_t *mask, u32 msr_no, struct msr *msrs);
229 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
230 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
231 #else  /*  CONFIG_SMP  */
232 static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
233 {
234         rdmsr(msr_no, *l, *h);
235         return 0;
236 }
237 static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
238 {
239         wrmsr(msr_no, l, h);
240         return 0;
241 }
242 static inline void rdmsr_on_cpus(const cpumask_t *m, u32 msr_no,
243                                 struct msr *msrs)
244 {
245        rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h));
246 }
247 static inline void wrmsr_on_cpus(const cpumask_t *m, u32 msr_no,
248                                 struct msr *msrs)
249 {
250        wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h);
251 }
252 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
253                                     u32 *l, u32 *h)
254 {
255         return rdmsr_safe(msr_no, l, h);
256 }
257 static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
258 {
259         return wrmsr_safe(msr_no, l, h);
260 }
261 #endif  /* CONFIG_SMP */
262 #endif /* __ASSEMBLY__ */
263 #endif /* __KERNEL__ */
264 #endif /* _ASM_X86_MSR_H */