1 #ifndef _ASM_X86_APICDEF_H
2 #define _ASM_X86_APICDEF_H
5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
7 * Alan Cox <Alan.Cox@linux.org>, 1995.
8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
11 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
12 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
17 #define APIC_LVR_MASK 0xFF00FF
18 #define GET_APIC_VERSION(x) ((x) & 0xFFu)
19 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
21 # define APIC_INTEGRATED(x) ((x) & 0xF0u)
23 # define APIC_INTEGRATED(x) (1)
25 #define APIC_XAPIC(x) ((x) >= 0x14)
26 #define APIC_EXT_SPACE(x) ((x) & 0x80000000)
27 #define APIC_TASKPRI 0x80
28 #define APIC_TPRI_MASK 0xFFu
29 #define APIC_ARBPRI 0x90
30 #define APIC_ARBPRI_MASK 0xFFu
31 #define APIC_PROCPRI 0xA0
33 #define APIC_EIO_ACK 0x0
36 #define APIC_LDR_MASK (0xFFu << 24)
37 #define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu)
38 #define SET_APIC_LOGICAL_ID(x) (((x) << 24))
39 #define APIC_ALL_CPUS 0xFFu
41 #define APIC_DFR_CLUSTER 0x0FFFFFFFul
42 #define APIC_DFR_FLAT 0xFFFFFFFFul
43 #define APIC_SPIV 0xF0
44 #define APIC_SPIV_FOCUS_DISABLED (1 << 9)
45 #define APIC_SPIV_APIC_ENABLED (1 << 8)
46 #define APIC_ISR 0x100
47 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
48 #define APIC_TMR 0x180
49 #define APIC_IRR 0x200
50 #define APIC_ESR 0x280
51 #define APIC_ESR_SEND_CS 0x00001
52 #define APIC_ESR_RECV_CS 0x00002
53 #define APIC_ESR_SEND_ACC 0x00004
54 #define APIC_ESR_RECV_ACC 0x00008
55 #define APIC_ESR_SENDILL 0x00020
56 #define APIC_ESR_RECVILL 0x00040
57 #define APIC_ESR_ILLREGA 0x00080
58 #define APIC_LVTCMCI 0x2f0
59 #define APIC_ICR 0x300
60 #define APIC_DEST_SELF 0x40000
61 #define APIC_DEST_ALLINC 0x80000
62 #define APIC_DEST_ALLBUT 0xC0000
63 #define APIC_ICR_RR_MASK 0x30000
64 #define APIC_ICR_RR_INVALID 0x00000
65 #define APIC_ICR_RR_INPROG 0x10000
66 #define APIC_ICR_RR_VALID 0x20000
67 #define APIC_INT_LEVELTRIG 0x08000
68 #define APIC_INT_ASSERT 0x04000
69 #define APIC_ICR_BUSY 0x01000
70 #define APIC_DEST_LOGICAL 0x00800
71 #define APIC_DEST_PHYSICAL 0x00000
72 #define APIC_DM_FIXED 0x00000
73 #define APIC_DM_LOWEST 0x00100
74 #define APIC_DM_SMI 0x00200
75 #define APIC_DM_REMRD 0x00300
76 #define APIC_DM_NMI 0x00400
77 #define APIC_DM_INIT 0x00500
78 #define APIC_DM_STARTUP 0x00600
79 #define APIC_DM_EXTINT 0x00700
80 #define APIC_VECTOR_MASK 0x000FF
81 #define APIC_ICR2 0x310
82 #define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
83 #define SET_APIC_DEST_FIELD(x) ((x) << 24)
84 #define APIC_LVTT 0x320
85 #define APIC_LVTTHMR 0x330
86 #define APIC_LVTPC 0x340
87 #define APIC_LVT0 0x350
88 #define APIC_LVT_TIMER_BASE_MASK (0x3 << 18)
89 #define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3)
90 #define SET_APIC_TIMER_BASE(x) (((x) << 18))
91 #define APIC_TIMER_BASE_CLKIN 0x0
92 #define APIC_TIMER_BASE_TMBASE 0x1
93 #define APIC_TIMER_BASE_DIV 0x2
94 #define APIC_LVT_TIMER_PERIODIC (1 << 17)
95 #define APIC_LVT_MASKED (1 << 16)
96 #define APIC_LVT_LEVEL_TRIGGER (1 << 15)
97 #define APIC_LVT_REMOTE_IRR (1 << 14)
98 #define APIC_INPUT_POLARITY (1 << 13)
99 #define APIC_SEND_PENDING (1 << 12)
100 #define APIC_MODE_MASK 0x700
101 #define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7)
102 #define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8))
103 #define APIC_MODE_FIXED 0x0
104 #define APIC_MODE_NMI 0x4
105 #define APIC_MODE_EXTINT 0x7
106 #define APIC_LVT1 0x360
107 #define APIC_LVTERR 0x370
108 #define APIC_TMICT 0x380
109 #define APIC_TMCCT 0x390
110 #define APIC_TDCR 0x3E0
111 #define APIC_SELF_IPI 0x3F0
112 #define APIC_TDR_DIV_TMBASE (1 << 2)
113 #define APIC_TDR_DIV_1 0xB
114 #define APIC_TDR_DIV_2 0x0
115 #define APIC_TDR_DIV_4 0x1
116 #define APIC_TDR_DIV_8 0x2
117 #define APIC_TDR_DIV_16 0x3
118 #define APIC_TDR_DIV_32 0x8
119 #define APIC_TDR_DIV_64 0x9
120 #define APIC_TDR_DIV_128 0xA
121 #define APIC_EFEAT 0x400
122 #define APIC_ECTRL 0x410
123 #define APIC_EILVTn(n) (0x500 + 0x10 * n)
124 #define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */
125 #define APIC_EILVT_NR_AMD_10H 4
126 #define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF)
127 #define APIC_EILVT_MSG_FIX 0x0
128 #define APIC_EILVT_MSG_SMI 0x2
129 #define APIC_EILVT_MSG_NMI 0x4
130 #define APIC_EILVT_MSG_EXT 0x7
131 #define APIC_EILVT_MASKED (1 << 16)
133 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
134 #define APIC_BASE_MSR 0x800
135 #define X2APIC_ENABLE (1UL << 10)
138 # define MAX_IO_APICS 64
140 # define MAX_IO_APICS 128
141 # define MAX_LOCAL_APIC 32768
145 * All x86-64 systems are xAPIC compatible.
146 * In the following, "apicid" is a physical APIC ID.
148 #define XAPIC_DEST_CPUS_SHIFT 4
149 #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
150 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
151 #define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
152 #define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
153 #define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK)
154 #define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
157 * the local APIC register structure, memory mapped. Not terribly well
158 * tested, but we might eventually use this one in the future - the
159 * problem why we cannot use it right now is the P5 APIC, it has an
160 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
162 #define u32 unsigned int
166 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
168 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
170 /*020*/ struct { /* APIC ID Register */
171 u32 __reserved_1 : 24,
178 struct { /* APIC Version Register */
186 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
188 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
190 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
192 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
194 /*080*/ struct { /* Task Priority Register */
201 struct { /* Arbitration Priority Register */
208 struct { /* Processor Priority Register */
214 /*0B0*/ struct { /* End Of Interrupt Register */
219 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
221 /*0D0*/ struct { /* Logical Destination Register */
222 u32 __reserved_1 : 24,
227 /*0E0*/ struct { /* Destination Format Register */
228 u32 __reserved_1 : 28,
233 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
234 u32 spurious_vector : 8,
241 /*100*/ struct { /* In Service Register */
242 /*170*/ u32 bitfield;
246 /*180*/ struct { /* Trigger Mode Register */
247 /*1F0*/ u32 bitfield;
251 /*200*/ struct { /* Interrupt Request Register */
252 /*270*/ u32 bitfield;
256 /*280*/ union { /* Error Status Register */
258 u32 send_cs_error : 1,
259 receive_cs_error : 1,
260 send_accept_error : 1,
261 receive_accept_error : 1,
263 send_illegal_vector : 1,
264 receive_illegal_vector : 1,
265 illegal_register_address : 1,
275 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
277 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
279 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
281 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
283 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
285 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
287 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
289 /*300*/ struct { /* Interrupt Command Register 1 */
292 destination_mode : 1,
303 /*310*/ struct { /* Interrupt Command Register 2 */
305 u32 __reserved_1 : 24,
308 u32 __reserved_3 : 24,
314 /*320*/ struct { /* LVT - Timer */
325 /*330*/ struct { /* LVT - Thermal Sensor */
336 /*340*/ struct { /* LVT - Performance Counter */
347 /*350*/ struct { /* LVT - LINT0 */
360 /*360*/ struct { /* LVT - LINT1 */
373 /*370*/ struct { /* LVT - Error */
383 /*380*/ struct { /* Timer Initial Count Register */
389 struct { /* Timer Current Count Register */
394 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
396 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
398 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
400 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
402 /*3E0*/ struct { /* Timer Divide Configuration Register */
408 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
410 } __attribute__ ((packed));
415 #define BAD_APICID 0xFFu
417 #define BAD_APICID 0xFFFFu
419 #endif /* _ASM_X86_APICDEF_H */