[SPARC64]: Hypervisor TSB context switching.
[linux-2.6.git] / arch / sparc64 / mm / tsb.c
1 /* arch/sparc64/mm/tsb.c
2  *
3  * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
4  */
5
6 #include <linux/kernel.h>
7 #include <asm/system.h>
8 #include <asm/page.h>
9 #include <asm/tlbflush.h>
10 #include <asm/tlb.h>
11 #include <asm/mmu_context.h>
12 #include <asm/pgtable.h>
13 #include <asm/tsb.h>
14
15 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
16
17 static inline unsigned long tsb_hash(unsigned long vaddr, unsigned long nentries)
18 {
19         vaddr >>= PAGE_SHIFT;
20         return vaddr & (nentries - 1);
21 }
22
23 static inline int tag_compare(unsigned long tag, unsigned long vaddr, unsigned long context)
24 {
25         return (tag == ((vaddr >> 22) | (context << 48)));
26 }
27
28 /* TSB flushes need only occur on the processor initiating the address
29  * space modification, not on each cpu the address space has run on.
30  * Only the TLB flush needs that treatment.
31  */
32
33 void flush_tsb_kernel_range(unsigned long start, unsigned long end)
34 {
35         unsigned long v;
36
37         for (v = start; v < end; v += PAGE_SIZE) {
38                 unsigned long hash = tsb_hash(v, KERNEL_TSB_NENTRIES);
39                 struct tsb *ent = &swapper_tsb[hash];
40
41                 if (tag_compare(ent->tag, v, 0)) {
42                         ent->tag = 0UL;
43                         membar_storeload_storestore();
44                 }
45         }
46 }
47
48 void flush_tsb_user(struct mmu_gather *mp)
49 {
50         struct mm_struct *mm = mp->mm;
51         struct tsb *tsb = mm->context.tsb;
52         unsigned long nentries = mm->context.tsb_nentries;
53         unsigned long ctx, base;
54         int i;
55
56         if (unlikely(!CTX_VALID(mm->context)))
57                 return;
58
59         ctx = CTX_HWBITS(mm->context);
60
61         if (tlb_type == cheetah_plus)
62                 base = __pa(tsb);
63         else
64                 base = (unsigned long) tsb;
65         
66         for (i = 0; i < mp->tlb_nr; i++) {
67                 unsigned long v = mp->vaddrs[i];
68                 unsigned long tag, ent, hash;
69
70                 v &= ~0x1UL;
71
72                 hash = tsb_hash(v, nentries);
73                 ent = base + (hash * sizeof(struct tsb));
74                 tag = (v >> 22UL) | (ctx << 48UL);
75
76                 tsb_flush(ent, tag);
77         }
78 }
79
80 static void setup_tsb_params(struct mm_struct *mm, unsigned long tsb_bytes)
81 {
82         unsigned long tsb_reg, base, tsb_paddr;
83         unsigned long page_sz, tte;
84
85         mm->context.tsb_nentries = tsb_bytes / sizeof(struct tsb);
86
87         base = TSBMAP_BASE;
88         tte = (_PAGE_VALID | _PAGE_L | _PAGE_CP |
89                _PAGE_CV    | _PAGE_P | _PAGE_W);
90         tsb_paddr = __pa(mm->context.tsb);
91         BUG_ON(tsb_paddr & (tsb_bytes - 1UL));
92
93         /* Use the smallest page size that can map the whole TSB
94          * in one TLB entry.
95          */
96         switch (tsb_bytes) {
97         case 8192 << 0:
98                 tsb_reg = 0x0UL;
99 #ifdef DCACHE_ALIASING_POSSIBLE
100                 base += (tsb_paddr & 8192);
101 #endif
102                 tte |= _PAGE_SZ8K;
103                 page_sz = 8192;
104                 break;
105
106         case 8192 << 1:
107                 tsb_reg = 0x1UL;
108                 tte |= _PAGE_SZ64K;
109                 page_sz = 64 * 1024;
110                 break;
111
112         case 8192 << 2:
113                 tsb_reg = 0x2UL;
114                 tte |= _PAGE_SZ64K;
115                 page_sz = 64 * 1024;
116                 break;
117
118         case 8192 << 3:
119                 tsb_reg = 0x3UL;
120                 tte |= _PAGE_SZ64K;
121                 page_sz = 64 * 1024;
122                 break;
123
124         case 8192 << 4:
125                 tsb_reg = 0x4UL;
126                 tte |= _PAGE_SZ512K;
127                 page_sz = 512 * 1024;
128                 break;
129
130         case 8192 << 5:
131                 tsb_reg = 0x5UL;
132                 tte |= _PAGE_SZ512K;
133                 page_sz = 512 * 1024;
134                 break;
135
136         case 8192 << 6:
137                 tsb_reg = 0x6UL;
138                 tte |= _PAGE_SZ512K;
139                 page_sz = 512 * 1024;
140                 break;
141
142         case 8192 << 7:
143                 tsb_reg = 0x7UL;
144                 tte |= _PAGE_SZ4MB;
145                 page_sz = 4 * 1024 * 1024;
146                 break;
147
148         default:
149                 BUG();
150         };
151
152         if (tlb_type == cheetah_plus || tlb_type == hypervisor) {
153                 /* Physical mapping, no locked TLB entry for TSB.  */
154                 tsb_reg |= tsb_paddr;
155
156                 mm->context.tsb_reg_val = tsb_reg;
157                 mm->context.tsb_map_vaddr = 0;
158                 mm->context.tsb_map_pte = 0;
159         } else {
160                 tsb_reg |= base;
161                 tsb_reg |= (tsb_paddr & (page_sz - 1UL));
162                 tte |= (tsb_paddr & ~(page_sz - 1UL));
163
164                 mm->context.tsb_reg_val = tsb_reg;
165                 mm->context.tsb_map_vaddr = base;
166                 mm->context.tsb_map_pte = tte;
167         }
168
169         /* Setup the Hypervisor TSB descriptor.  */
170         if (tlb_type == hypervisor) {
171                 struct hv_tsb_descr *hp = &mm->context.tsb_descr;
172
173                 switch (PAGE_SIZE) {
174                 case 8192:
175                 default:
176                         hp->pgsz_idx = HV_PGSZ_IDX_8K;
177                         break;
178
179                 case 64 * 1024:
180                         hp->pgsz_idx = HV_PGSZ_IDX_64K;
181                         break;
182
183                 case 512 * 1024:
184                         hp->pgsz_idx = HV_PGSZ_IDX_512K;
185                         break;
186
187                 case 4 * 1024 * 1024:
188                         hp->pgsz_idx = HV_PGSZ_IDX_4MB;
189                         break;
190                 };
191                 hp->assoc = 1;
192                 hp->num_ttes = tsb_bytes / 16;
193                 hp->ctx_idx = 0;
194                 switch (PAGE_SIZE) {
195                 case 8192:
196                 default:
197                         hp->pgsz_mask = HV_PGSZ_MASK_8K;
198                         break;
199
200                 case 64 * 1024:
201                         hp->pgsz_mask = HV_PGSZ_MASK_64K;
202                         break;
203
204                 case 512 * 1024:
205                         hp->pgsz_mask = HV_PGSZ_MASK_512K;
206                         break;
207
208                 case 4 * 1024 * 1024:
209                         hp->pgsz_mask = HV_PGSZ_MASK_4MB;
210                         break;
211                 };
212                 hp->tsb_base = tsb_paddr;
213                 hp->resv = 0;
214         }
215 }
216
217 /* The page tables are locked against modifications while this
218  * runs.
219  *
220  * XXX do some prefetching...
221  */
222 static void copy_tsb(struct tsb *old_tsb, unsigned long old_size,
223                      struct tsb *new_tsb, unsigned long new_size)
224 {
225         unsigned long old_nentries = old_size / sizeof(struct tsb);
226         unsigned long new_nentries = new_size / sizeof(struct tsb);
227         unsigned long i;
228
229         for (i = 0; i < old_nentries; i++) {
230                 register unsigned long tag asm("o4");
231                 register unsigned long pte asm("o5");
232                 unsigned long v, hash;
233
234                 if (tlb_type == cheetah_plus) {
235                         __asm__ __volatile__(
236                                 "ldda [%2] %3, %0"
237                                 : "=r" (tag), "=r" (pte)
238                                 : "r" (__pa(&old_tsb[i])),
239                                   "i" (ASI_QUAD_LDD_PHYS));
240                 } else {
241                         __asm__ __volatile__(
242                                 "ldda [%2] %3, %0"
243                                 : "=r" (tag), "=r" (pte)
244                                 : "r" (&old_tsb[i]),
245                                   "i" (ASI_NUCLEUS_QUAD_LDD));
246                 }
247
248                 if (!tag || (tag & (1UL << TSB_TAG_LOCK_BIT)))
249                         continue;
250
251                 /* We only put base page size PTEs into the TSB,
252                  * but that might change in the future.  This code
253                  * would need to be changed if we start putting larger
254                  * page size PTEs into there.
255                  */
256                 WARN_ON((pte & _PAGE_ALL_SZ_BITS) != _PAGE_SZBITS);
257
258                 /* The tag holds bits 22 to 63 of the virtual address
259                  * and the context.  Clear out the context, and shift
260                  * up to make a virtual address.
261                  */
262                 v = (tag & ((1UL << 42UL) - 1UL)) << 22UL;
263
264                 /* The implied bits of the tag (bits 13 to 21) are
265                  * determined by the TSB entry index, so fill that in.
266                  */
267                 v |= (i & (512UL - 1UL)) << 13UL;
268
269                 hash = tsb_hash(v, new_nentries);
270                 if (tlb_type == cheetah_plus) {
271                         __asm__ __volatile__(
272                                 "stxa   %0, [%1] %2\n\t"
273                                 "stxa   %3, [%4] %2"
274                                 : /* no outputs */
275                                 : "r" (tag),
276                                   "r" (__pa(&new_tsb[hash].tag)),
277                                   "i" (ASI_PHYS_USE_EC),
278                                   "r" (pte),
279                                   "r" (__pa(&new_tsb[hash].pte)));
280                 } else {
281                         new_tsb[hash].tag = tag;
282                         new_tsb[hash].pte = pte;
283                 }
284         }
285 }
286
287 /* When the RSS of an address space exceeds mm->context.tsb_rss_limit,
288  * update_mmu_cache() invokes this routine to try and grow the TSB.
289  * When we reach the maximum TSB size supported, we stick ~0UL into
290  * mm->context.tsb_rss_limit so the grow checks in update_mmu_cache()
291  * will not trigger any longer.
292  *
293  * The TSB can be anywhere from 8K to 1MB in size, in increasing powers
294  * of two.  The TSB must be aligned to it's size, so f.e. a 512K TSB
295  * must be 512K aligned.
296  *
297  * The idea here is to grow the TSB when the RSS of the process approaches
298  * the number of entries that the current TSB can hold at once.  Currently,
299  * we trigger when the RSS hits 3/4 of the TSB capacity.
300  */
301 void tsb_grow(struct mm_struct *mm, unsigned long rss, gfp_t gfp_flags)
302 {
303         unsigned long max_tsb_size = 1 * 1024 * 1024;
304         unsigned long size, old_size;
305         struct page *page;
306         struct tsb *old_tsb;
307
308         if (max_tsb_size > (PAGE_SIZE << MAX_ORDER))
309                 max_tsb_size = (PAGE_SIZE << MAX_ORDER);
310
311         for (size = PAGE_SIZE; size < max_tsb_size; size <<= 1UL) {
312                 unsigned long n_entries = size / sizeof(struct tsb);
313
314                 n_entries = (n_entries * 3) / 4;
315                 if (n_entries > rss)
316                         break;
317         }
318
319         page = alloc_pages(gfp_flags | __GFP_ZERO, get_order(size));
320         if (unlikely(!page))
321                 return;
322
323         if (size == max_tsb_size)
324                 mm->context.tsb_rss_limit = ~0UL;
325         else
326                 mm->context.tsb_rss_limit =
327                         ((size / sizeof(struct tsb)) * 3) / 4;
328
329         old_tsb = mm->context.tsb;
330         old_size = mm->context.tsb_nentries * sizeof(struct tsb);
331
332         if (old_tsb)
333                 copy_tsb(old_tsb, old_size, page_address(page), size);
334
335         mm->context.tsb = page_address(page);
336         setup_tsb_params(mm, size);
337
338         /* If old_tsb is NULL, we're being invoked for the first time
339          * from init_new_context().
340          */
341         if (old_tsb) {
342                 /* Now force all other processors to reload the new
343                  * TSB state.
344                  */
345                 smp_tsb_sync(mm);
346
347                 /* Finally reload it on the local cpu.  No further
348                  * references will remain to the old TSB and we can
349                  * thus free it up.
350                  */
351                 tsb_context_switch(mm);
352
353                 free_pages((unsigned long) old_tsb, get_order(old_size));
354         }
355 }
356
357 int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
358 {
359
360         mm->context.sparc64_ctx_val = 0UL;
361
362         /* copy_mm() copies over the parent's mm_struct before calling
363          * us, so we need to zero out the TSB pointer or else tsb_grow()
364          * will be confused and think there is an older TSB to free up.
365          */
366         mm->context.tsb = NULL;
367         tsb_grow(mm, 0, GFP_KERNEL);
368
369         if (unlikely(!mm->context.tsb))
370                 return -ENOMEM;
371
372         return 0;
373 }
374
375 void destroy_context(struct mm_struct *mm)
376 {
377         unsigned long size = mm->context.tsb_nentries * sizeof(struct tsb);
378
379         free_pages((unsigned long) mm->context.tsb, get_order(size));
380
381         /* We can remove these later, but for now it's useful
382          * to catch any bogus post-destroy_context() references
383          * to the TSB.
384          */
385         mm->context.tsb = NULL;
386         mm->context.tsb_reg_val = 0UL;
387
388         spin_lock(&ctx_alloc_lock);
389
390         if (CTX_VALID(mm->context)) {
391                 unsigned long nr = CTX_NRBITS(mm->context);
392                 mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63));
393         }
394
395         spin_unlock(&ctx_alloc_lock);
396 }