2c21d85de78f017af972a952349cd04b0e535ea2
[linux-2.6.git] / arch / sparc64 / mm / init.c
1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2  *  arch/sparc64/mm/init.c
3  *
4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6  */
7  
8 #include <linux/config.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/fs.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24 #include <linux/sort.h>
25
26 #include <asm/head.h>
27 #include <asm/system.h>
28 #include <asm/page.h>
29 #include <asm/pgalloc.h>
30 #include <asm/pgtable.h>
31 #include <asm/oplib.h>
32 #include <asm/iommu.h>
33 #include <asm/io.h>
34 #include <asm/uaccess.h>
35 #include <asm/mmu_context.h>
36 #include <asm/tlbflush.h>
37 #include <asm/dma.h>
38 #include <asm/starfire.h>
39 #include <asm/tlb.h>
40 #include <asm/spitfire.h>
41 #include <asm/sections.h>
42
43 extern void device_scan(void);
44
45 #define MAX_BANKS       32
46
47 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
48 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
49 static int pavail_ents __initdata;
50 static int pavail_rescan_ents __initdata;
51
52 static int cmp_p64(const void *a, const void *b)
53 {
54         const struct linux_prom64_registers *x = a, *y = b;
55
56         if (x->phys_addr > y->phys_addr)
57                 return 1;
58         if (x->phys_addr < y->phys_addr)
59                 return -1;
60         return 0;
61 }
62
63 static void __init read_obp_memory(const char *property,
64                                    struct linux_prom64_registers *regs,
65                                    int *num_ents)
66 {
67         int node = prom_finddevice("/memory");
68         int prop_size = prom_getproplen(node, property);
69         int ents, ret, i;
70
71         ents = prop_size / sizeof(struct linux_prom64_registers);
72         if (ents > MAX_BANKS) {
73                 prom_printf("The machine has more %s property entries than "
74                             "this kernel can support (%d).\n",
75                             property, MAX_BANKS);
76                 prom_halt();
77         }
78
79         ret = prom_getproperty(node, property, (char *) regs, prop_size);
80         if (ret == -1) {
81                 prom_printf("Couldn't get %s property from /memory.\n");
82                 prom_halt();
83         }
84
85         *num_ents = ents;
86
87         /* Sanitize what we got from the firmware, by page aligning
88          * everything.
89          */
90         for (i = 0; i < ents; i++) {
91                 unsigned long base, size;
92
93                 base = regs[i].phys_addr;
94                 size = regs[i].reg_size;
95
96                 size &= PAGE_MASK;
97                 if (base & ~PAGE_MASK) {
98                         unsigned long new_base = PAGE_ALIGN(base);
99
100                         size -= new_base - base;
101                         if ((long) size < 0L)
102                                 size = 0UL;
103                         base = new_base;
104                 }
105                 regs[i].phys_addr = base;
106                 regs[i].reg_size = size;
107         }
108         sort(regs, ents, sizeof(struct linux_prom64_registers),
109              cmp_p64, NULL);
110 }
111
112 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
113
114 /* Ugly, but necessary... -DaveM */
115 unsigned long phys_base __read_mostly;
116 unsigned long kern_base __read_mostly;
117 unsigned long kern_size __read_mostly;
118 unsigned long pfn_base __read_mostly;
119
120 /* get_new_mmu_context() uses "cache + 1".  */
121 DEFINE_SPINLOCK(ctx_alloc_lock);
122 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
123 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
124 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
125
126 /* References to special section boundaries */
127 extern char  _start[], _end[];
128
129 /* Initial ramdisk setup */
130 extern unsigned long sparc_ramdisk_image64;
131 extern unsigned int sparc_ramdisk_image;
132 extern unsigned int sparc_ramdisk_size;
133
134 struct page *mem_map_zero __read_mostly;
135
136 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
137
138 unsigned long sparc64_kern_pri_context __read_mostly;
139 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
140 unsigned long sparc64_kern_sec_context __read_mostly;
141
142 int bigkernel = 0;
143
144 kmem_cache_t *pgtable_cache __read_mostly;
145
146 static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
147 {
148         clear_page(addr);
149 }
150
151 void pgtable_cache_init(void)
152 {
153         pgtable_cache = kmem_cache_create("pgtable_cache",
154                                           PAGE_SIZE, PAGE_SIZE,
155                                           SLAB_HWCACHE_ALIGN |
156                                           SLAB_MUST_HWCACHE_ALIGN,
157                                           zero_ctor,
158                                           NULL);
159         if (!pgtable_cache) {
160                 prom_printf("pgtable_cache_init(): Could not create!\n");
161                 prom_halt();
162         }
163 }
164
165 #ifdef CONFIG_DEBUG_DCFLUSH
166 atomic_t dcpage_flushes = ATOMIC_INIT(0);
167 #ifdef CONFIG_SMP
168 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
169 #endif
170 #endif
171
172 __inline__ void flush_dcache_page_impl(struct page *page)
173 {
174 #ifdef CONFIG_DEBUG_DCFLUSH
175         atomic_inc(&dcpage_flushes);
176 #endif
177
178 #ifdef DCACHE_ALIASING_POSSIBLE
179         __flush_dcache_page(page_address(page),
180                             ((tlb_type == spitfire) &&
181                              page_mapping(page) != NULL));
182 #else
183         if (page_mapping(page) != NULL &&
184             tlb_type == spitfire)
185                 __flush_icache_page(__pa(page_address(page)));
186 #endif
187 }
188
189 #define PG_dcache_dirty         PG_arch_1
190 #define PG_dcache_cpu_shift     24
191 #define PG_dcache_cpu_mask      (256 - 1)
192
193 #if NR_CPUS > 256
194 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
195 #endif
196
197 #define dcache_dirty_cpu(page) \
198         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
199
200 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
201 {
202         unsigned long mask = this_cpu;
203         unsigned long non_cpu_bits;
204
205         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
206         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
207
208         __asm__ __volatile__("1:\n\t"
209                              "ldx       [%2], %%g7\n\t"
210                              "and       %%g7, %1, %%g1\n\t"
211                              "or        %%g1, %0, %%g1\n\t"
212                              "casx      [%2], %%g7, %%g1\n\t"
213                              "cmp       %%g7, %%g1\n\t"
214                              "membar    #StoreLoad | #StoreStore\n\t"
215                              "bne,pn    %%xcc, 1b\n\t"
216                              " nop"
217                              : /* no outputs */
218                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
219                              : "g1", "g7");
220 }
221
222 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
223 {
224         unsigned long mask = (1UL << PG_dcache_dirty);
225
226         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
227                              "1:\n\t"
228                              "ldx       [%2], %%g7\n\t"
229                              "srlx      %%g7, %4, %%g1\n\t"
230                              "and       %%g1, %3, %%g1\n\t"
231                              "cmp       %%g1, %0\n\t"
232                              "bne,pn    %%icc, 2f\n\t"
233                              " andn     %%g7, %1, %%g1\n\t"
234                              "casx      [%2], %%g7, %%g1\n\t"
235                              "cmp       %%g7, %%g1\n\t"
236                              "membar    #StoreLoad | #StoreStore\n\t"
237                              "bne,pn    %%xcc, 1b\n\t"
238                              " nop\n"
239                              "2:"
240                              : /* no outputs */
241                              : "r" (cpu), "r" (mask), "r" (&page->flags),
242                                "i" (PG_dcache_cpu_mask),
243                                "i" (PG_dcache_cpu_shift)
244                              : "g1", "g7");
245 }
246
247 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
248 {
249         struct mm_struct *mm;
250         struct page *page;
251         unsigned long pfn;
252         unsigned long pg_flags;
253         unsigned long mm_rss;
254
255         pfn = pte_pfn(pte);
256         if (pfn_valid(pfn) &&
257             (page = pfn_to_page(pfn), page_mapping(page)) &&
258             ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
259                 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
260                            PG_dcache_cpu_mask);
261                 int this_cpu = get_cpu();
262
263                 /* This is just to optimize away some function calls
264                  * in the SMP case.
265                  */
266                 if (cpu == this_cpu)
267                         flush_dcache_page_impl(page);
268                 else
269                         smp_flush_dcache_page_impl(page, cpu);
270
271                 clear_dcache_dirty_cpu(page, cpu);
272
273                 put_cpu();
274         }
275
276         mm = vma->vm_mm;
277         mm_rss = get_mm_rss(mm);
278         if (mm_rss >= mm->context.tsb_rss_limit)
279                 tsb_grow(mm, mm_rss, GFP_ATOMIC);
280
281         if ((pte_val(pte) & _PAGE_ALL_SZ_BITS) == _PAGE_SZBITS) {
282                 struct tsb *tsb;
283                 unsigned long tag;
284
285                 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
286                                        (mm->context.tsb_nentries - 1UL)];
287                 tag = (address >> 22UL) | CTX_HWBITS(mm->context) << 48UL;
288                 tsb_insert(tsb, tag, pte_val(pte));
289         }
290 }
291
292 void flush_dcache_page(struct page *page)
293 {
294         struct address_space *mapping;
295         int this_cpu;
296
297         /* Do not bother with the expensive D-cache flush if it
298          * is merely the zero page.  The 'bigcore' testcase in GDB
299          * causes this case to run millions of times.
300          */
301         if (page == ZERO_PAGE(0))
302                 return;
303
304         this_cpu = get_cpu();
305
306         mapping = page_mapping(page);
307         if (mapping && !mapping_mapped(mapping)) {
308                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
309                 if (dirty) {
310                         int dirty_cpu = dcache_dirty_cpu(page);
311
312                         if (dirty_cpu == this_cpu)
313                                 goto out;
314                         smp_flush_dcache_page_impl(page, dirty_cpu);
315                 }
316                 set_dcache_dirty(page, this_cpu);
317         } else {
318                 /* We could delay the flush for the !page_mapping
319                  * case too.  But that case is for exec env/arg
320                  * pages and those are %99 certainly going to get
321                  * faulted into the tlb (and thus flushed) anyways.
322                  */
323                 flush_dcache_page_impl(page);
324         }
325
326 out:
327         put_cpu();
328 }
329
330 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
331 {
332         /* Cheetah has coherent I-cache. */
333         if (tlb_type == spitfire) {
334                 unsigned long kaddr;
335
336                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
337                         __flush_icache_page(__get_phys(kaddr));
338         }
339 }
340
341 unsigned long page_to_pfn(struct page *page)
342 {
343         return (unsigned long) ((page - mem_map) + pfn_base);
344 }
345
346 struct page *pfn_to_page(unsigned long pfn)
347 {
348         return (mem_map + (pfn - pfn_base));
349 }
350
351 void show_mem(void)
352 {
353         printk("Mem-info:\n");
354         show_free_areas();
355         printk("Free swap:       %6ldkB\n",
356                nr_swap_pages << (PAGE_SHIFT-10));
357         printk("%ld pages of RAM\n", num_physpages);
358         printk("%d free pages\n", nr_free_pages());
359 }
360
361 void mmu_info(struct seq_file *m)
362 {
363         if (tlb_type == cheetah)
364                 seq_printf(m, "MMU Type\t: Cheetah\n");
365         else if (tlb_type == cheetah_plus)
366                 seq_printf(m, "MMU Type\t: Cheetah+\n");
367         else if (tlb_type == spitfire)
368                 seq_printf(m, "MMU Type\t: Spitfire\n");
369         else
370                 seq_printf(m, "MMU Type\t: ???\n");
371
372 #ifdef CONFIG_DEBUG_DCFLUSH
373         seq_printf(m, "DCPageFlushes\t: %d\n",
374                    atomic_read(&dcpage_flushes));
375 #ifdef CONFIG_SMP
376         seq_printf(m, "DCPageFlushesXC\t: %d\n",
377                    atomic_read(&dcpage_flushes_xcall));
378 #endif /* CONFIG_SMP */
379 #endif /* CONFIG_DEBUG_DCFLUSH */
380 }
381
382 struct linux_prom_translation {
383         unsigned long virt;
384         unsigned long size;
385         unsigned long data;
386 };
387
388 /* Exported for kernel TLB miss handling in ktlb.S */
389 struct linux_prom_translation prom_trans[512] __read_mostly;
390 unsigned int prom_trans_ents __read_mostly;
391
392 extern unsigned long prom_boot_page;
393 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
394 extern int prom_get_mmu_ihandle(void);
395 extern void register_prom_callbacks(void);
396
397 /* Exported for SMP bootup purposes. */
398 unsigned long kern_locked_tte_data;
399
400 /*
401  * Translate PROM's mapping we capture at boot time into physical address.
402  * The second parameter is only set from prom_callback() invocations.
403  */
404 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
405 {
406         int i;
407
408         for (i = 0; i < prom_trans_ents; i++) {
409                 struct linux_prom_translation *p = &prom_trans[i];
410
411                 if (promva >= p->virt &&
412                     promva < (p->virt + p->size)) {
413                         unsigned long base = p->data & _PAGE_PADDR;
414
415                         if (error)
416                                 *error = 0;
417                         return base + (promva & (8192 - 1));
418                 }
419         }
420         if (error)
421                 *error = 1;
422         return 0UL;
423 }
424
425 /* The obp translations are saved based on 8k pagesize, since obp can
426  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
427  * HI_OBP_ADDRESS range are handled in ktlb.S.
428  */
429 static inline int in_obp_range(unsigned long vaddr)
430 {
431         return (vaddr >= LOW_OBP_ADDRESS &&
432                 vaddr < HI_OBP_ADDRESS);
433 }
434
435 static int cmp_ptrans(const void *a, const void *b)
436 {
437         const struct linux_prom_translation *x = a, *y = b;
438
439         if (x->virt > y->virt)
440                 return 1;
441         if (x->virt < y->virt)
442                 return -1;
443         return 0;
444 }
445
446 /* Read OBP translations property into 'prom_trans[]'.  */
447 static void __init read_obp_translations(void)
448 {
449         int n, node, ents, first, last, i;
450
451         node = prom_finddevice("/virtual-memory");
452         n = prom_getproplen(node, "translations");
453         if (unlikely(n == 0 || n == -1)) {
454                 prom_printf("prom_mappings: Couldn't get size.\n");
455                 prom_halt();
456         }
457         if (unlikely(n > sizeof(prom_trans))) {
458                 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
459                 prom_halt();
460         }
461
462         if ((n = prom_getproperty(node, "translations",
463                                   (char *)&prom_trans[0],
464                                   sizeof(prom_trans))) == -1) {
465                 prom_printf("prom_mappings: Couldn't get property.\n");
466                 prom_halt();
467         }
468
469         n = n / sizeof(struct linux_prom_translation);
470
471         ents = n;
472
473         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
474              cmp_ptrans, NULL);
475
476         /* Now kick out all the non-OBP entries.  */
477         for (i = 0; i < ents; i++) {
478                 if (in_obp_range(prom_trans[i].virt))
479                         break;
480         }
481         first = i;
482         for (; i < ents; i++) {
483                 if (!in_obp_range(prom_trans[i].virt))
484                         break;
485         }
486         last = i;
487
488         for (i = 0; i < (last - first); i++) {
489                 struct linux_prom_translation *src = &prom_trans[i + first];
490                 struct linux_prom_translation *dest = &prom_trans[i];
491
492                 *dest = *src;
493         }
494         for (; i < ents; i++) {
495                 struct linux_prom_translation *dest = &prom_trans[i];
496                 dest->virt = dest->size = dest->data = 0x0UL;
497         }
498
499         prom_trans_ents = last - first;
500
501         if (tlb_type == spitfire) {
502                 /* Clear diag TTE bits. */
503                 for (i = 0; i < prom_trans_ents; i++)
504                         prom_trans[i].data &= ~0x0003fe0000000000UL;
505         }
506 }
507
508 static void __init remap_kernel(void)
509 {
510         unsigned long phys_page, tte_vaddr, tte_data;
511         int tlb_ent = sparc64_highest_locked_tlbent();
512
513         tte_vaddr = (unsigned long) KERNBASE;
514         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
515         tte_data = (phys_page | (_PAGE_VALID | _PAGE_SZ4MB |
516                                  _PAGE_CP | _PAGE_CV | _PAGE_P |
517                                  _PAGE_L | _PAGE_W));
518
519         kern_locked_tte_data = tte_data;
520
521         /* Now lock us into the TLBs via OBP. */
522         prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
523         prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
524         if (bigkernel) {
525                 tlb_ent -= 1;
526                 prom_dtlb_load(tlb_ent,
527                                tte_data + 0x400000, 
528                                tte_vaddr + 0x400000);
529                 prom_itlb_load(tlb_ent,
530                                tte_data + 0x400000, 
531                                tte_vaddr + 0x400000);
532         }
533         sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
534         if (tlb_type == cheetah_plus) {
535                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
536                                             CTX_CHEETAH_PLUS_NUC);
537                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
538                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
539         }
540 }
541
542
543 static void __init inherit_prom_mappings(void)
544 {
545         read_obp_translations();
546
547         /* Now fixup OBP's idea about where we really are mapped. */
548         prom_printf("Remapping the kernel... ");
549         remap_kernel();
550         prom_printf("done.\n");
551
552         prom_printf("Registering callbacks... ");
553         register_prom_callbacks();
554         prom_printf("done.\n");
555 }
556
557 void prom_world(int enter)
558 {
559         if (!enter)
560                 set_fs((mm_segment_t) { get_thread_current_ds() });
561
562         __asm__ __volatile__("flushw");
563 }
564
565 #ifdef DCACHE_ALIASING_POSSIBLE
566 void __flush_dcache_range(unsigned long start, unsigned long end)
567 {
568         unsigned long va;
569
570         if (tlb_type == spitfire) {
571                 int n = 0;
572
573                 for (va = start; va < end; va += 32) {
574                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
575                         if (++n >= 512)
576                                 break;
577                 }
578         } else {
579                 start = __pa(start);
580                 end = __pa(end);
581                 for (va = start; va < end; va += 32)
582                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
583                                              "membar #Sync"
584                                              : /* no outputs */
585                                              : "r" (va),
586                                                "i" (ASI_DCACHE_INVALIDATE));
587         }
588 }
589 #endif /* DCACHE_ALIASING_POSSIBLE */
590
591 /* If not locked, zap it. */
592 void __flush_tlb_all(void)
593 {
594         unsigned long pstate;
595         int i;
596
597         __asm__ __volatile__("flushw\n\t"
598                              "rdpr      %%pstate, %0\n\t"
599                              "wrpr      %0, %1, %%pstate"
600                              : "=r" (pstate)
601                              : "i" (PSTATE_IE));
602         if (tlb_type == spitfire) {
603                 for (i = 0; i < 64; i++) {
604                         /* Spitfire Errata #32 workaround */
605                         /* NOTE: Always runs on spitfire, so no
606                          *       cheetah+ page size encodings.
607                          */
608                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
609                                              "flush     %%g6"
610                                              : /* No outputs */
611                                              : "r" (0),
612                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
613
614                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
615                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
616                                                      "membar #Sync"
617                                                      : /* no outputs */
618                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
619                                 spitfire_put_dtlb_data(i, 0x0UL);
620                         }
621
622                         /* Spitfire Errata #32 workaround */
623                         /* NOTE: Always runs on spitfire, so no
624                          *       cheetah+ page size encodings.
625                          */
626                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
627                                              "flush     %%g6"
628                                              : /* No outputs */
629                                              : "r" (0),
630                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
631
632                         if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
633                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
634                                                      "membar #Sync"
635                                                      : /* no outputs */
636                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
637                                 spitfire_put_itlb_data(i, 0x0UL);
638                         }
639                 }
640         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
641                 cheetah_flush_dtlb_all();
642                 cheetah_flush_itlb_all();
643         }
644         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
645                              : : "r" (pstate));
646 }
647
648 /* Caller does TLB context flushing on local CPU if necessary.
649  * The caller also ensures that CTX_VALID(mm->context) is false.
650  *
651  * We must be careful about boundary cases so that we never
652  * let the user have CTX 0 (nucleus) or we ever use a CTX
653  * version of zero (and thus NO_CONTEXT would not be caught
654  * by version mis-match tests in mmu_context.h).
655  */
656 void get_new_mmu_context(struct mm_struct *mm)
657 {
658         unsigned long ctx, new_ctx;
659         unsigned long orig_pgsz_bits;
660         
661
662         spin_lock(&ctx_alloc_lock);
663         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
664         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
665         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
666         if (new_ctx >= (1 << CTX_NR_BITS)) {
667                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
668                 if (new_ctx >= ctx) {
669                         int i;
670                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
671                                 CTX_FIRST_VERSION;
672                         if (new_ctx == 1)
673                                 new_ctx = CTX_FIRST_VERSION;
674
675                         /* Don't call memset, for 16 entries that's just
676                          * plain silly...
677                          */
678                         mmu_context_bmap[0] = 3;
679                         mmu_context_bmap[1] = 0;
680                         mmu_context_bmap[2] = 0;
681                         mmu_context_bmap[3] = 0;
682                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
683                                 mmu_context_bmap[i + 0] = 0;
684                                 mmu_context_bmap[i + 1] = 0;
685                                 mmu_context_bmap[i + 2] = 0;
686                                 mmu_context_bmap[i + 3] = 0;
687                         }
688                         goto out;
689                 }
690         }
691         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
692         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
693 out:
694         tlb_context_cache = new_ctx;
695         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
696         spin_unlock(&ctx_alloc_lock);
697 }
698
699 void sparc_ultra_dump_itlb(void)
700 {
701         int slot;
702
703         if (tlb_type == spitfire) {
704                 printk ("Contents of itlb: ");
705                 for (slot = 0; slot < 14; slot++) printk ("    ");
706                 printk ("%2x:%016lx,%016lx\n",
707                         0,
708                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
709                 for (slot = 1; slot < 64; slot+=3) {
710                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n", 
711                                 slot,
712                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
713                                 slot+1,
714                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
715                                 slot+2,
716                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
717                 }
718         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
719                 printk ("Contents of itlb0:\n");
720                 for (slot = 0; slot < 16; slot+=2) {
721                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
722                                 slot,
723                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
724                                 slot+1,
725                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
726                 }
727                 printk ("Contents of itlb2:\n");
728                 for (slot = 0; slot < 128; slot+=2) {
729                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
730                                 slot,
731                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
732                                 slot+1,
733                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
734                 }
735         }
736 }
737
738 void sparc_ultra_dump_dtlb(void)
739 {
740         int slot;
741
742         if (tlb_type == spitfire) {
743                 printk ("Contents of dtlb: ");
744                 for (slot = 0; slot < 14; slot++) printk ("    ");
745                 printk ("%2x:%016lx,%016lx\n", 0,
746                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
747                 for (slot = 1; slot < 64; slot+=3) {
748                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n", 
749                                 slot,
750                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
751                                 slot+1,
752                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
753                                 slot+2,
754                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
755                 }
756         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
757                 printk ("Contents of dtlb0:\n");
758                 for (slot = 0; slot < 16; slot+=2) {
759                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
760                                 slot,
761                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
762                                 slot+1,
763                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
764                 }
765                 printk ("Contents of dtlb2:\n");
766                 for (slot = 0; slot < 512; slot+=2) {
767                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
768                                 slot,
769                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
770                                 slot+1,
771                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
772                 }
773                 if (tlb_type == cheetah_plus) {
774                         printk ("Contents of dtlb3:\n");
775                         for (slot = 0; slot < 512; slot+=2) {
776                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
777                                         slot,
778                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
779                                         slot+1,
780                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
781                         }
782                 }
783         }
784 }
785
786 static inline void spitfire_errata32(void)
787 {
788         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
789                              "flush     %%g6"
790                              : /* No outputs */
791                              : "r" (0),
792                                "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
793 }
794
795 extern unsigned long cmdline_memory_size;
796
797 unsigned long __init bootmem_init(unsigned long *pages_avail)
798 {
799         unsigned long bootmap_size, start_pfn, end_pfn;
800         unsigned long end_of_phys_memory = 0UL;
801         unsigned long bootmap_pfn, bytes_avail, size;
802         int i;
803
804 #ifdef CONFIG_DEBUG_BOOTMEM
805         prom_printf("bootmem_init: Scan pavail, ");
806 #endif
807
808         bytes_avail = 0UL;
809         for (i = 0; i < pavail_ents; i++) {
810                 end_of_phys_memory = pavail[i].phys_addr +
811                         pavail[i].reg_size;
812                 bytes_avail += pavail[i].reg_size;
813                 if (cmdline_memory_size) {
814                         if (bytes_avail > cmdline_memory_size) {
815                                 unsigned long slack = bytes_avail - cmdline_memory_size;
816
817                                 bytes_avail -= slack;
818                                 end_of_phys_memory -= slack;
819
820                                 pavail[i].reg_size -= slack;
821                                 if ((long)pavail[i].reg_size <= 0L) {
822                                         pavail[i].phys_addr = 0xdeadbeefUL;
823                                         pavail[i].reg_size = 0UL;
824                                         pavail_ents = i;
825                                 } else {
826                                         pavail[i+1].reg_size = 0Ul;
827                                         pavail[i+1].phys_addr = 0xdeadbeefUL;
828                                         pavail_ents = i + 1;
829                                 }
830                                 break;
831                         }
832                 }
833         }
834
835         *pages_avail = bytes_avail >> PAGE_SHIFT;
836
837         /* Start with page aligned address of last symbol in kernel
838          * image.  The kernel is hard mapped below PAGE_OFFSET in a
839          * 4MB locked TLB translation.
840          */
841         start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
842
843         bootmap_pfn = start_pfn;
844
845         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
846
847 #ifdef CONFIG_BLK_DEV_INITRD
848         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
849         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
850                 unsigned long ramdisk_image = sparc_ramdisk_image ?
851                         sparc_ramdisk_image : sparc_ramdisk_image64;
852                 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
853                         ramdisk_image -= KERNBASE;
854                 initrd_start = ramdisk_image + phys_base;
855                 initrd_end = initrd_start + sparc_ramdisk_size;
856                 if (initrd_end > end_of_phys_memory) {
857                         printk(KERN_CRIT "initrd extends beyond end of memory "
858                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
859                                initrd_end, end_of_phys_memory);
860                         initrd_start = 0;
861                 }
862                 if (initrd_start) {
863                         if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
864                             initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
865                                 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
866                 }
867         }
868 #endif  
869         /* Initialize the boot-time allocator. */
870         max_pfn = max_low_pfn = end_pfn;
871         min_low_pfn = pfn_base;
872
873 #ifdef CONFIG_DEBUG_BOOTMEM
874         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
875                     min_low_pfn, bootmap_pfn, max_low_pfn);
876 #endif
877         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
878
879         /* Now register the available physical memory with the
880          * allocator.
881          */
882         for (i = 0; i < pavail_ents; i++) {
883 #ifdef CONFIG_DEBUG_BOOTMEM
884                 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
885                             i, pavail[i].phys_addr, pavail[i].reg_size);
886 #endif
887                 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
888         }
889
890 #ifdef CONFIG_BLK_DEV_INITRD
891         if (initrd_start) {
892                 size = initrd_end - initrd_start;
893
894                 /* Resert the initrd image area. */
895 #ifdef CONFIG_DEBUG_BOOTMEM
896                 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
897                         initrd_start, initrd_end);
898 #endif
899                 reserve_bootmem(initrd_start, size);
900                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
901
902                 initrd_start += PAGE_OFFSET;
903                 initrd_end += PAGE_OFFSET;
904         }
905 #endif
906         /* Reserve the kernel text/data/bss. */
907 #ifdef CONFIG_DEBUG_BOOTMEM
908         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
909 #endif
910         reserve_bootmem(kern_base, kern_size);
911         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
912
913         /* Reserve the bootmem map.   We do not account for it
914          * in pages_avail because we will release that memory
915          * in free_all_bootmem.
916          */
917         size = bootmap_size;
918 #ifdef CONFIG_DEBUG_BOOTMEM
919         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
920                     (bootmap_pfn << PAGE_SHIFT), size);
921 #endif
922         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
923         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
924
925         return end_pfn;
926 }
927
928 #ifdef CONFIG_DEBUG_PAGEALLOC
929 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
930 {
931         unsigned long vstart = PAGE_OFFSET + pstart;
932         unsigned long vend = PAGE_OFFSET + pend;
933         unsigned long alloc_bytes = 0UL;
934
935         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
936                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
937                             vstart, vend);
938                 prom_halt();
939         }
940
941         while (vstart < vend) {
942                 unsigned long this_end, paddr = __pa(vstart);
943                 pgd_t *pgd = pgd_offset_k(vstart);
944                 pud_t *pud;
945                 pmd_t *pmd;
946                 pte_t *pte;
947
948                 pud = pud_offset(pgd, vstart);
949                 if (pud_none(*pud)) {
950                         pmd_t *new;
951
952                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
953                         alloc_bytes += PAGE_SIZE;
954                         pud_populate(&init_mm, pud, new);
955                 }
956
957                 pmd = pmd_offset(pud, vstart);
958                 if (!pmd_present(*pmd)) {
959                         pte_t *new;
960
961                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
962                         alloc_bytes += PAGE_SIZE;
963                         pmd_populate_kernel(&init_mm, pmd, new);
964                 }
965
966                 pte = pte_offset_kernel(pmd, vstart);
967                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
968                 if (this_end > vend)
969                         this_end = vend;
970
971                 while (vstart < this_end) {
972                         pte_val(*pte) = (paddr | pgprot_val(prot));
973
974                         vstart += PAGE_SIZE;
975                         paddr += PAGE_SIZE;
976                         pte++;
977                 }
978         }
979
980         return alloc_bytes;
981 }
982
983 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
984 static int pall_ents __initdata;
985
986 extern unsigned int kvmap_linear_patch[1];
987
988 static void __init kernel_physical_mapping_init(void)
989 {
990         unsigned long i, mem_alloced = 0UL;
991
992         read_obp_memory("reg", &pall[0], &pall_ents);
993
994         for (i = 0; i < pall_ents; i++) {
995                 unsigned long phys_start, phys_end;
996
997                 phys_start = pall[i].phys_addr;
998                 phys_end = phys_start + pall[i].reg_size;
999                 mem_alloced += kernel_map_range(phys_start, phys_end,
1000                                                 PAGE_KERNEL);
1001         }
1002
1003         printk("Allocated %ld bytes for kernel page tables.\n",
1004                mem_alloced);
1005
1006         kvmap_linear_patch[0] = 0x01000000; /* nop */
1007         flushi(&kvmap_linear_patch[0]);
1008
1009         __flush_tlb_all();
1010 }
1011
1012 void kernel_map_pages(struct page *page, int numpages, int enable)
1013 {
1014         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1015         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1016
1017         kernel_map_range(phys_start, phys_end,
1018                          (enable ? PAGE_KERNEL : __pgprot(0)));
1019
1020         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1021                                PAGE_OFFSET + phys_end);
1022
1023         /* we should perform an IPI and flush all tlbs,
1024          * but that can deadlock->flush only current cpu.
1025          */
1026         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1027                                  PAGE_OFFSET + phys_end);
1028 }
1029 #endif
1030
1031 unsigned long __init find_ecache_flush_span(unsigned long size)
1032 {
1033         int i;
1034
1035         for (i = 0; i < pavail_ents; i++) {
1036                 if (pavail[i].reg_size >= size)
1037                         return pavail[i].phys_addr;
1038         }
1039
1040         return ~0UL;
1041 }
1042
1043 /* paging_init() sets up the page tables */
1044
1045 extern void cheetah_ecache_flush_init(void);
1046
1047 static unsigned long last_valid_pfn;
1048 pgd_t swapper_pg_dir[2048];
1049
1050 void __init paging_init(void)
1051 {
1052         unsigned long end_pfn, pages_avail, shift;
1053         unsigned long real_end, i;
1054
1055         /* Find available physical memory... */
1056         read_obp_memory("available", &pavail[0], &pavail_ents);
1057
1058         phys_base = 0xffffffffffffffffUL;
1059         for (i = 0; i < pavail_ents; i++)
1060                 phys_base = min(phys_base, pavail[i].phys_addr);
1061
1062         pfn_base = phys_base >> PAGE_SHIFT;
1063
1064         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1065         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1066
1067         set_bit(0, mmu_context_bmap);
1068
1069         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1070
1071         real_end = (unsigned long)_end;
1072         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1073                 bigkernel = 1;
1074         if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1075                 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1076                 prom_halt();
1077         }
1078
1079         /* Set kernel pgd to upper alias so physical page computations
1080          * work.
1081          */
1082         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1083         
1084         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1085
1086         /* Now can init the kernel/bad page tables. */
1087         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1088                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1089         
1090         inherit_prom_mappings();
1091         
1092         /* Ok, we can use our TLB miss and window trap handlers safely.  */
1093         setup_tba();
1094
1095         __flush_tlb_all();
1096
1097         /* Setup bootmem... */
1098         pages_avail = 0;
1099         last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1100
1101 #ifdef CONFIG_DEBUG_PAGEALLOC
1102         kernel_physical_mapping_init();
1103 #endif
1104
1105         {
1106                 unsigned long zones_size[MAX_NR_ZONES];
1107                 unsigned long zholes_size[MAX_NR_ZONES];
1108                 unsigned long npages;
1109                 int znum;
1110
1111                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1112                         zones_size[znum] = zholes_size[znum] = 0;
1113
1114                 npages = end_pfn - pfn_base;
1115                 zones_size[ZONE_DMA] = npages;
1116                 zholes_size[ZONE_DMA] = npages - pages_avail;
1117
1118                 free_area_init_node(0, &contig_page_data, zones_size,
1119                                     phys_base >> PAGE_SHIFT, zholes_size);
1120         }
1121
1122         device_scan();
1123 }
1124
1125 static void __init taint_real_pages(void)
1126 {
1127         int i;
1128
1129         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1130
1131         /* Find changes discovered in the physmem available rescan and
1132          * reserve the lost portions in the bootmem maps.
1133          */
1134         for (i = 0; i < pavail_ents; i++) {
1135                 unsigned long old_start, old_end;
1136
1137                 old_start = pavail[i].phys_addr;
1138                 old_end = old_start +
1139                         pavail[i].reg_size;
1140                 while (old_start < old_end) {
1141                         int n;
1142
1143                         for (n = 0; pavail_rescan_ents; n++) {
1144                                 unsigned long new_start, new_end;
1145
1146                                 new_start = pavail_rescan[n].phys_addr;
1147                                 new_end = new_start +
1148                                         pavail_rescan[n].reg_size;
1149
1150                                 if (new_start <= old_start &&
1151                                     new_end >= (old_start + PAGE_SIZE)) {
1152                                         set_bit(old_start >> 22,
1153                                                 sparc64_valid_addr_bitmap);
1154                                         goto do_next_page;
1155                                 }
1156                         }
1157                         reserve_bootmem(old_start, PAGE_SIZE);
1158
1159                 do_next_page:
1160                         old_start += PAGE_SIZE;
1161                 }
1162         }
1163 }
1164
1165 void __init mem_init(void)
1166 {
1167         unsigned long codepages, datapages, initpages;
1168         unsigned long addr, last;
1169         int i;
1170
1171         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1172         i += 1;
1173         sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1174         if (sparc64_valid_addr_bitmap == NULL) {
1175                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1176                 prom_halt();
1177         }
1178         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1179
1180         addr = PAGE_OFFSET + kern_base;
1181         last = PAGE_ALIGN(kern_size) + addr;
1182         while (addr < last) {
1183                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1184                 addr += PAGE_SIZE;
1185         }
1186
1187         taint_real_pages();
1188
1189         max_mapnr = last_valid_pfn - pfn_base;
1190         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1191
1192 #ifdef CONFIG_DEBUG_BOOTMEM
1193         prom_printf("mem_init: Calling free_all_bootmem().\n");
1194 #endif
1195         totalram_pages = num_physpages = free_all_bootmem() - 1;
1196
1197         /*
1198          * Set up the zero page, mark it reserved, so that page count
1199          * is not manipulated when freeing the page from user ptes.
1200          */
1201         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1202         if (mem_map_zero == NULL) {
1203                 prom_printf("paging_init: Cannot alloc zero page.\n");
1204                 prom_halt();
1205         }
1206         SetPageReserved(mem_map_zero);
1207
1208         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1209         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1210         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1211         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1212         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1213         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1214
1215         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1216                nr_free_pages() << (PAGE_SHIFT-10),
1217                codepages << (PAGE_SHIFT-10),
1218                datapages << (PAGE_SHIFT-10), 
1219                initpages << (PAGE_SHIFT-10), 
1220                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1221
1222         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1223                 cheetah_ecache_flush_init();
1224 }
1225
1226 void free_initmem(void)
1227 {
1228         unsigned long addr, initend;
1229
1230         /*
1231          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1232          */
1233         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1234         initend = (unsigned long)(__init_end) & PAGE_MASK;
1235         for (; addr < initend; addr += PAGE_SIZE) {
1236                 unsigned long page;
1237                 struct page *p;
1238
1239                 page = (addr +
1240                         ((unsigned long) __va(kern_base)) -
1241                         ((unsigned long) KERNBASE));
1242                 memset((void *)addr, 0xcc, PAGE_SIZE);
1243                 p = virt_to_page(page);
1244
1245                 ClearPageReserved(p);
1246                 set_page_count(p, 1);
1247                 __free_page(p);
1248                 num_physpages++;
1249                 totalram_pages++;
1250         }
1251 }
1252
1253 #ifdef CONFIG_BLK_DEV_INITRD
1254 void free_initrd_mem(unsigned long start, unsigned long end)
1255 {
1256         if (start < end)
1257                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1258         for (; start < end; start += PAGE_SIZE) {
1259                 struct page *p = virt_to_page(start);
1260
1261                 ClearPageReserved(p);
1262                 set_page_count(p, 1);
1263                 __free_page(p);
1264                 num_physpages++;
1265                 totalram_pages++;
1266         }
1267 }
1268 #endif