[MIPS] IP32: Enable PCI bridges
[linux-2.6.git] / arch / sparc64 / kernel / smp.c
1 /* smp.c: Sparc64 SMP support.
2  *
3  * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net)
4  */
5
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <linux/mm.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
18 #include <linux/fs.h>
19 #include <linux/seq_file.h>
20 #include <linux/cache.h>
21 #include <linux/jiffies.h>
22 #include <linux/profile.h>
23 #include <linux/bootmem.h>
24
25 #include <asm/head.h>
26 #include <asm/ptrace.h>
27 #include <asm/atomic.h>
28 #include <asm/tlbflush.h>
29 #include <asm/mmu_context.h>
30 #include <asm/cpudata.h>
31 #include <asm/hvtramp.h>
32 #include <asm/io.h>
33
34 #include <asm/irq.h>
35 #include <asm/irq_regs.h>
36 #include <asm/page.h>
37 #include <asm/pgtable.h>
38 #include <asm/oplib.h>
39 #include <asm/uaccess.h>
40 #include <asm/timer.h>
41 #include <asm/starfire.h>
42 #include <asm/tlb.h>
43 #include <asm/sections.h>
44 #include <asm/prom.h>
45 #include <asm/mdesc.h>
46 #include <asm/ldc.h>
47 #include <asm/hypervisor.h>
48
49 extern void calibrate_delay(void);
50
51 int sparc64_multi_core __read_mostly;
52
53 cpumask_t cpu_possible_map __read_mostly = CPU_MASK_NONE;
54 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
55 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly =
56         { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
57 cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
58         { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
59
60 EXPORT_SYMBOL(cpu_possible_map);
61 EXPORT_SYMBOL(cpu_online_map);
62 EXPORT_SYMBOL(cpu_sibling_map);
63 EXPORT_SYMBOL(cpu_core_map);
64
65 static cpumask_t smp_commenced_mask;
66
67 void smp_info(struct seq_file *m)
68 {
69         int i;
70         
71         seq_printf(m, "State:\n");
72         for_each_online_cpu(i)
73                 seq_printf(m, "CPU%d:\t\tonline\n", i);
74 }
75
76 void smp_bogo(struct seq_file *m)
77 {
78         int i;
79         
80         for_each_online_cpu(i)
81                 seq_printf(m,
82                            "Cpu%dClkTck\t: %016lx\n",
83                            i, cpu_data(i).clock_tick);
84 }
85
86 static __cacheline_aligned_in_smp DEFINE_SPINLOCK(call_lock);
87
88 extern void setup_sparc64_timer(void);
89
90 static volatile unsigned long callin_flag = 0;
91
92 void __devinit smp_callin(void)
93 {
94         int cpuid = hard_smp_processor_id();
95
96         __local_per_cpu_offset = __per_cpu_offset(cpuid);
97
98         if (tlb_type == hypervisor)
99                 sun4v_ktsb_register();
100
101         __flush_tlb_all();
102
103         setup_sparc64_timer();
104
105         if (cheetah_pcache_forced_on)
106                 cheetah_enable_pcache();
107
108         local_irq_enable();
109
110         callin_flag = 1;
111         __asm__ __volatile__("membar #Sync\n\t"
112                              "flush  %%g6" : : : "memory");
113
114         /* Clear this or we will die instantly when we
115          * schedule back to this idler...
116          */
117         current_thread_info()->new_child = 0;
118
119         /* Attach to the address space of init_task. */
120         atomic_inc(&init_mm.mm_count);
121         current->active_mm = &init_mm;
122
123         while (!cpu_isset(cpuid, smp_commenced_mask))
124                 rmb();
125
126         spin_lock(&call_lock);
127         cpu_set(cpuid, cpu_online_map);
128         spin_unlock(&call_lock);
129
130         /* idle thread is expected to have preempt disabled */
131         preempt_disable();
132 }
133
134 void cpu_panic(void)
135 {
136         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
137         panic("SMP bolixed\n");
138 }
139
140 /* This tick register synchronization scheme is taken entirely from
141  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
142  *
143  * The only change I've made is to rework it so that the master
144  * initiates the synchonization instead of the slave. -DaveM
145  */
146
147 #define MASTER  0
148 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
149
150 #define NUM_ROUNDS      64      /* magic value */
151 #define NUM_ITERS       5       /* likewise */
152
153 static DEFINE_SPINLOCK(itc_sync_lock);
154 static unsigned long go[SLAVE + 1];
155
156 #define DEBUG_TICK_SYNC 0
157
158 static inline long get_delta (long *rt, long *master)
159 {
160         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
161         unsigned long tcenter, t0, t1, tm;
162         unsigned long i;
163
164         for (i = 0; i < NUM_ITERS; i++) {
165                 t0 = tick_ops->get_tick();
166                 go[MASTER] = 1;
167                 membar_storeload();
168                 while (!(tm = go[SLAVE]))
169                         rmb();
170                 go[SLAVE] = 0;
171                 wmb();
172                 t1 = tick_ops->get_tick();
173
174                 if (t1 - t0 < best_t1 - best_t0)
175                         best_t0 = t0, best_t1 = t1, best_tm = tm;
176         }
177
178         *rt = best_t1 - best_t0;
179         *master = best_tm - best_t0;
180
181         /* average best_t0 and best_t1 without overflow: */
182         tcenter = (best_t0/2 + best_t1/2);
183         if (best_t0 % 2 + best_t1 % 2 == 2)
184                 tcenter++;
185         return tcenter - best_tm;
186 }
187
188 void smp_synchronize_tick_client(void)
189 {
190         long i, delta, adj, adjust_latency = 0, done = 0;
191         unsigned long flags, rt, master_time_stamp, bound;
192 #if DEBUG_TICK_SYNC
193         struct {
194                 long rt;        /* roundtrip time */
195                 long master;    /* master's timestamp */
196                 long diff;      /* difference between midpoint and master's timestamp */
197                 long lat;       /* estimate of itc adjustment latency */
198         } t[NUM_ROUNDS];
199 #endif
200
201         go[MASTER] = 1;
202
203         while (go[MASTER])
204                 rmb();
205
206         local_irq_save(flags);
207         {
208                 for (i = 0; i < NUM_ROUNDS; i++) {
209                         delta = get_delta(&rt, &master_time_stamp);
210                         if (delta == 0) {
211                                 done = 1;       /* let's lock on to this... */
212                                 bound = rt;
213                         }
214
215                         if (!done) {
216                                 if (i > 0) {
217                                         adjust_latency += -delta;
218                                         adj = -delta + adjust_latency/4;
219                                 } else
220                                         adj = -delta;
221
222                                 tick_ops->add_tick(adj);
223                         }
224 #if DEBUG_TICK_SYNC
225                         t[i].rt = rt;
226                         t[i].master = master_time_stamp;
227                         t[i].diff = delta;
228                         t[i].lat = adjust_latency/4;
229 #endif
230                 }
231         }
232         local_irq_restore(flags);
233
234 #if DEBUG_TICK_SYNC
235         for (i = 0; i < NUM_ROUNDS; i++)
236                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
237                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
238 #endif
239
240         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
241                "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
242 }
243
244 static void smp_start_sync_tick_client(int cpu);
245
246 static void smp_synchronize_one_tick(int cpu)
247 {
248         unsigned long flags, i;
249
250         go[MASTER] = 0;
251
252         smp_start_sync_tick_client(cpu);
253
254         /* wait for client to be ready */
255         while (!go[MASTER])
256                 rmb();
257
258         /* now let the client proceed into his loop */
259         go[MASTER] = 0;
260         membar_storeload();
261
262         spin_lock_irqsave(&itc_sync_lock, flags);
263         {
264                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
265                         while (!go[MASTER])
266                                 rmb();
267                         go[MASTER] = 0;
268                         wmb();
269                         go[SLAVE] = tick_ops->get_tick();
270                         membar_storeload();
271                 }
272         }
273         spin_unlock_irqrestore(&itc_sync_lock, flags);
274 }
275
276 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
277 /* XXX Put this in some common place. XXX */
278 static unsigned long kimage_addr_to_ra(void *p)
279 {
280         unsigned long val = (unsigned long) p;
281
282         return kern_base + (val - KERNBASE);
283 }
284
285 static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg)
286 {
287         extern unsigned long sparc64_ttable_tl0;
288         extern unsigned long kern_locked_tte_data;
289         extern int bigkernel;
290         struct hvtramp_descr *hdesc;
291         unsigned long trampoline_ra;
292         struct trap_per_cpu *tb;
293         u64 tte_vaddr, tte_data;
294         unsigned long hv_err;
295
296         hdesc = kzalloc(sizeof(*hdesc), GFP_KERNEL);
297         if (!hdesc) {
298                 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
299                        "hvtramp_descr.\n");
300                 return;
301         }
302
303         hdesc->cpu = cpu;
304         hdesc->num_mappings = (bigkernel ? 2 : 1);
305
306         tb = &trap_block[cpu];
307         tb->hdesc = hdesc;
308
309         hdesc->fault_info_va = (unsigned long) &tb->fault_info;
310         hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
311
312         hdesc->thread_reg = thread_reg;
313
314         tte_vaddr = (unsigned long) KERNBASE;
315         tte_data = kern_locked_tte_data;
316
317         hdesc->maps[0].vaddr = tte_vaddr;
318         hdesc->maps[0].tte   = tte_data;
319         if (bigkernel) {
320                 tte_vaddr += 0x400000;
321                 tte_data  += 0x400000;
322                 hdesc->maps[1].vaddr = tte_vaddr;
323                 hdesc->maps[1].tte   = tte_data;
324         }
325
326         trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
327
328         hv_err = sun4v_cpu_start(cpu, trampoline_ra,
329                                  kimage_addr_to_ra(&sparc64_ttable_tl0),
330                                  __pa(hdesc));
331         if (hv_err)
332                 printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
333                        "gives error %lu\n", hv_err);
334 }
335 #endif
336
337 extern unsigned long sparc64_cpu_startup;
338
339 /* The OBP cpu startup callback truncates the 3rd arg cookie to
340  * 32-bits (I think) so to be safe we have it read the pointer
341  * contained here so we work on >4GB machines. -DaveM
342  */
343 static struct thread_info *cpu_new_thread = NULL;
344
345 static int __devinit smp_boot_one_cpu(unsigned int cpu)
346 {
347         struct trap_per_cpu *tb = &trap_block[cpu];
348         unsigned long entry =
349                 (unsigned long)(&sparc64_cpu_startup);
350         unsigned long cookie =
351                 (unsigned long)(&cpu_new_thread);
352         struct task_struct *p;
353         int timeout, ret;
354
355         p = fork_idle(cpu);
356         callin_flag = 0;
357         cpu_new_thread = task_thread_info(p);
358
359         if (tlb_type == hypervisor) {
360 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
361                 if (ldom_domaining_enabled)
362                         ldom_startcpu_cpuid(cpu,
363                                             (unsigned long) cpu_new_thread);
364                 else
365 #endif
366                         prom_startcpu_cpuid(cpu, entry, cookie);
367         } else {
368                 struct device_node *dp = of_find_node_by_cpuid(cpu);
369
370                 prom_startcpu(dp->node, entry, cookie);
371         }
372
373         for (timeout = 0; timeout < 50000; timeout++) {
374                 if (callin_flag)
375                         break;
376                 udelay(100);
377         }
378
379         if (callin_flag) {
380                 ret = 0;
381         } else {
382                 printk("Processor %d is stuck.\n", cpu);
383                 ret = -ENODEV;
384         }
385         cpu_new_thread = NULL;
386
387         if (tb->hdesc) {
388                 kfree(tb->hdesc);
389                 tb->hdesc = NULL;
390         }
391
392         return ret;
393 }
394
395 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
396 {
397         u64 result, target;
398         int stuck, tmp;
399
400         if (this_is_starfire) {
401                 /* map to real upaid */
402                 cpu = (((cpu & 0x3c) << 1) |
403                         ((cpu & 0x40) >> 4) |
404                         (cpu & 0x3));
405         }
406
407         target = (cpu << 14) | 0x70;
408 again:
409         /* Ok, this is the real Spitfire Errata #54.
410          * One must read back from a UDB internal register
411          * after writes to the UDB interrupt dispatch, but
412          * before the membar Sync for that write.
413          * So we use the high UDB control register (ASI 0x7f,
414          * ADDR 0x20) for the dummy read. -DaveM
415          */
416         tmp = 0x40;
417         __asm__ __volatile__(
418         "wrpr   %1, %2, %%pstate\n\t"
419         "stxa   %4, [%0] %3\n\t"
420         "stxa   %5, [%0+%8] %3\n\t"
421         "add    %0, %8, %0\n\t"
422         "stxa   %6, [%0+%8] %3\n\t"
423         "membar #Sync\n\t"
424         "stxa   %%g0, [%7] %3\n\t"
425         "membar #Sync\n\t"
426         "mov    0x20, %%g1\n\t"
427         "ldxa   [%%g1] 0x7f, %%g0\n\t"
428         "membar #Sync"
429         : "=r" (tmp)
430         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
431           "r" (data0), "r" (data1), "r" (data2), "r" (target),
432           "r" (0x10), "0" (tmp)
433         : "g1");
434
435         /* NOTE: PSTATE_IE is still clear. */
436         stuck = 100000;
437         do {
438                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
439                         : "=r" (result)
440                         : "i" (ASI_INTR_DISPATCH_STAT));
441                 if (result == 0) {
442                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
443                                              : : "r" (pstate));
444                         return;
445                 }
446                 stuck -= 1;
447                 if (stuck == 0)
448                         break;
449         } while (result & 0x1);
450         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
451                              : : "r" (pstate));
452         if (stuck == 0) {
453                 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
454                        smp_processor_id(), result);
455         } else {
456                 udelay(2);
457                 goto again;
458         }
459 }
460
461 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
462 {
463         u64 pstate;
464         int i;
465
466         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
467         for_each_cpu_mask(i, mask)
468                 spitfire_xcall_helper(data0, data1, data2, pstate, i);
469 }
470
471 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
472  * packet, but we have no use for that.  However we do take advantage of
473  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
474  */
475 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
476 {
477         u64 pstate, ver;
478         int nack_busy_id, is_jbus, need_more;
479
480         if (cpus_empty(mask))
481                 return;
482
483         /* Unfortunately, someone at Sun had the brilliant idea to make the
484          * busy/nack fields hard-coded by ITID number for this Ultra-III
485          * derivative processor.
486          */
487         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
488         is_jbus = ((ver >> 32) == __JALAPENO_ID ||
489                    (ver >> 32) == __SERRANO_ID);
490
491         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
492
493 retry:
494         need_more = 0;
495         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
496                              : : "r" (pstate), "i" (PSTATE_IE));
497
498         /* Setup the dispatch data registers. */
499         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
500                              "stxa      %1, [%4] %6\n\t"
501                              "stxa      %2, [%5] %6\n\t"
502                              "membar    #Sync\n\t"
503                              : /* no outputs */
504                              : "r" (data0), "r" (data1), "r" (data2),
505                                "r" (0x40), "r" (0x50), "r" (0x60),
506                                "i" (ASI_INTR_W));
507
508         nack_busy_id = 0;
509         {
510                 int i;
511
512                 for_each_cpu_mask(i, mask) {
513                         u64 target = (i << 14) | 0x70;
514
515                         if (!is_jbus)
516                                 target |= (nack_busy_id << 24);
517                         __asm__ __volatile__(
518                                 "stxa   %%g0, [%0] %1\n\t"
519                                 "membar #Sync\n\t"
520                                 : /* no outputs */
521                                 : "r" (target), "i" (ASI_INTR_W));
522                         nack_busy_id++;
523                         if (nack_busy_id == 32) {
524                                 need_more = 1;
525                                 break;
526                         }
527                 }
528         }
529
530         /* Now, poll for completion. */
531         {
532                 u64 dispatch_stat;
533                 long stuck;
534
535                 stuck = 100000 * nack_busy_id;
536                 do {
537                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
538                                              : "=r" (dispatch_stat)
539                                              : "i" (ASI_INTR_DISPATCH_STAT));
540                         if (dispatch_stat == 0UL) {
541                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
542                                                      : : "r" (pstate));
543                                 if (unlikely(need_more)) {
544                                         int i, cnt = 0;
545                                         for_each_cpu_mask(i, mask) {
546                                                 cpu_clear(i, mask);
547                                                 cnt++;
548                                                 if (cnt == 32)
549                                                         break;
550                                         }
551                                         goto retry;
552                                 }
553                                 return;
554                         }
555                         if (!--stuck)
556                                 break;
557                 } while (dispatch_stat & 0x5555555555555555UL);
558
559                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
560                                      : : "r" (pstate));
561
562                 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
563                         /* Busy bits will not clear, continue instead
564                          * of freezing up on this cpu.
565                          */
566                         printk("CPU[%d]: mondo stuckage result[%016lx]\n",
567                                smp_processor_id(), dispatch_stat);
568                 } else {
569                         int i, this_busy_nack = 0;
570
571                         /* Delay some random time with interrupts enabled
572                          * to prevent deadlock.
573                          */
574                         udelay(2 * nack_busy_id);
575
576                         /* Clear out the mask bits for cpus which did not
577                          * NACK us.
578                          */
579                         for_each_cpu_mask(i, mask) {
580                                 u64 check_mask;
581
582                                 if (is_jbus)
583                                         check_mask = (0x2UL << (2*i));
584                                 else
585                                         check_mask = (0x2UL <<
586                                                       this_busy_nack);
587                                 if ((dispatch_stat & check_mask) == 0)
588                                         cpu_clear(i, mask);
589                                 this_busy_nack += 2;
590                                 if (this_busy_nack == 64)
591                                         break;
592                         }
593
594                         goto retry;
595                 }
596         }
597 }
598
599 /* Multi-cpu list version.  */
600 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
601 {
602         struct trap_per_cpu *tb;
603         u16 *cpu_list;
604         u64 *mondo;
605         cpumask_t error_mask;
606         unsigned long flags, status;
607         int cnt, retries, this_cpu, prev_sent, i;
608
609         if (cpus_empty(mask))
610                 return;
611
612         /* We have to do this whole thing with interrupts fully disabled.
613          * Otherwise if we send an xcall from interrupt context it will
614          * corrupt both our mondo block and cpu list state.
615          *
616          * One consequence of this is that we cannot use timeout mechanisms
617          * that depend upon interrupts being delivered locally.  So, for
618          * example, we cannot sample jiffies and expect it to advance.
619          *
620          * Fortunately, udelay() uses %stick/%tick so we can use that.
621          */
622         local_irq_save(flags);
623
624         this_cpu = smp_processor_id();
625         tb = &trap_block[this_cpu];
626
627         mondo = __va(tb->cpu_mondo_block_pa);
628         mondo[0] = data0;
629         mondo[1] = data1;
630         mondo[2] = data2;
631         wmb();
632
633         cpu_list = __va(tb->cpu_list_pa);
634
635         /* Setup the initial cpu list.  */
636         cnt = 0;
637         for_each_cpu_mask(i, mask)
638                 cpu_list[cnt++] = i;
639
640         cpus_clear(error_mask);
641         retries = 0;
642         prev_sent = 0;
643         do {
644                 int forward_progress, n_sent;
645
646                 status = sun4v_cpu_mondo_send(cnt,
647                                               tb->cpu_list_pa,
648                                               tb->cpu_mondo_block_pa);
649
650                 /* HV_EOK means all cpus received the xcall, we're done.  */
651                 if (likely(status == HV_EOK))
652                         break;
653
654                 /* First, see if we made any forward progress.
655                  *
656                  * The hypervisor indicates successful sends by setting
657                  * cpu list entries to the value 0xffff.
658                  */
659                 n_sent = 0;
660                 for (i = 0; i < cnt; i++) {
661                         if (likely(cpu_list[i] == 0xffff))
662                                 n_sent++;
663                 }
664
665                 forward_progress = 0;
666                 if (n_sent > prev_sent)
667                         forward_progress = 1;
668
669                 prev_sent = n_sent;
670
671                 /* If we get a HV_ECPUERROR, then one or more of the cpus
672                  * in the list are in error state.  Use the cpu_state()
673                  * hypervisor call to find out which cpus are in error state.
674                  */
675                 if (unlikely(status == HV_ECPUERROR)) {
676                         for (i = 0; i < cnt; i++) {
677                                 long err;
678                                 u16 cpu;
679
680                                 cpu = cpu_list[i];
681                                 if (cpu == 0xffff)
682                                         continue;
683
684                                 err = sun4v_cpu_state(cpu);
685                                 if (err >= 0 &&
686                                     err == HV_CPU_STATE_ERROR) {
687                                         cpu_list[i] = 0xffff;
688                                         cpu_set(cpu, error_mask);
689                                 }
690                         }
691                 } else if (unlikely(status != HV_EWOULDBLOCK))
692                         goto fatal_mondo_error;
693
694                 /* Don't bother rewriting the CPU list, just leave the
695                  * 0xffff and non-0xffff entries in there and the
696                  * hypervisor will do the right thing.
697                  *
698                  * Only advance timeout state if we didn't make any
699                  * forward progress.
700                  */
701                 if (unlikely(!forward_progress)) {
702                         if (unlikely(++retries > 10000))
703                                 goto fatal_mondo_timeout;
704
705                         /* Delay a little bit to let other cpus catch up
706                          * on their cpu mondo queue work.
707                          */
708                         udelay(2 * cnt);
709                 }
710         } while (1);
711
712         local_irq_restore(flags);
713
714         if (unlikely(!cpus_empty(error_mask)))
715                 goto fatal_mondo_cpu_error;
716
717         return;
718
719 fatal_mondo_cpu_error:
720         printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
721                "were in error state\n",
722                this_cpu);
723         printk(KERN_CRIT "CPU[%d]: Error mask [ ", this_cpu);
724         for_each_cpu_mask(i, error_mask)
725                 printk("%d ", i);
726         printk("]\n");
727         return;
728
729 fatal_mondo_timeout:
730         local_irq_restore(flags);
731         printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
732                " progress after %d retries.\n",
733                this_cpu, retries);
734         goto dump_cpu_list_and_out;
735
736 fatal_mondo_error:
737         local_irq_restore(flags);
738         printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
739                this_cpu, status);
740         printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
741                "mondo_block_pa(%lx)\n",
742                this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
743
744 dump_cpu_list_and_out:
745         printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
746         for (i = 0; i < cnt; i++)
747                 printk("%u ", cpu_list[i]);
748         printk("]\n");
749 }
750
751 /* Send cross call to all processors mentioned in MASK
752  * except self.
753  */
754 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
755 {
756         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
757         int this_cpu = get_cpu();
758
759         cpus_and(mask, mask, cpu_online_map);
760         cpu_clear(this_cpu, mask);
761
762         if (tlb_type == spitfire)
763                 spitfire_xcall_deliver(data0, data1, data2, mask);
764         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
765                 cheetah_xcall_deliver(data0, data1, data2, mask);
766         else
767                 hypervisor_xcall_deliver(data0, data1, data2, mask);
768         /* NOTE: Caller runs local copy on master. */
769
770         put_cpu();
771 }
772
773 extern unsigned long xcall_sync_tick;
774
775 static void smp_start_sync_tick_client(int cpu)
776 {
777         cpumask_t mask = cpumask_of_cpu(cpu);
778
779         smp_cross_call_masked(&xcall_sync_tick,
780                               0, 0, 0, mask);
781 }
782
783 /* Send cross call to all processors except self. */
784 #define smp_cross_call(func, ctx, data1, data2) \
785         smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
786
787 struct call_data_struct {
788         void (*func) (void *info);
789         void *info;
790         atomic_t finished;
791         int wait;
792 };
793
794 static struct call_data_struct *call_data;
795
796 extern unsigned long xcall_call_function;
797
798 /**
799  * smp_call_function(): Run a function on all other CPUs.
800  * @func: The function to run. This must be fast and non-blocking.
801  * @info: An arbitrary pointer to pass to the function.
802  * @nonatomic: currently unused.
803  * @wait: If true, wait (atomically) until function has completed on other CPUs.
804  *
805  * Returns 0 on success, else a negative status code. Does not return until
806  * remote CPUs are nearly ready to execute <<func>> or are or have executed.
807  *
808  * You must not call this function with disabled interrupts or from a
809  * hardware interrupt handler or from a bottom half handler.
810  */
811 static int smp_call_function_mask(void (*func)(void *info), void *info,
812                                   int nonatomic, int wait, cpumask_t mask)
813 {
814         struct call_data_struct data;
815         int cpus;
816
817         /* Can deadlock when called with interrupts disabled */
818         WARN_ON(irqs_disabled());
819
820         data.func = func;
821         data.info = info;
822         atomic_set(&data.finished, 0);
823         data.wait = wait;
824
825         spin_lock(&call_lock);
826
827         cpu_clear(smp_processor_id(), mask);
828         cpus = cpus_weight(mask);
829         if (!cpus)
830                 goto out_unlock;
831
832         call_data = &data;
833         mb();
834
835         smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
836
837         /* Wait for response */
838         while (atomic_read(&data.finished) != cpus)
839                 cpu_relax();
840
841 out_unlock:
842         spin_unlock(&call_lock);
843
844         return 0;
845 }
846
847 int smp_call_function(void (*func)(void *info), void *info,
848                       int nonatomic, int wait)
849 {
850         return smp_call_function_mask(func, info, nonatomic, wait,
851                                       cpu_online_map);
852 }
853
854 void smp_call_function_client(int irq, struct pt_regs *regs)
855 {
856         void (*func) (void *info) = call_data->func;
857         void *info = call_data->info;
858
859         clear_softint(1 << irq);
860         if (call_data->wait) {
861                 /* let initiator proceed only after completion */
862                 func(info);
863                 atomic_inc(&call_data->finished);
864         } else {
865                 /* let initiator proceed after getting data */
866                 atomic_inc(&call_data->finished);
867                 func(info);
868         }
869 }
870
871 static void tsb_sync(void *info)
872 {
873         struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
874         struct mm_struct *mm = info;
875
876         /* It is not valid to test "currrent->active_mm == mm" here.
877          *
878          * The value of "current" is not changed atomically with
879          * switch_mm().  But that's OK, we just need to check the
880          * current cpu's trap block PGD physical address.
881          */
882         if (tp->pgd_paddr == __pa(mm->pgd))
883                 tsb_context_switch(mm);
884 }
885
886 void smp_tsb_sync(struct mm_struct *mm)
887 {
888         smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask);
889 }
890
891 extern unsigned long xcall_flush_tlb_mm;
892 extern unsigned long xcall_flush_tlb_pending;
893 extern unsigned long xcall_flush_tlb_kernel_range;
894 extern unsigned long xcall_report_regs;
895 extern unsigned long xcall_receive_signal;
896 extern unsigned long xcall_new_mmu_context_version;
897
898 #ifdef DCACHE_ALIASING_POSSIBLE
899 extern unsigned long xcall_flush_dcache_page_cheetah;
900 #endif
901 extern unsigned long xcall_flush_dcache_page_spitfire;
902
903 #ifdef CONFIG_DEBUG_DCFLUSH
904 extern atomic_t dcpage_flushes;
905 extern atomic_t dcpage_flushes_xcall;
906 #endif
907
908 static __inline__ void __local_flush_dcache_page(struct page *page)
909 {
910 #ifdef DCACHE_ALIASING_POSSIBLE
911         __flush_dcache_page(page_address(page),
912                             ((tlb_type == spitfire) &&
913                              page_mapping(page) != NULL));
914 #else
915         if (page_mapping(page) != NULL &&
916             tlb_type == spitfire)
917                 __flush_icache_page(__pa(page_address(page)));
918 #endif
919 }
920
921 void smp_flush_dcache_page_impl(struct page *page, int cpu)
922 {
923         cpumask_t mask = cpumask_of_cpu(cpu);
924         int this_cpu;
925
926         if (tlb_type == hypervisor)
927                 return;
928
929 #ifdef CONFIG_DEBUG_DCFLUSH
930         atomic_inc(&dcpage_flushes);
931 #endif
932
933         this_cpu = get_cpu();
934
935         if (cpu == this_cpu) {
936                 __local_flush_dcache_page(page);
937         } else if (cpu_online(cpu)) {
938                 void *pg_addr = page_address(page);
939                 u64 data0;
940
941                 if (tlb_type == spitfire) {
942                         data0 =
943                                 ((u64)&xcall_flush_dcache_page_spitfire);
944                         if (page_mapping(page) != NULL)
945                                 data0 |= ((u64)1 << 32);
946                         spitfire_xcall_deliver(data0,
947                                                __pa(pg_addr),
948                                                (u64) pg_addr,
949                                                mask);
950                 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
951 #ifdef DCACHE_ALIASING_POSSIBLE
952                         data0 =
953                                 ((u64)&xcall_flush_dcache_page_cheetah);
954                         cheetah_xcall_deliver(data0,
955                                               __pa(pg_addr),
956                                               0, mask);
957 #endif
958                 }
959 #ifdef CONFIG_DEBUG_DCFLUSH
960                 atomic_inc(&dcpage_flushes_xcall);
961 #endif
962         }
963
964         put_cpu();
965 }
966
967 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
968 {
969         void *pg_addr = page_address(page);
970         cpumask_t mask = cpu_online_map;
971         u64 data0;
972         int this_cpu;
973
974         if (tlb_type == hypervisor)
975                 return;
976
977         this_cpu = get_cpu();
978
979         cpu_clear(this_cpu, mask);
980
981 #ifdef CONFIG_DEBUG_DCFLUSH
982         atomic_inc(&dcpage_flushes);
983 #endif
984         if (cpus_empty(mask))
985                 goto flush_self;
986         if (tlb_type == spitfire) {
987                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
988                 if (page_mapping(page) != NULL)
989                         data0 |= ((u64)1 << 32);
990                 spitfire_xcall_deliver(data0,
991                                        __pa(pg_addr),
992                                        (u64) pg_addr,
993                                        mask);
994         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
995 #ifdef DCACHE_ALIASING_POSSIBLE
996                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
997                 cheetah_xcall_deliver(data0,
998                                       __pa(pg_addr),
999                                       0, mask);
1000 #endif
1001         }
1002 #ifdef CONFIG_DEBUG_DCFLUSH
1003         atomic_inc(&dcpage_flushes_xcall);
1004 #endif
1005  flush_self:
1006         __local_flush_dcache_page(page);
1007
1008         put_cpu();
1009 }
1010
1011 static void __smp_receive_signal_mask(cpumask_t mask)
1012 {
1013         smp_cross_call_masked(&xcall_receive_signal, 0, 0, 0, mask);
1014 }
1015
1016 void smp_receive_signal(int cpu)
1017 {
1018         cpumask_t mask = cpumask_of_cpu(cpu);
1019
1020         if (cpu_online(cpu))
1021                 __smp_receive_signal_mask(mask);
1022 }
1023
1024 void smp_receive_signal_client(int irq, struct pt_regs *regs)
1025 {
1026         clear_softint(1 << irq);
1027 }
1028
1029 void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
1030 {
1031         struct mm_struct *mm;
1032         unsigned long flags;
1033
1034         clear_softint(1 << irq);
1035
1036         /* See if we need to allocate a new TLB context because
1037          * the version of the one we are using is now out of date.
1038          */
1039         mm = current->active_mm;
1040         if (unlikely(!mm || (mm == &init_mm)))
1041                 return;
1042
1043         spin_lock_irqsave(&mm->context.lock, flags);
1044
1045         if (unlikely(!CTX_VALID(mm->context)))
1046                 get_new_mmu_context(mm);
1047
1048         spin_unlock_irqrestore(&mm->context.lock, flags);
1049
1050         load_secondary_context(mm);
1051         __flush_tlb_mm(CTX_HWBITS(mm->context),
1052                        SECONDARY_CONTEXT);
1053 }
1054
1055 void smp_new_mmu_context_version(void)
1056 {
1057         smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
1058 }
1059
1060 void smp_report_regs(void)
1061 {
1062         smp_cross_call(&xcall_report_regs, 0, 0, 0);
1063 }
1064
1065 /* We know that the window frames of the user have been flushed
1066  * to the stack before we get here because all callers of us
1067  * are flush_tlb_*() routines, and these run after flush_cache_*()
1068  * which performs the flushw.
1069  *
1070  * The SMP TLB coherency scheme we use works as follows:
1071  *
1072  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1073  *    space has (potentially) executed on, this is the heuristic
1074  *    we use to avoid doing cross calls.
1075  *
1076  *    Also, for flushing from kswapd and also for clones, we
1077  *    use cpu_vm_mask as the list of cpus to make run the TLB.
1078  *
1079  * 2) TLB context numbers are shared globally across all processors
1080  *    in the system, this allows us to play several games to avoid
1081  *    cross calls.
1082  *
1083  *    One invariant is that when a cpu switches to a process, and
1084  *    that processes tsk->active_mm->cpu_vm_mask does not have the
1085  *    current cpu's bit set, that tlb context is flushed locally.
1086  *
1087  *    If the address space is non-shared (ie. mm->count == 1) we avoid
1088  *    cross calls when we want to flush the currently running process's
1089  *    tlb state.  This is done by clearing all cpu bits except the current
1090  *    processor's in current->active_mm->cpu_vm_mask and performing the
1091  *    flush locally only.  This will force any subsequent cpus which run
1092  *    this task to flush the context from the local tlb if the process
1093  *    migrates to another cpu (again).
1094  *
1095  * 3) For shared address spaces (threads) and swapping we bite the
1096  *    bullet for most cases and perform the cross call (but only to
1097  *    the cpus listed in cpu_vm_mask).
1098  *
1099  *    The performance gain from "optimizing" away the cross call for threads is
1100  *    questionable (in theory the big win for threads is the massive sharing of
1101  *    address space state across processors).
1102  */
1103
1104 /* This currently is only used by the hugetlb arch pre-fault
1105  * hook on UltraSPARC-III+ and later when changing the pagesize
1106  * bits of the context register for an address space.
1107  */
1108 void smp_flush_tlb_mm(struct mm_struct *mm)
1109 {
1110         u32 ctx = CTX_HWBITS(mm->context);
1111         int cpu = get_cpu();
1112
1113         if (atomic_read(&mm->mm_users) == 1) {
1114                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1115                 goto local_flush_and_out;
1116         }
1117
1118         smp_cross_call_masked(&xcall_flush_tlb_mm,
1119                               ctx, 0, 0,
1120                               mm->cpu_vm_mask);
1121
1122 local_flush_and_out:
1123         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1124
1125         put_cpu();
1126 }
1127
1128 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1129 {
1130         u32 ctx = CTX_HWBITS(mm->context);
1131         int cpu = get_cpu();
1132
1133         if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
1134                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1135         else
1136                 smp_cross_call_masked(&xcall_flush_tlb_pending,
1137                                       ctx, nr, (unsigned long) vaddrs,
1138                                       mm->cpu_vm_mask);
1139
1140         __flush_tlb_pending(ctx, nr, vaddrs);
1141
1142         put_cpu();
1143 }
1144
1145 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1146 {
1147         start &= PAGE_MASK;
1148         end    = PAGE_ALIGN(end);
1149         if (start != end) {
1150                 smp_cross_call(&xcall_flush_tlb_kernel_range,
1151                                0, start, end);
1152
1153                 __flush_tlb_kernel_range(start, end);
1154         }
1155 }
1156
1157 /* CPU capture. */
1158 /* #define CAPTURE_DEBUG */
1159 extern unsigned long xcall_capture;
1160
1161 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1162 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1163 static unsigned long penguins_are_doing_time;
1164
1165 void smp_capture(void)
1166 {
1167         int result = atomic_add_ret(1, &smp_capture_depth);
1168
1169         if (result == 1) {
1170                 int ncpus = num_online_cpus();
1171
1172 #ifdef CAPTURE_DEBUG
1173                 printk("CPU[%d]: Sending penguins to jail...",
1174                        smp_processor_id());
1175 #endif
1176                 penguins_are_doing_time = 1;
1177                 membar_storestore_loadstore();
1178                 atomic_inc(&smp_capture_registry);
1179                 smp_cross_call(&xcall_capture, 0, 0, 0);
1180                 while (atomic_read(&smp_capture_registry) != ncpus)
1181                         rmb();
1182 #ifdef CAPTURE_DEBUG
1183                 printk("done\n");
1184 #endif
1185         }
1186 }
1187
1188 void smp_release(void)
1189 {
1190         if (atomic_dec_and_test(&smp_capture_depth)) {
1191 #ifdef CAPTURE_DEBUG
1192                 printk("CPU[%d]: Giving pardon to "
1193                        "imprisoned penguins\n",
1194                        smp_processor_id());
1195 #endif
1196                 penguins_are_doing_time = 0;
1197                 membar_storeload_storestore();
1198                 atomic_dec(&smp_capture_registry);
1199         }
1200 }
1201
1202 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1203  * can service tlb flush xcalls...
1204  */
1205 extern void prom_world(int);
1206
1207 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1208 {
1209         clear_softint(1 << irq);
1210
1211         preempt_disable();
1212
1213         __asm__ __volatile__("flushw");
1214         prom_world(1);
1215         atomic_inc(&smp_capture_registry);
1216         membar_storeload_storestore();
1217         while (penguins_are_doing_time)
1218                 rmb();
1219         atomic_dec(&smp_capture_registry);
1220         prom_world(0);
1221
1222         preempt_enable();
1223 }
1224
1225 /* /proc/profile writes can call this, don't __init it please. */
1226 int setup_profiling_timer(unsigned int multiplier)
1227 {
1228         return -EINVAL;
1229 }
1230
1231 void __init smp_prepare_cpus(unsigned int max_cpus)
1232 {
1233 }
1234
1235 void __devinit smp_prepare_boot_cpu(void)
1236 {
1237 }
1238
1239 void __devinit smp_fill_in_sib_core_maps(void)
1240 {
1241         unsigned int i;
1242
1243         for_each_present_cpu(i) {
1244                 unsigned int j;
1245
1246                 cpus_clear(cpu_core_map[i]);
1247                 if (cpu_data(i).core_id == 0) {
1248                         cpu_set(i, cpu_core_map[i]);
1249                         continue;
1250                 }
1251
1252                 for_each_present_cpu(j) {
1253                         if (cpu_data(i).core_id ==
1254                             cpu_data(j).core_id)
1255                                 cpu_set(j, cpu_core_map[i]);
1256                 }
1257         }
1258
1259         for_each_present_cpu(i) {
1260                 unsigned int j;
1261
1262                 cpus_clear(cpu_sibling_map[i]);
1263                 if (cpu_data(i).proc_id == -1) {
1264                         cpu_set(i, cpu_sibling_map[i]);
1265                         continue;
1266                 }
1267
1268                 for_each_present_cpu(j) {
1269                         if (cpu_data(i).proc_id ==
1270                             cpu_data(j).proc_id)
1271                                 cpu_set(j, cpu_sibling_map[i]);
1272                 }
1273         }
1274 }
1275
1276 int __cpuinit __cpu_up(unsigned int cpu)
1277 {
1278         int ret = smp_boot_one_cpu(cpu);
1279
1280         if (!ret) {
1281                 cpu_set(cpu, smp_commenced_mask);
1282                 while (!cpu_isset(cpu, cpu_online_map))
1283                         mb();
1284                 if (!cpu_isset(cpu, cpu_online_map)) {
1285                         ret = -ENODEV;
1286                 } else {
1287                         /* On SUN4V, writes to %tick and %stick are
1288                          * not allowed.
1289                          */
1290                         if (tlb_type != hypervisor)
1291                                 smp_synchronize_one_tick(cpu);
1292                 }
1293         }
1294         return ret;
1295 }
1296
1297 #ifdef CONFIG_HOTPLUG_CPU
1298 void cpu_play_dead(void)
1299 {
1300         int cpu = smp_processor_id();
1301         unsigned long pstate;
1302
1303         idle_task_exit();
1304
1305         if (tlb_type == hypervisor) {
1306                 struct trap_per_cpu *tb = &trap_block[cpu];
1307
1308                 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
1309                                 tb->cpu_mondo_pa, 0);
1310                 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
1311                                 tb->dev_mondo_pa, 0);
1312                 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
1313                                 tb->resum_mondo_pa, 0);
1314                 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
1315                                 tb->nonresum_mondo_pa, 0);
1316         }
1317
1318         cpu_clear(cpu, smp_commenced_mask);
1319         membar_safe("#Sync");
1320
1321         local_irq_disable();
1322
1323         __asm__ __volatile__(
1324                 "rdpr   %%pstate, %0\n\t"
1325                 "wrpr   %0, %1, %%pstate"
1326                 : "=r" (pstate)
1327                 : "i" (PSTATE_IE));
1328
1329         while (1)
1330                 barrier();
1331 }
1332
1333 int __cpu_disable(void)
1334 {
1335         int cpu = smp_processor_id();
1336         cpuinfo_sparc *c;
1337         int i;
1338
1339         for_each_cpu_mask(i, cpu_core_map[cpu])
1340                 cpu_clear(cpu, cpu_core_map[i]);
1341         cpus_clear(cpu_core_map[cpu]);
1342
1343         for_each_cpu_mask(i, cpu_sibling_map[cpu])
1344                 cpu_clear(cpu, cpu_sibling_map[i]);
1345         cpus_clear(cpu_sibling_map[cpu]);
1346
1347         c = &cpu_data(cpu);
1348
1349         c->core_id = 0;
1350         c->proc_id = -1;
1351
1352         spin_lock(&call_lock);
1353         cpu_clear(cpu, cpu_online_map);
1354         spin_unlock(&call_lock);
1355
1356         smp_wmb();
1357
1358         /* Make sure no interrupts point to this cpu.  */
1359         fixup_irqs();
1360
1361         local_irq_enable();
1362         mdelay(1);
1363         local_irq_disable();
1364
1365         return 0;
1366 }
1367
1368 void __cpu_die(unsigned int cpu)
1369 {
1370         int i;
1371
1372         for (i = 0; i < 100; i++) {
1373                 smp_rmb();
1374                 if (!cpu_isset(cpu, smp_commenced_mask))
1375                         break;
1376                 msleep(100);
1377         }
1378         if (cpu_isset(cpu, smp_commenced_mask)) {
1379                 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1380         } else {
1381 #if defined(CONFIG_SUN_LDOMS)
1382                 unsigned long hv_err;
1383                 int limit = 100;
1384
1385                 do {
1386                         hv_err = sun4v_cpu_stop(cpu);
1387                         if (hv_err == HV_EOK) {
1388                                 cpu_clear(cpu, cpu_present_map);
1389                                 break;
1390                         }
1391                 } while (--limit > 0);
1392                 if (limit <= 0) {
1393                         printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
1394                                hv_err);
1395                 }
1396 #endif
1397         }
1398 }
1399 #endif
1400
1401 void __init smp_cpus_done(unsigned int max_cpus)
1402 {
1403 }
1404
1405 void smp_send_reschedule(int cpu)
1406 {
1407         smp_receive_signal(cpu);
1408 }
1409
1410 /* This is a nop because we capture all other cpus
1411  * anyways when making the PROM active.
1412  */
1413 void smp_send_stop(void)
1414 {
1415 }
1416
1417 unsigned long __per_cpu_base __read_mostly;
1418 unsigned long __per_cpu_shift __read_mostly;
1419
1420 EXPORT_SYMBOL(__per_cpu_base);
1421 EXPORT_SYMBOL(__per_cpu_shift);
1422
1423 void __init real_setup_per_cpu_areas(void)
1424 {
1425         unsigned long goal, size, i;
1426         char *ptr;
1427
1428         /* Copy section for each CPU (we discard the original) */
1429         goal = PERCPU_ENOUGH_ROOM;
1430
1431         __per_cpu_shift = PAGE_SHIFT;
1432         for (size = PAGE_SIZE; size < goal; size <<= 1UL)
1433                 __per_cpu_shift++;
1434
1435         ptr = alloc_bootmem_pages(size * NR_CPUS);
1436
1437         __per_cpu_base = ptr - __per_cpu_start;
1438
1439         for (i = 0; i < NR_CPUS; i++, ptr += size)
1440                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1441
1442         /* Setup %g5 for the boot cpu.  */
1443         __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1444 }