[SPARC64]: Dynamically grow TSB in response to RSS growth.
[linux-2.6.git] / arch / sparc64 / kernel / smp.c
1 /* smp.c: Sparc64 SMP support.
2  *
3  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
4  */
5
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <linux/mm.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/smp_lock.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/fs.h>
20 #include <linux/seq_file.h>
21 #include <linux/cache.h>
22 #include <linux/jiffies.h>
23 #include <linux/profile.h>
24 #include <linux/bootmem.h>
25
26 #include <asm/head.h>
27 #include <asm/ptrace.h>
28 #include <asm/atomic.h>
29 #include <asm/tlbflush.h>
30 #include <asm/mmu_context.h>
31 #include <asm/cpudata.h>
32
33 #include <asm/irq.h>
34 #include <asm/page.h>
35 #include <asm/pgtable.h>
36 #include <asm/oplib.h>
37 #include <asm/uaccess.h>
38 #include <asm/timer.h>
39 #include <asm/starfire.h>
40 #include <asm/tlb.h>
41 #include <asm/sections.h>
42
43 extern void calibrate_delay(void);
44
45 /* Please don't make this stuff initdata!!!  --DaveM */
46 static unsigned char boot_cpu_id;
47
48 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
49 cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE;
50 static cpumask_t smp_commenced_mask;
51 static cpumask_t cpu_callout_map;
52
53 void smp_info(struct seq_file *m)
54 {
55         int i;
56         
57         seq_printf(m, "State:\n");
58         for (i = 0; i < NR_CPUS; i++) {
59                 if (cpu_online(i))
60                         seq_printf(m,
61                                    "CPU%d:\t\tonline\n", i);
62         }
63 }
64
65 void smp_bogo(struct seq_file *m)
66 {
67         int i;
68         
69         for (i = 0; i < NR_CPUS; i++)
70                 if (cpu_online(i))
71                         seq_printf(m,
72                                    "Cpu%dBogo\t: %lu.%02lu\n"
73                                    "Cpu%dClkTck\t: %016lx\n",
74                                    i, cpu_data(i).udelay_val / (500000/HZ),
75                                    (cpu_data(i).udelay_val / (5000/HZ)) % 100,
76                                    i, cpu_data(i).clock_tick);
77 }
78
79 void __init smp_store_cpu_info(int id)
80 {
81         int cpu_node;
82
83         /* multiplier and counter set by
84            smp_setup_percpu_timer()  */
85         cpu_data(id).udelay_val                 = loops_per_jiffy;
86
87         cpu_find_by_mid(id, &cpu_node);
88         cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
89                                                      "clock-frequency", 0);
90
91         cpu_data(id).idle_volume                = 1;
92
93         cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size",
94                                                       16 * 1024);
95         cpu_data(id).dcache_line_size =
96                 prom_getintdefault(cpu_node, "dcache-line-size", 32);
97         cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size",
98                                                       16 * 1024);
99         cpu_data(id).icache_line_size =
100                 prom_getintdefault(cpu_node, "icache-line-size", 32);
101         cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size",
102                                                       4 * 1024 * 1024);
103         cpu_data(id).ecache_line_size =
104                 prom_getintdefault(cpu_node, "ecache-line-size", 64);
105         printk("CPU[%d]: Caches "
106                "D[sz(%d):line_sz(%d)] "
107                "I[sz(%d):line_sz(%d)] "
108                "E[sz(%d):line_sz(%d)]\n",
109                id,
110                cpu_data(id).dcache_size, cpu_data(id).dcache_line_size,
111                cpu_data(id).icache_size, cpu_data(id).icache_line_size,
112                cpu_data(id).ecache_size, cpu_data(id).ecache_line_size);
113 }
114
115 static void smp_setup_percpu_timer(void);
116
117 static volatile unsigned long callin_flag = 0;
118
119 extern void inherit_locked_prom_mappings(int save_p);
120
121 void __init smp_callin(void)
122 {
123         int cpuid = hard_smp_processor_id();
124
125         inherit_locked_prom_mappings(0);
126
127         __local_per_cpu_offset = __per_cpu_offset(cpuid);
128
129         __flush_tlb_all();
130
131         smp_setup_percpu_timer();
132
133         if (cheetah_pcache_forced_on)
134                 cheetah_enable_pcache();
135
136         local_irq_enable();
137
138         calibrate_delay();
139         smp_store_cpu_info(cpuid);
140         callin_flag = 1;
141         __asm__ __volatile__("membar #Sync\n\t"
142                              "flush  %%g6" : : : "memory");
143
144         /* Clear this or we will die instantly when we
145          * schedule back to this idler...
146          */
147         current_thread_info()->new_child = 0;
148
149         /* Attach to the address space of init_task. */
150         atomic_inc(&init_mm.mm_count);
151         current->active_mm = &init_mm;
152
153         while (!cpu_isset(cpuid, smp_commenced_mask))
154                 rmb();
155
156         cpu_set(cpuid, cpu_online_map);
157
158         /* idle thread is expected to have preempt disabled */
159         preempt_disable();
160 }
161
162 void cpu_panic(void)
163 {
164         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
165         panic("SMP bolixed\n");
166 }
167
168 static unsigned long current_tick_offset __read_mostly;
169
170 /* This tick register synchronization scheme is taken entirely from
171  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
172  *
173  * The only change I've made is to rework it so that the master
174  * initiates the synchonization instead of the slave. -DaveM
175  */
176
177 #define MASTER  0
178 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
179
180 #define NUM_ROUNDS      64      /* magic value */
181 #define NUM_ITERS       5       /* likewise */
182
183 static DEFINE_SPINLOCK(itc_sync_lock);
184 static unsigned long go[SLAVE + 1];
185
186 #define DEBUG_TICK_SYNC 0
187
188 static inline long get_delta (long *rt, long *master)
189 {
190         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
191         unsigned long tcenter, t0, t1, tm;
192         unsigned long i;
193
194         for (i = 0; i < NUM_ITERS; i++) {
195                 t0 = tick_ops->get_tick();
196                 go[MASTER] = 1;
197                 membar_storeload();
198                 while (!(tm = go[SLAVE]))
199                         rmb();
200                 go[SLAVE] = 0;
201                 wmb();
202                 t1 = tick_ops->get_tick();
203
204                 if (t1 - t0 < best_t1 - best_t0)
205                         best_t0 = t0, best_t1 = t1, best_tm = tm;
206         }
207
208         *rt = best_t1 - best_t0;
209         *master = best_tm - best_t0;
210
211         /* average best_t0 and best_t1 without overflow: */
212         tcenter = (best_t0/2 + best_t1/2);
213         if (best_t0 % 2 + best_t1 % 2 == 2)
214                 tcenter++;
215         return tcenter - best_tm;
216 }
217
218 void smp_synchronize_tick_client(void)
219 {
220         long i, delta, adj, adjust_latency = 0, done = 0;
221         unsigned long flags, rt, master_time_stamp, bound;
222 #if DEBUG_TICK_SYNC
223         struct {
224                 long rt;        /* roundtrip time */
225                 long master;    /* master's timestamp */
226                 long diff;      /* difference between midpoint and master's timestamp */
227                 long lat;       /* estimate of itc adjustment latency */
228         } t[NUM_ROUNDS];
229 #endif
230
231         go[MASTER] = 1;
232
233         while (go[MASTER])
234                 rmb();
235
236         local_irq_save(flags);
237         {
238                 for (i = 0; i < NUM_ROUNDS; i++) {
239                         delta = get_delta(&rt, &master_time_stamp);
240                         if (delta == 0) {
241                                 done = 1;       /* let's lock on to this... */
242                                 bound = rt;
243                         }
244
245                         if (!done) {
246                                 if (i > 0) {
247                                         adjust_latency += -delta;
248                                         adj = -delta + adjust_latency/4;
249                                 } else
250                                         adj = -delta;
251
252                                 tick_ops->add_tick(adj, current_tick_offset);
253                         }
254 #if DEBUG_TICK_SYNC
255                         t[i].rt = rt;
256                         t[i].master = master_time_stamp;
257                         t[i].diff = delta;
258                         t[i].lat = adjust_latency/4;
259 #endif
260                 }
261         }
262         local_irq_restore(flags);
263
264 #if DEBUG_TICK_SYNC
265         for (i = 0; i < NUM_ROUNDS; i++)
266                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
267                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
268 #endif
269
270         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
271                "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
272 }
273
274 static void smp_start_sync_tick_client(int cpu);
275
276 static void smp_synchronize_one_tick(int cpu)
277 {
278         unsigned long flags, i;
279
280         go[MASTER] = 0;
281
282         smp_start_sync_tick_client(cpu);
283
284         /* wait for client to be ready */
285         while (!go[MASTER])
286                 rmb();
287
288         /* now let the client proceed into his loop */
289         go[MASTER] = 0;
290         membar_storeload();
291
292         spin_lock_irqsave(&itc_sync_lock, flags);
293         {
294                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
295                         while (!go[MASTER])
296                                 rmb();
297                         go[MASTER] = 0;
298                         wmb();
299                         go[SLAVE] = tick_ops->get_tick();
300                         membar_storeload();
301                 }
302         }
303         spin_unlock_irqrestore(&itc_sync_lock, flags);
304 }
305
306 extern unsigned long sparc64_cpu_startup;
307
308 /* The OBP cpu startup callback truncates the 3rd arg cookie to
309  * 32-bits (I think) so to be safe we have it read the pointer
310  * contained here so we work on >4GB machines. -DaveM
311  */
312 static struct thread_info *cpu_new_thread = NULL;
313
314 static int __devinit smp_boot_one_cpu(unsigned int cpu)
315 {
316         unsigned long entry =
317                 (unsigned long)(&sparc64_cpu_startup);
318         unsigned long cookie =
319                 (unsigned long)(&cpu_new_thread);
320         struct task_struct *p;
321         int timeout, ret, cpu_node;
322
323         p = fork_idle(cpu);
324         callin_flag = 0;
325         cpu_new_thread = task_thread_info(p);
326         cpu_set(cpu, cpu_callout_map);
327
328         cpu_find_by_mid(cpu, &cpu_node);
329         prom_startcpu(cpu_node, entry, cookie);
330
331         for (timeout = 0; timeout < 5000000; timeout++) {
332                 if (callin_flag)
333                         break;
334                 udelay(100);
335         }
336         if (callin_flag) {
337                 ret = 0;
338         } else {
339                 printk("Processor %d is stuck.\n", cpu);
340                 cpu_clear(cpu, cpu_callout_map);
341                 ret = -ENODEV;
342         }
343         cpu_new_thread = NULL;
344
345         return ret;
346 }
347
348 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
349 {
350         u64 result, target;
351         int stuck, tmp;
352
353         if (this_is_starfire) {
354                 /* map to real upaid */
355                 cpu = (((cpu & 0x3c) << 1) |
356                         ((cpu & 0x40) >> 4) |
357                         (cpu & 0x3));
358         }
359
360         target = (cpu << 14) | 0x70;
361 again:
362         /* Ok, this is the real Spitfire Errata #54.
363          * One must read back from a UDB internal register
364          * after writes to the UDB interrupt dispatch, but
365          * before the membar Sync for that write.
366          * So we use the high UDB control register (ASI 0x7f,
367          * ADDR 0x20) for the dummy read. -DaveM
368          */
369         tmp = 0x40;
370         __asm__ __volatile__(
371         "wrpr   %1, %2, %%pstate\n\t"
372         "stxa   %4, [%0] %3\n\t"
373         "stxa   %5, [%0+%8] %3\n\t"
374         "add    %0, %8, %0\n\t"
375         "stxa   %6, [%0+%8] %3\n\t"
376         "membar #Sync\n\t"
377         "stxa   %%g0, [%7] %3\n\t"
378         "membar #Sync\n\t"
379         "mov    0x20, %%g1\n\t"
380         "ldxa   [%%g1] 0x7f, %%g0\n\t"
381         "membar #Sync"
382         : "=r" (tmp)
383         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
384           "r" (data0), "r" (data1), "r" (data2), "r" (target),
385           "r" (0x10), "0" (tmp)
386         : "g1");
387
388         /* NOTE: PSTATE_IE is still clear. */
389         stuck = 100000;
390         do {
391                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
392                         : "=r" (result)
393                         : "i" (ASI_INTR_DISPATCH_STAT));
394                 if (result == 0) {
395                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
396                                              : : "r" (pstate));
397                         return;
398                 }
399                 stuck -= 1;
400                 if (stuck == 0)
401                         break;
402         } while (result & 0x1);
403         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
404                              : : "r" (pstate));
405         if (stuck == 0) {
406                 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
407                        smp_processor_id(), result);
408         } else {
409                 udelay(2);
410                 goto again;
411         }
412 }
413
414 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
415 {
416         u64 pstate;
417         int i;
418
419         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
420         for_each_cpu_mask(i, mask)
421                 spitfire_xcall_helper(data0, data1, data2, pstate, i);
422 }
423
424 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
425  * packet, but we have no use for that.  However we do take advantage of
426  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
427  */
428 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
429 {
430         u64 pstate, ver;
431         int nack_busy_id, is_jalapeno;
432
433         if (cpus_empty(mask))
434                 return;
435
436         /* Unfortunately, someone at Sun had the brilliant idea to make the
437          * busy/nack fields hard-coded by ITID number for this Ultra-III
438          * derivative processor.
439          */
440         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
441         is_jalapeno = ((ver >> 32) == 0x003e0016);
442
443         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
444
445 retry:
446         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
447                              : : "r" (pstate), "i" (PSTATE_IE));
448
449         /* Setup the dispatch data registers. */
450         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
451                              "stxa      %1, [%4] %6\n\t"
452                              "stxa      %2, [%5] %6\n\t"
453                              "membar    #Sync\n\t"
454                              : /* no outputs */
455                              : "r" (data0), "r" (data1), "r" (data2),
456                                "r" (0x40), "r" (0x50), "r" (0x60),
457                                "i" (ASI_INTR_W));
458
459         nack_busy_id = 0;
460         {
461                 int i;
462
463                 for_each_cpu_mask(i, mask) {
464                         u64 target = (i << 14) | 0x70;
465
466                         if (!is_jalapeno)
467                                 target |= (nack_busy_id << 24);
468                         __asm__ __volatile__(
469                                 "stxa   %%g0, [%0] %1\n\t"
470                                 "membar #Sync\n\t"
471                                 : /* no outputs */
472                                 : "r" (target), "i" (ASI_INTR_W));
473                         nack_busy_id++;
474                 }
475         }
476
477         /* Now, poll for completion. */
478         {
479                 u64 dispatch_stat;
480                 long stuck;
481
482                 stuck = 100000 * nack_busy_id;
483                 do {
484                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
485                                              : "=r" (dispatch_stat)
486                                              : "i" (ASI_INTR_DISPATCH_STAT));
487                         if (dispatch_stat == 0UL) {
488                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
489                                                      : : "r" (pstate));
490                                 return;
491                         }
492                         if (!--stuck)
493                                 break;
494                 } while (dispatch_stat & 0x5555555555555555UL);
495
496                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
497                                      : : "r" (pstate));
498
499                 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
500                         /* Busy bits will not clear, continue instead
501                          * of freezing up on this cpu.
502                          */
503                         printk("CPU[%d]: mondo stuckage result[%016lx]\n",
504                                smp_processor_id(), dispatch_stat);
505                 } else {
506                         int i, this_busy_nack = 0;
507
508                         /* Delay some random time with interrupts enabled
509                          * to prevent deadlock.
510                          */
511                         udelay(2 * nack_busy_id);
512
513                         /* Clear out the mask bits for cpus which did not
514                          * NACK us.
515                          */
516                         for_each_cpu_mask(i, mask) {
517                                 u64 check_mask;
518
519                                 if (is_jalapeno)
520                                         check_mask = (0x2UL << (2*i));
521                                 else
522                                         check_mask = (0x2UL <<
523                                                       this_busy_nack);
524                                 if ((dispatch_stat & check_mask) == 0)
525                                         cpu_clear(i, mask);
526                                 this_busy_nack += 2;
527                         }
528
529                         goto retry;
530                 }
531         }
532 }
533
534 /* Send cross call to all processors mentioned in MASK
535  * except self.
536  */
537 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
538 {
539         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
540         int this_cpu = get_cpu();
541
542         cpus_and(mask, mask, cpu_online_map);
543         cpu_clear(this_cpu, mask);
544
545         if (tlb_type == spitfire)
546                 spitfire_xcall_deliver(data0, data1, data2, mask);
547         else
548                 cheetah_xcall_deliver(data0, data1, data2, mask);
549         /* NOTE: Caller runs local copy on master. */
550
551         put_cpu();
552 }
553
554 extern unsigned long xcall_sync_tick;
555
556 static void smp_start_sync_tick_client(int cpu)
557 {
558         cpumask_t mask = cpumask_of_cpu(cpu);
559
560         smp_cross_call_masked(&xcall_sync_tick,
561                               0, 0, 0, mask);
562 }
563
564 /* Send cross call to all processors except self. */
565 #define smp_cross_call(func, ctx, data1, data2) \
566         smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
567
568 struct call_data_struct {
569         void (*func) (void *info);
570         void *info;
571         atomic_t finished;
572         int wait;
573 };
574
575 static DEFINE_SPINLOCK(call_lock);
576 static struct call_data_struct *call_data;
577
578 extern unsigned long xcall_call_function;
579
580 /*
581  * You must not call this function with disabled interrupts or from a
582  * hardware interrupt handler or from a bottom half handler.
583  */
584 static int smp_call_function_mask(void (*func)(void *info), void *info,
585                                   int nonatomic, int wait, cpumask_t mask)
586 {
587         struct call_data_struct data;
588         int cpus = cpus_weight(mask) - 1;
589         long timeout;
590
591         if (!cpus)
592                 return 0;
593
594         /* Can deadlock when called with interrupts disabled */
595         WARN_ON(irqs_disabled());
596
597         data.func = func;
598         data.info = info;
599         atomic_set(&data.finished, 0);
600         data.wait = wait;
601
602         spin_lock(&call_lock);
603
604         call_data = &data;
605
606         smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
607
608         /* 
609          * Wait for other cpus to complete function or at
610          * least snap the call data.
611          */
612         timeout = 1000000;
613         while (atomic_read(&data.finished) != cpus) {
614                 if (--timeout <= 0)
615                         goto out_timeout;
616                 barrier();
617                 udelay(1);
618         }
619
620         spin_unlock(&call_lock);
621
622         return 0;
623
624 out_timeout:
625         spin_unlock(&call_lock);
626         printk("XCALL: Remote cpus not responding, ncpus=%ld finished=%ld\n",
627                (long) num_online_cpus() - 1L,
628                (long) atomic_read(&data.finished));
629         return 0;
630 }
631
632 int smp_call_function(void (*func)(void *info), void *info,
633                       int nonatomic, int wait)
634 {
635         return smp_call_function_mask(func, info, nonatomic, wait,
636                                       cpu_online_map);
637 }
638
639 void smp_call_function_client(int irq, struct pt_regs *regs)
640 {
641         void (*func) (void *info) = call_data->func;
642         void *info = call_data->info;
643
644         clear_softint(1 << irq);
645         if (call_data->wait) {
646                 /* let initiator proceed only after completion */
647                 func(info);
648                 atomic_inc(&call_data->finished);
649         } else {
650                 /* let initiator proceed after getting data */
651                 atomic_inc(&call_data->finished);
652                 func(info);
653         }
654 }
655
656 static void tsb_sync(void *info)
657 {
658         struct mm_struct *mm = info;
659
660         if (current->active_mm == mm)
661                 tsb_context_switch(mm);
662 }
663
664 void smp_tsb_sync(struct mm_struct *mm)
665 {
666         smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask);
667 }
668
669 extern unsigned long xcall_flush_tlb_mm;
670 extern unsigned long xcall_flush_tlb_pending;
671 extern unsigned long xcall_flush_tlb_kernel_range;
672 extern unsigned long xcall_report_regs;
673 extern unsigned long xcall_receive_signal;
674
675 #ifdef DCACHE_ALIASING_POSSIBLE
676 extern unsigned long xcall_flush_dcache_page_cheetah;
677 #endif
678 extern unsigned long xcall_flush_dcache_page_spitfire;
679
680 #ifdef CONFIG_DEBUG_DCFLUSH
681 extern atomic_t dcpage_flushes;
682 extern atomic_t dcpage_flushes_xcall;
683 #endif
684
685 static __inline__ void __local_flush_dcache_page(struct page *page)
686 {
687 #ifdef DCACHE_ALIASING_POSSIBLE
688         __flush_dcache_page(page_address(page),
689                             ((tlb_type == spitfire) &&
690                              page_mapping(page) != NULL));
691 #else
692         if (page_mapping(page) != NULL &&
693             tlb_type == spitfire)
694                 __flush_icache_page(__pa(page_address(page)));
695 #endif
696 }
697
698 void smp_flush_dcache_page_impl(struct page *page, int cpu)
699 {
700         cpumask_t mask = cpumask_of_cpu(cpu);
701         int this_cpu = get_cpu();
702
703 #ifdef CONFIG_DEBUG_DCFLUSH
704         atomic_inc(&dcpage_flushes);
705 #endif
706         if (cpu == this_cpu) {
707                 __local_flush_dcache_page(page);
708         } else if (cpu_online(cpu)) {
709                 void *pg_addr = page_address(page);
710                 u64 data0;
711
712                 if (tlb_type == spitfire) {
713                         data0 =
714                                 ((u64)&xcall_flush_dcache_page_spitfire);
715                         if (page_mapping(page) != NULL)
716                                 data0 |= ((u64)1 << 32);
717                         spitfire_xcall_deliver(data0,
718                                                __pa(pg_addr),
719                                                (u64) pg_addr,
720                                                mask);
721                 } else {
722 #ifdef DCACHE_ALIASING_POSSIBLE
723                         data0 =
724                                 ((u64)&xcall_flush_dcache_page_cheetah);
725                         cheetah_xcall_deliver(data0,
726                                               __pa(pg_addr),
727                                               0, mask);
728 #endif
729                 }
730 #ifdef CONFIG_DEBUG_DCFLUSH
731                 atomic_inc(&dcpage_flushes_xcall);
732 #endif
733         }
734
735         put_cpu();
736 }
737
738 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
739 {
740         void *pg_addr = page_address(page);
741         cpumask_t mask = cpu_online_map;
742         u64 data0;
743         int this_cpu = get_cpu();
744
745         cpu_clear(this_cpu, mask);
746
747 #ifdef CONFIG_DEBUG_DCFLUSH
748         atomic_inc(&dcpage_flushes);
749 #endif
750         if (cpus_empty(mask))
751                 goto flush_self;
752         if (tlb_type == spitfire) {
753                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
754                 if (page_mapping(page) != NULL)
755                         data0 |= ((u64)1 << 32);
756                 spitfire_xcall_deliver(data0,
757                                        __pa(pg_addr),
758                                        (u64) pg_addr,
759                                        mask);
760         } else {
761 #ifdef DCACHE_ALIASING_POSSIBLE
762                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
763                 cheetah_xcall_deliver(data0,
764                                       __pa(pg_addr),
765                                       0, mask);
766 #endif
767         }
768 #ifdef CONFIG_DEBUG_DCFLUSH
769         atomic_inc(&dcpage_flushes_xcall);
770 #endif
771  flush_self:
772         __local_flush_dcache_page(page);
773
774         put_cpu();
775 }
776
777 void smp_receive_signal(int cpu)
778 {
779         cpumask_t mask = cpumask_of_cpu(cpu);
780
781         if (cpu_online(cpu)) {
782                 u64 data0 = (((u64)&xcall_receive_signal) & 0xffffffff);
783
784                 if (tlb_type == spitfire)
785                         spitfire_xcall_deliver(data0, 0, 0, mask);
786                 else
787                         cheetah_xcall_deliver(data0, 0, 0, mask);
788         }
789 }
790
791 void smp_receive_signal_client(int irq, struct pt_regs *regs)
792 {
793         /* Just return, rtrap takes care of the rest. */
794         clear_softint(1 << irq);
795 }
796
797 void smp_report_regs(void)
798 {
799         smp_cross_call(&xcall_report_regs, 0, 0, 0);
800 }
801
802 /* We know that the window frames of the user have been flushed
803  * to the stack before we get here because all callers of us
804  * are flush_tlb_*() routines, and these run after flush_cache_*()
805  * which performs the flushw.
806  *
807  * The SMP TLB coherency scheme we use works as follows:
808  *
809  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
810  *    space has (potentially) executed on, this is the heuristic
811  *    we use to avoid doing cross calls.
812  *
813  *    Also, for flushing from kswapd and also for clones, we
814  *    use cpu_vm_mask as the list of cpus to make run the TLB.
815  *
816  * 2) TLB context numbers are shared globally across all processors
817  *    in the system, this allows us to play several games to avoid
818  *    cross calls.
819  *
820  *    One invariant is that when a cpu switches to a process, and
821  *    that processes tsk->active_mm->cpu_vm_mask does not have the
822  *    current cpu's bit set, that tlb context is flushed locally.
823  *
824  *    If the address space is non-shared (ie. mm->count == 1) we avoid
825  *    cross calls when we want to flush the currently running process's
826  *    tlb state.  This is done by clearing all cpu bits except the current
827  *    processor's in current->active_mm->cpu_vm_mask and performing the
828  *    flush locally only.  This will force any subsequent cpus which run
829  *    this task to flush the context from the local tlb if the process
830  *    migrates to another cpu (again).
831  *
832  * 3) For shared address spaces (threads) and swapping we bite the
833  *    bullet for most cases and perform the cross call (but only to
834  *    the cpus listed in cpu_vm_mask).
835  *
836  *    The performance gain from "optimizing" away the cross call for threads is
837  *    questionable (in theory the big win for threads is the massive sharing of
838  *    address space state across processors).
839  */
840
841 /* This currently is only used by the hugetlb arch pre-fault
842  * hook on UltraSPARC-III+ and later when changing the pagesize
843  * bits of the context register for an address space.
844  */
845 void smp_flush_tlb_mm(struct mm_struct *mm)
846 {
847         u32 ctx = CTX_HWBITS(mm->context);
848         int cpu = get_cpu();
849
850         if (atomic_read(&mm->mm_users) == 1) {
851                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
852                 goto local_flush_and_out;
853         }
854
855         smp_cross_call_masked(&xcall_flush_tlb_mm,
856                               ctx, 0, 0,
857                               mm->cpu_vm_mask);
858
859 local_flush_and_out:
860         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
861
862         put_cpu();
863 }
864
865 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
866 {
867         u32 ctx = CTX_HWBITS(mm->context);
868         int cpu = get_cpu();
869
870         if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
871                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
872         else
873                 smp_cross_call_masked(&xcall_flush_tlb_pending,
874                                       ctx, nr, (unsigned long) vaddrs,
875                                       mm->cpu_vm_mask);
876
877         __flush_tlb_pending(ctx, nr, vaddrs);
878
879         put_cpu();
880 }
881
882 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
883 {
884         start &= PAGE_MASK;
885         end    = PAGE_ALIGN(end);
886         if (start != end) {
887                 smp_cross_call(&xcall_flush_tlb_kernel_range,
888                                0, start, end);
889
890                 __flush_tlb_kernel_range(start, end);
891         }
892 }
893
894 /* CPU capture. */
895 /* #define CAPTURE_DEBUG */
896 extern unsigned long xcall_capture;
897
898 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
899 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
900 static unsigned long penguins_are_doing_time;
901
902 void smp_capture(void)
903 {
904         int result = atomic_add_ret(1, &smp_capture_depth);
905
906         if (result == 1) {
907                 int ncpus = num_online_cpus();
908
909 #ifdef CAPTURE_DEBUG
910                 printk("CPU[%d]: Sending penguins to jail...",
911                        smp_processor_id());
912 #endif
913                 penguins_are_doing_time = 1;
914                 membar_storestore_loadstore();
915                 atomic_inc(&smp_capture_registry);
916                 smp_cross_call(&xcall_capture, 0, 0, 0);
917                 while (atomic_read(&smp_capture_registry) != ncpus)
918                         rmb();
919 #ifdef CAPTURE_DEBUG
920                 printk("done\n");
921 #endif
922         }
923 }
924
925 void smp_release(void)
926 {
927         if (atomic_dec_and_test(&smp_capture_depth)) {
928 #ifdef CAPTURE_DEBUG
929                 printk("CPU[%d]: Giving pardon to "
930                        "imprisoned penguins\n",
931                        smp_processor_id());
932 #endif
933                 penguins_are_doing_time = 0;
934                 membar_storeload_storestore();
935                 atomic_dec(&smp_capture_registry);
936         }
937 }
938
939 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
940  * can service tlb flush xcalls...
941  */
942 extern void prom_world(int);
943 extern void save_alternate_globals(unsigned long *);
944 extern void restore_alternate_globals(unsigned long *);
945 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
946 {
947         unsigned long global_save[24];
948
949         clear_softint(1 << irq);
950
951         preempt_disable();
952
953         __asm__ __volatile__("flushw");
954         save_alternate_globals(global_save);
955         prom_world(1);
956         atomic_inc(&smp_capture_registry);
957         membar_storeload_storestore();
958         while (penguins_are_doing_time)
959                 rmb();
960         restore_alternate_globals(global_save);
961         atomic_dec(&smp_capture_registry);
962         prom_world(0);
963
964         preempt_enable();
965 }
966
967 #define prof_multiplier(__cpu)          cpu_data(__cpu).multiplier
968 #define prof_counter(__cpu)             cpu_data(__cpu).counter
969
970 void smp_percpu_timer_interrupt(struct pt_regs *regs)
971 {
972         unsigned long compare, tick, pstate;
973         int cpu = smp_processor_id();
974         int user = user_mode(regs);
975
976         /*
977          * Check for level 14 softint.
978          */
979         {
980                 unsigned long tick_mask = tick_ops->softint_mask;
981
982                 if (!(get_softint() & tick_mask)) {
983                         extern void handler_irq(int, struct pt_regs *);
984
985                         handler_irq(14, regs);
986                         return;
987                 }
988                 clear_softint(tick_mask);
989         }
990
991         do {
992                 profile_tick(CPU_PROFILING, regs);
993                 if (!--prof_counter(cpu)) {
994                         irq_enter();
995
996                         if (cpu == boot_cpu_id) {
997                                 kstat_this_cpu.irqs[0]++;
998                                 timer_tick_interrupt(regs);
999                         }
1000
1001                         update_process_times(user);
1002
1003                         irq_exit();
1004
1005                         prof_counter(cpu) = prof_multiplier(cpu);
1006                 }
1007
1008                 /* Guarantee that the following sequences execute
1009                  * uninterrupted.
1010                  */
1011                 __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
1012                                      "wrpr      %0, %1, %%pstate"
1013                                      : "=r" (pstate)
1014                                      : "i" (PSTATE_IE));
1015
1016                 compare = tick_ops->add_compare(current_tick_offset);
1017                 tick = tick_ops->get_tick();
1018
1019                 /* Restore PSTATE_IE. */
1020                 __asm__ __volatile__("wrpr      %0, 0x0, %%pstate"
1021                                      : /* no outputs */
1022                                      : "r" (pstate));
1023         } while (time_after_eq(tick, compare));
1024 }
1025
1026 static void __init smp_setup_percpu_timer(void)
1027 {
1028         int cpu = smp_processor_id();
1029         unsigned long pstate;
1030
1031         prof_counter(cpu) = prof_multiplier(cpu) = 1;
1032
1033         /* Guarantee that the following sequences execute
1034          * uninterrupted.
1035          */
1036         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
1037                              "wrpr      %0, %1, %%pstate"
1038                              : "=r" (pstate)
1039                              : "i" (PSTATE_IE));
1040
1041         tick_ops->init_tick(current_tick_offset);
1042
1043         /* Restore PSTATE_IE. */
1044         __asm__ __volatile__("wrpr      %0, 0x0, %%pstate"
1045                              : /* no outputs */
1046                              : "r" (pstate));
1047 }
1048
1049 void __init smp_tick_init(void)
1050 {
1051         boot_cpu_id = hard_smp_processor_id();
1052         current_tick_offset = timer_tick_offset;
1053
1054         cpu_set(boot_cpu_id, cpu_online_map);
1055         prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1;
1056 }
1057
1058 /* /proc/profile writes can call this, don't __init it please. */
1059 static DEFINE_SPINLOCK(prof_setup_lock);
1060
1061 int setup_profiling_timer(unsigned int multiplier)
1062 {
1063         unsigned long flags;
1064         int i;
1065
1066         if ((!multiplier) || (timer_tick_offset / multiplier) < 1000)
1067                 return -EINVAL;
1068
1069         spin_lock_irqsave(&prof_setup_lock, flags);
1070         for (i = 0; i < NR_CPUS; i++)
1071                 prof_multiplier(i) = multiplier;
1072         current_tick_offset = (timer_tick_offset / multiplier);
1073         spin_unlock_irqrestore(&prof_setup_lock, flags);
1074
1075         return 0;
1076 }
1077
1078 /* Constrain the number of cpus to max_cpus.  */
1079 void __init smp_prepare_cpus(unsigned int max_cpus)
1080 {
1081         if (num_possible_cpus() > max_cpus) {
1082                 int instance, mid;
1083
1084                 instance = 0;
1085                 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1086                         if (mid != boot_cpu_id) {
1087                                 cpu_clear(mid, phys_cpu_present_map);
1088                                 if (num_possible_cpus() <= max_cpus)
1089                                         break;
1090                         }
1091                         instance++;
1092                 }
1093         }
1094
1095         smp_store_cpu_info(boot_cpu_id);
1096 }
1097
1098 /* Set this up early so that things like the scheduler can init
1099  * properly.  We use the same cpu mask for both the present and
1100  * possible cpu map.
1101  */
1102 void __init smp_setup_cpu_possible_map(void)
1103 {
1104         int instance, mid;
1105
1106         instance = 0;
1107         while (!cpu_find_by_instance(instance, NULL, &mid)) {
1108                 if (mid < NR_CPUS)
1109                         cpu_set(mid, phys_cpu_present_map);
1110                 instance++;
1111         }
1112 }
1113
1114 void __devinit smp_prepare_boot_cpu(void)
1115 {
1116         int cpu = hard_smp_processor_id();
1117
1118         if (cpu >= NR_CPUS) {
1119                 prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
1120                 prom_halt();
1121         }
1122
1123         current_thread_info()->cpu = cpu;
1124         __local_per_cpu_offset = __per_cpu_offset(cpu);
1125
1126         cpu_set(smp_processor_id(), cpu_online_map);
1127         cpu_set(smp_processor_id(), phys_cpu_present_map);
1128 }
1129
1130 int __devinit __cpu_up(unsigned int cpu)
1131 {
1132         int ret = smp_boot_one_cpu(cpu);
1133
1134         if (!ret) {
1135                 cpu_set(cpu, smp_commenced_mask);
1136                 while (!cpu_isset(cpu, cpu_online_map))
1137                         mb();
1138                 if (!cpu_isset(cpu, cpu_online_map)) {
1139                         ret = -ENODEV;
1140                 } else {
1141                         smp_synchronize_one_tick(cpu);
1142                 }
1143         }
1144         return ret;
1145 }
1146
1147 void __init smp_cpus_done(unsigned int max_cpus)
1148 {
1149         unsigned long bogosum = 0;
1150         int i;
1151
1152         for (i = 0; i < NR_CPUS; i++) {
1153                 if (cpu_online(i))
1154                         bogosum += cpu_data(i).udelay_val;
1155         }
1156         printk("Total of %ld processors activated "
1157                "(%lu.%02lu BogoMIPS).\n",
1158                (long) num_online_cpus(),
1159                bogosum/(500000/HZ),
1160                (bogosum/(5000/HZ))%100);
1161 }
1162
1163 void smp_send_reschedule(int cpu)
1164 {
1165         smp_receive_signal(cpu);
1166 }
1167
1168 /* This is a nop because we capture all other cpus
1169  * anyways when making the PROM active.
1170  */
1171 void smp_send_stop(void)
1172 {
1173 }
1174
1175 unsigned long __per_cpu_base __read_mostly;
1176 unsigned long __per_cpu_shift __read_mostly;
1177
1178 EXPORT_SYMBOL(__per_cpu_base);
1179 EXPORT_SYMBOL(__per_cpu_shift);
1180
1181 void __init setup_per_cpu_areas(void)
1182 {
1183         unsigned long goal, size, i;
1184         char *ptr;
1185
1186         /* Copy section for each CPU (we discard the original) */
1187         goal = ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES);
1188 #ifdef CONFIG_MODULES
1189         if (goal < PERCPU_ENOUGH_ROOM)
1190                 goal = PERCPU_ENOUGH_ROOM;
1191 #endif
1192         __per_cpu_shift = 0;
1193         for (size = 1UL; size < goal; size <<= 1UL)
1194                 __per_cpu_shift++;
1195
1196         ptr = alloc_bootmem(size * NR_CPUS);
1197
1198         __per_cpu_base = ptr - __per_cpu_start;
1199
1200         for (i = 0; i < NR_CPUS; i++, ptr += size)
1201                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1202 }