sh: Add SH7723 SCIF support
[linux-2.6.git] / arch / sh / kernel / cpu / sh4a / setup-sh7723.c
1 /*
2  * SH7723 Setup
3  *
4  *  Copyright (C) 2008  Paul Mundt
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License.  See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/mm.h>
14 #include <linux/serial_sci.h>
15 #include <asm/mmzone.h>
16
17 static struct plat_sci_port sci_platform_data[] = {
18         {
19                 .mapbase        = 0xffe00000,
20                 .flags          = UPF_BOOT_AUTOCONF,
21                 .type           = PORT_SCIF,
22                 .irqs           = { 80, 80, 80, 80 },
23         },{
24                 .mapbase        = 0xffe10000,
25                 .flags          = UPF_BOOT_AUTOCONF,
26                 .type           = PORT_SCIF,
27                 .irqs           = { 81, 81, 81, 81 },
28         },{
29                 .mapbase        = 0xffe20000,
30                 .flags          = UPF_BOOT_AUTOCONF,
31                 .type           = PORT_SCIF,
32                 .irqs           = { 82, 82, 82, 82 },
33         },{
34                 .mapbase        = 0xa4e30000,
35                 .flags          = UPF_BOOT_AUTOCONF,
36                 .type           = PORT_SCI,
37                 .irqs           = { 56, 56, 56, 56 },
38         },{
39                 .mapbase        = 0xa4e40000,
40                 .flags          = UPF_BOOT_AUTOCONF,
41                 .type           = PORT_SCI,
42                 .irqs           = { 88, 88, 88, 88 },
43         },{
44                 .mapbase        = 0xa4e50000,
45                 .flags          = UPF_BOOT_AUTOCONF,
46                 .type           = PORT_SCI,
47                 .irqs           = { 109, 109, 109, 109 },
48         }, {
49                 .flags = 0,
50         }
51 };
52
53 static struct platform_device sci_device = {
54         .name           = "sh-sci",
55         .id             = -1,
56         .dev            = {
57                 .platform_data  = sci_platform_data,
58         },
59 };
60
61 static struct resource rtc_resources[] = {
62         [0] = {
63                 .start  = 0xa465fec0,
64                 .end    = 0xa465fec0 + 0x58 - 1,
65                 .flags  = IORESOURCE_IO,
66         },
67         [1] = {
68                 /* Period IRQ */
69                 .start  = 69,
70                 .flags  = IORESOURCE_IRQ,
71         },
72         [2] = {
73                 /* Carry IRQ */
74                 .start  = 70,
75                 .flags  = IORESOURCE_IRQ,
76         },
77         [3] = {
78                 /* Alarm IRQ */
79                 .start  = 68,
80                 .flags  = IORESOURCE_IRQ,
81         },
82 };
83
84 static struct platform_device rtc_device = {
85         .name           = "sh-rtc",
86         .id             = -1,
87         .num_resources  = ARRAY_SIZE(rtc_resources),
88         .resource       = rtc_resources,
89 };
90
91 static struct platform_device *sh7723_devices[] __initdata = {
92         &sci_device,
93         &rtc_device,
94 };
95
96 static int __init sh7723_devices_setup(void)
97 {
98         return platform_add_devices(sh7723_devices,
99                                     ARRAY_SIZE(sh7723_devices));
100 }
101 __initcall(sh7723_devices_setup);
102
103 enum {
104         UNUSED=0,
105
106         /* interrupt sources */
107         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
108         HUDI,
109         DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
110         _2DG_TRI,_2DG_INI,_2DG_CEI,
111         DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
112         VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
113         SCIFA_SCIFA0,
114         VPU_VPUI,
115         TPU_TPUI,
116         ADC_ADI,
117         USB_USI0,
118         RTC_ATI,RTC_PRI,RTC_CUI,
119         DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
120         DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
121         KEYSC_KEYI,
122         SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
123         MSIOF_MSIOFI0,MSIOF_MSIOFI1,
124         SCIFA_SCIFA1,
125         FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
126         I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
127         SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
128         CMT_CMTI,
129         TSIF_TSIFI,
130         SIU_SIUI,
131         SCIFA_SCIFA2,
132         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
133         IRDA_IRDAI,
134         ATAPI_ATAPII,
135         SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
136         VEU2H1_VEU2HI,
137         LCDC_LCDCI,
138         TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
139
140         /* interrupt groups */
141         DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
142         SDHI1, RTC, DMAC1B, SDHI0,
143 };
144
145 static struct intc_vect vectors[] __initdata = {
146         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
147         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
148         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
149         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
150
151         INTC_VECT(DMAC1A_DEI0,0x700),
152         INTC_VECT(DMAC1A_DEI1,0x720),
153         INTC_VECT(DMAC1A_DEI2,0x740),
154         INTC_VECT(DMAC1A_DEI3,0x760),
155
156         INTC_VECT(_2DG_TRI, 0x780),
157         INTC_VECT(_2DG_INI, 0x7A0),
158         INTC_VECT(_2DG_CEI, 0x7C0),
159
160         INTC_VECT(DMAC0A_DEI0,0x800),
161         INTC_VECT(DMAC0A_DEI1,0x820),
162         INTC_VECT(DMAC0A_DEI2,0x840),
163         INTC_VECT(DMAC0A_DEI3,0x860),
164
165         INTC_VECT(VIO_CEUI,0x880),
166         INTC_VECT(VIO_BEUI,0x8A0),
167         INTC_VECT(VIO_VEU2HI,0x8C0),
168         INTC_VECT(VIO_VOUI,0x8E0),
169
170         INTC_VECT(SCIFA_SCIFA0,0x900),
171         INTC_VECT(VPU_VPUI,0x980),
172         INTC_VECT(TPU_TPUI,0x9A0),
173         INTC_VECT(ADC_ADI,0x9E0),
174         INTC_VECT(USB_USI0,0xA20),
175
176         INTC_VECT(RTC_ATI,0xA80),
177         INTC_VECT(RTC_PRI,0xAA0),
178         INTC_VECT(RTC_CUI,0xAC0),
179
180         INTC_VECT(DMAC1B_DEI4,0xB00),
181         INTC_VECT(DMAC1B_DEI5,0xB20),
182         INTC_VECT(DMAC1B_DADERR,0xB40),
183
184         INTC_VECT(DMAC0B_DEI4,0xB80),
185         INTC_VECT(DMAC0B_DEI5,0xBA0),
186         INTC_VECT(DMAC0B_DADERR,0xBC0),
187
188         INTC_VECT(KEYSC_KEYI,0xBE0),
189         INTC_VECT(SCIF_SCIF0,0xC00),
190         INTC_VECT(SCIF_SCIF1,0xC20),
191         INTC_VECT(SCIF_SCIF2,0xC40),
192         INTC_VECT(MSIOF_MSIOFI0,0xC80),
193         INTC_VECT(MSIOF_MSIOFI1,0xCA0),
194         INTC_VECT(SCIFA_SCIFA1,0xD00),
195
196         INTC_VECT(FLCTL_FLSTEI,0xD80),
197         INTC_VECT(FLCTL_FLTENDI,0xDA0),
198         INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
199         INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
200
201         INTC_VECT(I2C_ALI,0xE00),
202         INTC_VECT(I2C_TACKI,0xE20),
203         INTC_VECT(I2C_WAITI,0xE40),
204         INTC_VECT(I2C_DTEI,0xE60),
205
206         INTC_VECT(SDHI0_SDHII0,0xE80),
207         INTC_VECT(SDHI0_SDHII1,0xEA0),
208         INTC_VECT(SDHI0_SDHII2,0xEC0),
209
210         INTC_VECT(CMT_CMTI,0xF00),
211         INTC_VECT(TSIF_TSIFI,0xF20),
212         INTC_VECT(SIU_SIUI,0xF80),
213         INTC_VECT(SCIFA_SCIFA2,0xFA0),
214
215         INTC_VECT(TMU0_TUNI0,0x400),
216         INTC_VECT(TMU0_TUNI1,0x420),
217         INTC_VECT(TMU0_TUNI2,0x440),
218
219         INTC_VECT(IRDA_IRDAI,0x480),
220         INTC_VECT(ATAPI_ATAPII,0x4A0),
221
222         INTC_VECT(SDHI1_SDHII0,0x4E0),
223         INTC_VECT(SDHI1_SDHII1,0x500),
224         INTC_VECT(SDHI1_SDHII2,0x520),
225
226         INTC_VECT(VEU2H1_VEU2HI,0x560),
227         INTC_VECT(LCDC_LCDCI,0x580),
228
229         INTC_VECT(TMU1_TUNI0,0x920),
230         INTC_VECT(TMU1_TUNI1,0x940),
231         INTC_VECT(TMU1_TUNI2,0x960),
232
233 };
234
235 static struct intc_group groups[] __initdata = {
236         INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
237         INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
238         INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
239         INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
240         INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
241         INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
242         INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
243         INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
244         INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
245         INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
246         INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
247 };
248
249 static struct intc_mask_reg mask_registers[] __initdata = {
250         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
251           { 0,  TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
252         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
253           { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
254         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
255           { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
256         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
257           { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
258         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
259           { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
260         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
261           { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
262         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
263           { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
264         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
265           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
266             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
267         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
268           { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
269         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
270           { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
271         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
272           { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
273         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
274           { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
275         { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
276           { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
277         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
278           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
279 };
280
281 static struct intc_prio_reg prio_registers[] __initdata = {
282         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
283         { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
284         { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
285         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
286         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
287         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
288         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
289         { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
290         { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
291         { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
292         { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
293         { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
294         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
295           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
296 };
297
298 static struct intc_sense_reg sense_registers[] __initdata = {
299         { 0xa414001c, 16, 2, /* ICR1 */
300           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
301 };
302
303 static DECLARE_INTC_DESC(intc_desc, "sh7723", vectors, groups,
304                          mask_registers, prio_registers, sense_registers);
305
306 void __init plat_irq_setup(void)
307 {
308         register_intc_controller(&intc_desc);
309 }