fbac113bbfbfa846fe76e40f4a6fb722ab99973d
[linux-2.6.git] / arch / sh / include / asm / system.h
1 #ifndef __ASM_SH_SYSTEM_H
2 #define __ASM_SH_SYSTEM_H
3
4 /*
5  * Copyright (C) 1999, 2000  Niibe Yutaka  &  Kaz Kojima
6  * Copyright (C) 2002 Paul Mundt
7  */
8
9 #include <linux/irqflags.h>
10 #include <linux/compiler.h>
11 #include <linux/linkage.h>
12 #include <asm/types.h>
13 #include <asm/ptrace.h>
14
15 #define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
16
17 #if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
18 #define __icbi()                        \
19 {                                       \
20         unsigned long __addr;           \
21         __addr = 0xa8000000;            \
22         __asm__ __volatile__(           \
23                 "icbi   %0\n\t"         \
24                 : /* no output */       \
25                 : "m" (__m(__addr)));   \
26 }
27 #endif
28
29 /*
30  * A brief note on ctrl_barrier(), the control register write barrier.
31  *
32  * Legacy SH cores typically require a sequence of 8 nops after
33  * modification of a control register in order for the changes to take
34  * effect. On newer cores (like the sh4a and sh5) this is accomplished
35  * with icbi.
36  *
37  * Also note that on sh4a in the icbi case we can forego a synco for the
38  * write barrier, as it's not necessary for control registers.
39  *
40  * Historically we have only done this type of barrier for the MMUCR, but
41  * it's also necessary for the CCR, so we make it generic here instead.
42  */
43 #if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
44 #define mb()            __asm__ __volatile__ ("synco": : :"memory")
45 #define rmb()           mb()
46 #define wmb()           __asm__ __volatile__ ("synco": : :"memory")
47 #define ctrl_barrier()  __icbi()
48 #define read_barrier_depends()  do { } while(0)
49 #else
50 #define mb()            __asm__ __volatile__ ("": : :"memory")
51 #define rmb()           mb()
52 #define wmb()           __asm__ __volatile__ ("": : :"memory")
53 #define ctrl_barrier()  __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
54 #define read_barrier_depends()  do { } while(0)
55 #endif
56
57 #ifdef CONFIG_SMP
58 #define smp_mb()        mb()
59 #define smp_rmb()       rmb()
60 #define smp_wmb()       wmb()
61 #define smp_read_barrier_depends()      read_barrier_depends()
62 #else
63 #define smp_mb()        barrier()
64 #define smp_rmb()       barrier()
65 #define smp_wmb()       barrier()
66 #define smp_read_barrier_depends()      do { } while(0)
67 #endif
68
69 #define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
70
71 #ifdef CONFIG_GUSA_RB
72 #include <asm/cmpxchg-grb.h>
73 #elif defined(CONFIG_CPU_SH4A)
74 #include <asm/cmpxchg-llsc.h>
75 #else
76 #include <asm/cmpxchg-irq.h>
77 #endif
78
79 extern void __xchg_called_with_bad_pointer(void);
80
81 #define __xchg(ptr, x, size)                            \
82 ({                                                      \
83         unsigned long __xchg__res;                      \
84         volatile void *__xchg_ptr = (ptr);              \
85         switch (size) {                                 \
86         case 4:                                         \
87                 __xchg__res = xchg_u32(__xchg_ptr, x);  \
88                 break;                                  \
89         case 1:                                         \
90                 __xchg__res = xchg_u8(__xchg_ptr, x);   \
91                 break;                                  \
92         default:                                        \
93                 __xchg_called_with_bad_pointer();       \
94                 __xchg__res = x;                        \
95                 break;                                  \
96         }                                               \
97                                                         \
98         __xchg__res;                                    \
99 })
100
101 #define xchg(ptr,x)     \
102         ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
103
104 /* This function doesn't exist, so you'll get a linker error
105  * if something tries to do an invalid cmpxchg(). */
106 extern void __cmpxchg_called_with_bad_pointer(void);
107
108 #define __HAVE_ARCH_CMPXCHG 1
109
110 static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
111                 unsigned long new, int size)
112 {
113         switch (size) {
114         case 4:
115                 return __cmpxchg_u32(ptr, old, new);
116         }
117         __cmpxchg_called_with_bad_pointer();
118         return old;
119 }
120
121 #define cmpxchg(ptr,o,n)                                                 \
122   ({                                                                     \
123      __typeof__(*(ptr)) _o_ = (o);                                       \
124      __typeof__(*(ptr)) _n_ = (n);                                       \
125      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
126                                     (unsigned long)_n_, sizeof(*(ptr))); \
127   })
128
129 extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
130
131 extern void *set_exception_table_vec(unsigned int vec, void *handler);
132
133 static inline void *set_exception_table_evt(unsigned int evt, void *handler)
134 {
135         return set_exception_table_vec(evt >> 5, handler);
136 }
137
138 /*
139  * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
140  */
141 #ifdef CONFIG_CPU_SH2A
142 extern unsigned int instruction_size(unsigned int insn);
143 #elif defined(CONFIG_SUPERH32)
144 #define instruction_size(insn)  (2)
145 #else
146 #define instruction_size(insn)  (4)
147 #endif
148
149 extern unsigned long cached_to_uncached;
150
151 extern struct dentry *sh_debugfs_root;
152
153 void per_cpu_trap_init(void);
154
155 asmlinkage void break_point_trap(void);
156
157 #ifdef CONFIG_SUPERH32
158 #define BUILD_TRAP_HANDLER(name)                                        \
159 asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \
160                                     unsigned long r6, unsigned long r7, \
161                                     struct pt_regs __regs)
162
163 #define TRAP_HANDLER_DECL                               \
164         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);  \
165         unsigned int vec = regs->tra;                   \
166         (void)vec;
167 #else
168 #define BUILD_TRAP_HANDLER(name)        \
169 asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs)
170 #define TRAP_HANDLER_DECL
171 #endif
172
173 BUILD_TRAP_HANDLER(address_error);
174 BUILD_TRAP_HANDLER(debug);
175 BUILD_TRAP_HANDLER(bug);
176 BUILD_TRAP_HANDLER(fpu_error);
177 BUILD_TRAP_HANDLER(fpu_state_restore);
178
179 #define arch_align_stack(x) (x)
180
181 struct mem_access {
182         unsigned long (*from)(void *dst, const void *src, unsigned long cnt);
183         unsigned long (*to)(void *dst, const void *src, unsigned long cnt);
184 };
185
186 #ifdef CONFIG_SUPERH32
187 # include "system_32.h"
188 #else
189 # include "system_64.h"
190 #endif
191
192 #endif