9fd23ea55bc95e845de9a5e4930ce0f01db9fe54
[linux-2.6.git] / arch / ppc64 / kernel / pmac_smp.c
1 /*
2  * SMP support for power macintosh.
3  *
4  * We support both the old "powersurge" SMP architecture
5  * and the current Core99 (G4 PowerMac) machines.
6  *
7  * Note that we don't support the very first rev. of
8  * Apple/DayStar 2 CPUs board, the one with the funky
9  * watchdog. Hopefully, none of these should be there except
10  * maybe internally to Apple. I should probably still add some
11  * code to detect this card though and disable SMP. --BenH.
12  *
13  * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14  * and Ben Herrenschmidt <benh@kernel.crashing.org>.
15  *
16  * Support for DayStar quad CPU cards
17  * Copyright (C) XLR8, Inc. 1994-2000
18  *
19  *  This program is free software; you can redistribute it and/or
20  *  modify it under the terms of the GNU General Public License
21  *  as published by the Free Software Foundation; either version
22  *  2 of the License, or (at your option) any later version.
23  */
24
25 #undef DEBUG
26
27 #include <linux/config.h>
28 #include <linux/kernel.h>
29 #include <linux/sched.h>
30 #include <linux/smp.h>
31 #include <linux/smp_lock.h>
32 #include <linux/interrupt.h>
33 #include <linux/kernel_stat.h>
34 #include <linux/init.h>
35 #include <linux/spinlock.h>
36 #include <linux/errno.h>
37 #include <linux/irq.h>
38
39 #include <asm/ptrace.h>
40 #include <asm/atomic.h>
41 #include <asm/irq.h>
42 #include <asm/page.h>
43 #include <asm/pgtable.h>
44 #include <asm/sections.h>
45 #include <asm/io.h>
46 #include <asm/prom.h>
47 #include <asm/smp.h>
48 #include <asm/machdep.h>
49 #include <asm/pmac_feature.h>
50 #include <asm/time.h>
51 #include <asm/cacheflush.h>
52 #include <asm/keylargo.h>
53 #include <asm/pmac_low_i2c.h>
54
55 #include "mpic.h"
56
57 #ifdef DEBUG
58 #define DBG(fmt...) udbg_printf(fmt)
59 #else
60 #define DBG(fmt...)
61 #endif
62
63 extern void pmac_secondary_start_1(void);
64 extern void pmac_secondary_start_2(void);
65 extern void pmac_secondary_start_3(void);
66
67 extern struct smp_ops_t *smp_ops;
68
69 static void (*pmac_tb_freeze)(int freeze);
70 static struct device_node *pmac_tb_clock_chip_host;
71 static u8 pmac_tb_pulsar_addr;
72 static DEFINE_SPINLOCK(timebase_lock);
73 static unsigned long timebase;
74
75 static void smp_core99_cypress_tb_freeze(int freeze)
76 {
77         u8 data;
78         int rc;
79
80         /* Strangely, the device-tree says address is 0xd2, but darwin
81          * accesses 0xd0 ...
82          */
83         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_combined);
84         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
85                                0xd0 | pmac_low_i2c_read,
86                                0x81, &data, 1);
87         if (rc != 0)
88                 goto bail;
89
90         data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
91
92         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_stdsub);
93         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
94                                0xd0 | pmac_low_i2c_write,
95                                0x81, &data, 1);
96
97  bail:
98         if (rc != 0) {
99                 printk("Cypress Timebase %s rc: %d\n",
100                        freeze ? "freeze" : "unfreeze", rc);
101                 panic("Timebase freeze failed !\n");
102         }
103 }
104
105 static void smp_core99_pulsar_tb_freeze(int freeze)
106 {
107         u8 data;
108         int rc;
109
110         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_combined);
111         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
112                                pmac_tb_pulsar_addr | pmac_low_i2c_read,
113                                0x2e, &data, 1);
114         if (rc != 0)
115                 goto bail;
116
117         data = (data & 0x88) | (freeze ? 0x11 : 0x22);
118
119         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_stdsub);
120         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
121                                pmac_tb_pulsar_addr | pmac_low_i2c_write,
122                                0x2e, &data, 1);
123  bail:
124         if (rc != 0) {
125                 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
126                        freeze ? "freeze" : "unfreeze", rc);
127                 panic("Timebase freeze failed !\n");
128         }
129 }
130
131
132 static void smp_core99_give_timebase(void)
133 {
134         /* Open i2c bus for synchronous access */
135         if (pmac_low_i2c_open(pmac_tb_clock_chip_host, 0))
136                 panic("Can't open i2c for TB sync !\n");
137
138         spin_lock(&timebase_lock);
139         (*pmac_tb_freeze)(1);
140         mb();
141         timebase = get_tb();
142         spin_unlock(&timebase_lock);
143
144         while (timebase)
145                 barrier();
146
147         spin_lock(&timebase_lock);
148         (*pmac_tb_freeze)(0);
149         spin_unlock(&timebase_lock);
150
151         /* Close i2c bus */
152         pmac_low_i2c_close(pmac_tb_clock_chip_host);
153 }
154
155
156 static void __devinit smp_core99_take_timebase(void)
157 {
158         while (!timebase)
159                 barrier();
160         spin_lock(&timebase_lock);
161         set_tb(timebase >> 32, timebase & 0xffffffff);
162         timebase = 0;
163         spin_unlock(&timebase_lock);
164 }
165
166
167 static int __init smp_core99_probe(void)
168 {
169         struct device_node *cpus;       
170         struct device_node *cc; 
171         int ncpus = 0;
172
173         /* Maybe use systemconfiguration here ? */
174         if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
175
176         /* Count CPUs in the device-tree */
177         for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;)
178                 ++ncpus;
179
180         printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
181
182         /* Nothing more to do if less than 2 of them */
183         if (ncpus <= 1)
184                 return 1;
185
186         /* HW sync only on these platforms */
187         if (!machine_is_compatible("PowerMac7,2") &&
188             !machine_is_compatible("PowerMac7,3") &&
189             !machine_is_compatible("RackMac3,1"))
190                 goto nohwsync;
191
192         /* Look for the clock chip */
193         for (cc = NULL; (cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL;) {
194                 struct device_node *p = of_get_parent(cc);
195                 u32 *reg;
196                 int ok;
197                 ok = p && device_is_compatible(p, "uni-n-i2c");
198                 if (!ok)
199                         goto next;
200                 reg = (u32 *)get_property(cc, "reg", NULL);
201                 if (reg == NULL)
202                         goto next;
203                 switch (*reg) {
204                 case 0xd2:
205                         if (device_is_compatible(cc, "pulsar-legacy-slewing")) {
206                                 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
207                                 pmac_tb_pulsar_addr = 0xd2;
208                                 printk(KERN_INFO "Timebase clock is Pulsar chip\n");
209                         } else if (device_is_compatible(cc, "cy28508")) {
210                                 pmac_tb_freeze = smp_core99_cypress_tb_freeze;
211                                 printk(KERN_INFO "Timebase clock is Cypress chip\n");
212                         }
213                         break;
214                 case 0xd4:
215                         pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
216                         pmac_tb_pulsar_addr = 0xd4;
217                         printk(KERN_INFO "Timebase clock is Pulsar chip\n");
218                         break;
219                 }
220                 if (pmac_tb_freeze != NULL) {
221                         pmac_tb_clock_chip_host = p;
222                         smp_ops->give_timebase = smp_core99_give_timebase;
223                         smp_ops->take_timebase = smp_core99_take_timebase;
224                         of_node_put(cc);
225                         of_node_put(p);
226                         break;
227                 }
228         next:
229                 of_node_put(p);
230         }
231
232  nohwsync:
233         mpic_request_ipis();
234
235         return ncpus;
236 }
237
238 static void __init smp_core99_kick_cpu(int nr)
239 {
240         int save_vector, j;
241         unsigned long new_vector;
242         unsigned long flags;
243         volatile unsigned int *vector
244                  = ((volatile unsigned int *)(KERNELBASE+0x100));
245
246         if (nr < 1 || nr > 3)
247                 return;
248         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346);
249
250         local_irq_save(flags);
251         local_irq_disable();
252
253         /* Save reset vector */
254         save_vector = *vector;
255
256         /* Setup fake reset vector that does    
257          *   b .pmac_secondary_start - KERNELBASE
258          */
259         switch(nr) {
260         case 1:
261                 new_vector = (unsigned long)pmac_secondary_start_1;
262                 break;
263         case 2:
264                 new_vector = (unsigned long)pmac_secondary_start_2;
265                 break;                  
266         case 3:
267         default:
268                 new_vector = (unsigned long)pmac_secondary_start_3;
269                 break;
270         }
271         *vector = 0x48000002 + (new_vector - KERNELBASE);
272
273         /* flush data cache and inval instruction cache */
274         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
275
276         /* Put some life in our friend */
277         pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
278         paca[nr].cpu_start = 1;
279
280         /* FIXME: We wait a bit for the CPU to take the exception, I should
281          * instead wait for the entry code to set something for me. Well,
282          * ideally, all that crap will be done in prom.c and the CPU left
283          * in a RAM-based wait loop like CHRP.
284          */
285         for (j = 1; j < 1000000; j++)
286                 mb();
287
288         /* Restore our exception vector */
289         *vector = save_vector;
290         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
291
292         local_irq_restore(flags);
293         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
294 }
295
296 static void __init smp_core99_setup_cpu(int cpu_nr)
297 {
298         /* Setup MPIC */
299         mpic_setup_this_cpu();
300
301         if (cpu_nr == 0) {
302                 extern void g5_phy_disable_cpu1(void);
303
304                 /* If we didn't start the second CPU, we must take
305                  * it off the bus
306                  */
307                 if (num_online_cpus() < 2)              
308                         g5_phy_disable_cpu1();
309                 if (ppc_md.progress) ppc_md.progress("smp_core99_setup_cpu 0 done", 0x349);
310         }
311 }
312
313 struct smp_ops_t core99_smp_ops = {
314         .message_pass   = smp_mpic_message_pass,
315         .probe          = smp_core99_probe,
316         .kick_cpu       = smp_core99_kick_cpu,
317         .setup_cpu      = smp_core99_setup_cpu,
318         .give_timebase  = smp_generic_give_timebase,
319         .take_timebase  = smp_generic_take_timebase,
320 };
321
322 void __init pmac_setup_smp(void)
323 {
324         smp_ops = &core99_smp_ops;
325 #ifdef CONFIG_HOTPLUG_CPU
326         smp_ops->cpu_enable = generic_cpu_enable;
327         smp_ops->cpu_disable = generic_cpu_disable;
328         smp_ops->cpu_die = generic_cpu_die;
329 #endif
330 }