powerpc: clean up after powermac build merge
[linux-2.6.git] / arch / ppc64 / kernel / pmac_smp.c
1 /*
2  * SMP support for power macintosh.
3  *
4  * We support both the old "powersurge" SMP architecture
5  * and the current Core99 (G4 PowerMac) machines.
6  *
7  * Note that we don't support the very first rev. of
8  * Apple/DayStar 2 CPUs board, the one with the funky
9  * watchdog. Hopefully, none of these should be there except
10  * maybe internally to Apple. I should probably still add some
11  * code to detect this card though and disable SMP. --BenH.
12  *
13  * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14  * and Ben Herrenschmidt <benh@kernel.crashing.org>.
15  *
16  * Support for DayStar quad CPU cards
17  * Copyright (C) XLR8, Inc. 1994-2000
18  *
19  *  This program is free software; you can redistribute it and/or
20  *  modify it under the terms of the GNU General Public License
21  *  as published by the Free Software Foundation; either version
22  *  2 of the License, or (at your option) any later version.
23  */
24
25 #undef DEBUG
26
27 #include <linux/config.h>
28 #include <linux/kernel.h>
29 #include <linux/sched.h>
30 #include <linux/smp.h>
31 #include <linux/smp_lock.h>
32 #include <linux/interrupt.h>
33 #include <linux/kernel_stat.h>
34 #include <linux/init.h>
35 #include <linux/spinlock.h>
36 #include <linux/errno.h>
37 #include <linux/irq.h>
38
39 #include <asm/ptrace.h>
40 #include <asm/atomic.h>
41 #include <asm/irq.h>
42 #include <asm/page.h>
43 #include <asm/pgtable.h>
44 #include <asm/sections.h>
45 #include <asm/io.h>
46 #include <asm/prom.h>
47 #include <asm/smp.h>
48 #include <asm/machdep.h>
49 #include <asm/pmac_feature.h>
50 #include <asm/time.h>
51 #include <asm/cacheflush.h>
52 #include <asm/keylargo.h>
53 #include <asm/pmac_low_i2c.h>
54 #include <asm/mpic.h>
55
56 #ifdef DEBUG
57 #define DBG(fmt...) udbg_printf(fmt)
58 #else
59 #define DBG(fmt...)
60 #endif
61
62 extern void pmac_secondary_start_1(void);
63 extern void pmac_secondary_start_2(void);
64 extern void pmac_secondary_start_3(void);
65
66 extern struct smp_ops_t *smp_ops;
67
68 static void (*pmac_tb_freeze)(int freeze);
69 static struct device_node *pmac_tb_clock_chip_host;
70 static u8 pmac_tb_pulsar_addr;
71 static DEFINE_SPINLOCK(timebase_lock);
72 static unsigned long timebase;
73
74 static void smp_core99_cypress_tb_freeze(int freeze)
75 {
76         u8 data;
77         int rc;
78
79         /* Strangely, the device-tree says address is 0xd2, but darwin
80          * accesses 0xd0 ...
81          */
82         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_combined);
83         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
84                                0xd0 | pmac_low_i2c_read,
85                                0x81, &data, 1);
86         if (rc != 0)
87                 goto bail;
88
89         data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
90
91         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_stdsub);
92         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
93                                0xd0 | pmac_low_i2c_write,
94                                0x81, &data, 1);
95
96  bail:
97         if (rc != 0) {
98                 printk("Cypress Timebase %s rc: %d\n",
99                        freeze ? "freeze" : "unfreeze", rc);
100                 panic("Timebase freeze failed !\n");
101         }
102 }
103
104 static void smp_core99_pulsar_tb_freeze(int freeze)
105 {
106         u8 data;
107         int rc;
108
109         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_combined);
110         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
111                                pmac_tb_pulsar_addr | pmac_low_i2c_read,
112                                0x2e, &data, 1);
113         if (rc != 0)
114                 goto bail;
115
116         data = (data & 0x88) | (freeze ? 0x11 : 0x22);
117
118         pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_stdsub);
119         rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
120                                pmac_tb_pulsar_addr | pmac_low_i2c_write,
121                                0x2e, &data, 1);
122  bail:
123         if (rc != 0) {
124                 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
125                        freeze ? "freeze" : "unfreeze", rc);
126                 panic("Timebase freeze failed !\n");
127         }
128 }
129
130
131 static void smp_core99_give_timebase(void)
132 {
133         /* Open i2c bus for synchronous access */
134         if (pmac_low_i2c_open(pmac_tb_clock_chip_host, 0))
135                 panic("Can't open i2c for TB sync !\n");
136
137         spin_lock(&timebase_lock);
138         (*pmac_tb_freeze)(1);
139         mb();
140         timebase = get_tb();
141         spin_unlock(&timebase_lock);
142
143         while (timebase)
144                 barrier();
145
146         spin_lock(&timebase_lock);
147         (*pmac_tb_freeze)(0);
148         spin_unlock(&timebase_lock);
149
150         /* Close i2c bus */
151         pmac_low_i2c_close(pmac_tb_clock_chip_host);
152 }
153
154
155 static void __devinit smp_core99_take_timebase(void)
156 {
157         while (!timebase)
158                 barrier();
159         spin_lock(&timebase_lock);
160         set_tb(timebase >> 32, timebase & 0xffffffff);
161         timebase = 0;
162         spin_unlock(&timebase_lock);
163 }
164
165
166 static int __init smp_core99_probe(void)
167 {
168         struct device_node *cpus;       
169         struct device_node *cc; 
170         int ncpus = 0;
171
172         /* Maybe use systemconfiguration here ? */
173         if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
174
175         /* Count CPUs in the device-tree */
176         for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;)
177                 ++ncpus;
178
179         printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
180
181         /* Nothing more to do if less than 2 of them */
182         if (ncpus <= 1)
183                 return 1;
184
185         /* HW sync only on these platforms */
186         if (!machine_is_compatible("PowerMac7,2") &&
187             !machine_is_compatible("PowerMac7,3") &&
188             !machine_is_compatible("RackMac3,1"))
189                 goto nohwsync;
190
191         /* Look for the clock chip */
192         for (cc = NULL; (cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL;) {
193                 struct device_node *p = of_get_parent(cc);
194                 u32 *reg;
195                 int ok;
196                 ok = p && device_is_compatible(p, "uni-n-i2c");
197                 if (!ok)
198                         goto next;
199                 reg = (u32 *)get_property(cc, "reg", NULL);
200                 if (reg == NULL)
201                         goto next;
202                 switch (*reg) {
203                 case 0xd2:
204                         if (device_is_compatible(cc, "pulsar-legacy-slewing")) {
205                                 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
206                                 pmac_tb_pulsar_addr = 0xd2;
207                                 printk(KERN_INFO "Timebase clock is Pulsar chip\n");
208                         } else if (device_is_compatible(cc, "cy28508")) {
209                                 pmac_tb_freeze = smp_core99_cypress_tb_freeze;
210                                 printk(KERN_INFO "Timebase clock is Cypress chip\n");
211                         }
212                         break;
213                 case 0xd4:
214                         pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
215                         pmac_tb_pulsar_addr = 0xd4;
216                         printk(KERN_INFO "Timebase clock is Pulsar chip\n");
217                         break;
218                 }
219                 if (pmac_tb_freeze != NULL) {
220                         pmac_tb_clock_chip_host = p;
221                         smp_ops->give_timebase = smp_core99_give_timebase;
222                         smp_ops->take_timebase = smp_core99_take_timebase;
223                         of_node_put(cc);
224                         of_node_put(p);
225                         break;
226                 }
227         next:
228                 of_node_put(p);
229         }
230
231  nohwsync:
232         mpic_request_ipis();
233
234         return ncpus;
235 }
236
237 static void __init smp_core99_kick_cpu(int nr)
238 {
239         int save_vector, j;
240         unsigned long new_vector;
241         unsigned long flags;
242         volatile unsigned int *vector
243                  = ((volatile unsigned int *)(KERNELBASE+0x100));
244
245         if (nr < 1 || nr > 3)
246                 return;
247         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346);
248
249         local_irq_save(flags);
250         local_irq_disable();
251
252         /* Save reset vector */
253         save_vector = *vector;
254
255         /* Setup fake reset vector that does    
256          *   b .pmac_secondary_start - KERNELBASE
257          */
258         switch(nr) {
259         case 1:
260                 new_vector = (unsigned long)pmac_secondary_start_1;
261                 break;
262         case 2:
263                 new_vector = (unsigned long)pmac_secondary_start_2;
264                 break;                  
265         case 3:
266         default:
267                 new_vector = (unsigned long)pmac_secondary_start_3;
268                 break;
269         }
270         *vector = 0x48000002 + (new_vector - KERNELBASE);
271
272         /* flush data cache and inval instruction cache */
273         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
274
275         /* Put some life in our friend */
276         pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
277         paca[nr].cpu_start = 1;
278
279         /* FIXME: We wait a bit for the CPU to take the exception, I should
280          * instead wait for the entry code to set something for me. Well,
281          * ideally, all that crap will be done in prom.c and the CPU left
282          * in a RAM-based wait loop like CHRP.
283          */
284         for (j = 1; j < 1000000; j++)
285                 mb();
286
287         /* Restore our exception vector */
288         *vector = save_vector;
289         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
290
291         local_irq_restore(flags);
292         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
293 }
294
295 static void __init smp_core99_setup_cpu(int cpu_nr)
296 {
297         /* Setup MPIC */
298         mpic_setup_this_cpu();
299
300         if (cpu_nr == 0) {
301                 extern void g5_phy_disable_cpu1(void);
302
303                 /* If we didn't start the second CPU, we must take
304                  * it off the bus
305                  */
306                 if (num_online_cpus() < 2)              
307                         g5_phy_disable_cpu1();
308                 if (ppc_md.progress) ppc_md.progress("smp_core99_setup_cpu 0 done", 0x349);
309         }
310 }
311
312 struct smp_ops_t core99_smp_ops = {
313         .message_pass   = smp_mpic_message_pass,
314         .probe          = smp_core99_probe,
315         .kick_cpu       = smp_core99_kick_cpu,
316         .setup_cpu      = smp_core99_setup_cpu,
317         .give_timebase  = smp_generic_give_timebase,
318         .take_timebase  = smp_generic_take_timebase,
319 };
320
321 void __init pmac_setup_smp(void)
322 {
323         smp_ops = &core99_smp_ops;
324 #ifdef CONFIG_HOTPLUG_CPU
325         smp_ops->cpu_enable = generic_cpu_enable;
326         smp_ops->cpu_disable = generic_cpu_disable;
327         smp_ops->cpu_die = generic_cpu_die;
328 #endif
329 }