2 * SMP support for power macintosh.
4 * We support both the old "powersurge" SMP architecture
5 * and the current Core99 (G4 PowerMac) machines.
7 * Note that we don't support the very first rev. of
8 * Apple/DayStar 2 CPUs board, the one with the funky
9 * watchdog. Hopefully, none of these should be there except
10 * maybe internally to Apple. I should probably still add some
11 * code to detect this card though and disable SMP. --BenH.
13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14 * and Ben Herrenschmidt <benh@kernel.crashing.org>.
16 * Support for DayStar quad CPU cards
17 * Copyright (C) XLR8, Inc. 1994-2000
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
27 #include <linux/config.h>
28 #include <linux/kernel.h>
29 #include <linux/sched.h>
30 #include <linux/smp.h>
31 #include <linux/smp_lock.h>
32 #include <linux/interrupt.h>
33 #include <linux/kernel_stat.h>
34 #include <linux/init.h>
35 #include <linux/spinlock.h>
36 #include <linux/errno.h>
37 #include <linux/irq.h>
39 #include <asm/ptrace.h>
40 #include <asm/atomic.h>
43 #include <asm/pgtable.h>
44 #include <asm/sections.h>
48 #include <asm/machdep.h>
49 #include <asm/pmac_feature.h>
51 #include <asm/cacheflush.h>
52 #include <asm/keylargo.h>
53 #include <asm/pmac_low_i2c.h>
57 #define DBG(fmt...) udbg_printf(fmt)
62 extern void pmac_secondary_start_1(void);
63 extern void pmac_secondary_start_2(void);
64 extern void pmac_secondary_start_3(void);
66 extern struct smp_ops_t *smp_ops;
68 static void (*pmac_tb_freeze)(int freeze);
69 static struct device_node *pmac_tb_clock_chip_host;
70 static u8 pmac_tb_pulsar_addr;
71 static DEFINE_SPINLOCK(timebase_lock);
72 static unsigned long timebase;
74 static void smp_core99_cypress_tb_freeze(int freeze)
79 /* Strangely, the device-tree says address is 0xd2, but darwin
82 pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_combined);
83 rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
84 0xd0 | pmac_low_i2c_read,
89 data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
91 pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_stdsub);
92 rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
93 0xd0 | pmac_low_i2c_write,
98 printk("Cypress Timebase %s rc: %d\n",
99 freeze ? "freeze" : "unfreeze", rc);
100 panic("Timebase freeze failed !\n");
104 static void smp_core99_pulsar_tb_freeze(int freeze)
109 pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_combined);
110 rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
111 pmac_tb_pulsar_addr | pmac_low_i2c_read,
116 data = (data & 0x88) | (freeze ? 0x11 : 0x22);
118 pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_stdsub);
119 rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
120 pmac_tb_pulsar_addr | pmac_low_i2c_write,
124 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
125 freeze ? "freeze" : "unfreeze", rc);
126 panic("Timebase freeze failed !\n");
131 static void smp_core99_give_timebase(void)
133 /* Open i2c bus for synchronous access */
134 if (pmac_low_i2c_open(pmac_tb_clock_chip_host, 0))
135 panic("Can't open i2c for TB sync !\n");
137 spin_lock(&timebase_lock);
138 (*pmac_tb_freeze)(1);
141 spin_unlock(&timebase_lock);
146 spin_lock(&timebase_lock);
147 (*pmac_tb_freeze)(0);
148 spin_unlock(&timebase_lock);
151 pmac_low_i2c_close(pmac_tb_clock_chip_host);
155 static void __devinit smp_core99_take_timebase(void)
159 spin_lock(&timebase_lock);
160 set_tb(timebase >> 32, timebase & 0xffffffff);
162 spin_unlock(&timebase_lock);
166 static int __init smp_core99_probe(void)
168 struct device_node *cpus;
169 struct device_node *cc;
172 /* Maybe use systemconfiguration here ? */
173 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
175 /* Count CPUs in the device-tree */
176 for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;)
179 printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
181 /* Nothing more to do if less than 2 of them */
185 /* HW sync only on these platforms */
186 if (!machine_is_compatible("PowerMac7,2") &&
187 !machine_is_compatible("PowerMac7,3") &&
188 !machine_is_compatible("RackMac3,1"))
191 /* Look for the clock chip */
192 for (cc = NULL; (cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL;) {
193 struct device_node *p = of_get_parent(cc);
196 ok = p && device_is_compatible(p, "uni-n-i2c");
199 reg = (u32 *)get_property(cc, "reg", NULL);
204 if (device_is_compatible(cc, "pulsar-legacy-slewing")) {
205 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
206 pmac_tb_pulsar_addr = 0xd2;
207 printk(KERN_INFO "Timebase clock is Pulsar chip\n");
208 } else if (device_is_compatible(cc, "cy28508")) {
209 pmac_tb_freeze = smp_core99_cypress_tb_freeze;
210 printk(KERN_INFO "Timebase clock is Cypress chip\n");
214 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
215 pmac_tb_pulsar_addr = 0xd4;
216 printk(KERN_INFO "Timebase clock is Pulsar chip\n");
219 if (pmac_tb_freeze != NULL) {
220 pmac_tb_clock_chip_host = p;
221 smp_ops->give_timebase = smp_core99_give_timebase;
222 smp_ops->take_timebase = smp_core99_take_timebase;
237 static void __init smp_core99_kick_cpu(int nr)
240 unsigned long new_vector;
242 volatile unsigned int *vector
243 = ((volatile unsigned int *)(KERNELBASE+0x100));
245 if (nr < 1 || nr > 3)
247 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346);
249 local_irq_save(flags);
252 /* Save reset vector */
253 save_vector = *vector;
255 /* Setup fake reset vector that does
256 * b .pmac_secondary_start - KERNELBASE
260 new_vector = (unsigned long)pmac_secondary_start_1;
263 new_vector = (unsigned long)pmac_secondary_start_2;
267 new_vector = (unsigned long)pmac_secondary_start_3;
270 *vector = 0x48000002 + (new_vector - KERNELBASE);
272 /* flush data cache and inval instruction cache */
273 flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
275 /* Put some life in our friend */
276 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
277 paca[nr].cpu_start = 1;
279 /* FIXME: We wait a bit for the CPU to take the exception, I should
280 * instead wait for the entry code to set something for me. Well,
281 * ideally, all that crap will be done in prom.c and the CPU left
282 * in a RAM-based wait loop like CHRP.
284 for (j = 1; j < 1000000; j++)
287 /* Restore our exception vector */
288 *vector = save_vector;
289 flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
291 local_irq_restore(flags);
292 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
295 static void __init smp_core99_setup_cpu(int cpu_nr)
298 mpic_setup_this_cpu();
301 extern void g5_phy_disable_cpu1(void);
303 /* If we didn't start the second CPU, we must take
306 if (num_online_cpus() < 2)
307 g5_phy_disable_cpu1();
308 if (ppc_md.progress) ppc_md.progress("smp_core99_setup_cpu 0 done", 0x349);
312 struct smp_ops_t core99_smp_ops = {
313 .message_pass = smp_mpic_message_pass,
314 .probe = smp_core99_probe,
315 .kick_cpu = smp_core99_kick_cpu,
316 .setup_cpu = smp_core99_setup_cpu,
317 .give_timebase = smp_generic_give_timebase,
318 .take_timebase = smp_generic_take_timebase,
321 void __init pmac_setup_smp(void)
323 smp_ops = &core99_smp_ops;
324 #ifdef CONFIG_HOTPLUG_CPU
325 smp_ops->cpu_enable = generic_cpu_enable;
326 smp_ops->cpu_disable = generic_cpu_disable;
327 smp_ops->cpu_die = generic_cpu_die;