[PATCH] ppc32: add 440GX rev.F cputable entry
[linux-2.6.git] / arch / ppc / kernel / cputable.c
1 /*
2  *  arch/ppc/kernel/cputable.c
3  *
4  *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
5  *
6  *  This program is free software; you can redistribute it and/or
7  *  modify it under the terms of the GNU General Public License
8  *  as published by the Free Software Foundation; either version
9  *  2 of the License, or (at your option) any later version.
10  */
11
12 #include <linux/config.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/threads.h>
16 #include <linux/init.h>
17 #include <asm/cputable.h>
18
19 struct cpu_spec* cur_cpu_spec[NR_CPUS];
20
21 extern void __setup_cpu_601(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
22 extern void __setup_cpu_603(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
23 extern void __setup_cpu_604(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
24 extern void __setup_cpu_750(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
25 extern void __setup_cpu_750cx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
26 extern void __setup_cpu_750fx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
27 extern void __setup_cpu_7400(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
28 extern void __setup_cpu_7410(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
29 extern void __setup_cpu_745x(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
30 extern void __setup_cpu_power3(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
31 extern void __setup_cpu_power4(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
32 extern void __setup_cpu_ppc970(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
33 extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
34
35 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
36                      !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
37                      !defined(CONFIG_BOOKE))
38
39 /* This table only contains "desktop" CPUs, it need to be filled with embedded
40  * ones as well...
41  */
42 #define COMMON_PPC      (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
43                          PPC_FEATURE_HAS_MMU)
44
45 /* We only set the altivec features if the kernel was compiled with altivec
46  * support
47  */
48 #ifdef CONFIG_ALTIVEC
49 #define CPU_FTR_ALTIVEC_COMP            CPU_FTR_ALTIVEC
50 #define PPC_FEATURE_ALTIVEC_COMP        PPC_FEATURE_HAS_ALTIVEC
51 #else
52 #define CPU_FTR_ALTIVEC_COMP            0
53 #define PPC_FEATURE_ALTIVEC_COMP        0
54 #endif
55
56 /* We only set the spe features if the kernel was compiled with
57  * spe support
58  */
59 #ifdef CONFIG_SPE
60 #define PPC_FEATURE_SPE_COMP            PPC_FEATURE_HAS_SPE
61 #else
62 #define PPC_FEATURE_SPE_COMP            0
63 #endif
64
65 /* We need to mark all pages as being coherent if we're SMP or we
66  * have a 74[45]x and an MPC107 host bridge.
67  */
68 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
69 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
70 #else
71 #define CPU_FTR_COMMON                  0
72 #endif
73
74 /* The powersave features NAP & DOZE seems to confuse BDI when
75    debugging. So if a BDI is used, disable theses
76  */
77 #ifndef CONFIG_BDI_SWITCH
78 #define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
79 #define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
80 #else
81 #define CPU_FTR_MAYBE_CAN_DOZE  0
82 #define CPU_FTR_MAYBE_CAN_NAP   0
83 #endif
84
85 struct cpu_spec cpu_specs[] = {
86 #if CLASSIC_PPC
87         {       /* 601 */
88                 .pvr_mask               = 0xffff0000,
89                 .pvr_value              = 0x00010000,
90                 .cpu_name               = "601",
91                 .cpu_features           = CPU_FTR_COMMON | CPU_FTR_601 |
92                         CPU_FTR_HPTE_TABLE,
93                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_601_INSTR |
94                         PPC_FEATURE_UNIFIED_CACHE,
95                 .icache_bsize           = 32,
96                 .dcache_bsize           = 32,
97                 .cpu_setup              = __setup_cpu_601
98         },
99         {       /* 603 */
100                 .pvr_mask               = 0xffff0000,
101                 .pvr_value              = 0x00030000,
102                 .cpu_name               = "603",
103                 .cpu_features           = CPU_FTR_COMMON |
104                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
105                         CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
106                 .cpu_user_features      = COMMON_PPC,
107                 .icache_bsize           = 32,
108                 .dcache_bsize           = 32,
109                 .cpu_setup              = __setup_cpu_603
110         },
111         {       /* 603e */
112                 .pvr_mask               = 0xffff0000,
113                 .pvr_value              = 0x00060000,
114                 .cpu_name               = "603e",
115                 .cpu_features           = CPU_FTR_COMMON |
116                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
117                         CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
118                 .cpu_user_features      = COMMON_PPC,
119                 .icache_bsize           = 32,
120                 .dcache_bsize           = 32,
121                 .cpu_setup              = __setup_cpu_603
122         },
123         {       /* 603ev */
124                 .pvr_mask               = 0xffff0000,
125                 .pvr_value              = 0x00070000,
126                 .cpu_name               = "603ev",
127                 .cpu_features           = CPU_FTR_COMMON |
128                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
129                         CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
130                 .cpu_user_features      = COMMON_PPC,
131                 .icache_bsize           = 32,
132                 .dcache_bsize           = 32,
133                 .cpu_setup              = __setup_cpu_603
134         },
135         {       /* 604 */
136                 .pvr_mask               = 0xffff0000,
137                 .pvr_value              = 0x00040000,
138                 .cpu_name               = "604",
139                 .cpu_features           = CPU_FTR_COMMON |
140                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
141                         CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
142                 .cpu_user_features      = COMMON_PPC,
143                 .icache_bsize           = 32,
144                 .dcache_bsize           = 32,
145                 .num_pmcs               = 2,
146                 .cpu_setup              = __setup_cpu_604
147         },
148         {       /* 604e */
149                 .pvr_mask               = 0xfffff000,
150                 .pvr_value              = 0x00090000,
151                 .cpu_name               = "604e",
152                 .cpu_features           = CPU_FTR_COMMON |
153                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
154                         CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
155                 .cpu_user_features      = COMMON_PPC,
156                 .icache_bsize           = 32,
157                 .dcache_bsize           = 32,
158                 .num_pmcs               = 4,
159                 .cpu_setup              = __setup_cpu_604
160         },
161         {       /* 604r */
162                 .pvr_mask               = 0xffff0000,
163                 .pvr_value              = 0x00090000,
164                 .cpu_name               = "604r",
165                 .cpu_features           = CPU_FTR_COMMON |
166                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
167                         CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
168                 .cpu_user_features      = COMMON_PPC,
169                 .icache_bsize           = 32,
170                 .dcache_bsize           = 32,
171                 .num_pmcs               = 4,
172                 .cpu_setup              = __setup_cpu_604
173         },
174         {       /* 604ev */
175                 .pvr_mask               = 0xffff0000,
176                 .pvr_value              = 0x000a0000,
177                 .cpu_name               = "604ev",
178                 .cpu_features           = CPU_FTR_COMMON |
179                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
180                         CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
181                 .cpu_user_features      = COMMON_PPC,
182                 .icache_bsize           = 32,
183                 .dcache_bsize           = 32,
184                 .num_pmcs               = 4,
185                 .cpu_setup              = __setup_cpu_604
186         },
187         {       /* 740/750 (0x4202, don't support TAU ?) */
188                 .pvr_mask               = 0xffffffff,
189                 .pvr_value              = 0x00084202,
190                 .cpu_name               = "740/750",
191                 .cpu_features           = CPU_FTR_COMMON |
192                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
193                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE |
194                         CPU_FTR_MAYBE_CAN_NAP,
195                 .cpu_user_features      = COMMON_PPC,
196                 .icache_bsize           = 32,
197                 .dcache_bsize           = 32,
198                 .num_pmcs               = 4,
199                 .cpu_setup              = __setup_cpu_750
200         },
201         {       /* 745/755 */
202                 .pvr_mask               = 0xfffff000,
203                 .pvr_value              = 0x00083000,
204                 .cpu_name               = "745/755",
205                 .cpu_features           = CPU_FTR_COMMON |
206                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
207                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
208                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
209                 .cpu_user_features      = COMMON_PPC,
210                 .icache_bsize           = 32,
211                 .dcache_bsize           = 32,
212                 .num_pmcs               = 4,
213                 .cpu_setup              = __setup_cpu_750
214         },
215         {       /* 750CX (80100 and 8010x?) */
216                 .pvr_mask               = 0xfffffff0,
217                 .pvr_value              = 0x00080100,
218                 .cpu_name               = "750CX",
219                 .cpu_features           = CPU_FTR_COMMON |
220                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
221                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
222                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
223                 .cpu_user_features      = COMMON_PPC,
224                 .icache_bsize           = 32,
225                 .dcache_bsize           = 32,
226                 .num_pmcs               = 4,
227                 .cpu_setup              = __setup_cpu_750cx
228         },
229         {       /* 750CX (82201 and 82202) */
230                 .pvr_mask               = 0xfffffff0,
231                 .pvr_value              = 0x00082200,
232                 .cpu_name               = "750CX",
233                 .cpu_features           = CPU_FTR_COMMON |
234                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
235                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
236                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
237                 .cpu_user_features      = COMMON_PPC,
238                 .icache_bsize           = 32,
239                 .dcache_bsize           = 32,
240                 .num_pmcs               = 4,
241                 .cpu_setup              = __setup_cpu_750cx
242         },
243         {       /* 750CXe (82214) */
244                 .pvr_mask               = 0xfffffff0,
245                 .pvr_value              = 0x00082210,
246                 .cpu_name               = "750CXe",
247                 .cpu_features           = CPU_FTR_COMMON |
248                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
249                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
250                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
251                 .cpu_user_features      = COMMON_PPC,
252                 .icache_bsize           = 32,
253                 .dcache_bsize           = 32,
254                 .num_pmcs               = 4,
255                 .cpu_setup              = __setup_cpu_750cx
256         },
257         {       /* 750FX rev 1.x */
258                 .pvr_mask               = 0xffffff00,
259                 .pvr_value              = 0x70000100,
260                 .cpu_name               = "750FX",
261                 .cpu_features           = CPU_FTR_COMMON |
262                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
263                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
264                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
265                         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
266                 .cpu_user_features      = COMMON_PPC,
267                 .icache_bsize           = 32,
268                 .dcache_bsize           = 32,
269                 .num_pmcs               = 4,
270                 .cpu_setup              = __setup_cpu_750
271         },
272         {       /* 750FX rev 2.0 must disable HID0[DPM] */
273                 .pvr_mask               = 0xffffffff,
274                 .pvr_value              = 0x70000200,
275                 .cpu_name               = "750FX",
276                 .cpu_features           = CPU_FTR_COMMON |
277                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
278                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
279                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
280                         CPU_FTR_NO_DPM,
281                 .cpu_user_features      = COMMON_PPC,
282                 .icache_bsize           = 32,
283                 .dcache_bsize           = 32,
284                 .num_pmcs               = 4,
285                 .cpu_setup              = __setup_cpu_750
286         },
287         {       /* 750FX (All revs except 2.0) */
288                 .pvr_mask               = 0xffff0000,
289                 .pvr_value              = 0x70000000,
290                 .cpu_name               = "750FX",
291                 .cpu_features           = CPU_FTR_COMMON |
292                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
293                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
294                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
295                         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
296                 .cpu_user_features      = COMMON_PPC,
297                 .icache_bsize           = 32,
298                 .dcache_bsize           = 32,
299                 .num_pmcs               = 4,
300                 .cpu_setup              = __setup_cpu_750fx
301         },
302         {       /* 750GX */
303                 .pvr_mask               = 0xffff0000,
304                 .pvr_value              = 0x70020000,
305                 .cpu_name               = "750GX",
306                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
307                         CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
308                         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE |
309                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_DUAL_PLL_750FX |
310                         CPU_FTR_HAS_HIGH_BATS,
311                 .cpu_user_features      = COMMON_PPC,
312                 .icache_bsize           = 32,
313                 .dcache_bsize           = 32,
314                 .num_pmcs               = 4,
315                 .cpu_setup              = __setup_cpu_750fx
316         },
317         {       /* 740/750 (L2CR bit need fixup for 740) */
318                 .pvr_mask               = 0xffff0000,
319                 .pvr_value              = 0x00080000,
320                 .cpu_name               = "740/750",
321                 .cpu_features           = CPU_FTR_COMMON |
322                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
323                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
324                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
325                 .cpu_user_features      = COMMON_PPC,
326                 .icache_bsize           = 32,
327                 .dcache_bsize           = 32,
328                 .num_pmcs               = 4,
329                 .cpu_setup              = __setup_cpu_750
330         },
331         {       /* 7400 rev 1.1 ? (no TAU) */
332                 .pvr_mask               = 0xffffffff,
333                 .pvr_value              = 0x000c1101,
334                 .cpu_name               = "7400 (1.1)",
335                 .cpu_features           = CPU_FTR_COMMON |
336                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
337                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
338                         CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
339                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
340                 .icache_bsize           = 32,
341                 .dcache_bsize           = 32,
342                 .num_pmcs               = 4,
343                 .cpu_setup              = __setup_cpu_7400
344         },
345         {       /* 7400 */
346                 .pvr_mask               = 0xffff0000,
347                 .pvr_value              = 0x000c0000,
348                 .cpu_name               = "7400",
349                 .cpu_features           = CPU_FTR_COMMON |
350                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
351                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
352                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
353                         CPU_FTR_MAYBE_CAN_NAP,
354                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
355                 .icache_bsize           = 32,
356                 .dcache_bsize           = 32,
357                 .num_pmcs               = 4,
358                 .cpu_setup              = __setup_cpu_7400
359         },
360         {       /* 7410 */
361                 .pvr_mask               = 0xffff0000,
362                 .pvr_value              = 0x800c0000,
363                 .cpu_name               = "7410",
364                 .cpu_features           = CPU_FTR_COMMON |
365                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
366                         CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
367                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
368                         CPU_FTR_MAYBE_CAN_NAP,
369                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
370                 .icache_bsize           = 32,
371                 .dcache_bsize           = 32,
372                 .num_pmcs               = 4,
373                 .cpu_setup              = __setup_cpu_7410
374         },
375         {       /* 7450 2.0 - no doze/nap */
376                 .pvr_mask               = 0xffffffff,
377                 .pvr_value              = 0x80000200,
378                 .cpu_name               = "7450",
379                 .cpu_features           = CPU_FTR_COMMON |
380                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
381                         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
382                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
383                         CPU_FTR_NEED_COHERENT,
384                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
385                 .icache_bsize           = 32,
386                 .dcache_bsize           = 32,
387                 .num_pmcs               = 6,
388                 .cpu_setup              = __setup_cpu_745x
389         },
390         {       /* 7450 2.1 */
391                 .pvr_mask               = 0xffffffff,
392                 .pvr_value              = 0x80000201,
393                 .cpu_name               = "7450",
394                 .cpu_features           = CPU_FTR_COMMON |
395                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
396                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
397                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
398                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
399                         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
400                         CPU_FTR_NEED_COHERENT,
401                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
402                 .icache_bsize           = 32,
403                 .dcache_bsize           = 32,
404                 .num_pmcs               = 6,
405                 .cpu_setup              = __setup_cpu_745x
406         },
407         {       /* 7450 2.3 and newer */
408                 .pvr_mask               = 0xffff0000,
409                 .pvr_value              = 0x80000000,
410                 .cpu_name               = "7450",
411                 .cpu_features           = CPU_FTR_COMMON |
412                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
413                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
414                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
415                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
416                         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
417                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
418                 .icache_bsize           = 32,
419                 .dcache_bsize           = 32,
420                 .num_pmcs               = 6,
421                 .cpu_setup              = __setup_cpu_745x
422         },
423         {       /* 7455 rev 1.x */
424                 .pvr_mask               = 0xffffff00,
425                 .pvr_value              = 0x80010100,
426                 .cpu_name               = "7455",
427                 .cpu_features           = CPU_FTR_COMMON |
428                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
429                         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
430                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
431                         CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
432                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
433                 .icache_bsize           = 32,
434                 .dcache_bsize           = 32,
435                 .num_pmcs               = 6,
436                 .cpu_setup              = __setup_cpu_745x
437         },
438         {       /* 7455 rev 2.0 */
439                 .pvr_mask               = 0xffffffff,
440                 .pvr_value              = 0x80010200,
441                 .cpu_name               = "7455",
442                 .cpu_features           = CPU_FTR_COMMON |
443                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
444                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
445                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
446                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
447                         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
448                         CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
449                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
450                 .icache_bsize           = 32,
451                 .dcache_bsize           = 32,
452                 .num_pmcs               = 6,
453                 .cpu_setup              = __setup_cpu_745x
454         },
455         {       /* 7455 others */
456                 .pvr_mask               = 0xffff0000,
457                 .pvr_value              = 0x80010000,
458                 .cpu_name               = "7455",
459                 .cpu_features           = CPU_FTR_COMMON |
460                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
461                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
462                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
463                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
464                         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
465                         CPU_FTR_NEED_COHERENT,
466                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
467                 .icache_bsize           = 32,
468                 .dcache_bsize           = 32,
469                 .num_pmcs               = 6,
470                 .cpu_setup              = __setup_cpu_745x
471         },
472         {       /* 7447/7457 Rev 1.0 */
473                 .pvr_mask               = 0xffffffff,
474                 .pvr_value              = 0x80020100,
475                 .cpu_name               = "7447/7457",
476                 .cpu_features           = CPU_FTR_COMMON |
477                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
478                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
479                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
480                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
481                         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
482                         CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
483                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
484                 .icache_bsize           = 32,
485                 .dcache_bsize           = 32,
486                 .num_pmcs               = 6,
487                 .cpu_setup              = __setup_cpu_745x
488         },
489         {       /* 7447/7457 Rev 1.1 */
490                 .pvr_mask               = 0xffffffff,
491                 .pvr_value              = 0x80020101,
492                 .cpu_name               = "7447/7457",
493                 .cpu_features           = CPU_FTR_COMMON |
494                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
495                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
496                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
497                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
498                         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
499                         CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
500                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
501                 .icache_bsize           = 32,
502                 .dcache_bsize           = 32,
503                 .num_pmcs               = 6,
504                 .cpu_setup              = __setup_cpu_745x
505         },
506         {       /* 7447/7457 Rev 1.2 and later */
507                 .pvr_mask               = 0xffff0000,
508                 .pvr_value              = 0x80020000,
509                 .cpu_name               = "7447/7457",
510                 .cpu_features           = CPU_FTR_COMMON |
511                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
512                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
513                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
514                         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
515                         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
516                         CPU_FTR_NEED_COHERENT,
517                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
518                 .icache_bsize           = 32,
519                 .dcache_bsize           = 32,
520                 .num_pmcs               = 6,
521                 .cpu_setup              = __setup_cpu_745x
522         },
523         {       /* 7447A */
524                 .pvr_mask               = 0xffff0000,
525                 .pvr_value              = 0x80030000,
526                 .cpu_name               = "7447A",
527                 .cpu_features           = CPU_FTR_COMMON |
528                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
529                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
530                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
531                         CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
532                         CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
533                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
534                 .icache_bsize           = 32,
535                 .dcache_bsize           = 32,
536                 .num_pmcs               = 6,
537                 .cpu_setup              = __setup_cpu_745x
538         },
539         {       /* 82xx (8240, 8245, 8260 are all 603e cores) */
540                 .pvr_mask               = 0x7fff0000,
541                 .pvr_value              = 0x00810000,
542                 .cpu_name               = "82xx",
543                 .cpu_features           = CPU_FTR_COMMON |
544                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
545                         CPU_FTR_USE_TB,
546                 .cpu_user_features      = COMMON_PPC,
547                 .icache_bsize           = 32,
548                 .dcache_bsize           = 32,
549                 .cpu_setup              = __setup_cpu_603
550         },
551         {       /* All G2_LE (603e core, plus some) have the same pvr */
552                 .pvr_mask               = 0x7fff0000,
553                 .pvr_value              = 0x00820000,
554                 .cpu_name               = "G2_LE",
555                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
556                         CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
557                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
558                 .cpu_user_features      = COMMON_PPC,
559                 .icache_bsize           = 32,
560                 .dcache_bsize           = 32,
561                 .cpu_setup              = __setup_cpu_603
562         },
563         {       /* e300 (a 603e core, plus some) on 83xx */
564                 .pvr_mask               = 0x7fff0000,
565                 .pvr_value              = 0x00830000,
566                 .cpu_name               = "e300",
567                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
568                         CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
569                         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
570                 .cpu_user_features      = COMMON_PPC,
571                 .icache_bsize           = 32,
572                 .dcache_bsize           = 32,
573                 .cpu_setup              = __setup_cpu_603
574         },
575         {       /* default match, we assume split I/D cache & TB (non-601)... */
576                 .pvr_mask               = 0x00000000,
577                 .pvr_value              = 0x00000000,
578                 .cpu_name               = "(generic PPC)",
579                 .cpu_features           = CPU_FTR_COMMON |
580                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
581                         CPU_FTR_HPTE_TABLE,
582                 .cpu_user_features      = COMMON_PPC,
583                 .icache_bsize           = 32,
584                 .dcache_bsize           = 32,
585                 .cpu_setup              = __setup_cpu_generic
586         },
587 #endif /* CLASSIC_PPC */
588 #ifdef CONFIG_PPC64BRIDGE
589         {       /* Power3 */
590                 .pvr_mask               = 0xffff0000,
591                 .pvr_value              = 0x00400000,
592                 .cpu_name               = "Power3 (630)",
593                 .cpu_features           = CPU_FTR_COMMON |
594                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
595                         CPU_FTR_HPTE_TABLE,
596                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_64,
597                 .icache_bsize           = 128,
598                 .dcache_bsize           = 128,
599                 .num_pmcs               = 8,
600                 .cpu_setup              = __setup_cpu_power3
601         },
602         {       /* Power3+ */
603                 .pvr_mask               = 0xffff0000,
604                 .pvr_value              = 0x00410000,
605                 .cpu_name               = "Power3 (630+)",
606                 .cpu_features           = CPU_FTR_COMMON |
607                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
608                         CPU_FTR_HPTE_TABLE,
609                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_64,
610                 .icache_bsize           = 128,
611                 .dcache_bsize           = 128,
612                 .num_pmcs               = 8,
613                 .cpu_setup              = __setup_cpu_power3
614         },
615         {       /* I-star */
616                 .pvr_mask               = 0xffff0000,
617                 .pvr_value              = 0x00360000,
618                 .cpu_name               = "I-star",
619                 .cpu_features           = CPU_FTR_COMMON |
620                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
621                         CPU_FTR_HPTE_TABLE,
622                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_64,
623                 .icache_bsize           = 128,
624                 .dcache_bsize           = 128,
625                 .num_pmcs               = 8,
626                 .cpu_setup              = __setup_cpu_power3
627         },
628         {       /* S-star */
629                 .pvr_mask               = 0xffff0000,
630                 .pvr_value              = 0x00370000,
631                 .cpu_name               = "S-star",
632                 .cpu_features           = CPU_FTR_COMMON |
633                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
634                         CPU_FTR_HPTE_TABLE,
635                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_64,
636                 .icache_bsize           = 128,
637                 .dcache_bsize           = 128,
638                 .num_pmcs               = 8,
639                 .cpu_setup              = __setup_cpu_power3
640         },
641 #endif /* CONFIG_PPC64BRIDGE */
642 #ifdef CONFIG_POWER4
643         {       /* Power4 */
644                 .pvr_mask               = 0xffff0000,
645                 .pvr_value              = 0x00350000,
646                 .cpu_name               = "Power4",
647                 .cpu_features           = CPU_FTR_COMMON |
648                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
649                         CPU_FTR_HPTE_TABLE,
650                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_64,
651                 .icache_bsize           = 128,
652                 .dcache_bsize           = 128,
653                 .num_pmcs               = 8,
654                 .cpu_setup              = __setup_cpu_power4
655         },
656         {       /* PPC970 */
657                 .pvr_mask               = 0xffff0000,
658                 .pvr_value              = 0x00390000,
659                 .cpu_name               = "PPC970",
660                 .cpu_features           = CPU_FTR_COMMON |
661                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
662                         CPU_FTR_HPTE_TABLE |
663                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
664                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_64 |
665                         PPC_FEATURE_ALTIVEC_COMP,
666                 .icache_bsize           = 128,
667                 .dcache_bsize           = 128,
668                 .num_pmcs               = 8,
669                 .cpu_setup              = __setup_cpu_ppc970
670         },
671         {       /* PPC970FX */
672                 .pvr_mask               = 0xffff0000,
673                 .pvr_value              = 0x003c0000,
674                 .cpu_name               = "PPC970FX",
675                 .cpu_features           = CPU_FTR_COMMON |
676                         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
677                         CPU_FTR_HPTE_TABLE |
678                         CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
679                 .cpu_user_features      = COMMON_PPC | PPC_FEATURE_64 |
680                         PPC_FEATURE_ALTIVEC_COMP,
681                 .icache_bsize           = 128,
682                 .dcache_bsize           = 128,
683                 .num_pmcs               = 8,
684                 .cpu_setup              = __setup_cpu_ppc970
685         },
686 #endif /* CONFIG_POWER4 */
687 #ifdef CONFIG_8xx
688         {       /* 8xx */
689                 .pvr_mask               = 0xffff0000,
690                 .pvr_value              = 0x00500000,
691                 .cpu_name               = "8xx",
692                 /* CPU_FTR_MAYBE_CAN_DOZE is possible,
693                  * if the 8xx code is there.... */
694                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
695                         CPU_FTR_USE_TB,
696                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
697                 .icache_bsize           = 16,
698                 .dcache_bsize           = 16,
699         },
700 #endif /* CONFIG_8xx */
701 #ifdef CONFIG_40x
702         {       /* 403GC */
703                 .pvr_mask               = 0xffffff00,
704                 .pvr_value              = 0x00200200,
705                 .cpu_name               = "403GC",
706                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
707                         CPU_FTR_USE_TB,
708                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
709                 .icache_bsize           = 16,
710                 .dcache_bsize           = 16,
711         },
712         {       /* 403GCX */
713                 .pvr_mask               = 0xffffff00,
714                 .pvr_value              = 0x00201400,
715                 .cpu_name               = "403GCX",
716                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
717                         CPU_FTR_USE_TB,
718                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
719                 .icache_bsize           = 16,
720                 .dcache_bsize           = 16,
721         },
722         {       /* 403G ?? */
723                 .pvr_mask               = 0xffff0000,
724                 .pvr_value              = 0x00200000,
725                 .cpu_name               = "403G ??",
726                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
727                         CPU_FTR_USE_TB,
728                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
729                 .icache_bsize           = 16,
730                 .dcache_bsize           = 16,
731         },
732         {       /* 405GP */
733                 .pvr_mask               = 0xffff0000,
734                 .pvr_value              = 0x40110000,
735                 .cpu_name               = "405GP",
736                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
737                         CPU_FTR_USE_TB,
738                 .cpu_user_features      = PPC_FEATURE_32 |
739                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
740                 .icache_bsize           = 32,
741                 .dcache_bsize           = 32,
742         },
743         {       /* STB 03xxx */
744                 .pvr_mask               = 0xffff0000,
745                 .pvr_value              = 0x40130000,
746                 .cpu_name               = "STB03xxx",
747                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
748                         CPU_FTR_USE_TB,
749                 .cpu_user_features      = PPC_FEATURE_32 |
750                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
751                 .icache_bsize           = 32,
752                 .dcache_bsize           = 32,
753         },
754         {       /* STB 04xxx */
755                 .pvr_mask               = 0xffff0000,
756                 .pvr_value              = 0x41810000,
757                 .cpu_name               = "STB04xxx",
758                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
759                         CPU_FTR_USE_TB,
760                 .cpu_user_features      = PPC_FEATURE_32 |
761                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
762                 .icache_bsize           = 32,
763                 .dcache_bsize           = 32,
764         },
765         {       /* NP405L */
766                 .pvr_mask               = 0xffff0000,
767                 .pvr_value              = 0x41610000,
768                 .cpu_name               = "NP405L",
769                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
770                         CPU_FTR_USE_TB,
771                 .cpu_user_features      = PPC_FEATURE_32 |
772                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
773                 .icache_bsize           = 32,
774                 .dcache_bsize           = 32,
775         },
776         {       /* NP4GS3 */
777                 .pvr_mask               = 0xffff0000,
778                 .pvr_value              = 0x40B10000,
779                 .cpu_name               = "NP4GS3",
780                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
781                         CPU_FTR_USE_TB,
782                 .cpu_user_features      = PPC_FEATURE_32 |
783                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
784                 .icache_bsize           = 32,
785                 .dcache_bsize           = 32,
786         },
787         {   /* NP405H */
788                 .pvr_mask               = 0xffff0000,
789                 .pvr_value              = 0x41410000,
790                 .cpu_name               = "NP405H",
791                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
792                         CPU_FTR_USE_TB,
793                 .cpu_user_features      = PPC_FEATURE_32 |
794                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
795                 .icache_bsize           = 32,
796                 .dcache_bsize           = 32,
797         },
798         {       /* 405GPr */
799                 .pvr_mask               = 0xffff0000,
800                 .pvr_value              = 0x50910000,
801                 .cpu_name               = "405GPr",
802                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
803                         CPU_FTR_USE_TB,
804                 .cpu_user_features      = PPC_FEATURE_32 |
805                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
806                 .icache_bsize           = 32,
807                 .dcache_bsize           = 32,
808         },
809         {   /* STBx25xx */
810                 .pvr_mask               = 0xffff0000,
811                 .pvr_value              = 0x51510000,
812                 .cpu_name               = "STBx25xx",
813                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
814                         CPU_FTR_USE_TB,
815                 .cpu_user_features      = PPC_FEATURE_32 |
816                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
817                 .icache_bsize           = 32,
818                 .dcache_bsize           = 32,
819         },
820         {       /* 405LP */
821                 .pvr_mask               = 0xffff0000,
822                 .pvr_value              = 0x41F10000,
823                 .cpu_name               = "405LP",
824                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
825                         CPU_FTR_USE_TB,
826                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
827                 .icache_bsize           = 32,
828                 .dcache_bsize           = 32,
829         },
830         {       /* Xilinx Virtex-II Pro  */
831                 .pvr_mask               = 0xffff0000,
832                 .pvr_value              = 0x20010000,
833                 .cpu_name               = "Virtex-II Pro",
834                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
835                         CPU_FTR_USE_TB,
836                 .cpu_user_features      = PPC_FEATURE_32 |
837                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
838                 .icache_bsize           = 32,
839                 .dcache_bsize           = 32,
840         },
841         {       /* 405EP */
842                 .pvr_mask               = 0xffff0000,
843                 .pvr_value              = 0x51210000,
844                 .cpu_name               = "405EP",
845                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
846                         CPU_FTR_USE_TB,
847                 .cpu_user_features      = PPC_FEATURE_32 |
848                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
849                 .icache_bsize           = 32,
850                 .dcache_bsize           = 32,
851         },
852
853 #endif /* CONFIG_40x */
854 #ifdef CONFIG_44x
855         {
856                 .pvr_mask               = 0xf0000fff,
857                 .pvr_value              = 0x40000850,
858                 .cpu_name               = "440EP Rev. A",
859                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
860                         CPU_FTR_USE_TB,
861                 .cpu_user_features      = COMMON_PPC, /* 440EP has an FPU */
862                 .icache_bsize           = 32,
863                 .dcache_bsize           = 32,
864         },
865         {
866                 .pvr_mask               = 0xf0000fff,
867                 .pvr_value              = 0x400008d3,
868                 .cpu_name               = "440EP Rev. B",
869                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
870                         CPU_FTR_USE_TB,
871                 .cpu_user_features      = COMMON_PPC, /* 440EP has an FPU */
872                 .icache_bsize           = 32,
873                 .dcache_bsize           = 32,
874         },
875         {       /* 440GP Rev. B */
876                 .pvr_mask               = 0xf0000fff,
877                 .pvr_value              = 0x40000440,
878                 .cpu_name               = "440GP Rev. B",
879                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
880                         CPU_FTR_USE_TB,
881                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
882                 .icache_bsize           = 32,
883                 .dcache_bsize           = 32,
884         },
885         {       /* 440GP Rev. C */
886                 .pvr_mask               = 0xf0000fff,
887                 .pvr_value              = 0x40000481,
888                 .cpu_name               = "440GP Rev. C",
889                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
890                         CPU_FTR_USE_TB,
891                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
892                 .icache_bsize           = 32,
893                 .dcache_bsize           = 32,
894         },
895         { /* 440GX Rev. A */
896                 .pvr_mask               = 0xf0000fff,
897                 .pvr_value              = 0x50000850,
898                 .cpu_name               = "440GX Rev. A",
899                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
900                         CPU_FTR_USE_TB,
901                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
902                 .icache_bsize           = 32,
903                 .dcache_bsize           = 32,
904         },
905         { /* 440GX Rev. B */
906                 .pvr_mask               = 0xf0000fff,
907                 .pvr_value              = 0x50000851,
908                 .cpu_name               = "440GX Rev. B",
909                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
910                         CPU_FTR_USE_TB,
911                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
912                 .icache_bsize           = 32,
913                 .dcache_bsize           = 32,
914         },
915         { /* 440GX Rev. C */
916                 .pvr_mask               = 0xf0000fff,
917                 .pvr_value              = 0x50000892,
918                 .cpu_name               = "440GX Rev. C",
919                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
920                         CPU_FTR_USE_TB,
921                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
922                 .icache_bsize           = 32,
923                 .dcache_bsize           = 32,
924         },
925         { /* 440GX Rev. F */
926                 .pvr_mask               = 0xf0000fff,
927                 .pvr_value              = 0x50000894,
928                 .cpu_name               = "440GX Rev. F",
929                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
930                         CPU_FTR_USE_TB,
931                 .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
932                 .icache_bsize           = 32,
933                 .dcache_bsize           = 32,
934         },
935 #endif /* CONFIG_44x */
936 #ifdef CONFIG_FSL_BOOKE
937         {       /* e200z5 */
938                 .pvr_mask               = 0xfff00000,
939                 .pvr_value              = 0x81000000,
940                 .cpu_name               = "e200z5",
941                 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
942                 .cpu_features           = CPU_FTR_USE_TB,
943                 .cpu_user_features      = PPC_FEATURE_32 |
944                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |
945                         PPC_FEATURE_UNIFIED_CACHE,
946                 .dcache_bsize           = 32,
947         },
948         {       /* e200z6 */
949                 .pvr_mask               = 0xfff00000,
950                 .pvr_value              = 0x81100000,
951                 .cpu_name               = "e200z6",
952                 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
953                 .cpu_features           = CPU_FTR_USE_TB,
954                 .cpu_user_features      = PPC_FEATURE_32 |
955                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
956                         PPC_FEATURE_HAS_EFP_SINGLE |
957                         PPC_FEATURE_UNIFIED_CACHE,
958                 .dcache_bsize           = 32,
959         },
960         {       /* e500 */
961                 .pvr_mask               = 0xffff0000,
962                 .pvr_value              = 0x80200000,
963                 .cpu_name               = "e500",
964                 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
965                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
966                         CPU_FTR_USE_TB,
967                 .cpu_user_features      = PPC_FEATURE_32 |
968                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
969                         PPC_FEATURE_HAS_EFP_SINGLE,
970                 .icache_bsize           = 32,
971                 .dcache_bsize           = 32,
972                 .num_pmcs               = 4,
973         },
974         {       /* e500v2 */
975                 .pvr_mask               = 0xffff0000,
976                 .pvr_value              = 0x80210000,
977                 .cpu_name               = "e500v2",
978                 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
979                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
980                         CPU_FTR_USE_TB | CPU_FTR_BIG_PHYS,
981                 .cpu_user_features      = PPC_FEATURE_32 |
982                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
983                         PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
984                 .icache_bsize           = 32,
985                 .dcache_bsize           = 32,
986                 .num_pmcs               = 4,
987         },
988 #endif
989 #if !CLASSIC_PPC
990         {       /* default match */
991                 .pvr_mask               = 0x00000000,
992                 .pvr_value              = 0x00000000,
993                 .cpu_name               = "(generic PPC)",
994                 .cpu_features           = CPU_FTR_COMMON,
995                 .cpu_user_features      = PPC_FEATURE_32,
996                 .icache_bsize           = 32,
997                 .dcache_bsize           = 32,
998         }
999 #endif /* !CLASSIC_PPC */
1000 };