[POWERPC] CPM: Rename commproc to cpm1 and cpm2_common.c to cpm2.c
[linux-2.6.git] / arch / powerpc / sysdev / cpm1.c
1 /*
2  * General Purpose functions for the global management of the
3  * Communication Processor Module.
4  * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
5  *
6  * In addition to the individual control of the communication
7  * channels, there are a few functions that globally affect the
8  * communication processor.
9  *
10  * Buffer descriptors must be allocated from the dual ported memory
11  * space.  The allocator for that is here.  When the communication
12  * process is reset, we reclaim the memory available.  There is
13  * currently no deallocator for this memory.
14  * The amount of space available is platform dependent.  On the
15  * MBX, the EPPC software loads additional microcode into the
16  * communication processor, and uses some of the DP ram for this
17  * purpose.  Current, the first 512 bytes and the last 256 bytes of
18  * memory are used.  Right now I am conservative and only use the
19  * memory that can never be used for microcode.  If there are
20  * applications that require more DP ram, we can expand the boundaries
21  * but then we have to be careful of any downloaded microcode.
22  */
23 #include <linux/errno.h>
24 #include <linux/sched.h>
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/param.h>
28 #include <linux/string.h>
29 #include <linux/mm.h>
30 #include <linux/interrupt.h>
31 #include <linux/irq.h>
32 #include <linux/module.h>
33 #include <asm/page.h>
34 #include <asm/pgtable.h>
35 #include <asm/8xx_immap.h>
36 #include <asm/cpm1.h>
37 #include <asm/io.h>
38 #include <asm/tlbflush.h>
39 #include <asm/rheap.h>
40 #include <asm/prom.h>
41 #include <asm/cpm.h>
42
43 #include <asm/fs_pd.h>
44
45 #define CPM_MAP_SIZE    (0x4000)
46
47 #ifndef CONFIG_PPC_CPM_NEW_BINDING
48 static void m8xx_cpm_dpinit(void);
49 #endif
50 cpm8xx_t __iomem *cpmp;  /* Pointer to comm processor space */
51 immap_t __iomem *mpc8xx_immr;
52 static cpic8xx_t __iomem *cpic_reg;
53
54 static struct irq_host *cpm_pic_host;
55
56 static void cpm_mask_irq(unsigned int irq)
57 {
58         unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
59
60         clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
61 }
62
63 static void cpm_unmask_irq(unsigned int irq)
64 {
65         unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
66
67         setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
68 }
69
70 static void cpm_end_irq(unsigned int irq)
71 {
72         unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
73
74         out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
75 }
76
77 static struct irq_chip cpm_pic = {
78         .typename = " CPM PIC ",
79         .mask = cpm_mask_irq,
80         .unmask = cpm_unmask_irq,
81         .eoi = cpm_end_irq,
82 };
83
84 int cpm_get_irq(void)
85 {
86         int cpm_vec;
87
88         /* Get the vector by setting the ACK bit and then reading
89          * the register.
90          */
91         out_be16(&cpic_reg->cpic_civr, 1);
92         cpm_vec = in_be16(&cpic_reg->cpic_civr);
93         cpm_vec >>= 11;
94
95         return irq_linear_revmap(cpm_pic_host, cpm_vec);
96 }
97
98 static int cpm_pic_host_map(struct irq_host *h, unsigned int virq,
99                           irq_hw_number_t hw)
100 {
101         pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
102
103         get_irq_desc(virq)->status |= IRQ_LEVEL;
104         set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
105         return 0;
106 }
107
108 /* The CPM can generate the error interrupt when there is a race condition
109  * between generating and masking interrupts.  All we have to do is ACK it
110  * and return.  This is a no-op function so we don't need any special
111  * tests in the interrupt handler.
112  */
113 static irqreturn_t cpm_error_interrupt(int irq, void *dev)
114 {
115         return IRQ_HANDLED;
116 }
117
118 static struct irqaction cpm_error_irqaction = {
119         .handler = cpm_error_interrupt,
120         .mask = CPU_MASK_NONE,
121         .name = "error",
122 };
123
124 static struct irq_host_ops cpm_pic_host_ops = {
125         .map = cpm_pic_host_map,
126 };
127
128 unsigned int cpm_pic_init(void)
129 {
130         struct device_node *np = NULL;
131         struct resource res;
132         unsigned int sirq = NO_IRQ, hwirq, eirq;
133         int ret;
134
135         pr_debug("cpm_pic_init\n");
136
137         np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
138         if (np == NULL)
139                 np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
140         if (np == NULL) {
141                 printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
142                 return sirq;
143         }
144
145         ret = of_address_to_resource(np, 0, &res);
146         if (ret)
147                 goto end;
148
149         cpic_reg = ioremap(res.start, res.end - res.start + 1);
150         if (cpic_reg == NULL)
151                 goto end;
152
153         sirq = irq_of_parse_and_map(np, 0);
154         if (sirq == NO_IRQ)
155                 goto end;
156
157         /* Initialize the CPM interrupt controller. */
158         hwirq = (unsigned int)irq_map[sirq].hwirq;
159         out_be32(&cpic_reg->cpic_cicr,
160             (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
161                 ((hwirq/2) << 13) | CICR_HP_MASK);
162
163         out_be32(&cpic_reg->cpic_cimr, 0);
164
165         cpm_pic_host = irq_alloc_host(of_node_get(np), IRQ_HOST_MAP_LINEAR,
166                                       64, &cpm_pic_host_ops, 64);
167         if (cpm_pic_host == NULL) {
168                 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
169                 sirq = NO_IRQ;
170                 goto end;
171         }
172
173         /* Install our own error handler. */
174         np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
175         if (np == NULL)
176                 np = of_find_node_by_type(NULL, "cpm");
177         if (np == NULL) {
178                 printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
179                 goto end;
180         }
181
182         eirq = irq_of_parse_and_map(np, 0);
183         if (eirq == NO_IRQ)
184                 goto end;
185
186         if (setup_irq(eirq, &cpm_error_irqaction))
187                 printk(KERN_ERR "Could not allocate CPM error IRQ!");
188
189         setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
190
191 end:
192         of_node_put(np);
193         return sirq;
194 }
195
196 void __init cpm_reset(void)
197 {
198         sysconf8xx_t __iomem *siu_conf;
199
200         mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
201         if (!mpc8xx_immr) {
202                 printk(KERN_CRIT "Could not map IMMR\n");
203                 return;
204         }
205
206         cpmp = &mpc8xx_immr->im_cpm;
207
208 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
209         /* Perform a reset.
210         */
211         out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
212
213         /* Wait for it.
214         */
215         while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
216 #endif
217
218 #ifdef CONFIG_UCODE_PATCH
219         cpm_load_patch(cpmp);
220 #endif
221
222         /* Set SDMA Bus Request priority 5.
223          * On 860T, this also enables FEC priority 6.  I am not sure
224          * this is what we realy want for some applications, but the
225          * manual recommends it.
226          * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
227          */
228         siu_conf = immr_map(im_siu_conf);
229         out_be32(&siu_conf->sc_sdcr, 1);
230         immr_unmap(siu_conf);
231
232 #ifdef CONFIG_PPC_CPM_NEW_BINDING
233         cpm_muram_init();
234 #else
235         /* Reclaim the DP memory for our use. */
236         m8xx_cpm_dpinit();
237 #endif
238 }
239
240 static DEFINE_SPINLOCK(cmd_lock);
241
242 #define MAX_CR_CMD_LOOPS        10000
243
244 int cpm_command(u32 command, u8 opcode)
245 {
246         int i, ret;
247         unsigned long flags;
248
249         if (command & 0xffffff0f)
250                 return -EINVAL;
251
252         spin_lock_irqsave(&cmd_lock, flags);
253
254         ret = 0;
255         out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8));
256         for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
257                 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
258                         goto out;
259
260         printk(KERN_ERR "%s(): Not able to issue CPM command\n", __FUNCTION__);
261         ret = -EIO;
262 out:
263         spin_unlock_irqrestore(&cmd_lock, flags);
264         return ret;
265 }
266 EXPORT_SYMBOL(cpm_command);
267
268 /* Set a baud rate generator.  This needs lots of work.  There are
269  * four BRGs, any of which can be wired to any channel.
270  * The internal baud rate clock is the system clock divided by 16.
271  * This assumes the baudrate is 16x oversampled by the uart.
272  */
273 #define BRG_INT_CLK             (get_brgfreq())
274 #define BRG_UART_CLK            (BRG_INT_CLK/16)
275 #define BRG_UART_CLK_DIV16      (BRG_UART_CLK/16)
276
277 void
278 cpm_setbrg(uint brg, uint rate)
279 {
280         u32 __iomem *bp;
281
282         /* This is good enough to get SMCs running.....
283         */
284         bp = &cpmp->cp_brgc1;
285         bp += brg;
286         /* The BRG has a 12-bit counter.  For really slow baud rates (or
287          * really fast processors), we may have to further divide by 16.
288          */
289         if (((BRG_UART_CLK / rate) - 1) < 4096)
290                 out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
291         else
292                 out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
293                               CPM_BRG_EN | CPM_BRG_DIV16);
294 }
295
296 #ifndef CONFIG_PPC_CPM_NEW_BINDING
297 /*
298  * dpalloc / dpfree bits.
299  */
300 static spinlock_t cpm_dpmem_lock;
301 /*
302  * 16 blocks should be enough to satisfy all requests
303  * until the memory subsystem goes up...
304  */
305 static rh_block_t cpm_boot_dpmem_rh_block[16];
306 static rh_info_t cpm_dpmem_info;
307
308 #define CPM_DPMEM_ALIGNMENT     8
309 static u8 __iomem *dpram_vbase;
310 static phys_addr_t dpram_pbase;
311
312 static void m8xx_cpm_dpinit(void)
313 {
314         spin_lock_init(&cpm_dpmem_lock);
315
316         dpram_vbase = cpmp->cp_dpmem;
317         dpram_pbase = get_immrbase() + offsetof(immap_t, im_cpm.cp_dpmem);
318
319         /* Initialize the info header */
320         rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT,
321                         sizeof(cpm_boot_dpmem_rh_block) /
322                         sizeof(cpm_boot_dpmem_rh_block[0]),
323                         cpm_boot_dpmem_rh_block);
324
325         /*
326          * Attach the usable dpmem area.
327          * XXX: This is actually crap.  CPM_DATAONLY_BASE and
328          * CPM_DATAONLY_SIZE are a subset of the available dparm.  It varies
329          * with the processor and the microcode patches applied / activated.
330          * But the following should be at least safe.
331          */
332         rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
333 }
334
335 /*
336  * Allocate the requested size worth of DP memory.
337  * This function returns an offset into the DPRAM area.
338  * Use cpm_dpram_addr() to get the virtual address of the area.
339  */
340 unsigned long cpm_dpalloc(uint size, uint align)
341 {
342         unsigned long start;
343         unsigned long flags;
344
345         spin_lock_irqsave(&cpm_dpmem_lock, flags);
346         cpm_dpmem_info.alignment = align;
347         start = rh_alloc(&cpm_dpmem_info, size, "commproc");
348         spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
349
350         return (uint)start;
351 }
352 EXPORT_SYMBOL(cpm_dpalloc);
353
354 int cpm_dpfree(unsigned long offset)
355 {
356         int ret;
357         unsigned long flags;
358
359         spin_lock_irqsave(&cpm_dpmem_lock, flags);
360         ret = rh_free(&cpm_dpmem_info, offset);
361         spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
362
363         return ret;
364 }
365 EXPORT_SYMBOL(cpm_dpfree);
366
367 unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
368 {
369         unsigned long start;
370         unsigned long flags;
371
372         spin_lock_irqsave(&cpm_dpmem_lock, flags);
373         cpm_dpmem_info.alignment = align;
374         start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
375         spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
376
377         return start;
378 }
379 EXPORT_SYMBOL(cpm_dpalloc_fixed);
380
381 void cpm_dpdump(void)
382 {
383         rh_dump(&cpm_dpmem_info);
384 }
385 EXPORT_SYMBOL(cpm_dpdump);
386
387 void *cpm_dpram_addr(unsigned long offset)
388 {
389         return (void *)(dpram_vbase + offset);
390 }
391 EXPORT_SYMBOL(cpm_dpram_addr);
392
393 uint cpm_dpram_phys(u8 *addr)
394 {
395         return (dpram_pbase + (uint)(addr - dpram_vbase));
396 }
397 EXPORT_SYMBOL(cpm_dpram_phys);
398 #endif /* !CONFIG_PPC_CPM_NEW_BINDING */
399
400 struct cpm_ioport16 {
401         __be16 dir, par, odr_sor, dat, intr;
402         __be16 res[3];
403 };
404
405 struct cpm_ioport32 {
406         __be32 dir, par, sor;
407 };
408
409 static void cpm1_set_pin32(int port, int pin, int flags)
410 {
411         struct cpm_ioport32 __iomem *iop;
412         pin = 1 << (31 - pin);
413
414         if (port == CPM_PORTB)
415                 iop = (struct cpm_ioport32 __iomem *)
416                       &mpc8xx_immr->im_cpm.cp_pbdir;
417         else
418                 iop = (struct cpm_ioport32 __iomem *)
419                       &mpc8xx_immr->im_cpm.cp_pedir;
420
421         if (flags & CPM_PIN_OUTPUT)
422                 setbits32(&iop->dir, pin);
423         else
424                 clrbits32(&iop->dir, pin);
425
426         if (!(flags & CPM_PIN_GPIO))
427                 setbits32(&iop->par, pin);
428         else
429                 clrbits32(&iop->par, pin);
430
431         if (port == CPM_PORTB) {
432                 if (flags & CPM_PIN_OPENDRAIN)
433                         setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
434                 else
435                         clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
436         }
437
438         if (port == CPM_PORTE) {
439                 if (flags & CPM_PIN_SECONDARY)
440                         setbits32(&iop->sor, pin);
441                 else
442                         clrbits32(&iop->sor, pin);
443
444                 if (flags & CPM_PIN_OPENDRAIN)
445                         setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
446                 else
447                         clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
448         }
449 }
450
451 static void cpm1_set_pin16(int port, int pin, int flags)
452 {
453         struct cpm_ioport16 __iomem *iop =
454                 (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
455
456         pin = 1 << (15 - pin);
457
458         if (port != 0)
459                 iop += port - 1;
460
461         if (flags & CPM_PIN_OUTPUT)
462                 setbits16(&iop->dir, pin);
463         else
464                 clrbits16(&iop->dir, pin);
465
466         if (!(flags & CPM_PIN_GPIO))
467                 setbits16(&iop->par, pin);
468         else
469                 clrbits16(&iop->par, pin);
470
471         if (port == CPM_PORTA) {
472                 if (flags & CPM_PIN_OPENDRAIN)
473                         setbits16(&iop->odr_sor, pin);
474                 else
475                         clrbits16(&iop->odr_sor, pin);
476         }
477         if (port == CPM_PORTC) {
478                 if (flags & CPM_PIN_SECONDARY)
479                         setbits16(&iop->odr_sor, pin);
480                 else
481                         clrbits16(&iop->odr_sor, pin);
482         }
483 }
484
485 void cpm1_set_pin(enum cpm_port port, int pin, int flags)
486 {
487         if (port == CPM_PORTB || port == CPM_PORTE)
488                 cpm1_set_pin32(port, pin, flags);
489         else
490                 cpm1_set_pin16(port, pin, flags);
491 }
492
493 int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
494 {
495         int shift;
496         int i, bits = 0;
497         u32 __iomem *reg;
498         u32 mask = 7;
499
500         u8 clk_map[][3] = {
501                 {CPM_CLK_SCC1, CPM_BRG1, 0},
502                 {CPM_CLK_SCC1, CPM_BRG2, 1},
503                 {CPM_CLK_SCC1, CPM_BRG3, 2},
504                 {CPM_CLK_SCC1, CPM_BRG4, 3},
505                 {CPM_CLK_SCC1, CPM_CLK1, 4},
506                 {CPM_CLK_SCC1, CPM_CLK2, 5},
507                 {CPM_CLK_SCC1, CPM_CLK3, 6},
508                 {CPM_CLK_SCC1, CPM_CLK4, 7},
509
510                 {CPM_CLK_SCC2, CPM_BRG1, 0},
511                 {CPM_CLK_SCC2, CPM_BRG2, 1},
512                 {CPM_CLK_SCC2, CPM_BRG3, 2},
513                 {CPM_CLK_SCC2, CPM_BRG4, 3},
514                 {CPM_CLK_SCC2, CPM_CLK1, 4},
515                 {CPM_CLK_SCC2, CPM_CLK2, 5},
516                 {CPM_CLK_SCC2, CPM_CLK3, 6},
517                 {CPM_CLK_SCC2, CPM_CLK4, 7},
518
519                 {CPM_CLK_SCC3, CPM_BRG1, 0},
520                 {CPM_CLK_SCC3, CPM_BRG2, 1},
521                 {CPM_CLK_SCC3, CPM_BRG3, 2},
522                 {CPM_CLK_SCC3, CPM_BRG4, 3},
523                 {CPM_CLK_SCC3, CPM_CLK5, 4},
524                 {CPM_CLK_SCC3, CPM_CLK6, 5},
525                 {CPM_CLK_SCC3, CPM_CLK7, 6},
526                 {CPM_CLK_SCC3, CPM_CLK8, 7},
527
528                 {CPM_CLK_SCC4, CPM_BRG1, 0},
529                 {CPM_CLK_SCC4, CPM_BRG2, 1},
530                 {CPM_CLK_SCC4, CPM_BRG3, 2},
531                 {CPM_CLK_SCC4, CPM_BRG4, 3},
532                 {CPM_CLK_SCC4, CPM_CLK5, 4},
533                 {CPM_CLK_SCC4, CPM_CLK6, 5},
534                 {CPM_CLK_SCC4, CPM_CLK7, 6},
535                 {CPM_CLK_SCC4, CPM_CLK8, 7},
536
537                 {CPM_CLK_SMC1, CPM_BRG1, 0},
538                 {CPM_CLK_SMC1, CPM_BRG2, 1},
539                 {CPM_CLK_SMC1, CPM_BRG3, 2},
540                 {CPM_CLK_SMC1, CPM_BRG4, 3},
541                 {CPM_CLK_SMC1, CPM_CLK1, 4},
542                 {CPM_CLK_SMC1, CPM_CLK2, 5},
543                 {CPM_CLK_SMC1, CPM_CLK3, 6},
544                 {CPM_CLK_SMC1, CPM_CLK4, 7},
545
546                 {CPM_CLK_SMC2, CPM_BRG1, 0},
547                 {CPM_CLK_SMC2, CPM_BRG2, 1},
548                 {CPM_CLK_SMC2, CPM_BRG3, 2},
549                 {CPM_CLK_SMC2, CPM_BRG4, 3},
550                 {CPM_CLK_SMC2, CPM_CLK5, 4},
551                 {CPM_CLK_SMC2, CPM_CLK6, 5},
552                 {CPM_CLK_SMC2, CPM_CLK7, 6},
553                 {CPM_CLK_SMC2, CPM_CLK8, 7},
554         };
555
556         switch (target) {
557         case CPM_CLK_SCC1:
558                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
559                 shift = 0;
560                 break;
561
562         case CPM_CLK_SCC2:
563                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
564                 shift = 8;
565                 break;
566
567         case CPM_CLK_SCC3:
568                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
569                 shift = 16;
570                 break;
571
572         case CPM_CLK_SCC4:
573                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
574                 shift = 24;
575                 break;
576
577         case CPM_CLK_SMC1:
578                 reg = &mpc8xx_immr->im_cpm.cp_simode;
579                 shift = 12;
580                 break;
581
582         case CPM_CLK_SMC2:
583                 reg = &mpc8xx_immr->im_cpm.cp_simode;
584                 shift = 28;
585                 break;
586
587         default:
588                 printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
589                 return -EINVAL;
590         }
591
592         if (reg == &mpc8xx_immr->im_cpm.cp_sicr && mode == CPM_CLK_RX)
593                 shift += 3;
594
595         for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
596                 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
597                         bits = clk_map[i][2];
598                         break;
599                 }
600         }
601
602         if (i == ARRAY_SIZE(clk_map)) {
603                 printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
604                 return -EINVAL;
605         }
606
607         bits <<= shift;
608         mask <<= shift;
609         out_be32(reg, (in_be32(reg) & ~mask) | bits);
610
611         return 0;
612 }