powerpc: Make the 64-bit kernel as a position-independent executable
[linux-2.6.git] / arch / powerpc / platforms / powermac / smp.c
1 /*
2  * SMP support for power macintosh.
3  *
4  * We support both the old "powersurge" SMP architecture
5  * and the current Core99 (G4 PowerMac) machines.
6  *
7  * Note that we don't support the very first rev. of
8  * Apple/DayStar 2 CPUs board, the one with the funky
9  * watchdog. Hopefully, none of these should be there except
10  * maybe internally to Apple. I should probably still add some
11  * code to detect this card though and disable SMP. --BenH.
12  *
13  * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14  * and Ben Herrenschmidt <benh@kernel.crashing.org>.
15  *
16  * Support for DayStar quad CPU cards
17  * Copyright (C) XLR8, Inc. 1994-2000
18  *
19  *  This program is free software; you can redistribute it and/or
20  *  modify it under the terms of the GNU General Public License
21  *  as published by the Free Software Foundation; either version
22  *  2 of the License, or (at your option) any later version.
23  */
24 #include <linux/kernel.h>
25 #include <linux/sched.h>
26 #include <linux/smp.h>
27 #include <linux/interrupt.h>
28 #include <linux/kernel_stat.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/hardirq.h>
34 #include <linux/cpu.h>
35 #include <linux/compiler.h>
36
37 #include <asm/ptrace.h>
38 #include <asm/atomic.h>
39 #include <asm/code-patching.h>
40 #include <asm/irq.h>
41 #include <asm/page.h>
42 #include <asm/pgtable.h>
43 #include <asm/sections.h>
44 #include <asm/io.h>
45 #include <asm/prom.h>
46 #include <asm/smp.h>
47 #include <asm/machdep.h>
48 #include <asm/pmac_feature.h>
49 #include <asm/time.h>
50 #include <asm/mpic.h>
51 #include <asm/cacheflush.h>
52 #include <asm/keylargo.h>
53 #include <asm/pmac_low_i2c.h>
54 #include <asm/pmac_pfunc.h>
55
56 #define DEBUG
57
58 #ifdef DEBUG
59 #define DBG(fmt...) udbg_printf(fmt)
60 #else
61 #define DBG(fmt...)
62 #endif
63
64 extern void __secondary_start_pmac_0(void);
65 extern int pmac_pfunc_base_install(void);
66
67 #ifdef CONFIG_PPC32
68
69 /* Sync flag for HW tb sync */
70 static volatile int sec_tb_reset = 0;
71
72 /*
73  * Powersurge (old powermac SMP) support.
74  */
75
76 /* Addresses for powersurge registers */
77 #define HAMMERHEAD_BASE         0xf8000000
78 #define HHEAD_CONFIG            0x90
79 #define HHEAD_SEC_INTR          0xc0
80
81 /* register for interrupting the primary processor on the powersurge */
82 /* N.B. this is actually the ethernet ROM! */
83 #define PSURGE_PRI_INTR         0xf3019000
84
85 /* register for storing the start address for the secondary processor */
86 /* N.B. this is the PCI config space address register for the 1st bridge */
87 #define PSURGE_START            0xf2800000
88
89 /* Daystar/XLR8 4-CPU card */
90 #define PSURGE_QUAD_REG_ADDR    0xf8800000
91
92 #define PSURGE_QUAD_IRQ_SET     0
93 #define PSURGE_QUAD_IRQ_CLR     1
94 #define PSURGE_QUAD_IRQ_PRIMARY 2
95 #define PSURGE_QUAD_CKSTOP_CTL  3
96 #define PSURGE_QUAD_PRIMARY_ARB 4
97 #define PSURGE_QUAD_BOARD_ID    6
98 #define PSURGE_QUAD_WHICH_CPU   7
99 #define PSURGE_QUAD_CKSTOP_RDBK 8
100 #define PSURGE_QUAD_RESET_CTL   11
101
102 #define PSURGE_QUAD_OUT(r, v)   (out_8(quad_base + ((r) << 4) + 4, (v)))
103 #define PSURGE_QUAD_IN(r)       (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
104 #define PSURGE_QUAD_BIS(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
105 #define PSURGE_QUAD_BIC(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
106
107 /* virtual addresses for the above */
108 static volatile u8 __iomem *hhead_base;
109 static volatile u8 __iomem *quad_base;
110 static volatile u32 __iomem *psurge_pri_intr;
111 static volatile u8 __iomem *psurge_sec_intr;
112 static volatile u32 __iomem *psurge_start;
113
114 /* values for psurge_type */
115 #define PSURGE_NONE             -1
116 #define PSURGE_DUAL             0
117 #define PSURGE_QUAD_OKEE        1
118 #define PSURGE_QUAD_COTTON      2
119 #define PSURGE_QUAD_ICEGRASS    3
120
121 /* what sort of powersurge board we have */
122 static int psurge_type = PSURGE_NONE;
123
124 /*
125  * Set and clear IPIs for powersurge.
126  */
127 static inline void psurge_set_ipi(int cpu)
128 {
129         if (psurge_type == PSURGE_NONE)
130                 return;
131         if (cpu == 0)
132                 in_be32(psurge_pri_intr);
133         else if (psurge_type == PSURGE_DUAL)
134                 out_8(psurge_sec_intr, 0);
135         else
136                 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
137 }
138
139 static inline void psurge_clr_ipi(int cpu)
140 {
141         if (cpu > 0) {
142                 switch(psurge_type) {
143                 case PSURGE_DUAL:
144                         out_8(psurge_sec_intr, ~0);
145                 case PSURGE_NONE:
146                         break;
147                 default:
148                         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
149                 }
150         }
151 }
152
153 /*
154  * On powersurge (old SMP powermac architecture) we don't have
155  * separate IPIs for separate messages like openpic does.  Instead
156  * we have a bitmap for each processor, where a 1 bit means that
157  * the corresponding message is pending for that processor.
158  * Ideally each cpu's entry would be in a different cache line.
159  *  -- paulus.
160  */
161 static unsigned long psurge_smp_message[NR_CPUS];
162
163 void psurge_smp_message_recv(void)
164 {
165         int cpu = smp_processor_id();
166         int msg;
167
168         /* clear interrupt */
169         psurge_clr_ipi(cpu);
170
171         if (num_online_cpus() < 2)
172                 return;
173
174         /* make sure there is a message there */
175         for (msg = 0; msg < 4; msg++)
176                 if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
177                         smp_message_recv(msg);
178 }
179
180 irqreturn_t psurge_primary_intr(int irq, void *d)
181 {
182         psurge_smp_message_recv();
183         return IRQ_HANDLED;
184 }
185
186 static void smp_psurge_message_pass(int target, int msg)
187 {
188         int i;
189
190         if (num_online_cpus() < 2)
191                 return;
192
193         for_each_online_cpu(i) {
194                 if (target == MSG_ALL
195                     || (target == MSG_ALL_BUT_SELF && i != smp_processor_id())
196                     || target == i) {
197                         set_bit(msg, &psurge_smp_message[i]);
198                         psurge_set_ipi(i);
199                 }
200         }
201 }
202
203 /*
204  * Determine a quad card presence. We read the board ID register, we
205  * force the data bus to change to something else, and we read it again.
206  * It it's stable, then the register probably exist (ugh !)
207  */
208 static int __init psurge_quad_probe(void)
209 {
210         int type;
211         unsigned int i;
212
213         type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
214         if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
215             || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
216                 return PSURGE_DUAL;
217
218         /* looks OK, try a slightly more rigorous test */
219         /* bogus is not necessarily cacheline-aligned,
220            though I don't suppose that really matters.  -- paulus */
221         for (i = 0; i < 100; i++) {
222                 volatile u32 bogus[8];
223                 bogus[(0+i)%8] = 0x00000000;
224                 bogus[(1+i)%8] = 0x55555555;
225                 bogus[(2+i)%8] = 0xFFFFFFFF;
226                 bogus[(3+i)%8] = 0xAAAAAAAA;
227                 bogus[(4+i)%8] = 0x33333333;
228                 bogus[(5+i)%8] = 0xCCCCCCCC;
229                 bogus[(6+i)%8] = 0xCCCCCCCC;
230                 bogus[(7+i)%8] = 0x33333333;
231                 wmb();
232                 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
233                 mb();
234                 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
235                         return PSURGE_DUAL;
236         }
237         return type;
238 }
239
240 static void __init psurge_quad_init(void)
241 {
242         int procbits;
243
244         if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
245         procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
246         if (psurge_type == PSURGE_QUAD_ICEGRASS)
247                 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
248         else
249                 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
250         mdelay(33);
251         out_8(psurge_sec_intr, ~0);
252         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
253         PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
254         if (psurge_type != PSURGE_QUAD_ICEGRASS)
255                 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
256         PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
257         mdelay(33);
258         PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
259         mdelay(33);
260         PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
261         mdelay(33);
262 }
263
264 static int __init smp_psurge_probe(void)
265 {
266         int i, ncpus;
267         struct device_node *dn;
268
269         /* We don't do SMP on the PPC601 -- paulus */
270         if (PVR_VER(mfspr(SPRN_PVR)) == 1)
271                 return 1;
272
273         /*
274          * The powersurge cpu board can be used in the generation
275          * of powermacs that have a socket for an upgradeable cpu card,
276          * including the 7500, 8500, 9500, 9600.
277          * The device tree doesn't tell you if you have 2 cpus because
278          * OF doesn't know anything about the 2nd processor.
279          * Instead we look for magic bits in magic registers,
280          * in the hammerhead memory controller in the case of the
281          * dual-cpu powersurge board.  -- paulus.
282          */
283         dn = of_find_node_by_name(NULL, "hammerhead");
284         if (dn == NULL)
285                 return 1;
286         of_node_put(dn);
287
288         hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
289         quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
290         psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
291
292         psurge_type = psurge_quad_probe();
293         if (psurge_type != PSURGE_DUAL) {
294                 psurge_quad_init();
295                 /* All released cards using this HW design have 4 CPUs */
296                 ncpus = 4;
297         } else {
298                 iounmap(quad_base);
299                 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
300                         /* not a dual-cpu card */
301                         iounmap(hhead_base);
302                         psurge_type = PSURGE_NONE;
303                         return 1;
304                 }
305                 ncpus = 2;
306         }
307
308         psurge_start = ioremap(PSURGE_START, 4);
309         psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
310
311         /*
312          * This is necessary because OF doesn't know about the
313          * secondary cpu(s), and thus there aren't nodes in the
314          * device tree for them, and smp_setup_cpu_maps hasn't
315          * set their bits in cpu_possible_map and cpu_present_map.
316          */
317         if (ncpus > NR_CPUS)
318                 ncpus = NR_CPUS;
319         for (i = 1; i < ncpus ; ++i) {
320                 cpu_set(i, cpu_present_map);
321                 set_hard_smp_processor_id(i, i);
322         }
323
324         if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
325
326         return ncpus;
327 }
328
329 static void __init smp_psurge_kick_cpu(int nr)
330 {
331         unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
332         unsigned long a;
333         int i;
334
335         /* may need to flush here if secondary bats aren't setup */
336         for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
337                 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
338         asm volatile("sync");
339
340         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
341
342         out_be32(psurge_start, start);
343         mb();
344
345         psurge_set_ipi(nr);
346         /*
347          * We can't use udelay here because the timebase is now frozen.
348          */
349         for (i = 0; i < 2000; ++i)
350                 barrier();
351         psurge_clr_ipi(nr);
352
353         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
354 }
355
356 /*
357  * With the dual-cpu powersurge board, the decrementers and timebases
358  * of both cpus are frozen after the secondary cpu is started up,
359  * until we give the secondary cpu another interrupt.  This routine
360  * uses this to get the timebases synchronized.
361  *  -- paulus.
362  */
363 static void __init psurge_dual_sync_tb(int cpu_nr)
364 {
365         int t;
366
367         set_dec(tb_ticks_per_jiffy);
368         /* XXX fixme */
369         set_tb(0, 0);
370
371         if (cpu_nr > 0) {
372                 mb();
373                 sec_tb_reset = 1;
374                 return;
375         }
376
377         /* wait for the secondary to have reset its TB before proceeding */
378         for (t = 10000000; t > 0 && !sec_tb_reset; --t)
379                 ;
380
381         /* now interrupt the secondary, starting both TBs */
382         psurge_set_ipi(1);
383 }
384
385 static struct irqaction psurge_irqaction = {
386         .handler = psurge_primary_intr,
387         .flags = IRQF_DISABLED,
388         .mask = CPU_MASK_NONE,
389         .name = "primary IPI",
390 };
391
392 static void __init smp_psurge_setup_cpu(int cpu_nr)
393 {
394
395         if (cpu_nr == 0) {
396                 /* If we failed to start the second CPU, we should still
397                  * send it an IPI to start the timebase & DEC or we might
398                  * have them stuck.
399                  */
400                 if (num_online_cpus() < 2) {
401                         if (psurge_type == PSURGE_DUAL)
402                                 psurge_set_ipi(1);
403                         return;
404                 }
405                 /* reset the entry point so if we get another intr we won't
406                  * try to startup again */
407                 out_be32(psurge_start, 0x100);
408                 if (setup_irq(30, &psurge_irqaction))
409                         printk(KERN_ERR "Couldn't get primary IPI interrupt");
410         }
411
412         if (psurge_type == PSURGE_DUAL)
413                 psurge_dual_sync_tb(cpu_nr);
414 }
415
416 void __init smp_psurge_take_timebase(void)
417 {
418         /* Dummy implementation */
419 }
420
421 void __init smp_psurge_give_timebase(void)
422 {
423         /* Dummy implementation */
424 }
425
426 /* PowerSurge-style Macs */
427 struct smp_ops_t psurge_smp_ops = {
428         .message_pass   = smp_psurge_message_pass,
429         .probe          = smp_psurge_probe,
430         .kick_cpu       = smp_psurge_kick_cpu,
431         .setup_cpu      = smp_psurge_setup_cpu,
432         .give_timebase  = smp_psurge_give_timebase,
433         .take_timebase  = smp_psurge_take_timebase,
434 };
435 #endif /* CONFIG_PPC32 - actually powersurge support */
436
437 /*
438  * Core 99 and later support
439  */
440
441 static void (*pmac_tb_freeze)(int freeze);
442 static u64 timebase;
443 static int tb_req;
444
445 static void smp_core99_give_timebase(void)
446 {
447         unsigned long flags;
448
449         local_irq_save(flags);
450
451         while(!tb_req)
452                 barrier();
453         tb_req = 0;
454         (*pmac_tb_freeze)(1);
455         mb();
456         timebase = get_tb();
457         mb();
458         while (timebase)
459                 barrier();
460         mb();
461         (*pmac_tb_freeze)(0);
462         mb();
463
464         local_irq_restore(flags);
465 }
466
467
468 static void __devinit smp_core99_take_timebase(void)
469 {
470         unsigned long flags;
471
472         local_irq_save(flags);
473
474         tb_req = 1;
475         mb();
476         while (!timebase)
477                 barrier();
478         mb();
479         set_tb(timebase >> 32, timebase & 0xffffffff);
480         timebase = 0;
481         mb();
482         set_dec(tb_ticks_per_jiffy/2);
483
484         local_irq_restore(flags);
485 }
486
487 #ifdef CONFIG_PPC64
488 /*
489  * G5s enable/disable the timebase via an i2c-connected clock chip.
490  */
491 static struct pmac_i2c_bus *pmac_tb_clock_chip_host;
492 static u8 pmac_tb_pulsar_addr;
493
494 static void smp_core99_cypress_tb_freeze(int freeze)
495 {
496         u8 data;
497         int rc;
498
499         /* Strangely, the device-tree says address is 0xd2, but darwin
500          * accesses 0xd0 ...
501          */
502         pmac_i2c_setmode(pmac_tb_clock_chip_host,
503                          pmac_i2c_mode_combined);
504         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
505                            0xd0 | pmac_i2c_read,
506                            1, 0x81, &data, 1);
507         if (rc != 0)
508                 goto bail;
509
510         data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
511
512         pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
513         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
514                            0xd0 | pmac_i2c_write,
515                            1, 0x81, &data, 1);
516
517  bail:
518         if (rc != 0) {
519                 printk("Cypress Timebase %s rc: %d\n",
520                        freeze ? "freeze" : "unfreeze", rc);
521                 panic("Timebase freeze failed !\n");
522         }
523 }
524
525
526 static void smp_core99_pulsar_tb_freeze(int freeze)
527 {
528         u8 data;
529         int rc;
530
531         pmac_i2c_setmode(pmac_tb_clock_chip_host,
532                          pmac_i2c_mode_combined);
533         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
534                            pmac_tb_pulsar_addr | pmac_i2c_read,
535                            1, 0x2e, &data, 1);
536         if (rc != 0)
537                 goto bail;
538
539         data = (data & 0x88) | (freeze ? 0x11 : 0x22);
540
541         pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
542         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
543                            pmac_tb_pulsar_addr | pmac_i2c_write,
544                            1, 0x2e, &data, 1);
545  bail:
546         if (rc != 0) {
547                 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
548                        freeze ? "freeze" : "unfreeze", rc);
549                 panic("Timebase freeze failed !\n");
550         }
551 }
552
553 static void __init smp_core99_setup_i2c_hwsync(int ncpus)
554 {
555         struct device_node *cc = NULL;  
556         struct device_node *p;
557         const char *name = NULL;
558         const u32 *reg;
559         int ok;
560
561         /* Look for the clock chip */
562         while ((cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL) {
563                 p = of_get_parent(cc);
564                 ok = p && of_device_is_compatible(p, "uni-n-i2c");
565                 of_node_put(p);
566                 if (!ok)
567                         continue;
568
569                 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc);
570                 if (pmac_tb_clock_chip_host == NULL)
571                         continue;
572                 reg = of_get_property(cc, "reg", NULL);
573                 if (reg == NULL)
574                         continue;
575                 switch (*reg) {
576                 case 0xd2:
577                         if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) {
578                                 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
579                                 pmac_tb_pulsar_addr = 0xd2;
580                                 name = "Pulsar";
581                         } else if (of_device_is_compatible(cc, "cy28508")) {
582                                 pmac_tb_freeze = smp_core99_cypress_tb_freeze;
583                                 name = "Cypress";
584                         }
585                         break;
586                 case 0xd4:
587                         pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
588                         pmac_tb_pulsar_addr = 0xd4;
589                         name = "Pulsar";
590                         break;
591                 }
592                 if (pmac_tb_freeze != NULL)
593                         break;
594         }
595         if (pmac_tb_freeze != NULL) {
596                 /* Open i2c bus for synchronous access */
597                 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) {
598                         printk(KERN_ERR "Failed top open i2c bus for clock"
599                                " sync, fallback to software sync !\n");
600                         goto no_i2c_sync;
601                 }
602                 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n",
603                        name);
604                 return;
605         }
606  no_i2c_sync:
607         pmac_tb_freeze = NULL;
608         pmac_tb_clock_chip_host = NULL;
609 }
610
611
612
613 /*
614  * Newer G5s uses a platform function
615  */
616
617 static void smp_core99_pfunc_tb_freeze(int freeze)
618 {
619         struct device_node *cpus;
620         struct pmf_args args;
621
622         cpus = of_find_node_by_path("/cpus");
623         BUG_ON(cpus == NULL);
624         args.count = 1;
625         args.u[0].v = !freeze;
626         pmf_call_function(cpus, "cpu-timebase", &args);
627         of_node_put(cpus);
628 }
629
630 #else /* CONFIG_PPC64 */
631
632 /*
633  * SMP G4 use a GPIO to enable/disable the timebase.
634  */
635
636 static unsigned int core99_tb_gpio;     /* Timebase freeze GPIO */
637
638 static void smp_core99_gpio_tb_freeze(int freeze)
639 {
640         if (freeze)
641                 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
642         else
643                 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
644         pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
645 }
646
647
648 #endif /* !CONFIG_PPC64 */
649
650 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
651 volatile static long int core99_l2_cache;
652 volatile static long int core99_l3_cache;
653
654 static void __devinit core99_init_caches(int cpu)
655 {
656 #ifndef CONFIG_PPC64
657         if (!cpu_has_feature(CPU_FTR_L2CR))
658                 return;
659
660         if (cpu == 0) {
661                 core99_l2_cache = _get_L2CR();
662                 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
663         } else {
664                 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
665                 _set_L2CR(0);
666                 _set_L2CR(core99_l2_cache);
667                 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
668         }
669
670         if (!cpu_has_feature(CPU_FTR_L3CR))
671                 return;
672
673         if (cpu == 0){
674                 core99_l3_cache = _get_L3CR();
675                 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
676         } else {
677                 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
678                 _set_L3CR(0);
679                 _set_L3CR(core99_l3_cache);
680                 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
681         }
682 #endif /* !CONFIG_PPC64 */
683 }
684
685 static void __init smp_core99_setup(int ncpus)
686 {
687 #ifdef CONFIG_PPC64
688
689         /* i2c based HW sync on some G5s */
690         if (machine_is_compatible("PowerMac7,2") ||
691             machine_is_compatible("PowerMac7,3") ||
692             machine_is_compatible("RackMac3,1"))
693                 smp_core99_setup_i2c_hwsync(ncpus);
694
695         /* pfunc based HW sync on recent G5s */
696         if (pmac_tb_freeze == NULL) {
697                 struct device_node *cpus =
698                         of_find_node_by_path("/cpus");
699                 if (cpus &&
700                     of_get_property(cpus, "platform-cpu-timebase", NULL)) {
701                         pmac_tb_freeze = smp_core99_pfunc_tb_freeze;
702                         printk(KERN_INFO "Processor timebase sync using"
703                                " platform function\n");
704                 }
705         }
706
707 #else /* CONFIG_PPC64 */
708
709         /* GPIO based HW sync on ppc32 Core99 */
710         if (pmac_tb_freeze == NULL && !machine_is_compatible("MacRISC4")) {
711                 struct device_node *cpu;
712                 const u32 *tbprop = NULL;
713
714                 core99_tb_gpio = KL_GPIO_TB_ENABLE;     /* default value */
715                 cpu = of_find_node_by_type(NULL, "cpu");
716                 if (cpu != NULL) {
717                         tbprop = of_get_property(cpu, "timebase-enable", NULL);
718                         if (tbprop)
719                                 core99_tb_gpio = *tbprop;
720                         of_node_put(cpu);
721                 }
722                 pmac_tb_freeze = smp_core99_gpio_tb_freeze;
723                 printk(KERN_INFO "Processor timebase sync using"
724                        " GPIO 0x%02x\n", core99_tb_gpio);
725         }
726
727 #endif /* CONFIG_PPC64 */
728
729         /* No timebase sync, fallback to software */
730         if (pmac_tb_freeze == NULL) {
731                 smp_ops->give_timebase = smp_generic_give_timebase;
732                 smp_ops->take_timebase = smp_generic_take_timebase;
733                 printk(KERN_INFO "Processor timebase sync using software\n");
734         }
735
736 #ifndef CONFIG_PPC64
737         {
738                 int i;
739
740                 /* XXX should get this from reg properties */
741                 for (i = 1; i < ncpus; ++i)
742                         smp_hw_index[i] = i;
743         }
744 #endif
745
746         /* 32 bits SMP can't NAP */
747         if (!machine_is_compatible("MacRISC4"))
748                 powersave_nap = 0;
749 }
750
751 static int __init smp_core99_probe(void)
752 {
753         struct device_node *cpus;
754         int ncpus = 0;
755
756         if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
757
758         /* Count CPUs in the device-tree */
759         for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;)
760                 ++ncpus;
761
762         printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
763
764         /* Nothing more to do if less than 2 of them */
765         if (ncpus <= 1)
766                 return 1;
767
768         /* We need to perform some early initialisations before we can start
769          * setting up SMP as we are running before initcalls
770          */
771         pmac_pfunc_base_install();
772         pmac_i2c_init();
773
774         /* Setup various bits like timebase sync method, ability to nap, ... */
775         smp_core99_setup(ncpus);
776
777         /* Install IPIs */
778         mpic_request_ipis();
779
780         /* Collect l2cr and l3cr values from CPU 0 */
781         core99_init_caches(0);
782
783         return ncpus;
784 }
785
786 static void __devinit smp_core99_kick_cpu(int nr)
787 {
788         unsigned int save_vector;
789         unsigned long target, flags;
790         unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100);
791
792         if (nr < 0 || nr > 3)
793                 return;
794
795         if (ppc_md.progress)
796                 ppc_md.progress("smp_core99_kick_cpu", 0x346);
797
798         local_irq_save(flags);
799
800         /* Save reset vector */
801         save_vector = *vector;
802
803         /* Setup fake reset vector that does
804          *   b __secondary_start_pmac_0 + nr*8
805          */
806         target = (unsigned long) __secondary_start_pmac_0 + nr * 8;
807         patch_branch(vector, target, BRANCH_SET_LINK);
808
809         /* Put some life in our friend */
810         pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
811
812         /* FIXME: We wait a bit for the CPU to take the exception, I should
813          * instead wait for the entry code to set something for me. Well,
814          * ideally, all that crap will be done in prom.c and the CPU left
815          * in a RAM-based wait loop like CHRP.
816          */
817         mdelay(1);
818
819         /* Restore our exception vector */
820         *vector = save_vector;
821         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
822
823         local_irq_restore(flags);
824         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
825 }
826
827 static void __devinit smp_core99_setup_cpu(int cpu_nr)
828 {
829         /* Setup L2/L3 */
830         if (cpu_nr != 0)
831                 core99_init_caches(cpu_nr);
832
833         /* Setup openpic */
834         mpic_setup_this_cpu();
835
836         if (cpu_nr == 0) {
837 #ifdef CONFIG_PPC64
838                 extern void g5_phy_disable_cpu1(void);
839
840                 /* Close i2c bus if it was used for tb sync */
841                 if (pmac_tb_clock_chip_host) {
842                         pmac_i2c_close(pmac_tb_clock_chip_host);
843                         pmac_tb_clock_chip_host = NULL;
844                 }
845
846                 /* If we didn't start the second CPU, we must take
847                  * it off the bus
848                  */
849                 if (machine_is_compatible("MacRISC4") &&
850                     num_online_cpus() < 2)              
851                         g5_phy_disable_cpu1();
852 #endif /* CONFIG_PPC64 */
853
854                 if (ppc_md.progress)
855                         ppc_md.progress("core99_setup_cpu 0 done", 0x349);
856         }
857 }
858
859
860 #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32)
861
862 int smp_core99_cpu_disable(void)
863 {
864         cpu_clear(smp_processor_id(), cpu_online_map);
865
866         /* XXX reset cpu affinity here */
867         mpic_cpu_set_priority(0xf);
868         asm volatile("mtdec %0" : : "r" (0x7fffffff));
869         mb();
870         udelay(20);
871         asm volatile("mtdec %0" : : "r" (0x7fffffff));
872         return 0;
873 }
874
875 extern void low_cpu_die(void) __attribute__((noreturn)); /* in sleep.S */
876 static int cpu_dead[NR_CPUS];
877
878 void cpu_die(void)
879 {
880         local_irq_disable();
881         cpu_dead[smp_processor_id()] = 1;
882         mb();
883         low_cpu_die();
884 }
885
886 void smp_core99_cpu_die(unsigned int cpu)
887 {
888         int timeout;
889
890         timeout = 1000;
891         while (!cpu_dead[cpu]) {
892                 if (--timeout == 0) {
893                         printk("CPU %u refused to die!\n", cpu);
894                         break;
895                 }
896                 msleep(1);
897         }
898         cpu_dead[cpu] = 0;
899 }
900
901 #endif /* CONFIG_HOTPLUG_CPU && CONFIG_PP32 */
902
903 /* Core99 Macs (dual G4s and G5s) */
904 struct smp_ops_t core99_smp_ops = {
905         .message_pass   = smp_mpic_message_pass,
906         .probe          = smp_core99_probe,
907         .kick_cpu       = smp_core99_kick_cpu,
908         .setup_cpu      = smp_core99_setup_cpu,
909         .give_timebase  = smp_core99_give_timebase,
910         .take_timebase  = smp_core99_take_timebase,
911 #if defined(CONFIG_HOTPLUG_CPU)
912 # if defined(CONFIG_PPC32)
913         .cpu_disable    = smp_core99_cpu_disable,
914         .cpu_die        = smp_core99_cpu_die,
915 # endif
916 # if defined(CONFIG_PPC64)
917         .cpu_disable    = generic_cpu_disable,
918         .cpu_die        = generic_cpu_die,
919         /* intentionally do *NOT* assign cpu_enable,
920          * the generic code will use kick_cpu then! */
921 # endif
922 #endif
923 };